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[SCSI] qla2xxx: Add EDC-update support.
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34
35 #define QLA2XXX_DRIVER_NAME "qla2xxx"
36
37 /*
38 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
39 * but that's fine as we don't look at the last 24 ones for
40 * ISP2100 HBAs.
41 */
42 #define MAILBOX_REGISTER_COUNT_2100 8
43 #define MAILBOX_REGISTER_COUNT 32
44
45 #define QLA2200A_RISC_ROM_VER 4
46 #define FPM_2300 6
47 #define FPM_2310 7
48
49 #include "qla_settings.h"
50
51 /*
52 * Data bit definitions
53 */
54 #define BIT_0 0x1
55 #define BIT_1 0x2
56 #define BIT_2 0x4
57 #define BIT_3 0x8
58 #define BIT_4 0x10
59 #define BIT_5 0x20
60 #define BIT_6 0x40
61 #define BIT_7 0x80
62 #define BIT_8 0x100
63 #define BIT_9 0x200
64 #define BIT_10 0x400
65 #define BIT_11 0x800
66 #define BIT_12 0x1000
67 #define BIT_13 0x2000
68 #define BIT_14 0x4000
69 #define BIT_15 0x8000
70 #define BIT_16 0x10000
71 #define BIT_17 0x20000
72 #define BIT_18 0x40000
73 #define BIT_19 0x80000
74 #define BIT_20 0x100000
75 #define BIT_21 0x200000
76 #define BIT_22 0x400000
77 #define BIT_23 0x800000
78 #define BIT_24 0x1000000
79 #define BIT_25 0x2000000
80 #define BIT_26 0x4000000
81 #define BIT_27 0x8000000
82 #define BIT_28 0x10000000
83 #define BIT_29 0x20000000
84 #define BIT_30 0x40000000
85 #define BIT_31 0x80000000
86
87 #define LSB(x) ((uint8_t)(x))
88 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
89
90 #define LSW(x) ((uint16_t)(x))
91 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
92
93 #define LSD(x) ((uint32_t)((uint64_t)(x)))
94 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
95
96
97 /*
98 * I/O register
99 */
100
101 #define RD_REG_BYTE(addr) readb(addr)
102 #define RD_REG_WORD(addr) readw(addr)
103 #define RD_REG_DWORD(addr) readl(addr)
104 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
105 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
106 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
107 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
108 #define WRT_REG_WORD(addr, data) writew(data,addr)
109 #define WRT_REG_DWORD(addr, data) writel(data,addr)
110
111 /*
112 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
113 * 133Mhz slot.
114 */
115 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
116 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
117
118 /*
119 * Fibre Channel device definitions.
120 */
121 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
122 #define MAX_FIBRE_DEVICES 512
123 #define MAX_FIBRE_LUNS 0xFFFF
124 #define MAX_RSCN_COUNT 32
125 #define MAX_HOST_COUNT 16
126
127 /*
128 * Host adapter default definitions.
129 */
130 #define MAX_BUSES 1 /* We only have one bus today */
131 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
132 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
133 #define MIN_LUNS 8
134 #define MAX_LUNS MAX_FIBRE_LUNS
135 #define MAX_CMDS_PER_LUN 255
136
137 /*
138 * Fibre Channel device definitions.
139 */
140 #define SNS_LAST_LOOP_ID_2100 0xfe
141 #define SNS_LAST_LOOP_ID_2300 0x7ff
142
143 #define LAST_LOCAL_LOOP_ID 0x7d
144 #define SNS_FL_PORT 0x7e
145 #define FABRIC_CONTROLLER 0x7f
146 #define SIMPLE_NAME_SERVER 0x80
147 #define SNS_FIRST_LOOP_ID 0x81
148 #define MANAGEMENT_SERVER 0xfe
149 #define BROADCAST 0xff
150
151 /*
152 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
153 * valid range of an N-PORT id is 0 through 0x7ef.
154 */
155 #define NPH_LAST_HANDLE 0x7ef
156 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
157 #define NPH_SNS 0x7fc /* FFFFFC */
158 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
159 #define NPH_F_PORT 0x7fe /* FFFFFE */
160 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
161
162 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
163 #include "qla_fw.h"
164
165 /*
166 * Timeout timer counts in seconds
167 */
168 #define PORT_RETRY_TIME 1
169 #define LOOP_DOWN_TIMEOUT 60
170 #define LOOP_DOWN_TIME 255 /* 240 */
171 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
172
173 /* Maximum outstanding commands in ISP queues (1-65535) */
174 #define MAX_OUTSTANDING_COMMANDS 1024
175
176 /* ISP request and response entry counts (37-65535) */
177 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
178 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
179 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
180 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
181 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
182 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
183
184 struct req_que;
185
186 /*
187 * SCSI Request Block
188 */
189 typedef struct srb {
190 struct req_que *que;
191 struct fc_port *fcport;
192
193 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
194
195 uint16_t flags;
196
197 uint32_t request_sense_length;
198 uint8_t *request_sense_ptr;
199 } srb_t;
200
201 /*
202 * SRB flag definitions
203 */
204 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
205
206 /*
207 * ISP I/O Register Set structure definitions.
208 */
209 struct device_reg_2xxx {
210 uint16_t flash_address; /* Flash BIOS address */
211 uint16_t flash_data; /* Flash BIOS data */
212 uint16_t unused_1[1]; /* Gap */
213 uint16_t ctrl_status; /* Control/Status */
214 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
215 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
216 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
217
218 uint16_t ictrl; /* Interrupt control */
219 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
220 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
221
222 uint16_t istatus; /* Interrupt status */
223 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
224
225 uint16_t semaphore; /* Semaphore */
226 uint16_t nvram; /* NVRAM register. */
227 #define NVR_DESELECT 0
228 #define NVR_BUSY BIT_15
229 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
230 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
231 #define NVR_DATA_IN BIT_3
232 #define NVR_DATA_OUT BIT_2
233 #define NVR_SELECT BIT_1
234 #define NVR_CLOCK BIT_0
235
236 #define NVR_WAIT_CNT 20000
237
238 union {
239 struct {
240 uint16_t mailbox0;
241 uint16_t mailbox1;
242 uint16_t mailbox2;
243 uint16_t mailbox3;
244 uint16_t mailbox4;
245 uint16_t mailbox5;
246 uint16_t mailbox6;
247 uint16_t mailbox7;
248 uint16_t unused_2[59]; /* Gap */
249 } __attribute__((packed)) isp2100;
250 struct {
251 /* Request Queue */
252 uint16_t req_q_in; /* In-Pointer */
253 uint16_t req_q_out; /* Out-Pointer */
254 /* Response Queue */
255 uint16_t rsp_q_in; /* In-Pointer */
256 uint16_t rsp_q_out; /* Out-Pointer */
257
258 /* RISC to Host Status */
259 uint32_t host_status;
260 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
261 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
262
263 /* Host to Host Semaphore */
264 uint16_t host_semaphore;
265 uint16_t unused_3[17]; /* Gap */
266 uint16_t mailbox0;
267 uint16_t mailbox1;
268 uint16_t mailbox2;
269 uint16_t mailbox3;
270 uint16_t mailbox4;
271 uint16_t mailbox5;
272 uint16_t mailbox6;
273 uint16_t mailbox7;
274 uint16_t mailbox8;
275 uint16_t mailbox9;
276 uint16_t mailbox10;
277 uint16_t mailbox11;
278 uint16_t mailbox12;
279 uint16_t mailbox13;
280 uint16_t mailbox14;
281 uint16_t mailbox15;
282 uint16_t mailbox16;
283 uint16_t mailbox17;
284 uint16_t mailbox18;
285 uint16_t mailbox19;
286 uint16_t mailbox20;
287 uint16_t mailbox21;
288 uint16_t mailbox22;
289 uint16_t mailbox23;
290 uint16_t mailbox24;
291 uint16_t mailbox25;
292 uint16_t mailbox26;
293 uint16_t mailbox27;
294 uint16_t mailbox28;
295 uint16_t mailbox29;
296 uint16_t mailbox30;
297 uint16_t mailbox31;
298 uint16_t fb_cmd;
299 uint16_t unused_4[10]; /* Gap */
300 } __attribute__((packed)) isp2300;
301 } u;
302
303 uint16_t fpm_diag_config;
304 uint16_t unused_5[0x4]; /* Gap */
305 uint16_t risc_hw;
306 uint16_t unused_5_1; /* Gap */
307 uint16_t pcr; /* Processor Control Register. */
308 uint16_t unused_6[0x5]; /* Gap */
309 uint16_t mctr; /* Memory Configuration and Timing. */
310 uint16_t unused_7[0x3]; /* Gap */
311 uint16_t fb_cmd_2100; /* Unused on 23XX */
312 uint16_t unused_8[0x3]; /* Gap */
313 uint16_t hccr; /* Host command & control register. */
314 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
315 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
316 /* HCCR commands */
317 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
318 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
319 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
320 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
321 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
322 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
323 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
324 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
325
326 uint16_t unused_9[5]; /* Gap */
327 uint16_t gpiod; /* GPIO Data register. */
328 uint16_t gpioe; /* GPIO Enable register. */
329 #define GPIO_LED_MASK 0x00C0
330 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
331 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
332 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
333 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
334 #define GPIO_LED_ALL_OFF 0x0000
335 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
336 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
337
338 union {
339 struct {
340 uint16_t unused_10[8]; /* Gap */
341 uint16_t mailbox8;
342 uint16_t mailbox9;
343 uint16_t mailbox10;
344 uint16_t mailbox11;
345 uint16_t mailbox12;
346 uint16_t mailbox13;
347 uint16_t mailbox14;
348 uint16_t mailbox15;
349 uint16_t mailbox16;
350 uint16_t mailbox17;
351 uint16_t mailbox18;
352 uint16_t mailbox19;
353 uint16_t mailbox20;
354 uint16_t mailbox21;
355 uint16_t mailbox22;
356 uint16_t mailbox23; /* Also probe reg. */
357 } __attribute__((packed)) isp2200;
358 } u_end;
359 };
360
361 struct device_reg_25xxmq {
362 uint32_t req_q_in;
363 uint32_t req_q_out;
364 uint32_t rsp_q_in;
365 uint32_t rsp_q_out;
366 };
367
368 typedef union {
369 struct device_reg_2xxx isp;
370 struct device_reg_24xx isp24;
371 struct device_reg_25xxmq isp25mq;
372 } device_reg_t;
373
374 #define ISP_REQ_Q_IN(ha, reg) \
375 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
376 &(reg)->u.isp2100.mailbox4 : \
377 &(reg)->u.isp2300.req_q_in)
378 #define ISP_REQ_Q_OUT(ha, reg) \
379 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
380 &(reg)->u.isp2100.mailbox4 : \
381 &(reg)->u.isp2300.req_q_out)
382 #define ISP_RSP_Q_IN(ha, reg) \
383 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
384 &(reg)->u.isp2100.mailbox5 : \
385 &(reg)->u.isp2300.rsp_q_in)
386 #define ISP_RSP_Q_OUT(ha, reg) \
387 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
388 &(reg)->u.isp2100.mailbox5 : \
389 &(reg)->u.isp2300.rsp_q_out)
390
391 #define MAILBOX_REG(ha, reg, num) \
392 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
393 (num < 8 ? \
394 &(reg)->u.isp2100.mailbox0 + (num) : \
395 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
396 &(reg)->u.isp2300.mailbox0 + (num))
397 #define RD_MAILBOX_REG(ha, reg, num) \
398 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
399 #define WRT_MAILBOX_REG(ha, reg, num, data) \
400 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
401
402 #define FB_CMD_REG(ha, reg) \
403 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
404 &(reg)->fb_cmd_2100 : \
405 &(reg)->u.isp2300.fb_cmd)
406 #define RD_FB_CMD_REG(ha, reg) \
407 RD_REG_WORD(FB_CMD_REG(ha, reg))
408 #define WRT_FB_CMD_REG(ha, reg, data) \
409 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
410
411 typedef struct {
412 uint32_t out_mb; /* outbound from driver */
413 uint32_t in_mb; /* Incoming from RISC */
414 uint16_t mb[MAILBOX_REGISTER_COUNT];
415 long buf_size;
416 void *bufp;
417 uint32_t tov;
418 uint8_t flags;
419 #define MBX_DMA_IN BIT_0
420 #define MBX_DMA_OUT BIT_1
421 #define IOCTL_CMD BIT_2
422 } mbx_cmd_t;
423
424 #define MBX_TOV_SECONDS 30
425
426 /*
427 * ISP product identification definitions in mailboxes after reset.
428 */
429 #define PROD_ID_1 0x4953
430 #define PROD_ID_2 0x0000
431 #define PROD_ID_2a 0x5020
432 #define PROD_ID_3 0x2020
433
434 /*
435 * ISP mailbox Self-Test status codes
436 */
437 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
438 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
439 #define MBS_BUSY 4 /* Busy. */
440
441 /*
442 * ISP mailbox command complete status codes
443 */
444 #define MBS_COMMAND_COMPLETE 0x4000
445 #define MBS_INVALID_COMMAND 0x4001
446 #define MBS_HOST_INTERFACE_ERROR 0x4002
447 #define MBS_TEST_FAILED 0x4003
448 #define MBS_COMMAND_ERROR 0x4005
449 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
450 #define MBS_PORT_ID_USED 0x4007
451 #define MBS_LOOP_ID_USED 0x4008
452 #define MBS_ALL_IDS_IN_USE 0x4009
453 #define MBS_NOT_LOGGED_IN 0x400A
454 #define MBS_LINK_DOWN_ERROR 0x400B
455 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
456
457 /*
458 * ISP mailbox asynchronous event status codes
459 */
460 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
461 #define MBA_RESET 0x8001 /* Reset Detected. */
462 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
463 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
464 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
465 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
466 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
467 /* occurred. */
468 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
469 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
470 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
471 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
472 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
473 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
474 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
475 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
476 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
477 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
478 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
479 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
480 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
481 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
482 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
483 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
484 /* used. */
485 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
486 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
487 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
488 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
489 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
490 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
491 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
492 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
493 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
494 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
495 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
496 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
497 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
498 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
499
500 /*
501 * Firmware options 1, 2, 3.
502 */
503 #define FO1_AE_ON_LIPF8 BIT_0
504 #define FO1_AE_ALL_LIP_RESET BIT_1
505 #define FO1_CTIO_RETRY BIT_3
506 #define FO1_DISABLE_LIP_F7_SW BIT_4
507 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
508 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
509 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
510 #define FO1_SET_EMPHASIS_SWING BIT_8
511 #define FO1_AE_AUTO_BYPASS BIT_9
512 #define FO1_ENABLE_PURE_IOCB BIT_10
513 #define FO1_AE_PLOGI_RJT BIT_11
514 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
515 #define FO1_AE_QUEUE_FULL BIT_13
516
517 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
518 #define FO2_REV_LOOPBACK BIT_1
519
520 #define FO3_ENABLE_EMERG_IOCB BIT_0
521 #define FO3_AE_RND_ERROR BIT_1
522
523 /* 24XX additional firmware options */
524 #define ADD_FO_COUNT 3
525 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
526 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
527
528 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
529
530 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
531
532 /*
533 * ISP mailbox commands
534 */
535 #define MBC_LOAD_RAM 1 /* Load RAM. */
536 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
537 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
538 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
539 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
540 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
541 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
542 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
543 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
544 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
545 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
546 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
547 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
548 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
549 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
550 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
551 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
552 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
553 #define MBC_RESET 0x18 /* Reset. */
554 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
555 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
556 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
557 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
558 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
559 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
560 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
561 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
562 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
563 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
564 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
565 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
566 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
567 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
568 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
569 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
570 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
571 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
572 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
573 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
574 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
575 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
576 /* Initialization Procedure */
577 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
578 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
579 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
580 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
581 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
582 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
583 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
584 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
585 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
586 #define MBC_LIP_RESET 0x6c /* LIP reset. */
587 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
588 /* commandd. */
589 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
590 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
591 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
592 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
593 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
594 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
595 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
596 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
597 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
598 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
599 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
600
601 /*
602 * ISP24xx mailbox commands
603 */
604 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
605 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
606 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
607 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
608 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
609 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
610 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
611 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
612 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
613 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
614 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
615 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
616 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
617 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
618 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
619 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
620
621 /* Firmware return data sizes */
622 #define FCAL_MAP_SIZE 128
623
624 /* Mailbox bit definitions for out_mb and in_mb */
625 #define MBX_31 BIT_31
626 #define MBX_30 BIT_30
627 #define MBX_29 BIT_29
628 #define MBX_28 BIT_28
629 #define MBX_27 BIT_27
630 #define MBX_26 BIT_26
631 #define MBX_25 BIT_25
632 #define MBX_24 BIT_24
633 #define MBX_23 BIT_23
634 #define MBX_22 BIT_22
635 #define MBX_21 BIT_21
636 #define MBX_20 BIT_20
637 #define MBX_19 BIT_19
638 #define MBX_18 BIT_18
639 #define MBX_17 BIT_17
640 #define MBX_16 BIT_16
641 #define MBX_15 BIT_15
642 #define MBX_14 BIT_14
643 #define MBX_13 BIT_13
644 #define MBX_12 BIT_12
645 #define MBX_11 BIT_11
646 #define MBX_10 BIT_10
647 #define MBX_9 BIT_9
648 #define MBX_8 BIT_8
649 #define MBX_7 BIT_7
650 #define MBX_6 BIT_6
651 #define MBX_5 BIT_5
652 #define MBX_4 BIT_4
653 #define MBX_3 BIT_3
654 #define MBX_2 BIT_2
655 #define MBX_1 BIT_1
656 #define MBX_0 BIT_0
657
658 /*
659 * Firmware state codes from get firmware state mailbox command
660 */
661 #define FSTATE_CONFIG_WAIT 0
662 #define FSTATE_WAIT_AL_PA 1
663 #define FSTATE_WAIT_LOGIN 2
664 #define FSTATE_READY 3
665 #define FSTATE_LOSS_OF_SYNC 4
666 #define FSTATE_ERROR 5
667 #define FSTATE_REINIT 6
668 #define FSTATE_NON_PART 7
669
670 #define FSTATE_CONFIG_CORRECT 0
671 #define FSTATE_P2P_RCV_LIP 1
672 #define FSTATE_P2P_CHOOSE_LOOP 2
673 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
674 #define FSTATE_FATAL_ERROR 4
675 #define FSTATE_LOOP_BACK_CONN 5
676
677 /*
678 * Port Database structure definition
679 * Little endian except where noted.
680 */
681 #define PORT_DATABASE_SIZE 128 /* bytes */
682 typedef struct {
683 uint8_t options;
684 uint8_t control;
685 uint8_t master_state;
686 uint8_t slave_state;
687 uint8_t reserved[2];
688 uint8_t hard_address;
689 uint8_t reserved_1;
690 uint8_t port_id[4];
691 uint8_t node_name[WWN_SIZE];
692 uint8_t port_name[WWN_SIZE];
693 uint16_t execution_throttle;
694 uint16_t execution_count;
695 uint8_t reset_count;
696 uint8_t reserved_2;
697 uint16_t resource_allocation;
698 uint16_t current_allocation;
699 uint16_t queue_head;
700 uint16_t queue_tail;
701 uint16_t transmit_execution_list_next;
702 uint16_t transmit_execution_list_previous;
703 uint16_t common_features;
704 uint16_t total_concurrent_sequences;
705 uint16_t RO_by_information_category;
706 uint8_t recipient;
707 uint8_t initiator;
708 uint16_t receive_data_size;
709 uint16_t concurrent_sequences;
710 uint16_t open_sequences_per_exchange;
711 uint16_t lun_abort_flags;
712 uint16_t lun_stop_flags;
713 uint16_t stop_queue_head;
714 uint16_t stop_queue_tail;
715 uint16_t port_retry_timer;
716 uint16_t next_sequence_id;
717 uint16_t frame_count;
718 uint16_t PRLI_payload_length;
719 uint8_t prli_svc_param_word_0[2]; /* Big endian */
720 /* Bits 15-0 of word 0 */
721 uint8_t prli_svc_param_word_3[2]; /* Big endian */
722 /* Bits 15-0 of word 3 */
723 uint16_t loop_id;
724 uint16_t extended_lun_info_list_pointer;
725 uint16_t extended_lun_stop_list_pointer;
726 } port_database_t;
727
728 /*
729 * Port database slave/master states
730 */
731 #define PD_STATE_DISCOVERY 0
732 #define PD_STATE_WAIT_DISCOVERY_ACK 1
733 #define PD_STATE_PORT_LOGIN 2
734 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
735 #define PD_STATE_PROCESS_LOGIN 4
736 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
737 #define PD_STATE_PORT_LOGGED_IN 6
738 #define PD_STATE_PORT_UNAVAILABLE 7
739 #define PD_STATE_PROCESS_LOGOUT 8
740 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
741 #define PD_STATE_PORT_LOGOUT 10
742 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
743
744
745 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
746 #define QLA_ZIO_DISABLED 0
747 #define QLA_ZIO_DEFAULT_TIMER 2
748
749 /*
750 * ISP Initialization Control Block.
751 * Little endian except where noted.
752 */
753 #define ICB_VERSION 1
754 typedef struct {
755 uint8_t version;
756 uint8_t reserved_1;
757
758 /*
759 * LSB BIT 0 = Enable Hard Loop Id
760 * LSB BIT 1 = Enable Fairness
761 * LSB BIT 2 = Enable Full-Duplex
762 * LSB BIT 3 = Enable Fast Posting
763 * LSB BIT 4 = Enable Target Mode
764 * LSB BIT 5 = Disable Initiator Mode
765 * LSB BIT 6 = Enable ADISC
766 * LSB BIT 7 = Enable Target Inquiry Data
767 *
768 * MSB BIT 0 = Enable PDBC Notify
769 * MSB BIT 1 = Non Participating LIP
770 * MSB BIT 2 = Descending Loop ID Search
771 * MSB BIT 3 = Acquire Loop ID in LIPA
772 * MSB BIT 4 = Stop PortQ on Full Status
773 * MSB BIT 5 = Full Login after LIP
774 * MSB BIT 6 = Node Name Option
775 * MSB BIT 7 = Ext IFWCB enable bit
776 */
777 uint8_t firmware_options[2];
778
779 uint16_t frame_payload_size;
780 uint16_t max_iocb_allocation;
781 uint16_t execution_throttle;
782 uint8_t retry_count;
783 uint8_t retry_delay; /* unused */
784 uint8_t port_name[WWN_SIZE]; /* Big endian. */
785 uint16_t hard_address;
786 uint8_t inquiry_data;
787 uint8_t login_timeout;
788 uint8_t node_name[WWN_SIZE]; /* Big endian. */
789
790 uint16_t request_q_outpointer;
791 uint16_t response_q_inpointer;
792 uint16_t request_q_length;
793 uint16_t response_q_length;
794 uint32_t request_q_address[2];
795 uint32_t response_q_address[2];
796
797 uint16_t lun_enables;
798 uint8_t command_resource_count;
799 uint8_t immediate_notify_resource_count;
800 uint16_t timeout;
801 uint8_t reserved_2[2];
802
803 /*
804 * LSB BIT 0 = Timer Operation mode bit 0
805 * LSB BIT 1 = Timer Operation mode bit 1
806 * LSB BIT 2 = Timer Operation mode bit 2
807 * LSB BIT 3 = Timer Operation mode bit 3
808 * LSB BIT 4 = Init Config Mode bit 0
809 * LSB BIT 5 = Init Config Mode bit 1
810 * LSB BIT 6 = Init Config Mode bit 2
811 * LSB BIT 7 = Enable Non part on LIHA failure
812 *
813 * MSB BIT 0 = Enable class 2
814 * MSB BIT 1 = Enable ACK0
815 * MSB BIT 2 =
816 * MSB BIT 3 =
817 * MSB BIT 4 = FC Tape Enable
818 * MSB BIT 5 = Enable FC Confirm
819 * MSB BIT 6 = Enable command queuing in target mode
820 * MSB BIT 7 = No Logo On Link Down
821 */
822 uint8_t add_firmware_options[2];
823
824 uint8_t response_accumulation_timer;
825 uint8_t interrupt_delay_timer;
826
827 /*
828 * LSB BIT 0 = Enable Read xfr_rdy
829 * LSB BIT 1 = Soft ID only
830 * LSB BIT 2 =
831 * LSB BIT 3 =
832 * LSB BIT 4 = FCP RSP Payload [0]
833 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
834 * LSB BIT 6 = Enable Out-of-Order frame handling
835 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
836 *
837 * MSB BIT 0 = Sbus enable - 2300
838 * MSB BIT 1 =
839 * MSB BIT 2 =
840 * MSB BIT 3 =
841 * MSB BIT 4 = LED mode
842 * MSB BIT 5 = enable 50 ohm termination
843 * MSB BIT 6 = Data Rate (2300 only)
844 * MSB BIT 7 = Data Rate (2300 only)
845 */
846 uint8_t special_options[2];
847
848 uint8_t reserved_3[26];
849 } init_cb_t;
850
851 /*
852 * Get Link Status mailbox command return buffer.
853 */
854 #define GLSO_SEND_RPS BIT_0
855 #define GLSO_USE_DID BIT_3
856
857 struct link_statistics {
858 uint32_t link_fail_cnt;
859 uint32_t loss_sync_cnt;
860 uint32_t loss_sig_cnt;
861 uint32_t prim_seq_err_cnt;
862 uint32_t inval_xmit_word_cnt;
863 uint32_t inval_crc_cnt;
864 uint32_t lip_cnt;
865 uint32_t unused1[0x1a];
866 uint32_t tx_frames;
867 uint32_t rx_frames;
868 uint32_t dumped_frames;
869 uint32_t unused2[2];
870 uint32_t nos_rcvd;
871 };
872
873 /*
874 * NVRAM Command values.
875 */
876 #define NV_START_BIT BIT_2
877 #define NV_WRITE_OP (BIT_26+BIT_24)
878 #define NV_READ_OP (BIT_26+BIT_25)
879 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
880 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
881 #define NV_DELAY_COUNT 10
882
883 /*
884 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
885 */
886 typedef struct {
887 /*
888 * NVRAM header
889 */
890 uint8_t id[4];
891 uint8_t nvram_version;
892 uint8_t reserved_0;
893
894 /*
895 * NVRAM RISC parameter block
896 */
897 uint8_t parameter_block_version;
898 uint8_t reserved_1;
899
900 /*
901 * LSB BIT 0 = Enable Hard Loop Id
902 * LSB BIT 1 = Enable Fairness
903 * LSB BIT 2 = Enable Full-Duplex
904 * LSB BIT 3 = Enable Fast Posting
905 * LSB BIT 4 = Enable Target Mode
906 * LSB BIT 5 = Disable Initiator Mode
907 * LSB BIT 6 = Enable ADISC
908 * LSB BIT 7 = Enable Target Inquiry Data
909 *
910 * MSB BIT 0 = Enable PDBC Notify
911 * MSB BIT 1 = Non Participating LIP
912 * MSB BIT 2 = Descending Loop ID Search
913 * MSB BIT 3 = Acquire Loop ID in LIPA
914 * MSB BIT 4 = Stop PortQ on Full Status
915 * MSB BIT 5 = Full Login after LIP
916 * MSB BIT 6 = Node Name Option
917 * MSB BIT 7 = Ext IFWCB enable bit
918 */
919 uint8_t firmware_options[2];
920
921 uint16_t frame_payload_size;
922 uint16_t max_iocb_allocation;
923 uint16_t execution_throttle;
924 uint8_t retry_count;
925 uint8_t retry_delay; /* unused */
926 uint8_t port_name[WWN_SIZE]; /* Big endian. */
927 uint16_t hard_address;
928 uint8_t inquiry_data;
929 uint8_t login_timeout;
930 uint8_t node_name[WWN_SIZE]; /* Big endian. */
931
932 /*
933 * LSB BIT 0 = Timer Operation mode bit 0
934 * LSB BIT 1 = Timer Operation mode bit 1
935 * LSB BIT 2 = Timer Operation mode bit 2
936 * LSB BIT 3 = Timer Operation mode bit 3
937 * LSB BIT 4 = Init Config Mode bit 0
938 * LSB BIT 5 = Init Config Mode bit 1
939 * LSB BIT 6 = Init Config Mode bit 2
940 * LSB BIT 7 = Enable Non part on LIHA failure
941 *
942 * MSB BIT 0 = Enable class 2
943 * MSB BIT 1 = Enable ACK0
944 * MSB BIT 2 =
945 * MSB BIT 3 =
946 * MSB BIT 4 = FC Tape Enable
947 * MSB BIT 5 = Enable FC Confirm
948 * MSB BIT 6 = Enable command queuing in target mode
949 * MSB BIT 7 = No Logo On Link Down
950 */
951 uint8_t add_firmware_options[2];
952
953 uint8_t response_accumulation_timer;
954 uint8_t interrupt_delay_timer;
955
956 /*
957 * LSB BIT 0 = Enable Read xfr_rdy
958 * LSB BIT 1 = Soft ID only
959 * LSB BIT 2 =
960 * LSB BIT 3 =
961 * LSB BIT 4 = FCP RSP Payload [0]
962 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
963 * LSB BIT 6 = Enable Out-of-Order frame handling
964 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
965 *
966 * MSB BIT 0 = Sbus enable - 2300
967 * MSB BIT 1 =
968 * MSB BIT 2 =
969 * MSB BIT 3 =
970 * MSB BIT 4 = LED mode
971 * MSB BIT 5 = enable 50 ohm termination
972 * MSB BIT 6 = Data Rate (2300 only)
973 * MSB BIT 7 = Data Rate (2300 only)
974 */
975 uint8_t special_options[2];
976
977 /* Reserved for expanded RISC parameter block */
978 uint8_t reserved_2[22];
979
980 /*
981 * LSB BIT 0 = Tx Sensitivity 1G bit 0
982 * LSB BIT 1 = Tx Sensitivity 1G bit 1
983 * LSB BIT 2 = Tx Sensitivity 1G bit 2
984 * LSB BIT 3 = Tx Sensitivity 1G bit 3
985 * LSB BIT 4 = Rx Sensitivity 1G bit 0
986 * LSB BIT 5 = Rx Sensitivity 1G bit 1
987 * LSB BIT 6 = Rx Sensitivity 1G bit 2
988 * LSB BIT 7 = Rx Sensitivity 1G bit 3
989 *
990 * MSB BIT 0 = Tx Sensitivity 2G bit 0
991 * MSB BIT 1 = Tx Sensitivity 2G bit 1
992 * MSB BIT 2 = Tx Sensitivity 2G bit 2
993 * MSB BIT 3 = Tx Sensitivity 2G bit 3
994 * MSB BIT 4 = Rx Sensitivity 2G bit 0
995 * MSB BIT 5 = Rx Sensitivity 2G bit 1
996 * MSB BIT 6 = Rx Sensitivity 2G bit 2
997 * MSB BIT 7 = Rx Sensitivity 2G bit 3
998 *
999 * LSB BIT 0 = Output Swing 1G bit 0
1000 * LSB BIT 1 = Output Swing 1G bit 1
1001 * LSB BIT 2 = Output Swing 1G bit 2
1002 * LSB BIT 3 = Output Emphasis 1G bit 0
1003 * LSB BIT 4 = Output Emphasis 1G bit 1
1004 * LSB BIT 5 = Output Swing 2G bit 0
1005 * LSB BIT 6 = Output Swing 2G bit 1
1006 * LSB BIT 7 = Output Swing 2G bit 2
1007 *
1008 * MSB BIT 0 = Output Emphasis 2G bit 0
1009 * MSB BIT 1 = Output Emphasis 2G bit 1
1010 * MSB BIT 2 = Output Enable
1011 * MSB BIT 3 =
1012 * MSB BIT 4 =
1013 * MSB BIT 5 =
1014 * MSB BIT 6 =
1015 * MSB BIT 7 =
1016 */
1017 uint8_t seriallink_options[4];
1018
1019 /*
1020 * NVRAM host parameter block
1021 *
1022 * LSB BIT 0 = Enable spinup delay
1023 * LSB BIT 1 = Disable BIOS
1024 * LSB BIT 2 = Enable Memory Map BIOS
1025 * LSB BIT 3 = Enable Selectable Boot
1026 * LSB BIT 4 = Disable RISC code load
1027 * LSB BIT 5 = Set cache line size 1
1028 * LSB BIT 6 = PCI Parity Disable
1029 * LSB BIT 7 = Enable extended logging
1030 *
1031 * MSB BIT 0 = Enable 64bit addressing
1032 * MSB BIT 1 = Enable lip reset
1033 * MSB BIT 2 = Enable lip full login
1034 * MSB BIT 3 = Enable target reset
1035 * MSB BIT 4 = Enable database storage
1036 * MSB BIT 5 = Enable cache flush read
1037 * MSB BIT 6 = Enable database load
1038 * MSB BIT 7 = Enable alternate WWN
1039 */
1040 uint8_t host_p[2];
1041
1042 uint8_t boot_node_name[WWN_SIZE];
1043 uint8_t boot_lun_number;
1044 uint8_t reset_delay;
1045 uint8_t port_down_retry_count;
1046 uint8_t boot_id_number;
1047 uint16_t max_luns_per_target;
1048 uint8_t fcode_boot_port_name[WWN_SIZE];
1049 uint8_t alternate_port_name[WWN_SIZE];
1050 uint8_t alternate_node_name[WWN_SIZE];
1051
1052 /*
1053 * BIT 0 = Selective Login
1054 * BIT 1 = Alt-Boot Enable
1055 * BIT 2 =
1056 * BIT 3 = Boot Order List
1057 * BIT 4 =
1058 * BIT 5 = Selective LUN
1059 * BIT 6 =
1060 * BIT 7 = unused
1061 */
1062 uint8_t efi_parameters;
1063
1064 uint8_t link_down_timeout;
1065
1066 uint8_t adapter_id[16];
1067
1068 uint8_t alt1_boot_node_name[WWN_SIZE];
1069 uint16_t alt1_boot_lun_number;
1070 uint8_t alt2_boot_node_name[WWN_SIZE];
1071 uint16_t alt2_boot_lun_number;
1072 uint8_t alt3_boot_node_name[WWN_SIZE];
1073 uint16_t alt3_boot_lun_number;
1074 uint8_t alt4_boot_node_name[WWN_SIZE];
1075 uint16_t alt4_boot_lun_number;
1076 uint8_t alt5_boot_node_name[WWN_SIZE];
1077 uint16_t alt5_boot_lun_number;
1078 uint8_t alt6_boot_node_name[WWN_SIZE];
1079 uint16_t alt6_boot_lun_number;
1080 uint8_t alt7_boot_node_name[WWN_SIZE];
1081 uint16_t alt7_boot_lun_number;
1082
1083 uint8_t reserved_3[2];
1084
1085 /* Offset 200-215 : Model Number */
1086 uint8_t model_number[16];
1087
1088 /* OEM related items */
1089 uint8_t oem_specific[16];
1090
1091 /*
1092 * NVRAM Adapter Features offset 232-239
1093 *
1094 * LSB BIT 0 = External GBIC
1095 * LSB BIT 1 = Risc RAM parity
1096 * LSB BIT 2 = Buffer Plus Module
1097 * LSB BIT 3 = Multi Chip Adapter
1098 * LSB BIT 4 = Internal connector
1099 * LSB BIT 5 =
1100 * LSB BIT 6 =
1101 * LSB BIT 7 =
1102 *
1103 * MSB BIT 0 =
1104 * MSB BIT 1 =
1105 * MSB BIT 2 =
1106 * MSB BIT 3 =
1107 * MSB BIT 4 =
1108 * MSB BIT 5 =
1109 * MSB BIT 6 =
1110 * MSB BIT 7 =
1111 */
1112 uint8_t adapter_features[2];
1113
1114 uint8_t reserved_4[16];
1115
1116 /* Subsystem vendor ID for ISP2200 */
1117 uint16_t subsystem_vendor_id_2200;
1118
1119 /* Subsystem device ID for ISP2200 */
1120 uint16_t subsystem_device_id_2200;
1121
1122 uint8_t reserved_5;
1123 uint8_t checksum;
1124 } nvram_t;
1125
1126 /*
1127 * ISP queue - response queue entry definition.
1128 */
1129 typedef struct {
1130 uint8_t data[60];
1131 uint32_t signature;
1132 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1133 } response_t;
1134
1135 typedef union {
1136 uint16_t extended;
1137 struct {
1138 uint8_t reserved;
1139 uint8_t standard;
1140 } id;
1141 } target_id_t;
1142
1143 #define SET_TARGET_ID(ha, to, from) \
1144 do { \
1145 if (HAS_EXTENDED_IDS(ha)) \
1146 to.extended = cpu_to_le16(from); \
1147 else \
1148 to.id.standard = (uint8_t)from; \
1149 } while (0)
1150
1151 /*
1152 * ISP queue - command entry structure definition.
1153 */
1154 #define COMMAND_TYPE 0x11 /* Command entry */
1155 typedef struct {
1156 uint8_t entry_type; /* Entry type. */
1157 uint8_t entry_count; /* Entry count. */
1158 uint8_t sys_define; /* System defined. */
1159 uint8_t entry_status; /* Entry Status. */
1160 uint32_t handle; /* System handle. */
1161 target_id_t target; /* SCSI ID */
1162 uint16_t lun; /* SCSI LUN */
1163 uint16_t control_flags; /* Control flags. */
1164 #define CF_WRITE BIT_6
1165 #define CF_READ BIT_5
1166 #define CF_SIMPLE_TAG BIT_3
1167 #define CF_ORDERED_TAG BIT_2
1168 #define CF_HEAD_TAG BIT_1
1169 uint16_t reserved_1;
1170 uint16_t timeout; /* Command timeout. */
1171 uint16_t dseg_count; /* Data segment count. */
1172 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1173 uint32_t byte_count; /* Total byte count. */
1174 uint32_t dseg_0_address; /* Data segment 0 address. */
1175 uint32_t dseg_0_length; /* Data segment 0 length. */
1176 uint32_t dseg_1_address; /* Data segment 1 address. */
1177 uint32_t dseg_1_length; /* Data segment 1 length. */
1178 uint32_t dseg_2_address; /* Data segment 2 address. */
1179 uint32_t dseg_2_length; /* Data segment 2 length. */
1180 } cmd_entry_t;
1181
1182 /*
1183 * ISP queue - 64-Bit addressing, command entry structure definition.
1184 */
1185 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1186 typedef struct {
1187 uint8_t entry_type; /* Entry type. */
1188 uint8_t entry_count; /* Entry count. */
1189 uint8_t sys_define; /* System defined. */
1190 uint8_t entry_status; /* Entry Status. */
1191 uint32_t handle; /* System handle. */
1192 target_id_t target; /* SCSI ID */
1193 uint16_t lun; /* SCSI LUN */
1194 uint16_t control_flags; /* Control flags. */
1195 uint16_t reserved_1;
1196 uint16_t timeout; /* Command timeout. */
1197 uint16_t dseg_count; /* Data segment count. */
1198 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1199 uint32_t byte_count; /* Total byte count. */
1200 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1201 uint32_t dseg_0_length; /* Data segment 0 length. */
1202 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1203 uint32_t dseg_1_length; /* Data segment 1 length. */
1204 } cmd_a64_entry_t, request_t;
1205
1206 /*
1207 * ISP queue - continuation entry structure definition.
1208 */
1209 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1210 typedef struct {
1211 uint8_t entry_type; /* Entry type. */
1212 uint8_t entry_count; /* Entry count. */
1213 uint8_t sys_define; /* System defined. */
1214 uint8_t entry_status; /* Entry Status. */
1215 uint32_t reserved;
1216 uint32_t dseg_0_address; /* Data segment 0 address. */
1217 uint32_t dseg_0_length; /* Data segment 0 length. */
1218 uint32_t dseg_1_address; /* Data segment 1 address. */
1219 uint32_t dseg_1_length; /* Data segment 1 length. */
1220 uint32_t dseg_2_address; /* Data segment 2 address. */
1221 uint32_t dseg_2_length; /* Data segment 2 length. */
1222 uint32_t dseg_3_address; /* Data segment 3 address. */
1223 uint32_t dseg_3_length; /* Data segment 3 length. */
1224 uint32_t dseg_4_address; /* Data segment 4 address. */
1225 uint32_t dseg_4_length; /* Data segment 4 length. */
1226 uint32_t dseg_5_address; /* Data segment 5 address. */
1227 uint32_t dseg_5_length; /* Data segment 5 length. */
1228 uint32_t dseg_6_address; /* Data segment 6 address. */
1229 uint32_t dseg_6_length; /* Data segment 6 length. */
1230 } cont_entry_t;
1231
1232 /*
1233 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1234 */
1235 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1236 typedef struct {
1237 uint8_t entry_type; /* Entry type. */
1238 uint8_t entry_count; /* Entry count. */
1239 uint8_t sys_define; /* System defined. */
1240 uint8_t entry_status; /* Entry Status. */
1241 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1242 uint32_t dseg_0_length; /* Data segment 0 length. */
1243 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1244 uint32_t dseg_1_length; /* Data segment 1 length. */
1245 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1246 uint32_t dseg_2_length; /* Data segment 2 length. */
1247 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1248 uint32_t dseg_3_length; /* Data segment 3 length. */
1249 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1250 uint32_t dseg_4_length; /* Data segment 4 length. */
1251 } cont_a64_entry_t;
1252
1253 /*
1254 * ISP queue - status entry structure definition.
1255 */
1256 #define STATUS_TYPE 0x03 /* Status entry. */
1257 typedef struct {
1258 uint8_t entry_type; /* Entry type. */
1259 uint8_t entry_count; /* Entry count. */
1260 uint8_t sys_define; /* System defined. */
1261 uint8_t entry_status; /* Entry Status. */
1262 uint32_t handle; /* System handle. */
1263 uint16_t scsi_status; /* SCSI status. */
1264 uint16_t comp_status; /* Completion status. */
1265 uint16_t state_flags; /* State flags. */
1266 uint16_t status_flags; /* Status flags. */
1267 uint16_t rsp_info_len; /* Response Info Length. */
1268 uint16_t req_sense_length; /* Request sense data length. */
1269 uint32_t residual_length; /* Residual transfer length. */
1270 uint8_t rsp_info[8]; /* FCP response information. */
1271 uint8_t req_sense_data[32]; /* Request sense data. */
1272 } sts_entry_t;
1273
1274 /*
1275 * Status entry entry status
1276 */
1277 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1278 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1279 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1280 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1281 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1282 #define RF_BUSY BIT_1 /* Busy */
1283 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1284 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1285 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1286 RF_INV_E_TYPE)
1287
1288 /*
1289 * Status entry SCSI status bit definitions.
1290 */
1291 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1292 #define SS_RESIDUAL_UNDER BIT_11
1293 #define SS_RESIDUAL_OVER BIT_10
1294 #define SS_SENSE_LEN_VALID BIT_9
1295 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1296
1297 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1298 #define SS_BUSY_CONDITION BIT_3
1299 #define SS_CONDITION_MET BIT_2
1300 #define SS_CHECK_CONDITION BIT_1
1301
1302 /*
1303 * Status entry completion status
1304 */
1305 #define CS_COMPLETE 0x0 /* No errors */
1306 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1307 #define CS_DMA 0x2 /* A DMA direction error. */
1308 #define CS_TRANSPORT 0x3 /* Transport error. */
1309 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1310 #define CS_ABORTED 0x5 /* System aborted command. */
1311 #define CS_TIMEOUT 0x6 /* Timeout error. */
1312 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1313
1314 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1315 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1316 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1317 /* (selection timeout) */
1318 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1319 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1320 #define CS_PORT_BUSY 0x2B /* Port Busy */
1321 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1322 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1323 #define CS_UNKNOWN 0x81 /* Driver defined */
1324 #define CS_RETRY 0x82 /* Driver defined */
1325 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1326
1327 /*
1328 * Status entry status flags
1329 */
1330 #define SF_ABTS_TERMINATED BIT_10
1331 #define SF_LOGOUT_SENT BIT_13
1332
1333 /*
1334 * ISP queue - status continuation entry structure definition.
1335 */
1336 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1337 typedef struct {
1338 uint8_t entry_type; /* Entry type. */
1339 uint8_t entry_count; /* Entry count. */
1340 uint8_t sys_define; /* System defined. */
1341 uint8_t entry_status; /* Entry Status. */
1342 uint8_t data[60]; /* data */
1343 } sts_cont_entry_t;
1344
1345 /*
1346 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1347 * structure definition.
1348 */
1349 #define STATUS_TYPE_21 0x21 /* Status entry. */
1350 typedef struct {
1351 uint8_t entry_type; /* Entry type. */
1352 uint8_t entry_count; /* Entry count. */
1353 uint8_t handle_count; /* Handle count. */
1354 uint8_t entry_status; /* Entry Status. */
1355 uint32_t handle[15]; /* System handles. */
1356 } sts21_entry_t;
1357
1358 /*
1359 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1360 * structure definition.
1361 */
1362 #define STATUS_TYPE_22 0x22 /* Status entry. */
1363 typedef struct {
1364 uint8_t entry_type; /* Entry type. */
1365 uint8_t entry_count; /* Entry count. */
1366 uint8_t handle_count; /* Handle count. */
1367 uint8_t entry_status; /* Entry Status. */
1368 uint16_t handle[30]; /* System handles. */
1369 } sts22_entry_t;
1370
1371 /*
1372 * ISP queue - marker entry structure definition.
1373 */
1374 #define MARKER_TYPE 0x04 /* Marker entry. */
1375 typedef struct {
1376 uint8_t entry_type; /* Entry type. */
1377 uint8_t entry_count; /* Entry count. */
1378 uint8_t handle_count; /* Handle count. */
1379 uint8_t entry_status; /* Entry Status. */
1380 uint32_t sys_define_2; /* System defined. */
1381 target_id_t target; /* SCSI ID */
1382 uint8_t modifier; /* Modifier (7-0). */
1383 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1384 #define MK_SYNC_ID 1 /* Synchronize ID */
1385 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1386 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1387 /* clear port changed, */
1388 /* use sequence number. */
1389 uint8_t reserved_1;
1390 uint16_t sequence_number; /* Sequence number of event */
1391 uint16_t lun; /* SCSI LUN */
1392 uint8_t reserved_2[48];
1393 } mrk_entry_t;
1394
1395 /*
1396 * ISP queue - Management Server entry structure definition.
1397 */
1398 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1399 typedef struct {
1400 uint8_t entry_type; /* Entry type. */
1401 uint8_t entry_count; /* Entry count. */
1402 uint8_t handle_count; /* Handle count. */
1403 uint8_t entry_status; /* Entry Status. */
1404 uint32_t handle1; /* System handle. */
1405 target_id_t loop_id;
1406 uint16_t status;
1407 uint16_t control_flags; /* Control flags. */
1408 uint16_t reserved2;
1409 uint16_t timeout;
1410 uint16_t cmd_dsd_count;
1411 uint16_t total_dsd_count;
1412 uint8_t type;
1413 uint8_t r_ctl;
1414 uint16_t rx_id;
1415 uint16_t reserved3;
1416 uint32_t handle2;
1417 uint32_t rsp_bytecount;
1418 uint32_t req_bytecount;
1419 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1420 uint32_t dseg_req_length; /* Data segment 0 length. */
1421 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1422 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1423 } ms_iocb_entry_t;
1424
1425
1426 /*
1427 * ISP queue - Mailbox Command entry structure definition.
1428 */
1429 #define MBX_IOCB_TYPE 0x39
1430 struct mbx_entry {
1431 uint8_t entry_type;
1432 uint8_t entry_count;
1433 uint8_t sys_define1;
1434 /* Use sys_define1 for source type */
1435 #define SOURCE_SCSI 0x00
1436 #define SOURCE_IP 0x01
1437 #define SOURCE_VI 0x02
1438 #define SOURCE_SCTP 0x03
1439 #define SOURCE_MP 0x04
1440 #define SOURCE_MPIOCTL 0x05
1441 #define SOURCE_ASYNC_IOCB 0x07
1442
1443 uint8_t entry_status;
1444
1445 uint32_t handle;
1446 target_id_t loop_id;
1447
1448 uint16_t status;
1449 uint16_t state_flags;
1450 uint16_t status_flags;
1451
1452 uint32_t sys_define2[2];
1453
1454 uint16_t mb0;
1455 uint16_t mb1;
1456 uint16_t mb2;
1457 uint16_t mb3;
1458 uint16_t mb6;
1459 uint16_t mb7;
1460 uint16_t mb9;
1461 uint16_t mb10;
1462 uint32_t reserved_2[2];
1463 uint8_t node_name[WWN_SIZE];
1464 uint8_t port_name[WWN_SIZE];
1465 };
1466
1467 /*
1468 * ISP request and response queue entry sizes
1469 */
1470 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1471 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1472
1473
1474 /*
1475 * 24 bit port ID type definition.
1476 */
1477 typedef union {
1478 uint32_t b24 : 24;
1479
1480 struct {
1481 #ifdef __BIG_ENDIAN
1482 uint8_t domain;
1483 uint8_t area;
1484 uint8_t al_pa;
1485 #elif __LITTLE_ENDIAN
1486 uint8_t al_pa;
1487 uint8_t area;
1488 uint8_t domain;
1489 #else
1490 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1491 #endif
1492 uint8_t rsvd_1;
1493 } b;
1494 } port_id_t;
1495 #define INVALID_PORT_ID 0xFFFFFF
1496
1497 /*
1498 * Switch info gathering structure.
1499 */
1500 typedef struct {
1501 port_id_t d_id;
1502 uint8_t node_name[WWN_SIZE];
1503 uint8_t port_name[WWN_SIZE];
1504 uint8_t fabric_port_name[WWN_SIZE];
1505 uint16_t fp_speed;
1506 } sw_info_t;
1507
1508 /*
1509 * Fibre channel port type.
1510 */
1511 typedef enum {
1512 FCT_UNKNOWN,
1513 FCT_RSCN,
1514 FCT_SWITCH,
1515 FCT_BROADCAST,
1516 FCT_INITIATOR,
1517 FCT_TARGET
1518 } fc_port_type_t;
1519
1520 /*
1521 * Fibre channel port structure.
1522 */
1523 typedef struct fc_port {
1524 struct list_head list;
1525 struct scsi_qla_host *vha;
1526
1527 uint8_t node_name[WWN_SIZE];
1528 uint8_t port_name[WWN_SIZE];
1529 port_id_t d_id;
1530 uint16_t loop_id;
1531 uint16_t old_loop_id;
1532
1533 uint8_t fabric_port_name[WWN_SIZE];
1534 uint16_t fp_speed;
1535
1536 fc_port_type_t port_type;
1537
1538 atomic_t state;
1539 uint32_t flags;
1540
1541 int port_login_retry_count;
1542 int login_retry;
1543 atomic_t port_down_timer;
1544
1545 struct fc_rport *rport, *drport;
1546 u32 supported_classes;
1547
1548 unsigned long last_queue_full;
1549 unsigned long last_ramp_up;
1550
1551 uint16_t vp_idx;
1552 } fc_port_t;
1553
1554 /*
1555 * Fibre channel port/lun states.
1556 */
1557 #define FCS_UNCONFIGURED 1
1558 #define FCS_DEVICE_DEAD 2
1559 #define FCS_DEVICE_LOST 3
1560 #define FCS_ONLINE 4
1561
1562 /*
1563 * FC port flags.
1564 */
1565 #define FCF_FABRIC_DEVICE BIT_0
1566 #define FCF_LOGIN_NEEDED BIT_1
1567 #define FCF_TAPE_PRESENT BIT_2
1568
1569 /* No loop ID flag. */
1570 #define FC_NO_LOOP_ID 0x1000
1571
1572 /*
1573 * FC-CT interface
1574 *
1575 * NOTE: All structures are big-endian in form.
1576 */
1577
1578 #define CT_REJECT_RESPONSE 0x8001
1579 #define CT_ACCEPT_RESPONSE 0x8002
1580 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1581 #define CT_REASON_CANNOT_PERFORM 0x09
1582 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1583 #define CT_EXPL_ALREADY_REGISTERED 0x10
1584
1585 #define NS_N_PORT_TYPE 0x01
1586 #define NS_NL_PORT_TYPE 0x02
1587 #define NS_NX_PORT_TYPE 0x7F
1588
1589 #define GA_NXT_CMD 0x100
1590 #define GA_NXT_REQ_SIZE (16 + 4)
1591 #define GA_NXT_RSP_SIZE (16 + 620)
1592
1593 #define GID_PT_CMD 0x1A1
1594 #define GID_PT_REQ_SIZE (16 + 4)
1595 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1596
1597 #define GPN_ID_CMD 0x112
1598 #define GPN_ID_REQ_SIZE (16 + 4)
1599 #define GPN_ID_RSP_SIZE (16 + 8)
1600
1601 #define GNN_ID_CMD 0x113
1602 #define GNN_ID_REQ_SIZE (16 + 4)
1603 #define GNN_ID_RSP_SIZE (16 + 8)
1604
1605 #define GFT_ID_CMD 0x117
1606 #define GFT_ID_REQ_SIZE (16 + 4)
1607 #define GFT_ID_RSP_SIZE (16 + 32)
1608
1609 #define RFT_ID_CMD 0x217
1610 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1611 #define RFT_ID_RSP_SIZE 16
1612
1613 #define RFF_ID_CMD 0x21F
1614 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1615 #define RFF_ID_RSP_SIZE 16
1616
1617 #define RNN_ID_CMD 0x213
1618 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1619 #define RNN_ID_RSP_SIZE 16
1620
1621 #define RSNN_NN_CMD 0x239
1622 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1623 #define RSNN_NN_RSP_SIZE 16
1624
1625 #define GFPN_ID_CMD 0x11C
1626 #define GFPN_ID_REQ_SIZE (16 + 4)
1627 #define GFPN_ID_RSP_SIZE (16 + 8)
1628
1629 #define GPSC_CMD 0x127
1630 #define GPSC_REQ_SIZE (16 + 8)
1631 #define GPSC_RSP_SIZE (16 + 2 + 2)
1632
1633
1634 /*
1635 * HBA attribute types.
1636 */
1637 #define FDMI_HBA_ATTR_COUNT 9
1638 #define FDMI_HBA_NODE_NAME 1
1639 #define FDMI_HBA_MANUFACTURER 2
1640 #define FDMI_HBA_SERIAL_NUMBER 3
1641 #define FDMI_HBA_MODEL 4
1642 #define FDMI_HBA_MODEL_DESCRIPTION 5
1643 #define FDMI_HBA_HARDWARE_VERSION 6
1644 #define FDMI_HBA_DRIVER_VERSION 7
1645 #define FDMI_HBA_OPTION_ROM_VERSION 8
1646 #define FDMI_HBA_FIRMWARE_VERSION 9
1647 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1648 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1649
1650 struct ct_fdmi_hba_attr {
1651 uint16_t type;
1652 uint16_t len;
1653 union {
1654 uint8_t node_name[WWN_SIZE];
1655 uint8_t manufacturer[32];
1656 uint8_t serial_num[8];
1657 uint8_t model[16];
1658 uint8_t model_desc[80];
1659 uint8_t hw_version[16];
1660 uint8_t driver_version[32];
1661 uint8_t orom_version[16];
1662 uint8_t fw_version[16];
1663 uint8_t os_version[128];
1664 uint8_t max_ct_len[4];
1665 } a;
1666 };
1667
1668 struct ct_fdmi_hba_attributes {
1669 uint32_t count;
1670 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1671 };
1672
1673 /*
1674 * Port attribute types.
1675 */
1676 #define FDMI_PORT_ATTR_COUNT 6
1677 #define FDMI_PORT_FC4_TYPES 1
1678 #define FDMI_PORT_SUPPORT_SPEED 2
1679 #define FDMI_PORT_CURRENT_SPEED 3
1680 #define FDMI_PORT_MAX_FRAME_SIZE 4
1681 #define FDMI_PORT_OS_DEVICE_NAME 5
1682 #define FDMI_PORT_HOST_NAME 6
1683
1684 #define FDMI_PORT_SPEED_1GB 0x1
1685 #define FDMI_PORT_SPEED_2GB 0x2
1686 #define FDMI_PORT_SPEED_10GB 0x4
1687 #define FDMI_PORT_SPEED_4GB 0x8
1688 #define FDMI_PORT_SPEED_8GB 0x10
1689 #define FDMI_PORT_SPEED_16GB 0x20
1690 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1691
1692 struct ct_fdmi_port_attr {
1693 uint16_t type;
1694 uint16_t len;
1695 union {
1696 uint8_t fc4_types[32];
1697 uint32_t sup_speed;
1698 uint32_t cur_speed;
1699 uint32_t max_frame_size;
1700 uint8_t os_dev_name[32];
1701 uint8_t host_name[32];
1702 } a;
1703 };
1704
1705 /*
1706 * Port Attribute Block.
1707 */
1708 struct ct_fdmi_port_attributes {
1709 uint32_t count;
1710 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1711 };
1712
1713 /* FDMI definitions. */
1714 #define GRHL_CMD 0x100
1715 #define GHAT_CMD 0x101
1716 #define GRPL_CMD 0x102
1717 #define GPAT_CMD 0x110
1718
1719 #define RHBA_CMD 0x200
1720 #define RHBA_RSP_SIZE 16
1721
1722 #define RHAT_CMD 0x201
1723 #define RPRT_CMD 0x210
1724
1725 #define RPA_CMD 0x211
1726 #define RPA_RSP_SIZE 16
1727
1728 #define DHBA_CMD 0x300
1729 #define DHBA_REQ_SIZE (16 + 8)
1730 #define DHBA_RSP_SIZE 16
1731
1732 #define DHAT_CMD 0x301
1733 #define DPRT_CMD 0x310
1734 #define DPA_CMD 0x311
1735
1736 /* CT command header -- request/response common fields */
1737 struct ct_cmd_hdr {
1738 uint8_t revision;
1739 uint8_t in_id[3];
1740 uint8_t gs_type;
1741 uint8_t gs_subtype;
1742 uint8_t options;
1743 uint8_t reserved;
1744 };
1745
1746 /* CT command request */
1747 struct ct_sns_req {
1748 struct ct_cmd_hdr header;
1749 uint16_t command;
1750 uint16_t max_rsp_size;
1751 uint8_t fragment_id;
1752 uint8_t reserved[3];
1753
1754 union {
1755 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1756 struct {
1757 uint8_t reserved;
1758 uint8_t port_id[3];
1759 } port_id;
1760
1761 struct {
1762 uint8_t port_type;
1763 uint8_t domain;
1764 uint8_t area;
1765 uint8_t reserved;
1766 } gid_pt;
1767
1768 struct {
1769 uint8_t reserved;
1770 uint8_t port_id[3];
1771 uint8_t fc4_types[32];
1772 } rft_id;
1773
1774 struct {
1775 uint8_t reserved;
1776 uint8_t port_id[3];
1777 uint16_t reserved2;
1778 uint8_t fc4_feature;
1779 uint8_t fc4_type;
1780 } rff_id;
1781
1782 struct {
1783 uint8_t reserved;
1784 uint8_t port_id[3];
1785 uint8_t node_name[8];
1786 } rnn_id;
1787
1788 struct {
1789 uint8_t node_name[8];
1790 uint8_t name_len;
1791 uint8_t sym_node_name[255];
1792 } rsnn_nn;
1793
1794 struct {
1795 uint8_t hba_indentifier[8];
1796 } ghat;
1797
1798 struct {
1799 uint8_t hba_identifier[8];
1800 uint32_t entry_count;
1801 uint8_t port_name[8];
1802 struct ct_fdmi_hba_attributes attrs;
1803 } rhba;
1804
1805 struct {
1806 uint8_t hba_identifier[8];
1807 struct ct_fdmi_hba_attributes attrs;
1808 } rhat;
1809
1810 struct {
1811 uint8_t port_name[8];
1812 struct ct_fdmi_port_attributes attrs;
1813 } rpa;
1814
1815 struct {
1816 uint8_t port_name[8];
1817 } dhba;
1818
1819 struct {
1820 uint8_t port_name[8];
1821 } dhat;
1822
1823 struct {
1824 uint8_t port_name[8];
1825 } dprt;
1826
1827 struct {
1828 uint8_t port_name[8];
1829 } dpa;
1830
1831 struct {
1832 uint8_t port_name[8];
1833 } gpsc;
1834 } req;
1835 };
1836
1837 /* CT command response header */
1838 struct ct_rsp_hdr {
1839 struct ct_cmd_hdr header;
1840 uint16_t response;
1841 uint16_t residual;
1842 uint8_t fragment_id;
1843 uint8_t reason_code;
1844 uint8_t explanation_code;
1845 uint8_t vendor_unique;
1846 };
1847
1848 struct ct_sns_gid_pt_data {
1849 uint8_t control_byte;
1850 uint8_t port_id[3];
1851 };
1852
1853 struct ct_sns_rsp {
1854 struct ct_rsp_hdr header;
1855
1856 union {
1857 struct {
1858 uint8_t port_type;
1859 uint8_t port_id[3];
1860 uint8_t port_name[8];
1861 uint8_t sym_port_name_len;
1862 uint8_t sym_port_name[255];
1863 uint8_t node_name[8];
1864 uint8_t sym_node_name_len;
1865 uint8_t sym_node_name[255];
1866 uint8_t init_proc_assoc[8];
1867 uint8_t node_ip_addr[16];
1868 uint8_t class_of_service[4];
1869 uint8_t fc4_types[32];
1870 uint8_t ip_address[16];
1871 uint8_t fabric_port_name[8];
1872 uint8_t reserved;
1873 uint8_t hard_address[3];
1874 } ga_nxt;
1875
1876 struct {
1877 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1878 } gid_pt;
1879
1880 struct {
1881 uint8_t port_name[8];
1882 } gpn_id;
1883
1884 struct {
1885 uint8_t node_name[8];
1886 } gnn_id;
1887
1888 struct {
1889 uint8_t fc4_types[32];
1890 } gft_id;
1891
1892 struct {
1893 uint32_t entry_count;
1894 uint8_t port_name[8];
1895 struct ct_fdmi_hba_attributes attrs;
1896 } ghat;
1897
1898 struct {
1899 uint8_t port_name[8];
1900 } gfpn_id;
1901
1902 struct {
1903 uint16_t speeds;
1904 uint16_t speed;
1905 } gpsc;
1906 } rsp;
1907 };
1908
1909 struct ct_sns_pkt {
1910 union {
1911 struct ct_sns_req req;
1912 struct ct_sns_rsp rsp;
1913 } p;
1914 };
1915
1916 /*
1917 * SNS command structures -- for 2200 compatability.
1918 */
1919 #define RFT_ID_SNS_SCMD_LEN 22
1920 #define RFT_ID_SNS_CMD_SIZE 60
1921 #define RFT_ID_SNS_DATA_SIZE 16
1922
1923 #define RNN_ID_SNS_SCMD_LEN 10
1924 #define RNN_ID_SNS_CMD_SIZE 36
1925 #define RNN_ID_SNS_DATA_SIZE 16
1926
1927 #define GA_NXT_SNS_SCMD_LEN 6
1928 #define GA_NXT_SNS_CMD_SIZE 28
1929 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1930
1931 #define GID_PT_SNS_SCMD_LEN 6
1932 #define GID_PT_SNS_CMD_SIZE 28
1933 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1934
1935 #define GPN_ID_SNS_SCMD_LEN 6
1936 #define GPN_ID_SNS_CMD_SIZE 28
1937 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1938
1939 #define GNN_ID_SNS_SCMD_LEN 6
1940 #define GNN_ID_SNS_CMD_SIZE 28
1941 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1942
1943 struct sns_cmd_pkt {
1944 union {
1945 struct {
1946 uint16_t buffer_length;
1947 uint16_t reserved_1;
1948 uint32_t buffer_address[2];
1949 uint16_t subcommand_length;
1950 uint16_t reserved_2;
1951 uint16_t subcommand;
1952 uint16_t size;
1953 uint32_t reserved_3;
1954 uint8_t param[36];
1955 } cmd;
1956
1957 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1958 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1959 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1960 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1961 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1962 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1963 } p;
1964 };
1965
1966 struct fw_blob {
1967 char *name;
1968 uint32_t segs[4];
1969 const struct firmware *fw;
1970 };
1971
1972 /* Return data from MBC_GET_ID_LIST call. */
1973 struct gid_list_info {
1974 uint8_t al_pa;
1975 uint8_t area;
1976 uint8_t domain;
1977 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
1978 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
1979 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1980 };
1981 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
1982
1983 /* NPIV */
1984 typedef struct vport_info {
1985 uint8_t port_name[WWN_SIZE];
1986 uint8_t node_name[WWN_SIZE];
1987 int vp_id;
1988 uint16_t loop_id;
1989 unsigned long host_no;
1990 uint8_t port_id[3];
1991 int loop_state;
1992 } vport_info_t;
1993
1994 typedef struct vport_params {
1995 uint8_t port_name[WWN_SIZE];
1996 uint8_t node_name[WWN_SIZE];
1997 uint32_t options;
1998 #define VP_OPTS_RETRY_ENABLE BIT_0
1999 #define VP_OPTS_VP_DISABLE BIT_1
2000 } vport_params_t;
2001
2002 /* NPIV - return codes of VP create and modify */
2003 #define VP_RET_CODE_OK 0
2004 #define VP_RET_CODE_FATAL 1
2005 #define VP_RET_CODE_WRONG_ID 2
2006 #define VP_RET_CODE_WWPN 3
2007 #define VP_RET_CODE_RESOURCES 4
2008 #define VP_RET_CODE_NO_MEM 5
2009 #define VP_RET_CODE_NOT_FOUND 6
2010
2011 struct qla_hw_data;
2012
2013 /*
2014 * ISP operations
2015 */
2016 struct isp_operations {
2017
2018 int (*pci_config) (struct scsi_qla_host *);
2019 void (*reset_chip) (struct scsi_qla_host *);
2020 int (*chip_diag) (struct scsi_qla_host *);
2021 void (*config_rings) (struct scsi_qla_host *);
2022 void (*reset_adapter) (struct scsi_qla_host *);
2023 int (*nvram_config) (struct scsi_qla_host *);
2024 void (*update_fw_options) (struct scsi_qla_host *);
2025 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2026
2027 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2028 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2029
2030 irq_handler_t intr_handler;
2031 void (*enable_intrs) (struct qla_hw_data *);
2032 void (*disable_intrs) (struct qla_hw_data *);
2033
2034 int (*abort_command) (struct scsi_qla_host *, srb_t *,
2035 struct req_que *);
2036 int (*target_reset) (struct fc_port *, unsigned int);
2037 int (*lun_reset) (struct fc_port *, unsigned int);
2038 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2039 uint8_t, uint8_t, uint16_t *, uint8_t);
2040 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2041 uint8_t, uint8_t);
2042
2043 uint16_t (*calc_req_entries) (uint16_t);
2044 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2045 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2046 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2047 uint32_t);
2048
2049 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2050 uint32_t, uint32_t);
2051 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2052 uint32_t);
2053
2054 void (*fw_dump) (struct scsi_qla_host *, int);
2055
2056 int (*beacon_on) (struct scsi_qla_host *);
2057 int (*beacon_off) (struct scsi_qla_host *);
2058 void (*beacon_blink) (struct scsi_qla_host *);
2059
2060 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2061 uint32_t, uint32_t);
2062 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2063 uint32_t);
2064
2065 int (*get_flash_version) (struct scsi_qla_host *, void *);
2066 int (*start_scsi) (srb_t *);
2067 };
2068
2069 /* MSI-X Support *************************************************************/
2070
2071 #define QLA_MSIX_CHIP_REV_24XX 3
2072 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2073 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2074
2075 #define QLA_MSIX_DEFAULT 0x00
2076 #define QLA_MSIX_RSP_Q 0x01
2077
2078 #define QLA_MIDX_DEFAULT 0
2079 #define QLA_MIDX_RSP_Q 1
2080 #define QLA_PCI_MSIX_CONTROL 0xa2
2081
2082 struct scsi_qla_host;
2083 struct rsp_que;
2084
2085 struct qla_msix_entry {
2086 int have_irq;
2087 uint32_t vector;
2088 uint16_t entry;
2089 struct rsp_que *rsp;
2090 };
2091
2092 #define WATCH_INTERVAL 1 /* number of seconds */
2093
2094 /* Work events. */
2095 enum qla_work_type {
2096 QLA_EVT_AEN,
2097 QLA_EVT_IDC_ACK,
2098 };
2099
2100
2101 struct qla_work_evt {
2102 struct list_head list;
2103 enum qla_work_type type;
2104 u32 flags;
2105 #define QLA_EVT_FLAG_FREE 0x1
2106
2107 union {
2108 struct {
2109 enum fc_host_event_code code;
2110 u32 data;
2111 } aen;
2112 struct {
2113 #define QLA_IDC_ACK_REGS 7
2114 uint16_t mb[QLA_IDC_ACK_REGS];
2115 } idc_ack;
2116 } u;
2117 };
2118
2119 struct qla_chip_state_84xx {
2120 struct list_head list;
2121 struct kref kref;
2122
2123 void *bus;
2124 spinlock_t access_lock;
2125 struct mutex fw_update_mutex;
2126 uint32_t fw_update;
2127 uint32_t op_fw_version;
2128 uint32_t op_fw_size;
2129 uint32_t op_fw_seq_size;
2130 uint32_t diag_fw_version;
2131 uint32_t gold_fw_version;
2132 };
2133
2134 struct qla_statistics {
2135 uint32_t total_isp_aborts;
2136 uint64_t input_bytes;
2137 uint64_t output_bytes;
2138 };
2139
2140 /* Multi queue support */
2141 #define MBC_INITIALIZE_MULTIQ 0x1f
2142 #define QLA_QUE_PAGE 0X1000
2143 #define QLA_MQ_SIZE 32
2144 #define QLA_MAX_HOST_QUES 16
2145 #define QLA_MAX_QUEUES 256
2146 #define ISP_QUE_REG(ha, id) \
2147 ((ha->mqenable) ? \
2148 ((void *)(ha->mqiobase) +\
2149 (QLA_QUE_PAGE * id)) :\
2150 ((void *)(ha->iobase)))
2151 #define QLA_REQ_QUE_ID(tag) \
2152 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2153 #define QLA_DEFAULT_QUE_QOS 5
2154 #define QLA_PRECONFIG_VPORTS 32
2155 #define QLA_MAX_VPORTS_QLA24XX 128
2156 #define QLA_MAX_VPORTS_QLA25XX 256
2157 /* Response queue data structure */
2158 struct rsp_que {
2159 dma_addr_t dma;
2160 response_t *ring;
2161 response_t *ring_ptr;
2162 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2163 uint32_t __iomem *rsp_q_out;
2164 uint16_t ring_index;
2165 uint16_t out_ptr;
2166 uint16_t length;
2167 uint16_t options;
2168 uint16_t rid;
2169 uint16_t id;
2170 uint16_t vp_idx;
2171 struct qla_hw_data *hw;
2172 struct qla_msix_entry *msix;
2173 struct req_que *req;
2174 };
2175
2176 /* Request queue data structure */
2177 struct req_que {
2178 dma_addr_t dma;
2179 request_t *ring;
2180 request_t *ring_ptr;
2181 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2182 uint32_t __iomem *req_q_out;
2183 uint16_t ring_index;
2184 uint16_t in_ptr;
2185 uint16_t cnt;
2186 uint16_t length;
2187 uint16_t options;
2188 uint16_t rid;
2189 uint16_t id;
2190 uint16_t qos;
2191 uint16_t vp_idx;
2192 struct rsp_que *rsp;
2193 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2194 uint32_t current_outstanding_cmd;
2195 int max_q_depth;
2196 };
2197
2198 /*
2199 * Qlogic host adapter specific data structure.
2200 */
2201 struct qla_hw_data {
2202 struct pci_dev *pdev;
2203 /* SRB cache. */
2204 #define SRB_MIN_REQ 128
2205 mempool_t *srb_mempool;
2206
2207 volatile struct {
2208 uint32_t mbox_int :1;
2209 uint32_t mbox_busy :1;
2210
2211 uint32_t disable_risc_code_load :1;
2212 uint32_t enable_64bit_addressing :1;
2213 uint32_t enable_lip_reset :1;
2214 uint32_t enable_target_reset :1;
2215 uint32_t enable_lip_full_login :1;
2216 uint32_t enable_led_scheme :1;
2217 uint32_t inta_enabled :1;
2218 uint32_t msi_enabled :1;
2219 uint32_t msix_enabled :1;
2220 uint32_t disable_serdes :1;
2221 uint32_t gpsc_supported :1;
2222 uint32_t npiv_supported :1;
2223 uint32_t fce_enabled :1;
2224 uint32_t fac_supported :1;
2225 uint32_t chip_reset_done :1;
2226 } flags;
2227
2228 /* This spinlock is used to protect "io transactions", you must
2229 * acquire it before doing any IO to the card, eg with RD_REG*() and
2230 * WRT_REG*() for the duration of your entire commandtransaction.
2231 *
2232 * This spinlock is of lower priority than the io request lock.
2233 */
2234
2235 spinlock_t hardware_lock ____cacheline_aligned;
2236 int bars;
2237 int mem_only;
2238 device_reg_t __iomem *iobase; /* Base I/O address */
2239 resource_size_t pio_address;
2240
2241 #define MIN_IOBASE_LEN 0x100
2242 /* Multi queue data structs */
2243 device_reg_t __iomem *mqiobase;
2244 uint16_t msix_count;
2245 uint8_t mqenable;
2246 struct req_que **req_q_map;
2247 struct rsp_que **rsp_q_map;
2248 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2249 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2250 uint16_t max_queues;
2251 struct qla_npiv_entry *npiv_info;
2252 uint16_t nvram_npiv_size;
2253
2254 uint16_t switch_cap;
2255 #define FLOGI_SEQ_DEL BIT_8
2256 #define FLOGI_MID_SUPPORT BIT_10
2257 #define FLOGI_VSAN_SUPPORT BIT_12
2258 #define FLOGI_SP_SUPPORT BIT_13
2259 /* Timeout timers. */
2260 uint8_t loop_down_abort_time; /* port down timer */
2261 atomic_t loop_down_timer; /* loop down timer */
2262 uint8_t link_down_timeout; /* link down timeout */
2263 uint16_t max_loop_id;
2264
2265 uint16_t fb_rev;
2266 uint16_t min_external_loopid; /* First external loop Id */
2267
2268 #define PORT_SPEED_UNKNOWN 0xFFFF
2269 #define PORT_SPEED_1GB 0x00
2270 #define PORT_SPEED_2GB 0x01
2271 #define PORT_SPEED_4GB 0x03
2272 #define PORT_SPEED_8GB 0x04
2273 #define PORT_SPEED_10GB 0x13
2274 uint16_t link_data_rate; /* F/W operating speed */
2275
2276 uint8_t current_topology;
2277 uint8_t prev_topology;
2278 #define ISP_CFG_NL 1
2279 #define ISP_CFG_N 2
2280 #define ISP_CFG_FL 4
2281 #define ISP_CFG_F 8
2282
2283 uint8_t operating_mode; /* F/W operating mode */
2284 #define LOOP 0
2285 #define P2P 1
2286 #define LOOP_P2P 2
2287 #define P2P_LOOP 3
2288 uint8_t interrupts_on;
2289 uint32_t isp_abort_cnt;
2290
2291 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2292 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2293 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2294 uint32_t device_type;
2295 #define DT_ISP2100 BIT_0
2296 #define DT_ISP2200 BIT_1
2297 #define DT_ISP2300 BIT_2
2298 #define DT_ISP2312 BIT_3
2299 #define DT_ISP2322 BIT_4
2300 #define DT_ISP6312 BIT_5
2301 #define DT_ISP6322 BIT_6
2302 #define DT_ISP2422 BIT_7
2303 #define DT_ISP2432 BIT_8
2304 #define DT_ISP5422 BIT_9
2305 #define DT_ISP5432 BIT_10
2306 #define DT_ISP2532 BIT_11
2307 #define DT_ISP8432 BIT_12
2308 #define DT_ISP8001 BIT_13
2309 #define DT_ISP_LAST (DT_ISP8001 << 1)
2310
2311 #define DT_IIDMA BIT_26
2312 #define DT_FWI2 BIT_27
2313 #define DT_ZIO_SUPPORTED BIT_28
2314 #define DT_OEM_001 BIT_29
2315 #define DT_ISP2200A BIT_30
2316 #define DT_EXTENDED_IDS BIT_31
2317 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2318 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2319 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2320 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2321 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2322 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2323 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2324 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2325 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2326 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2327 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2328 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2329 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2330 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2331 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2332
2333 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2334 IS_QLA6312(ha) || IS_QLA6322(ha))
2335 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2336 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2337 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2338 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2339 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2340 IS_QLA84XX(ha))
2341 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2342 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2343 IS_QLA25XX(ha) || IS_QLA81XX(ha))
2344 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2345 (ha)->flags.msix_enabled)
2346 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2347
2348 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2349 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2350 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2351 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2352 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2353
2354 /* HBA serial number */
2355 uint8_t serial0;
2356 uint8_t serial1;
2357 uint8_t serial2;
2358
2359 /* NVRAM configuration data */
2360 #define MAX_NVRAM_SIZE 4096
2361 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2362 uint16_t nvram_size;
2363 uint16_t nvram_base;
2364 void *nvram;
2365 uint16_t vpd_size;
2366 uint16_t vpd_base;
2367 void *vpd;
2368
2369 uint16_t loop_reset_delay;
2370 uint8_t retry_count;
2371 uint8_t login_timeout;
2372 uint16_t r_a_tov;
2373 int port_down_retry_count;
2374 uint8_t mbx_count;
2375
2376 uint32_t login_retry_count;
2377 /* SNS command interfaces. */
2378 ms_iocb_entry_t *ms_iocb;
2379 dma_addr_t ms_iocb_dma;
2380 struct ct_sns_pkt *ct_sns;
2381 dma_addr_t ct_sns_dma;
2382 /* SNS command interfaces for 2200. */
2383 struct sns_cmd_pkt *sns_cmd;
2384 dma_addr_t sns_cmd_dma;
2385
2386 #define SFP_DEV_SIZE 256
2387 #define SFP_BLOCK_SIZE 64
2388 void *sfp_data;
2389 dma_addr_t sfp_data_dma;
2390
2391 uint8_t *edc_data;
2392 dma_addr_t edc_data_dma;
2393 uint16_t edc_data_len;
2394
2395 struct task_struct *dpc_thread;
2396 uint8_t dpc_active; /* DPC routine is active */
2397
2398 dma_addr_t gid_list_dma;
2399 struct gid_list_info *gid_list;
2400 int gid_list_info_size;
2401
2402 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2403 #define DMA_POOL_SIZE 256
2404 struct dma_pool *s_dma_pool;
2405
2406 dma_addr_t init_cb_dma;
2407 init_cb_t *init_cb;
2408 int init_cb_size;
2409 dma_addr_t ex_init_cb_dma;
2410 struct ex_init_cb_81xx *ex_init_cb;
2411
2412 /* These are used by mailbox operations. */
2413 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2414
2415 mbx_cmd_t *mcp;
2416 unsigned long mbx_cmd_flags;
2417 #define MBX_INTERRUPT 1
2418 #define MBX_INTR_WAIT 2
2419 #define MBX_UPDATE_FLASH_ACTIVE 3
2420
2421 struct mutex vport_lock; /* Virtual port synchronization */
2422 struct completion mbx_cmd_comp; /* Serialize mbx access */
2423 struct completion mbx_intr_comp; /* Used for completion notification */
2424
2425 /* Basic firmware related information. */
2426 uint16_t fw_major_version;
2427 uint16_t fw_minor_version;
2428 uint16_t fw_subminor_version;
2429 uint16_t fw_attributes;
2430 uint32_t fw_memory_size;
2431 uint32_t fw_transfer_size;
2432 uint32_t fw_srisc_address;
2433 #define RISC_START_ADDRESS_2100 0x1000
2434 #define RISC_START_ADDRESS_2300 0x800
2435 #define RISC_START_ADDRESS_2400 0x100000
2436
2437 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2438 uint8_t fw_seriallink_options[4];
2439 uint16_t fw_seriallink_options24[4];
2440
2441 uint8_t mpi_version[3];
2442 uint32_t mpi_capabilities;
2443 uint8_t phy_version[3];
2444
2445 /* Firmware dump information. */
2446 struct qla2xxx_fw_dump *fw_dump;
2447 uint32_t fw_dump_len;
2448 int fw_dumped;
2449 int fw_dump_reading;
2450 dma_addr_t eft_dma;
2451 void *eft;
2452
2453 uint32_t chain_offset;
2454 struct dentry *dfs_dir;
2455 struct dentry *dfs_fce;
2456 dma_addr_t fce_dma;
2457 void *fce;
2458 uint32_t fce_bufs;
2459 uint16_t fce_mb[8];
2460 uint64_t fce_wr, fce_rd;
2461 struct mutex fce_mutex;
2462
2463 uint32_t pci_attr;
2464 uint16_t chip_revision;
2465
2466 uint16_t product_id[4];
2467
2468 uint8_t model_number[16+1];
2469 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2470 char model_desc[80];
2471 uint8_t adapter_id[16+1];
2472
2473 /* Option ROM information. */
2474 char *optrom_buffer;
2475 uint32_t optrom_size;
2476 int optrom_state;
2477 #define QLA_SWAITING 0
2478 #define QLA_SREADING 1
2479 #define QLA_SWRITING 2
2480 uint32_t optrom_region_start;
2481 uint32_t optrom_region_size;
2482
2483 /* PCI expansion ROM image information. */
2484 #define ROM_CODE_TYPE_BIOS 0
2485 #define ROM_CODE_TYPE_FCODE 1
2486 #define ROM_CODE_TYPE_EFI 3
2487 uint8_t bios_revision[2];
2488 uint8_t efi_revision[2];
2489 uint8_t fcode_revision[16];
2490 uint32_t fw_revision[4];
2491
2492 /* Offsets for flash/nvram access (set to ~0 if not used). */
2493 uint32_t flash_conf_off;
2494 uint32_t flash_data_off;
2495 uint32_t nvram_conf_off;
2496 uint32_t nvram_data_off;
2497
2498 uint32_t fdt_wrt_disable;
2499 uint32_t fdt_erase_cmd;
2500 uint32_t fdt_block_size;
2501 uint32_t fdt_unprotect_sec_cmd;
2502 uint32_t fdt_protect_sec_cmd;
2503
2504 uint32_t flt_region_flt;
2505 uint32_t flt_region_fdt;
2506 uint32_t flt_region_boot;
2507 uint32_t flt_region_fw;
2508 uint32_t flt_region_vpd_nvram;
2509 uint32_t flt_region_npiv_conf;
2510
2511 /* Needed for BEACON */
2512 uint16_t beacon_blink_led;
2513 uint8_t beacon_color_state;
2514 #define QLA_LED_GRN_ON 0x01
2515 #define QLA_LED_YLW_ON 0x02
2516 #define QLA_LED_ABR_ON 0x04
2517 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2518 /* ISP2322: red, green, amber. */
2519 uint16_t zio_mode;
2520 uint16_t zio_timer;
2521 struct fc_host_statistics fc_host_stat;
2522
2523 struct qla_msix_entry *msix_entries;
2524
2525 struct list_head vp_list; /* list of VP */
2526 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2527 sizeof(unsigned long)];
2528 uint16_t num_vhosts; /* number of vports created */
2529 uint16_t num_vsans; /* number of vsan created */
2530 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2531 int cur_vport_count;
2532
2533 struct qla_chip_state_84xx *cs84xx;
2534 struct qla_statistics qla_stats;
2535 struct isp_operations *isp_ops;
2536 };
2537
2538 /*
2539 * Qlogic scsi host structure
2540 */
2541 typedef struct scsi_qla_host {
2542 struct list_head list;
2543 struct list_head vp_fcports; /* list of fcports */
2544 struct list_head work_list;
2545 /* Commonly used flags and state information. */
2546 struct Scsi_Host *host;
2547 unsigned long host_no;
2548 uint8_t host_str[16];
2549
2550 volatile struct {
2551 uint32_t init_done :1;
2552 uint32_t online :1;
2553 uint32_t rscn_queue_overflow :1;
2554 uint32_t reset_active :1;
2555
2556 uint32_t management_server_logged_in :1;
2557 uint32_t process_response_queue :1;
2558 } flags;
2559
2560 atomic_t loop_state;
2561 #define LOOP_TIMEOUT 1
2562 #define LOOP_DOWN 2
2563 #define LOOP_UP 3
2564 #define LOOP_UPDATE 4
2565 #define LOOP_READY 5
2566 #define LOOP_DEAD 6
2567
2568 unsigned long dpc_flags;
2569 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2570 #define RESET_ACTIVE 1
2571 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2572 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2573 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2574 #define LOOP_RESYNC_ACTIVE 5
2575 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2576 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2577 #define RELOGIN_NEEDED 8
2578 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2579 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2580 #define BEACON_BLINK_NEEDED 11
2581 #define REGISTER_FDMI_NEEDED 12
2582 #define FCPORT_UPDATE_NEEDED 13
2583 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2584 #define UNLOADING 15
2585 #define NPIV_CONFIG_NEEDED 16
2586
2587 uint32_t device_flags;
2588 #define SWITCH_FOUND BIT_0
2589 #define DFLG_NO_CABLE BIT_1
2590
2591 srb_t *status_srb; /* Status continuation entry. */
2592
2593 /* ISP configuration data. */
2594 uint16_t loop_id; /* Host adapter loop id */
2595
2596 port_id_t d_id; /* Host adapter port id */
2597 uint8_t marker_needed;
2598 uint16_t mgmt_svr_loop_id;
2599
2600
2601
2602 /* RSCN queue. */
2603 uint32_t rscn_queue[MAX_RSCN_COUNT];
2604 uint8_t rscn_in_ptr;
2605 uint8_t rscn_out_ptr;
2606
2607 /* Timeout timers. */
2608 uint8_t loop_down_abort_time; /* port down timer */
2609 atomic_t loop_down_timer; /* loop down timer */
2610 uint8_t link_down_timeout; /* link down timeout */
2611
2612 uint32_t timer_active;
2613 struct timer_list timer;
2614
2615 uint8_t node_name[WWN_SIZE];
2616 uint8_t port_name[WWN_SIZE];
2617 uint8_t fabric_node_name[WWN_SIZE];
2618 uint32_t vp_abort_cnt;
2619
2620 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2621 uint16_t vp_idx; /* vport ID */
2622
2623 unsigned long vp_flags;
2624 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2625 #define VP_CREATE_NEEDED 1
2626 #define VP_BIND_NEEDED 2
2627 #define VP_DELETE_NEEDED 3
2628 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2629 atomic_t vp_state;
2630 #define VP_OFFLINE 0
2631 #define VP_ACTIVE 1
2632 #define VP_FAILED 2
2633 // #define VP_DISABLE 3
2634 uint16_t vp_err_state;
2635 uint16_t vp_prev_err_state;
2636 #define VP_ERR_UNKWN 0
2637 #define VP_ERR_PORTDWN 1
2638 #define VP_ERR_FAB_UNSUPPORTED 2
2639 #define VP_ERR_FAB_NORESOURCES 3
2640 #define VP_ERR_FAB_LOGOUT 4
2641 #define VP_ERR_ADAP_NORESOURCES 5
2642 struct qla_hw_data *hw;
2643 int req_ques[QLA_MAX_HOST_QUES];
2644 } scsi_qla_host_t;
2645
2646 /*
2647 * Macros to help code, maintain, etc.
2648 */
2649 #define LOOP_TRANSITION(ha) \
2650 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2651 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2652 atomic_read(&ha->loop_state) == LOOP_DOWN)
2653
2654 #define qla_printk(level, ha, format, arg...) \
2655 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2656
2657 /*
2658 * qla2x00 local function return status codes
2659 */
2660 #define MBS_MASK 0x3fff
2661
2662 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2663 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2664 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2665 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2666 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2667 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2668 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2669 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2670 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2671 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2672
2673 #define QLA_FUNCTION_TIMEOUT 0x100
2674 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2675 #define QLA_FUNCTION_FAILED 0x102
2676 #define QLA_MEMORY_ALLOC_FAILED 0x103
2677 #define QLA_LOCK_TIMEOUT 0x104
2678 #define QLA_ABORTED 0x105
2679 #define QLA_SUSPENDED 0x106
2680 #define QLA_BUSY 0x107
2681 #define QLA_RSCNS_HANDLED 0x108
2682 #define QLA_ALREADY_REGISTERED 0x109
2683
2684 #define NVRAM_DELAY() udelay(10)
2685
2686 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2687
2688 /*
2689 * Flash support definitions
2690 */
2691 #define OPTROM_SIZE_2300 0x20000
2692 #define OPTROM_SIZE_2322 0x100000
2693 #define OPTROM_SIZE_24XX 0x100000
2694 #define OPTROM_SIZE_25XX 0x200000
2695 #define OPTROM_SIZE_81XX 0x400000
2696
2697 #include "qla_gbl.h"
2698 #include "qla_dbg.h"
2699 #include "qla_inline.h"
2700
2701 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2702
2703 #endif
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