2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
35 #define QLA2XXX_DRIVER_NAME "qla2xxx"
38 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
39 * but that's fine as we don't look at the last 24 ones for
42 #define MAILBOX_REGISTER_COUNT_2100 8
43 #define MAILBOX_REGISTER_COUNT 32
45 #define QLA2200A_RISC_ROM_VER 4
49 #include "qla_settings.h"
52 * Data bit definitions
70 #define BIT_16 0x10000
71 #define BIT_17 0x20000
72 #define BIT_18 0x40000
73 #define BIT_19 0x80000
74 #define BIT_20 0x100000
75 #define BIT_21 0x200000
76 #define BIT_22 0x400000
77 #define BIT_23 0x800000
78 #define BIT_24 0x1000000
79 #define BIT_25 0x2000000
80 #define BIT_26 0x4000000
81 #define BIT_27 0x8000000
82 #define BIT_28 0x10000000
83 #define BIT_29 0x20000000
84 #define BIT_30 0x40000000
85 #define BIT_31 0x80000000
87 #define LSB(x) ((uint8_t)(x))
88 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
90 #define LSW(x) ((uint16_t)(x))
91 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
93 #define LSD(x) ((uint32_t)((uint64_t)(x)))
94 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
96 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
102 #define RD_REG_BYTE(addr) readb(addr)
103 #define RD_REG_WORD(addr) readw(addr)
104 #define RD_REG_DWORD(addr) readl(addr)
105 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
106 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
107 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
108 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
109 #define WRT_REG_WORD(addr, data) writew(data,addr)
110 #define WRT_REG_DWORD(addr, data) writel(data,addr)
113 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
116 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
117 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
120 * Fibre Channel device definitions.
122 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
123 #define MAX_FIBRE_DEVICES 512
124 #define MAX_FIBRE_LUNS 0xFFFF
125 #define MAX_RSCN_COUNT 32
126 #define MAX_HOST_COUNT 16
129 * Host adapter default definitions.
131 #define MAX_BUSES 1 /* We only have one bus today */
132 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
133 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
135 #define MAX_LUNS MAX_FIBRE_LUNS
136 #define MAX_CMDS_PER_LUN 255
139 * Fibre Channel device definitions.
141 #define SNS_LAST_LOOP_ID_2100 0xfe
142 #define SNS_LAST_LOOP_ID_2300 0x7ff
144 #define LAST_LOCAL_LOOP_ID 0x7d
145 #define SNS_FL_PORT 0x7e
146 #define FABRIC_CONTROLLER 0x7f
147 #define SIMPLE_NAME_SERVER 0x80
148 #define SNS_FIRST_LOOP_ID 0x81
149 #define MANAGEMENT_SERVER 0xfe
150 #define BROADCAST 0xff
153 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
154 * valid range of an N-PORT id is 0 through 0x7ef.
156 #define NPH_LAST_HANDLE 0x7ef
157 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
158 #define NPH_SNS 0x7fc /* FFFFFC */
159 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
160 #define NPH_F_PORT 0x7fe /* FFFFFE */
161 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
163 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
167 * Timeout timer counts in seconds
169 #define PORT_RETRY_TIME 1
170 #define LOOP_DOWN_TIMEOUT 60
171 #define LOOP_DOWN_TIME 255 /* 240 */
172 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
174 /* Maximum outstanding commands in ISP queues (1-65535) */
175 #define MAX_OUTSTANDING_COMMANDS 1024
177 /* ISP request and response entry counts (37-65535) */
178 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
179 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
180 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
181 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
182 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
183 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
191 struct fc_port
*fcport
;
193 struct scsi_cmnd
*cmd
; /* Linux SCSI command pkt */
197 uint32_t request_sense_length
;
198 uint8_t *request_sense_ptr
;
202 * SRB flag definitions
204 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
207 * ISP I/O Register Set structure definitions.
209 struct device_reg_2xxx
{
210 uint16_t flash_address
; /* Flash BIOS address */
211 uint16_t flash_data
; /* Flash BIOS data */
212 uint16_t unused_1
[1]; /* Gap */
213 uint16_t ctrl_status
; /* Control/Status */
214 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
215 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
216 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
218 uint16_t ictrl
; /* Interrupt control */
219 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
220 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
222 uint16_t istatus
; /* Interrupt status */
223 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
225 uint16_t semaphore
; /* Semaphore */
226 uint16_t nvram
; /* NVRAM register. */
227 #define NVR_DESELECT 0
228 #define NVR_BUSY BIT_15
229 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
230 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
231 #define NVR_DATA_IN BIT_3
232 #define NVR_DATA_OUT BIT_2
233 #define NVR_SELECT BIT_1
234 #define NVR_CLOCK BIT_0
236 #define NVR_WAIT_CNT 20000
248 uint16_t unused_2
[59]; /* Gap */
249 } __attribute__((packed
)) isp2100
;
252 uint16_t req_q_in
; /* In-Pointer */
253 uint16_t req_q_out
; /* Out-Pointer */
255 uint16_t rsp_q_in
; /* In-Pointer */
256 uint16_t rsp_q_out
; /* Out-Pointer */
258 /* RISC to Host Status */
259 uint32_t host_status
;
260 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
261 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
263 /* Host to Host Semaphore */
264 uint16_t host_semaphore
;
265 uint16_t unused_3
[17]; /* Gap */
299 uint16_t unused_4
[10]; /* Gap */
300 } __attribute__((packed
)) isp2300
;
303 uint16_t fpm_diag_config
;
304 uint16_t unused_5
[0x4]; /* Gap */
306 uint16_t unused_5_1
; /* Gap */
307 uint16_t pcr
; /* Processor Control Register. */
308 uint16_t unused_6
[0x5]; /* Gap */
309 uint16_t mctr
; /* Memory Configuration and Timing. */
310 uint16_t unused_7
[0x3]; /* Gap */
311 uint16_t fb_cmd_2100
; /* Unused on 23XX */
312 uint16_t unused_8
[0x3]; /* Gap */
313 uint16_t hccr
; /* Host command & control register. */
314 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
315 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
317 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
318 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
319 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
320 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
321 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
322 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
323 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
324 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
326 uint16_t unused_9
[5]; /* Gap */
327 uint16_t gpiod
; /* GPIO Data register. */
328 uint16_t gpioe
; /* GPIO Enable register. */
329 #define GPIO_LED_MASK 0x00C0
330 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
331 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
332 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
333 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
334 #define GPIO_LED_ALL_OFF 0x0000
335 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
336 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
340 uint16_t unused_10
[8]; /* Gap */
356 uint16_t mailbox23
; /* Also probe reg. */
357 } __attribute__((packed
)) isp2200
;
361 struct device_reg_25xxmq
{
369 struct device_reg_2xxx isp
;
370 struct device_reg_24xx isp24
;
371 struct device_reg_25xxmq isp25mq
;
374 #define ISP_REQ_Q_IN(ha, reg) \
375 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
376 &(reg)->u.isp2100.mailbox4 : \
377 &(reg)->u.isp2300.req_q_in)
378 #define ISP_REQ_Q_OUT(ha, reg) \
379 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
380 &(reg)->u.isp2100.mailbox4 : \
381 &(reg)->u.isp2300.req_q_out)
382 #define ISP_RSP_Q_IN(ha, reg) \
383 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
384 &(reg)->u.isp2100.mailbox5 : \
385 &(reg)->u.isp2300.rsp_q_in)
386 #define ISP_RSP_Q_OUT(ha, reg) \
387 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
388 &(reg)->u.isp2100.mailbox5 : \
389 &(reg)->u.isp2300.rsp_q_out)
391 #define MAILBOX_REG(ha, reg, num) \
392 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
394 &(reg)->u.isp2100.mailbox0 + (num) : \
395 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
396 &(reg)->u.isp2300.mailbox0 + (num))
397 #define RD_MAILBOX_REG(ha, reg, num) \
398 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
399 #define WRT_MAILBOX_REG(ha, reg, num, data) \
400 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
402 #define FB_CMD_REG(ha, reg) \
403 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
404 &(reg)->fb_cmd_2100 : \
405 &(reg)->u.isp2300.fb_cmd)
406 #define RD_FB_CMD_REG(ha, reg) \
407 RD_REG_WORD(FB_CMD_REG(ha, reg))
408 #define WRT_FB_CMD_REG(ha, reg, data) \
409 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
412 uint32_t out_mb
; /* outbound from driver */
413 uint32_t in_mb
; /* Incoming from RISC */
414 uint16_t mb
[MAILBOX_REGISTER_COUNT
];
419 #define MBX_DMA_IN BIT_0
420 #define MBX_DMA_OUT BIT_1
421 #define IOCTL_CMD BIT_2
424 #define MBX_TOV_SECONDS 30
427 * ISP product identification definitions in mailboxes after reset.
429 #define PROD_ID_1 0x4953
430 #define PROD_ID_2 0x0000
431 #define PROD_ID_2a 0x5020
432 #define PROD_ID_3 0x2020
435 * ISP mailbox Self-Test status codes
437 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
438 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
439 #define MBS_BUSY 4 /* Busy. */
442 * ISP mailbox command complete status codes
444 #define MBS_COMMAND_COMPLETE 0x4000
445 #define MBS_INVALID_COMMAND 0x4001
446 #define MBS_HOST_INTERFACE_ERROR 0x4002
447 #define MBS_TEST_FAILED 0x4003
448 #define MBS_COMMAND_ERROR 0x4005
449 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
450 #define MBS_PORT_ID_USED 0x4007
451 #define MBS_LOOP_ID_USED 0x4008
452 #define MBS_ALL_IDS_IN_USE 0x4009
453 #define MBS_NOT_LOGGED_IN 0x400A
454 #define MBS_LINK_DOWN_ERROR 0x400B
455 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
458 * ISP mailbox asynchronous event status codes
460 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
461 #define MBA_RESET 0x8001 /* Reset Detected. */
462 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
463 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
464 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
465 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
466 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
468 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
469 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
470 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
471 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
472 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
473 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
474 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
475 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
476 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
477 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
478 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
479 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
480 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
481 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
482 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
483 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
485 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
486 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
487 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
488 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
489 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
490 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
491 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
492 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
493 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
494 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
495 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
496 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
497 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
498 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
501 * Firmware options 1, 2, 3.
503 #define FO1_AE_ON_LIPF8 BIT_0
504 #define FO1_AE_ALL_LIP_RESET BIT_1
505 #define FO1_CTIO_RETRY BIT_3
506 #define FO1_DISABLE_LIP_F7_SW BIT_4
507 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
508 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
509 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
510 #define FO1_SET_EMPHASIS_SWING BIT_8
511 #define FO1_AE_AUTO_BYPASS BIT_9
512 #define FO1_ENABLE_PURE_IOCB BIT_10
513 #define FO1_AE_PLOGI_RJT BIT_11
514 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
515 #define FO1_AE_QUEUE_FULL BIT_13
517 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
518 #define FO2_REV_LOOPBACK BIT_1
520 #define FO3_ENABLE_EMERG_IOCB BIT_0
521 #define FO3_AE_RND_ERROR BIT_1
523 /* 24XX additional firmware options */
524 #define ADD_FO_COUNT 3
525 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
526 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
528 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
530 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
533 * ISP mailbox commands
535 #define MBC_LOAD_RAM 1 /* Load RAM. */
536 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
537 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
538 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
539 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
540 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
541 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
542 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
543 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
544 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
545 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
546 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
547 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
548 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
549 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
550 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
551 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
552 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
553 #define MBC_RESET 0x18 /* Reset. */
554 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
555 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
556 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
557 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
558 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
559 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
560 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
561 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
562 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
563 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
564 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
565 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
566 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
567 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
568 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
569 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
570 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
571 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
572 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
573 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
574 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
575 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
576 /* Initialization Procedure */
577 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
578 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
579 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
580 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
581 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
582 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
583 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
584 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
585 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
586 #define MBC_LIP_RESET 0x6c /* LIP reset. */
587 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
589 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
590 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
591 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
592 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
593 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
594 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
595 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
596 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
597 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
598 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
599 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
602 * ISP24xx mailbox commands
604 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
605 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
606 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
607 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
608 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
609 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
610 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
611 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
612 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
613 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
614 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
615 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
616 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
617 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
618 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
619 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
621 /* Firmware return data sizes */
622 #define FCAL_MAP_SIZE 128
624 /* Mailbox bit definitions for out_mb and in_mb */
625 #define MBX_31 BIT_31
626 #define MBX_30 BIT_30
627 #define MBX_29 BIT_29
628 #define MBX_28 BIT_28
629 #define MBX_27 BIT_27
630 #define MBX_26 BIT_26
631 #define MBX_25 BIT_25
632 #define MBX_24 BIT_24
633 #define MBX_23 BIT_23
634 #define MBX_22 BIT_22
635 #define MBX_21 BIT_21
636 #define MBX_20 BIT_20
637 #define MBX_19 BIT_19
638 #define MBX_18 BIT_18
639 #define MBX_17 BIT_17
640 #define MBX_16 BIT_16
641 #define MBX_15 BIT_15
642 #define MBX_14 BIT_14
643 #define MBX_13 BIT_13
644 #define MBX_12 BIT_12
645 #define MBX_11 BIT_11
646 #define MBX_10 BIT_10
659 * Firmware state codes from get firmware state mailbox command
661 #define FSTATE_CONFIG_WAIT 0
662 #define FSTATE_WAIT_AL_PA 1
663 #define FSTATE_WAIT_LOGIN 2
664 #define FSTATE_READY 3
665 #define FSTATE_LOSS_OF_SYNC 4
666 #define FSTATE_ERROR 5
667 #define FSTATE_REINIT 6
668 #define FSTATE_NON_PART 7
670 #define FSTATE_CONFIG_CORRECT 0
671 #define FSTATE_P2P_RCV_LIP 1
672 #define FSTATE_P2P_CHOOSE_LOOP 2
673 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
674 #define FSTATE_FATAL_ERROR 4
675 #define FSTATE_LOOP_BACK_CONN 5
678 * Port Database structure definition
679 * Little endian except where noted.
681 #define PORT_DATABASE_SIZE 128 /* bytes */
685 uint8_t master_state
;
688 uint8_t hard_address
;
691 uint8_t node_name
[WWN_SIZE
];
692 uint8_t port_name
[WWN_SIZE
];
693 uint16_t execution_throttle
;
694 uint16_t execution_count
;
697 uint16_t resource_allocation
;
698 uint16_t current_allocation
;
701 uint16_t transmit_execution_list_next
;
702 uint16_t transmit_execution_list_previous
;
703 uint16_t common_features
;
704 uint16_t total_concurrent_sequences
;
705 uint16_t RO_by_information_category
;
708 uint16_t receive_data_size
;
709 uint16_t concurrent_sequences
;
710 uint16_t open_sequences_per_exchange
;
711 uint16_t lun_abort_flags
;
712 uint16_t lun_stop_flags
;
713 uint16_t stop_queue_head
;
714 uint16_t stop_queue_tail
;
715 uint16_t port_retry_timer
;
716 uint16_t next_sequence_id
;
717 uint16_t frame_count
;
718 uint16_t PRLI_payload_length
;
719 uint8_t prli_svc_param_word_0
[2]; /* Big endian */
720 /* Bits 15-0 of word 0 */
721 uint8_t prli_svc_param_word_3
[2]; /* Big endian */
722 /* Bits 15-0 of word 3 */
724 uint16_t extended_lun_info_list_pointer
;
725 uint16_t extended_lun_stop_list_pointer
;
729 * Port database slave/master states
731 #define PD_STATE_DISCOVERY 0
732 #define PD_STATE_WAIT_DISCOVERY_ACK 1
733 #define PD_STATE_PORT_LOGIN 2
734 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
735 #define PD_STATE_PROCESS_LOGIN 4
736 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
737 #define PD_STATE_PORT_LOGGED_IN 6
738 #define PD_STATE_PORT_UNAVAILABLE 7
739 #define PD_STATE_PROCESS_LOGOUT 8
740 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
741 #define PD_STATE_PORT_LOGOUT 10
742 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
745 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
746 #define QLA_ZIO_DISABLED 0
747 #define QLA_ZIO_DEFAULT_TIMER 2
750 * ISP Initialization Control Block.
751 * Little endian except where noted.
753 #define ICB_VERSION 1
759 * LSB BIT 0 = Enable Hard Loop Id
760 * LSB BIT 1 = Enable Fairness
761 * LSB BIT 2 = Enable Full-Duplex
762 * LSB BIT 3 = Enable Fast Posting
763 * LSB BIT 4 = Enable Target Mode
764 * LSB BIT 5 = Disable Initiator Mode
765 * LSB BIT 6 = Enable ADISC
766 * LSB BIT 7 = Enable Target Inquiry Data
768 * MSB BIT 0 = Enable PDBC Notify
769 * MSB BIT 1 = Non Participating LIP
770 * MSB BIT 2 = Descending Loop ID Search
771 * MSB BIT 3 = Acquire Loop ID in LIPA
772 * MSB BIT 4 = Stop PortQ on Full Status
773 * MSB BIT 5 = Full Login after LIP
774 * MSB BIT 6 = Node Name Option
775 * MSB BIT 7 = Ext IFWCB enable bit
777 uint8_t firmware_options
[2];
779 uint16_t frame_payload_size
;
780 uint16_t max_iocb_allocation
;
781 uint16_t execution_throttle
;
783 uint8_t retry_delay
; /* unused */
784 uint8_t port_name
[WWN_SIZE
]; /* Big endian. */
785 uint16_t hard_address
;
786 uint8_t inquiry_data
;
787 uint8_t login_timeout
;
788 uint8_t node_name
[WWN_SIZE
]; /* Big endian. */
790 uint16_t request_q_outpointer
;
791 uint16_t response_q_inpointer
;
792 uint16_t request_q_length
;
793 uint16_t response_q_length
;
794 uint32_t request_q_address
[2];
795 uint32_t response_q_address
[2];
797 uint16_t lun_enables
;
798 uint8_t command_resource_count
;
799 uint8_t immediate_notify_resource_count
;
801 uint8_t reserved_2
[2];
804 * LSB BIT 0 = Timer Operation mode bit 0
805 * LSB BIT 1 = Timer Operation mode bit 1
806 * LSB BIT 2 = Timer Operation mode bit 2
807 * LSB BIT 3 = Timer Operation mode bit 3
808 * LSB BIT 4 = Init Config Mode bit 0
809 * LSB BIT 5 = Init Config Mode bit 1
810 * LSB BIT 6 = Init Config Mode bit 2
811 * LSB BIT 7 = Enable Non part on LIHA failure
813 * MSB BIT 0 = Enable class 2
814 * MSB BIT 1 = Enable ACK0
817 * MSB BIT 4 = FC Tape Enable
818 * MSB BIT 5 = Enable FC Confirm
819 * MSB BIT 6 = Enable command queuing in target mode
820 * MSB BIT 7 = No Logo On Link Down
822 uint8_t add_firmware_options
[2];
824 uint8_t response_accumulation_timer
;
825 uint8_t interrupt_delay_timer
;
828 * LSB BIT 0 = Enable Read xfr_rdy
829 * LSB BIT 1 = Soft ID only
832 * LSB BIT 4 = FCP RSP Payload [0]
833 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
834 * LSB BIT 6 = Enable Out-of-Order frame handling
835 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
837 * MSB BIT 0 = Sbus enable - 2300
841 * MSB BIT 4 = LED mode
842 * MSB BIT 5 = enable 50 ohm termination
843 * MSB BIT 6 = Data Rate (2300 only)
844 * MSB BIT 7 = Data Rate (2300 only)
846 uint8_t special_options
[2];
848 uint8_t reserved_3
[26];
852 * Get Link Status mailbox command return buffer.
854 #define GLSO_SEND_RPS BIT_0
855 #define GLSO_USE_DID BIT_3
857 struct link_statistics
{
858 uint32_t link_fail_cnt
;
859 uint32_t loss_sync_cnt
;
860 uint32_t loss_sig_cnt
;
861 uint32_t prim_seq_err_cnt
;
862 uint32_t inval_xmit_word_cnt
;
863 uint32_t inval_crc_cnt
;
865 uint32_t unused1
[0x1a];
868 uint32_t dumped_frames
;
874 * NVRAM Command values.
876 #define NV_START_BIT BIT_2
877 #define NV_WRITE_OP (BIT_26+BIT_24)
878 #define NV_READ_OP (BIT_26+BIT_25)
879 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
880 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
881 #define NV_DELAY_COUNT 10
884 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
891 uint8_t nvram_version
;
895 * NVRAM RISC parameter block
897 uint8_t parameter_block_version
;
901 * LSB BIT 0 = Enable Hard Loop Id
902 * LSB BIT 1 = Enable Fairness
903 * LSB BIT 2 = Enable Full-Duplex
904 * LSB BIT 3 = Enable Fast Posting
905 * LSB BIT 4 = Enable Target Mode
906 * LSB BIT 5 = Disable Initiator Mode
907 * LSB BIT 6 = Enable ADISC
908 * LSB BIT 7 = Enable Target Inquiry Data
910 * MSB BIT 0 = Enable PDBC Notify
911 * MSB BIT 1 = Non Participating LIP
912 * MSB BIT 2 = Descending Loop ID Search
913 * MSB BIT 3 = Acquire Loop ID in LIPA
914 * MSB BIT 4 = Stop PortQ on Full Status
915 * MSB BIT 5 = Full Login after LIP
916 * MSB BIT 6 = Node Name Option
917 * MSB BIT 7 = Ext IFWCB enable bit
919 uint8_t firmware_options
[2];
921 uint16_t frame_payload_size
;
922 uint16_t max_iocb_allocation
;
923 uint16_t execution_throttle
;
925 uint8_t retry_delay
; /* unused */
926 uint8_t port_name
[WWN_SIZE
]; /* Big endian. */
927 uint16_t hard_address
;
928 uint8_t inquiry_data
;
929 uint8_t login_timeout
;
930 uint8_t node_name
[WWN_SIZE
]; /* Big endian. */
933 * LSB BIT 0 = Timer Operation mode bit 0
934 * LSB BIT 1 = Timer Operation mode bit 1
935 * LSB BIT 2 = Timer Operation mode bit 2
936 * LSB BIT 3 = Timer Operation mode bit 3
937 * LSB BIT 4 = Init Config Mode bit 0
938 * LSB BIT 5 = Init Config Mode bit 1
939 * LSB BIT 6 = Init Config Mode bit 2
940 * LSB BIT 7 = Enable Non part on LIHA failure
942 * MSB BIT 0 = Enable class 2
943 * MSB BIT 1 = Enable ACK0
946 * MSB BIT 4 = FC Tape Enable
947 * MSB BIT 5 = Enable FC Confirm
948 * MSB BIT 6 = Enable command queuing in target mode
949 * MSB BIT 7 = No Logo On Link Down
951 uint8_t add_firmware_options
[2];
953 uint8_t response_accumulation_timer
;
954 uint8_t interrupt_delay_timer
;
957 * LSB BIT 0 = Enable Read xfr_rdy
958 * LSB BIT 1 = Soft ID only
961 * LSB BIT 4 = FCP RSP Payload [0]
962 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
963 * LSB BIT 6 = Enable Out-of-Order frame handling
964 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
966 * MSB BIT 0 = Sbus enable - 2300
970 * MSB BIT 4 = LED mode
971 * MSB BIT 5 = enable 50 ohm termination
972 * MSB BIT 6 = Data Rate (2300 only)
973 * MSB BIT 7 = Data Rate (2300 only)
975 uint8_t special_options
[2];
977 /* Reserved for expanded RISC parameter block */
978 uint8_t reserved_2
[22];
981 * LSB BIT 0 = Tx Sensitivity 1G bit 0
982 * LSB BIT 1 = Tx Sensitivity 1G bit 1
983 * LSB BIT 2 = Tx Sensitivity 1G bit 2
984 * LSB BIT 3 = Tx Sensitivity 1G bit 3
985 * LSB BIT 4 = Rx Sensitivity 1G bit 0
986 * LSB BIT 5 = Rx Sensitivity 1G bit 1
987 * LSB BIT 6 = Rx Sensitivity 1G bit 2
988 * LSB BIT 7 = Rx Sensitivity 1G bit 3
990 * MSB BIT 0 = Tx Sensitivity 2G bit 0
991 * MSB BIT 1 = Tx Sensitivity 2G bit 1
992 * MSB BIT 2 = Tx Sensitivity 2G bit 2
993 * MSB BIT 3 = Tx Sensitivity 2G bit 3
994 * MSB BIT 4 = Rx Sensitivity 2G bit 0
995 * MSB BIT 5 = Rx Sensitivity 2G bit 1
996 * MSB BIT 6 = Rx Sensitivity 2G bit 2
997 * MSB BIT 7 = Rx Sensitivity 2G bit 3
999 * LSB BIT 0 = Output Swing 1G bit 0
1000 * LSB BIT 1 = Output Swing 1G bit 1
1001 * LSB BIT 2 = Output Swing 1G bit 2
1002 * LSB BIT 3 = Output Emphasis 1G bit 0
1003 * LSB BIT 4 = Output Emphasis 1G bit 1
1004 * LSB BIT 5 = Output Swing 2G bit 0
1005 * LSB BIT 6 = Output Swing 2G bit 1
1006 * LSB BIT 7 = Output Swing 2G bit 2
1008 * MSB BIT 0 = Output Emphasis 2G bit 0
1009 * MSB BIT 1 = Output Emphasis 2G bit 1
1010 * MSB BIT 2 = Output Enable
1017 uint8_t seriallink_options
[4];
1020 * NVRAM host parameter block
1022 * LSB BIT 0 = Enable spinup delay
1023 * LSB BIT 1 = Disable BIOS
1024 * LSB BIT 2 = Enable Memory Map BIOS
1025 * LSB BIT 3 = Enable Selectable Boot
1026 * LSB BIT 4 = Disable RISC code load
1027 * LSB BIT 5 = Set cache line size 1
1028 * LSB BIT 6 = PCI Parity Disable
1029 * LSB BIT 7 = Enable extended logging
1031 * MSB BIT 0 = Enable 64bit addressing
1032 * MSB BIT 1 = Enable lip reset
1033 * MSB BIT 2 = Enable lip full login
1034 * MSB BIT 3 = Enable target reset
1035 * MSB BIT 4 = Enable database storage
1036 * MSB BIT 5 = Enable cache flush read
1037 * MSB BIT 6 = Enable database load
1038 * MSB BIT 7 = Enable alternate WWN
1042 uint8_t boot_node_name
[WWN_SIZE
];
1043 uint8_t boot_lun_number
;
1044 uint8_t reset_delay
;
1045 uint8_t port_down_retry_count
;
1046 uint8_t boot_id_number
;
1047 uint16_t max_luns_per_target
;
1048 uint8_t fcode_boot_port_name
[WWN_SIZE
];
1049 uint8_t alternate_port_name
[WWN_SIZE
];
1050 uint8_t alternate_node_name
[WWN_SIZE
];
1053 * BIT 0 = Selective Login
1054 * BIT 1 = Alt-Boot Enable
1056 * BIT 3 = Boot Order List
1058 * BIT 5 = Selective LUN
1062 uint8_t efi_parameters
;
1064 uint8_t link_down_timeout
;
1066 uint8_t adapter_id
[16];
1068 uint8_t alt1_boot_node_name
[WWN_SIZE
];
1069 uint16_t alt1_boot_lun_number
;
1070 uint8_t alt2_boot_node_name
[WWN_SIZE
];
1071 uint16_t alt2_boot_lun_number
;
1072 uint8_t alt3_boot_node_name
[WWN_SIZE
];
1073 uint16_t alt3_boot_lun_number
;
1074 uint8_t alt4_boot_node_name
[WWN_SIZE
];
1075 uint16_t alt4_boot_lun_number
;
1076 uint8_t alt5_boot_node_name
[WWN_SIZE
];
1077 uint16_t alt5_boot_lun_number
;
1078 uint8_t alt6_boot_node_name
[WWN_SIZE
];
1079 uint16_t alt6_boot_lun_number
;
1080 uint8_t alt7_boot_node_name
[WWN_SIZE
];
1081 uint16_t alt7_boot_lun_number
;
1083 uint8_t reserved_3
[2];
1085 /* Offset 200-215 : Model Number */
1086 uint8_t model_number
[16];
1088 /* OEM related items */
1089 uint8_t oem_specific
[16];
1092 * NVRAM Adapter Features offset 232-239
1094 * LSB BIT 0 = External GBIC
1095 * LSB BIT 1 = Risc RAM parity
1096 * LSB BIT 2 = Buffer Plus Module
1097 * LSB BIT 3 = Multi Chip Adapter
1098 * LSB BIT 4 = Internal connector
1112 uint8_t adapter_features
[2];
1114 uint8_t reserved_4
[16];
1116 /* Subsystem vendor ID for ISP2200 */
1117 uint16_t subsystem_vendor_id_2200
;
1119 /* Subsystem device ID for ISP2200 */
1120 uint16_t subsystem_device_id_2200
;
1127 * ISP queue - response queue entry definition.
1132 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1143 #define SET_TARGET_ID(ha, to, from) \
1145 if (HAS_EXTENDED_IDS(ha)) \
1146 to.extended = cpu_to_le16(from); \
1148 to.id.standard = (uint8_t)from; \
1152 * ISP queue - command entry structure definition.
1154 #define COMMAND_TYPE 0x11 /* Command entry */
1156 uint8_t entry_type
; /* Entry type. */
1157 uint8_t entry_count
; /* Entry count. */
1158 uint8_t sys_define
; /* System defined. */
1159 uint8_t entry_status
; /* Entry Status. */
1160 uint32_t handle
; /* System handle. */
1161 target_id_t target
; /* SCSI ID */
1162 uint16_t lun
; /* SCSI LUN */
1163 uint16_t control_flags
; /* Control flags. */
1164 #define CF_WRITE BIT_6
1165 #define CF_READ BIT_5
1166 #define CF_SIMPLE_TAG BIT_3
1167 #define CF_ORDERED_TAG BIT_2
1168 #define CF_HEAD_TAG BIT_1
1169 uint16_t reserved_1
;
1170 uint16_t timeout
; /* Command timeout. */
1171 uint16_t dseg_count
; /* Data segment count. */
1172 uint8_t scsi_cdb
[MAX_CMDSZ
]; /* SCSI command words. */
1173 uint32_t byte_count
; /* Total byte count. */
1174 uint32_t dseg_0_address
; /* Data segment 0 address. */
1175 uint32_t dseg_0_length
; /* Data segment 0 length. */
1176 uint32_t dseg_1_address
; /* Data segment 1 address. */
1177 uint32_t dseg_1_length
; /* Data segment 1 length. */
1178 uint32_t dseg_2_address
; /* Data segment 2 address. */
1179 uint32_t dseg_2_length
; /* Data segment 2 length. */
1183 * ISP queue - 64-Bit addressing, command entry structure definition.
1185 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1187 uint8_t entry_type
; /* Entry type. */
1188 uint8_t entry_count
; /* Entry count. */
1189 uint8_t sys_define
; /* System defined. */
1190 uint8_t entry_status
; /* Entry Status. */
1191 uint32_t handle
; /* System handle. */
1192 target_id_t target
; /* SCSI ID */
1193 uint16_t lun
; /* SCSI LUN */
1194 uint16_t control_flags
; /* Control flags. */
1195 uint16_t reserved_1
;
1196 uint16_t timeout
; /* Command timeout. */
1197 uint16_t dseg_count
; /* Data segment count. */
1198 uint8_t scsi_cdb
[MAX_CMDSZ
]; /* SCSI command words. */
1199 uint32_t byte_count
; /* Total byte count. */
1200 uint32_t dseg_0_address
[2]; /* Data segment 0 address. */
1201 uint32_t dseg_0_length
; /* Data segment 0 length. */
1202 uint32_t dseg_1_address
[2]; /* Data segment 1 address. */
1203 uint32_t dseg_1_length
; /* Data segment 1 length. */
1204 } cmd_a64_entry_t
, request_t
;
1207 * ISP queue - continuation entry structure definition.
1209 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1211 uint8_t entry_type
; /* Entry type. */
1212 uint8_t entry_count
; /* Entry count. */
1213 uint8_t sys_define
; /* System defined. */
1214 uint8_t entry_status
; /* Entry Status. */
1216 uint32_t dseg_0_address
; /* Data segment 0 address. */
1217 uint32_t dseg_0_length
; /* Data segment 0 length. */
1218 uint32_t dseg_1_address
; /* Data segment 1 address. */
1219 uint32_t dseg_1_length
; /* Data segment 1 length. */
1220 uint32_t dseg_2_address
; /* Data segment 2 address. */
1221 uint32_t dseg_2_length
; /* Data segment 2 length. */
1222 uint32_t dseg_3_address
; /* Data segment 3 address. */
1223 uint32_t dseg_3_length
; /* Data segment 3 length. */
1224 uint32_t dseg_4_address
; /* Data segment 4 address. */
1225 uint32_t dseg_4_length
; /* Data segment 4 length. */
1226 uint32_t dseg_5_address
; /* Data segment 5 address. */
1227 uint32_t dseg_5_length
; /* Data segment 5 length. */
1228 uint32_t dseg_6_address
; /* Data segment 6 address. */
1229 uint32_t dseg_6_length
; /* Data segment 6 length. */
1233 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1235 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1237 uint8_t entry_type
; /* Entry type. */
1238 uint8_t entry_count
; /* Entry count. */
1239 uint8_t sys_define
; /* System defined. */
1240 uint8_t entry_status
; /* Entry Status. */
1241 uint32_t dseg_0_address
[2]; /* Data segment 0 address. */
1242 uint32_t dseg_0_length
; /* Data segment 0 length. */
1243 uint32_t dseg_1_address
[2]; /* Data segment 1 address. */
1244 uint32_t dseg_1_length
; /* Data segment 1 length. */
1245 uint32_t dseg_2_address
[2]; /* Data segment 2 address. */
1246 uint32_t dseg_2_length
; /* Data segment 2 length. */
1247 uint32_t dseg_3_address
[2]; /* Data segment 3 address. */
1248 uint32_t dseg_3_length
; /* Data segment 3 length. */
1249 uint32_t dseg_4_address
[2]; /* Data segment 4 address. */
1250 uint32_t dseg_4_length
; /* Data segment 4 length. */
1254 * ISP queue - status entry structure definition.
1256 #define STATUS_TYPE 0x03 /* Status entry. */
1258 uint8_t entry_type
; /* Entry type. */
1259 uint8_t entry_count
; /* Entry count. */
1260 uint8_t sys_define
; /* System defined. */
1261 uint8_t entry_status
; /* Entry Status. */
1262 uint32_t handle
; /* System handle. */
1263 uint16_t scsi_status
; /* SCSI status. */
1264 uint16_t comp_status
; /* Completion status. */
1265 uint16_t state_flags
; /* State flags. */
1266 uint16_t status_flags
; /* Status flags. */
1267 uint16_t rsp_info_len
; /* Response Info Length. */
1268 uint16_t req_sense_length
; /* Request sense data length. */
1269 uint32_t residual_length
; /* Residual transfer length. */
1270 uint8_t rsp_info
[8]; /* FCP response information. */
1271 uint8_t req_sense_data
[32]; /* Request sense data. */
1275 * Status entry entry status
1277 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1278 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1279 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1280 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1281 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1282 #define RF_BUSY BIT_1 /* Busy */
1283 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1284 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1285 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1289 * Status entry SCSI status bit definitions.
1291 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1292 #define SS_RESIDUAL_UNDER BIT_11
1293 #define SS_RESIDUAL_OVER BIT_10
1294 #define SS_SENSE_LEN_VALID BIT_9
1295 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1297 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1298 #define SS_BUSY_CONDITION BIT_3
1299 #define SS_CONDITION_MET BIT_2
1300 #define SS_CHECK_CONDITION BIT_1
1303 * Status entry completion status
1305 #define CS_COMPLETE 0x0 /* No errors */
1306 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1307 #define CS_DMA 0x2 /* A DMA direction error. */
1308 #define CS_TRANSPORT 0x3 /* Transport error. */
1309 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1310 #define CS_ABORTED 0x5 /* System aborted command. */
1311 #define CS_TIMEOUT 0x6 /* Timeout error. */
1312 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1314 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1315 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1316 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1317 /* (selection timeout) */
1318 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1319 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1320 #define CS_PORT_BUSY 0x2B /* Port Busy */
1321 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1322 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1323 #define CS_UNKNOWN 0x81 /* Driver defined */
1324 #define CS_RETRY 0x82 /* Driver defined */
1325 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1328 * Status entry status flags
1330 #define SF_ABTS_TERMINATED BIT_10
1331 #define SF_LOGOUT_SENT BIT_13
1334 * ISP queue - status continuation entry structure definition.
1336 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1338 uint8_t entry_type
; /* Entry type. */
1339 uint8_t entry_count
; /* Entry count. */
1340 uint8_t sys_define
; /* System defined. */
1341 uint8_t entry_status
; /* Entry Status. */
1342 uint8_t data
[60]; /* data */
1346 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1347 * structure definition.
1349 #define STATUS_TYPE_21 0x21 /* Status entry. */
1351 uint8_t entry_type
; /* Entry type. */
1352 uint8_t entry_count
; /* Entry count. */
1353 uint8_t handle_count
; /* Handle count. */
1354 uint8_t entry_status
; /* Entry Status. */
1355 uint32_t handle
[15]; /* System handles. */
1359 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1360 * structure definition.
1362 #define STATUS_TYPE_22 0x22 /* Status entry. */
1364 uint8_t entry_type
; /* Entry type. */
1365 uint8_t entry_count
; /* Entry count. */
1366 uint8_t handle_count
; /* Handle count. */
1367 uint8_t entry_status
; /* Entry Status. */
1368 uint16_t handle
[30]; /* System handles. */
1372 * ISP queue - marker entry structure definition.
1374 #define MARKER_TYPE 0x04 /* Marker entry. */
1376 uint8_t entry_type
; /* Entry type. */
1377 uint8_t entry_count
; /* Entry count. */
1378 uint8_t handle_count
; /* Handle count. */
1379 uint8_t entry_status
; /* Entry Status. */
1380 uint32_t sys_define_2
; /* System defined. */
1381 target_id_t target
; /* SCSI ID */
1382 uint8_t modifier
; /* Modifier (7-0). */
1383 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1384 #define MK_SYNC_ID 1 /* Synchronize ID */
1385 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1386 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1387 /* clear port changed, */
1388 /* use sequence number. */
1390 uint16_t sequence_number
; /* Sequence number of event */
1391 uint16_t lun
; /* SCSI LUN */
1392 uint8_t reserved_2
[48];
1396 * ISP queue - Management Server entry structure definition.
1398 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1400 uint8_t entry_type
; /* Entry type. */
1401 uint8_t entry_count
; /* Entry count. */
1402 uint8_t handle_count
; /* Handle count. */
1403 uint8_t entry_status
; /* Entry Status. */
1404 uint32_t handle1
; /* System handle. */
1405 target_id_t loop_id
;
1407 uint16_t control_flags
; /* Control flags. */
1410 uint16_t cmd_dsd_count
;
1411 uint16_t total_dsd_count
;
1417 uint32_t rsp_bytecount
;
1418 uint32_t req_bytecount
;
1419 uint32_t dseg_req_address
[2]; /* Data segment 0 address. */
1420 uint32_t dseg_req_length
; /* Data segment 0 length. */
1421 uint32_t dseg_rsp_address
[2]; /* Data segment 1 address. */
1422 uint32_t dseg_rsp_length
; /* Data segment 1 length. */
1427 * ISP queue - Mailbox Command entry structure definition.
1429 #define MBX_IOCB_TYPE 0x39
1432 uint8_t entry_count
;
1433 uint8_t sys_define1
;
1434 /* Use sys_define1 for source type */
1435 #define SOURCE_SCSI 0x00
1436 #define SOURCE_IP 0x01
1437 #define SOURCE_VI 0x02
1438 #define SOURCE_SCTP 0x03
1439 #define SOURCE_MP 0x04
1440 #define SOURCE_MPIOCTL 0x05
1441 #define SOURCE_ASYNC_IOCB 0x07
1443 uint8_t entry_status
;
1446 target_id_t loop_id
;
1449 uint16_t state_flags
;
1450 uint16_t status_flags
;
1452 uint32_t sys_define2
[2];
1462 uint32_t reserved_2
[2];
1463 uint8_t node_name
[WWN_SIZE
];
1464 uint8_t port_name
[WWN_SIZE
];
1468 * ISP request and response queue entry sizes
1470 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1471 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1475 * 24 bit port ID type definition.
1485 #elif defined(__LITTLE_ENDIAN)
1490 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1495 #define INVALID_PORT_ID 0xFFFFFF
1498 * Switch info gathering structure.
1502 uint8_t node_name
[WWN_SIZE
];
1503 uint8_t port_name
[WWN_SIZE
];
1504 uint8_t fabric_port_name
[WWN_SIZE
];
1509 * Fibre channel port type.
1521 * Fibre channel port structure.
1523 typedef struct fc_port
{
1524 struct list_head list
;
1525 struct scsi_qla_host
*vha
;
1527 uint8_t node_name
[WWN_SIZE
];
1528 uint8_t port_name
[WWN_SIZE
];
1531 uint16_t old_loop_id
;
1533 uint8_t fabric_port_name
[WWN_SIZE
];
1536 fc_port_type_t port_type
;
1541 int port_login_retry_count
;
1543 atomic_t port_down_timer
;
1545 struct fc_rport
*rport
, *drport
;
1546 u32 supported_classes
;
1548 unsigned long last_queue_full
;
1549 unsigned long last_ramp_up
;
1555 * Fibre channel port/lun states.
1557 #define FCS_UNCONFIGURED 1
1558 #define FCS_DEVICE_DEAD 2
1559 #define FCS_DEVICE_LOST 3
1560 #define FCS_ONLINE 4
1565 #define FCF_FABRIC_DEVICE BIT_0
1566 #define FCF_LOGIN_NEEDED BIT_1
1567 #define FCF_TAPE_PRESENT BIT_2
1569 /* No loop ID flag. */
1570 #define FC_NO_LOOP_ID 0x1000
1575 * NOTE: All structures are big-endian in form.
1578 #define CT_REJECT_RESPONSE 0x8001
1579 #define CT_ACCEPT_RESPONSE 0x8002
1580 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1581 #define CT_REASON_CANNOT_PERFORM 0x09
1582 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1583 #define CT_EXPL_ALREADY_REGISTERED 0x10
1585 #define NS_N_PORT_TYPE 0x01
1586 #define NS_NL_PORT_TYPE 0x02
1587 #define NS_NX_PORT_TYPE 0x7F
1589 #define GA_NXT_CMD 0x100
1590 #define GA_NXT_REQ_SIZE (16 + 4)
1591 #define GA_NXT_RSP_SIZE (16 + 620)
1593 #define GID_PT_CMD 0x1A1
1594 #define GID_PT_REQ_SIZE (16 + 4)
1595 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1597 #define GPN_ID_CMD 0x112
1598 #define GPN_ID_REQ_SIZE (16 + 4)
1599 #define GPN_ID_RSP_SIZE (16 + 8)
1601 #define GNN_ID_CMD 0x113
1602 #define GNN_ID_REQ_SIZE (16 + 4)
1603 #define GNN_ID_RSP_SIZE (16 + 8)
1605 #define GFT_ID_CMD 0x117
1606 #define GFT_ID_REQ_SIZE (16 + 4)
1607 #define GFT_ID_RSP_SIZE (16 + 32)
1609 #define RFT_ID_CMD 0x217
1610 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1611 #define RFT_ID_RSP_SIZE 16
1613 #define RFF_ID_CMD 0x21F
1614 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1615 #define RFF_ID_RSP_SIZE 16
1617 #define RNN_ID_CMD 0x213
1618 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1619 #define RNN_ID_RSP_SIZE 16
1621 #define RSNN_NN_CMD 0x239
1622 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1623 #define RSNN_NN_RSP_SIZE 16
1625 #define GFPN_ID_CMD 0x11C
1626 #define GFPN_ID_REQ_SIZE (16 + 4)
1627 #define GFPN_ID_RSP_SIZE (16 + 8)
1629 #define GPSC_CMD 0x127
1630 #define GPSC_REQ_SIZE (16 + 8)
1631 #define GPSC_RSP_SIZE (16 + 2 + 2)
1635 * HBA attribute types.
1637 #define FDMI_HBA_ATTR_COUNT 9
1638 #define FDMI_HBA_NODE_NAME 1
1639 #define FDMI_HBA_MANUFACTURER 2
1640 #define FDMI_HBA_SERIAL_NUMBER 3
1641 #define FDMI_HBA_MODEL 4
1642 #define FDMI_HBA_MODEL_DESCRIPTION 5
1643 #define FDMI_HBA_HARDWARE_VERSION 6
1644 #define FDMI_HBA_DRIVER_VERSION 7
1645 #define FDMI_HBA_OPTION_ROM_VERSION 8
1646 #define FDMI_HBA_FIRMWARE_VERSION 9
1647 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1648 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1650 struct ct_fdmi_hba_attr
{
1654 uint8_t node_name
[WWN_SIZE
];
1655 uint8_t manufacturer
[32];
1656 uint8_t serial_num
[8];
1658 uint8_t model_desc
[80];
1659 uint8_t hw_version
[16];
1660 uint8_t driver_version
[32];
1661 uint8_t orom_version
[16];
1662 uint8_t fw_version
[16];
1663 uint8_t os_version
[128];
1664 uint8_t max_ct_len
[4];
1668 struct ct_fdmi_hba_attributes
{
1670 struct ct_fdmi_hba_attr entry
[FDMI_HBA_ATTR_COUNT
];
1674 * Port attribute types.
1676 #define FDMI_PORT_ATTR_COUNT 6
1677 #define FDMI_PORT_FC4_TYPES 1
1678 #define FDMI_PORT_SUPPORT_SPEED 2
1679 #define FDMI_PORT_CURRENT_SPEED 3
1680 #define FDMI_PORT_MAX_FRAME_SIZE 4
1681 #define FDMI_PORT_OS_DEVICE_NAME 5
1682 #define FDMI_PORT_HOST_NAME 6
1684 #define FDMI_PORT_SPEED_1GB 0x1
1685 #define FDMI_PORT_SPEED_2GB 0x2
1686 #define FDMI_PORT_SPEED_10GB 0x4
1687 #define FDMI_PORT_SPEED_4GB 0x8
1688 #define FDMI_PORT_SPEED_8GB 0x10
1689 #define FDMI_PORT_SPEED_16GB 0x20
1690 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1692 struct ct_fdmi_port_attr
{
1696 uint8_t fc4_types
[32];
1699 uint32_t max_frame_size
;
1700 uint8_t os_dev_name
[32];
1701 uint8_t host_name
[32];
1706 * Port Attribute Block.
1708 struct ct_fdmi_port_attributes
{
1710 struct ct_fdmi_port_attr entry
[FDMI_PORT_ATTR_COUNT
];
1713 /* FDMI definitions. */
1714 #define GRHL_CMD 0x100
1715 #define GHAT_CMD 0x101
1716 #define GRPL_CMD 0x102
1717 #define GPAT_CMD 0x110
1719 #define RHBA_CMD 0x200
1720 #define RHBA_RSP_SIZE 16
1722 #define RHAT_CMD 0x201
1723 #define RPRT_CMD 0x210
1725 #define RPA_CMD 0x211
1726 #define RPA_RSP_SIZE 16
1728 #define DHBA_CMD 0x300
1729 #define DHBA_REQ_SIZE (16 + 8)
1730 #define DHBA_RSP_SIZE 16
1732 #define DHAT_CMD 0x301
1733 #define DPRT_CMD 0x310
1734 #define DPA_CMD 0x311
1736 /* CT command header -- request/response common fields */
1746 /* CT command request */
1748 struct ct_cmd_hdr header
;
1750 uint16_t max_rsp_size
;
1751 uint8_t fragment_id
;
1752 uint8_t reserved
[3];
1755 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1771 uint8_t fc4_types
[32];
1778 uint8_t fc4_feature
;
1785 uint8_t node_name
[8];
1789 uint8_t node_name
[8];
1791 uint8_t sym_node_name
[255];
1795 uint8_t hba_indentifier
[8];
1799 uint8_t hba_identifier
[8];
1800 uint32_t entry_count
;
1801 uint8_t port_name
[8];
1802 struct ct_fdmi_hba_attributes attrs
;
1806 uint8_t hba_identifier
[8];
1807 struct ct_fdmi_hba_attributes attrs
;
1811 uint8_t port_name
[8];
1812 struct ct_fdmi_port_attributes attrs
;
1816 uint8_t port_name
[8];
1820 uint8_t port_name
[8];
1824 uint8_t port_name
[8];
1828 uint8_t port_name
[8];
1832 uint8_t port_name
[8];
1837 /* CT command response header */
1839 struct ct_cmd_hdr header
;
1842 uint8_t fragment_id
;
1843 uint8_t reason_code
;
1844 uint8_t explanation_code
;
1845 uint8_t vendor_unique
;
1848 struct ct_sns_gid_pt_data
{
1849 uint8_t control_byte
;
1854 struct ct_rsp_hdr header
;
1860 uint8_t port_name
[8];
1861 uint8_t sym_port_name_len
;
1862 uint8_t sym_port_name
[255];
1863 uint8_t node_name
[8];
1864 uint8_t sym_node_name_len
;
1865 uint8_t sym_node_name
[255];
1866 uint8_t init_proc_assoc
[8];
1867 uint8_t node_ip_addr
[16];
1868 uint8_t class_of_service
[4];
1869 uint8_t fc4_types
[32];
1870 uint8_t ip_address
[16];
1871 uint8_t fabric_port_name
[8];
1873 uint8_t hard_address
[3];
1877 struct ct_sns_gid_pt_data entries
[MAX_FIBRE_DEVICES
];
1881 uint8_t port_name
[8];
1885 uint8_t node_name
[8];
1889 uint8_t fc4_types
[32];
1893 uint32_t entry_count
;
1894 uint8_t port_name
[8];
1895 struct ct_fdmi_hba_attributes attrs
;
1899 uint8_t port_name
[8];
1911 struct ct_sns_req req
;
1912 struct ct_sns_rsp rsp
;
1917 * SNS command structures -- for 2200 compatability.
1919 #define RFT_ID_SNS_SCMD_LEN 22
1920 #define RFT_ID_SNS_CMD_SIZE 60
1921 #define RFT_ID_SNS_DATA_SIZE 16
1923 #define RNN_ID_SNS_SCMD_LEN 10
1924 #define RNN_ID_SNS_CMD_SIZE 36
1925 #define RNN_ID_SNS_DATA_SIZE 16
1927 #define GA_NXT_SNS_SCMD_LEN 6
1928 #define GA_NXT_SNS_CMD_SIZE 28
1929 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1931 #define GID_PT_SNS_SCMD_LEN 6
1932 #define GID_PT_SNS_CMD_SIZE 28
1933 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1935 #define GPN_ID_SNS_SCMD_LEN 6
1936 #define GPN_ID_SNS_CMD_SIZE 28
1937 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1939 #define GNN_ID_SNS_SCMD_LEN 6
1940 #define GNN_ID_SNS_CMD_SIZE 28
1941 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1943 struct sns_cmd_pkt
{
1946 uint16_t buffer_length
;
1947 uint16_t reserved_1
;
1948 uint32_t buffer_address
[2];
1949 uint16_t subcommand_length
;
1950 uint16_t reserved_2
;
1951 uint16_t subcommand
;
1953 uint32_t reserved_3
;
1957 uint8_t rft_data
[RFT_ID_SNS_DATA_SIZE
];
1958 uint8_t rnn_data
[RNN_ID_SNS_DATA_SIZE
];
1959 uint8_t gan_data
[GA_NXT_SNS_DATA_SIZE
];
1960 uint8_t gid_data
[GID_PT_SNS_DATA_SIZE
];
1961 uint8_t gpn_data
[GPN_ID_SNS_DATA_SIZE
];
1962 uint8_t gnn_data
[GNN_ID_SNS_DATA_SIZE
];
1969 const struct firmware
*fw
;
1972 /* Return data from MBC_GET_ID_LIST call. */
1973 struct gid_list_info
{
1977 uint8_t loop_id_2100
; /* ISP2100/ISP2200 -- 4 bytes. */
1978 uint16_t loop_id
; /* ISP23XX -- 6 bytes. */
1979 uint16_t reserved_1
; /* ISP24XX -- 8 bytes. */
1981 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
1984 typedef struct vport_info
{
1985 uint8_t port_name
[WWN_SIZE
];
1986 uint8_t node_name
[WWN_SIZE
];
1989 unsigned long host_no
;
1994 typedef struct vport_params
{
1995 uint8_t port_name
[WWN_SIZE
];
1996 uint8_t node_name
[WWN_SIZE
];
1998 #define VP_OPTS_RETRY_ENABLE BIT_0
1999 #define VP_OPTS_VP_DISABLE BIT_1
2002 /* NPIV - return codes of VP create and modify */
2003 #define VP_RET_CODE_OK 0
2004 #define VP_RET_CODE_FATAL 1
2005 #define VP_RET_CODE_WRONG_ID 2
2006 #define VP_RET_CODE_WWPN 3
2007 #define VP_RET_CODE_RESOURCES 4
2008 #define VP_RET_CODE_NO_MEM 5
2009 #define VP_RET_CODE_NOT_FOUND 6
2016 struct isp_operations
{
2018 int (*pci_config
) (struct scsi_qla_host
*);
2019 void (*reset_chip
) (struct scsi_qla_host
*);
2020 int (*chip_diag
) (struct scsi_qla_host
*);
2021 void (*config_rings
) (struct scsi_qla_host
*);
2022 void (*reset_adapter
) (struct scsi_qla_host
*);
2023 int (*nvram_config
) (struct scsi_qla_host
*);
2024 void (*update_fw_options
) (struct scsi_qla_host
*);
2025 int (*load_risc
) (struct scsi_qla_host
*, uint32_t *);
2027 char * (*pci_info_str
) (struct scsi_qla_host
*, char *);
2028 char * (*fw_version_str
) (struct scsi_qla_host
*, char *);
2030 irq_handler_t intr_handler
;
2031 void (*enable_intrs
) (struct qla_hw_data
*);
2032 void (*disable_intrs
) (struct qla_hw_data
*);
2034 int (*abort_command
) (srb_t
*);
2035 int (*target_reset
) (struct fc_port
*, unsigned int, int);
2036 int (*lun_reset
) (struct fc_port
*, unsigned int, int);
2037 int (*fabric_login
) (struct scsi_qla_host
*, uint16_t, uint8_t,
2038 uint8_t, uint8_t, uint16_t *, uint8_t);
2039 int (*fabric_logout
) (struct scsi_qla_host
*, uint16_t, uint8_t,
2042 uint16_t (*calc_req_entries
) (uint16_t);
2043 void (*build_iocbs
) (srb_t
*, cmd_entry_t
*, uint16_t);
2044 void * (*prep_ms_iocb
) (struct scsi_qla_host
*, uint32_t, uint32_t);
2045 void * (*prep_ms_fdmi_iocb
) (struct scsi_qla_host
*, uint32_t,
2048 uint8_t * (*read_nvram
) (struct scsi_qla_host
*, uint8_t *,
2049 uint32_t, uint32_t);
2050 int (*write_nvram
) (struct scsi_qla_host
*, uint8_t *, uint32_t,
2053 void (*fw_dump
) (struct scsi_qla_host
*, int);
2055 int (*beacon_on
) (struct scsi_qla_host
*);
2056 int (*beacon_off
) (struct scsi_qla_host
*);
2057 void (*beacon_blink
) (struct scsi_qla_host
*);
2059 uint8_t * (*read_optrom
) (struct scsi_qla_host
*, uint8_t *,
2060 uint32_t, uint32_t);
2061 int (*write_optrom
) (struct scsi_qla_host
*, uint8_t *, uint32_t,
2064 int (*get_flash_version
) (struct scsi_qla_host
*, void *);
2065 int (*start_scsi
) (srb_t
*);
2068 /* MSI-X Support *************************************************************/
2070 #define QLA_MSIX_CHIP_REV_24XX 3
2071 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2072 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2074 #define QLA_MSIX_DEFAULT 0x00
2075 #define QLA_MSIX_RSP_Q 0x01
2077 #define QLA_MIDX_DEFAULT 0
2078 #define QLA_MIDX_RSP_Q 1
2079 #define QLA_PCI_MSIX_CONTROL 0xa2
2081 struct scsi_qla_host
;
2083 struct qla_msix_entry
{
2087 struct rsp_que
*rsp
;
2090 #define WATCH_INTERVAL 1 /* number of seconds */
2093 enum qla_work_type
{
2099 struct qla_work_evt
{
2100 struct list_head list
;
2101 enum qla_work_type type
;
2103 #define QLA_EVT_FLAG_FREE 0x1
2107 enum fc_host_event_code code
;
2111 #define QLA_IDC_ACK_REGS 7
2112 uint16_t mb
[QLA_IDC_ACK_REGS
];
2117 struct qla_chip_state_84xx
{
2118 struct list_head list
;
2122 spinlock_t access_lock
;
2123 struct mutex fw_update_mutex
;
2125 uint32_t op_fw_version
;
2126 uint32_t op_fw_size
;
2127 uint32_t op_fw_seq_size
;
2128 uint32_t diag_fw_version
;
2129 uint32_t gold_fw_version
;
2132 struct qla_statistics
{
2133 uint32_t total_isp_aborts
;
2134 uint64_t input_bytes
;
2135 uint64_t output_bytes
;
2138 /* Multi queue support */
2139 #define MBC_INITIALIZE_MULTIQ 0x1f
2140 #define QLA_QUE_PAGE 0X1000
2141 #define QLA_MQ_SIZE 32
2142 #define QLA_MAX_QUEUES 256
2143 #define ISP_QUE_REG(ha, id) \
2145 ((void *)(ha->mqiobase) +\
2146 (QLA_QUE_PAGE * id)) :\
2147 ((void *)(ha->iobase)))
2148 #define QLA_REQ_QUE_ID(tag) \
2149 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2150 #define QLA_DEFAULT_QUE_QOS 5
2151 #define QLA_PRECONFIG_VPORTS 32
2152 #define QLA_MAX_VPORTS_QLA24XX 128
2153 #define QLA_MAX_VPORTS_QLA25XX 256
2154 /* Response queue data structure */
2158 response_t
*ring_ptr
;
2159 uint32_t __iomem
*rsp_q_in
; /* FWI2-capable only. */
2160 uint32_t __iomem
*rsp_q_out
;
2161 uint16_t ring_index
;
2168 struct qla_hw_data
*hw
;
2169 struct qla_msix_entry
*msix
;
2170 struct req_que
*req
;
2171 srb_t
*status_srb
; /* status continuation entry */
2172 struct work_struct q_work
;
2175 /* Request queue data structure */
2179 request_t
*ring_ptr
;
2180 uint32_t __iomem
*req_q_in
; /* FWI2-capable only. */
2181 uint32_t __iomem
*req_q_out
;
2182 uint16_t ring_index
;
2191 struct rsp_que
*rsp
;
2192 srb_t
*outstanding_cmds
[MAX_OUTSTANDING_COMMANDS
];
2193 uint32_t current_outstanding_cmd
;
2198 * Qlogic host adapter specific data structure.
2200 struct qla_hw_data
{
2201 struct pci_dev
*pdev
;
2203 #define SRB_MIN_REQ 128
2204 mempool_t
*srb_mempool
;
2207 uint32_t mbox_int
:1;
2208 uint32_t mbox_busy
:1;
2210 uint32_t disable_risc_code_load
:1;
2211 uint32_t enable_64bit_addressing
:1;
2212 uint32_t enable_lip_reset
:1;
2213 uint32_t enable_target_reset
:1;
2214 uint32_t enable_lip_full_login
:1;
2215 uint32_t enable_led_scheme
:1;
2216 uint32_t inta_enabled
:1;
2217 uint32_t msi_enabled
:1;
2218 uint32_t msix_enabled
:1;
2219 uint32_t disable_serdes
:1;
2220 uint32_t gpsc_supported
:1;
2221 uint32_t npiv_supported
:1;
2222 uint32_t fce_enabled
:1;
2223 uint32_t fac_supported
:1;
2224 uint32_t chip_reset_done
:1;
2226 uint32_t running_gold_fw
:1;
2227 uint32_t cpu_affinity_enabled
:1;
2230 /* This spinlock is used to protect "io transactions", you must
2231 * acquire it before doing any IO to the card, eg with RD_REG*() and
2232 * WRT_REG*() for the duration of your entire commandtransaction.
2234 * This spinlock is of lower priority than the io request lock.
2237 spinlock_t hardware_lock ____cacheline_aligned
;
2240 device_reg_t __iomem
*iobase
; /* Base I/O address */
2241 resource_size_t pio_address
;
2243 #define MIN_IOBASE_LEN 0x100
2244 /* Multi queue data structs */
2245 device_reg_t __iomem
*mqiobase
;
2246 uint16_t msix_count
;
2248 struct req_que
**req_q_map
;
2249 struct rsp_que
**rsp_q_map
;
2250 unsigned long req_qid_map
[(QLA_MAX_QUEUES
/ 8) / sizeof(unsigned long)];
2251 unsigned long rsp_qid_map
[(QLA_MAX_QUEUES
/ 8) / sizeof(unsigned long)];
2252 uint8_t max_req_queues
;
2253 uint8_t max_rsp_queues
;
2254 struct qla_npiv_entry
*npiv_info
;
2255 uint16_t nvram_npiv_size
;
2257 uint16_t switch_cap
;
2258 #define FLOGI_SEQ_DEL BIT_8
2259 #define FLOGI_MID_SUPPORT BIT_10
2260 #define FLOGI_VSAN_SUPPORT BIT_12
2261 #define FLOGI_SP_SUPPORT BIT_13
2263 uint8_t port_no
; /* Physical port of adapter */
2265 /* Timeout timers. */
2266 uint8_t loop_down_abort_time
; /* port down timer */
2267 atomic_t loop_down_timer
; /* loop down timer */
2268 uint8_t link_down_timeout
; /* link down timeout */
2269 uint16_t max_loop_id
;
2272 uint16_t min_external_loopid
; /* First external loop Id */
2274 #define PORT_SPEED_UNKNOWN 0xFFFF
2275 #define PORT_SPEED_1GB 0x00
2276 #define PORT_SPEED_2GB 0x01
2277 #define PORT_SPEED_4GB 0x03
2278 #define PORT_SPEED_8GB 0x04
2279 #define PORT_SPEED_10GB 0x13
2280 uint16_t link_data_rate
; /* F/W operating speed */
2282 uint8_t current_topology
;
2283 uint8_t prev_topology
;
2284 #define ISP_CFG_NL 1
2286 #define ISP_CFG_FL 4
2289 uint8_t operating_mode
; /* F/W operating mode */
2294 uint8_t interrupts_on
;
2295 uint32_t isp_abort_cnt
;
2297 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2298 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2299 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2300 uint32_t device_type
;
2301 #define DT_ISP2100 BIT_0
2302 #define DT_ISP2200 BIT_1
2303 #define DT_ISP2300 BIT_2
2304 #define DT_ISP2312 BIT_3
2305 #define DT_ISP2322 BIT_4
2306 #define DT_ISP6312 BIT_5
2307 #define DT_ISP6322 BIT_6
2308 #define DT_ISP2422 BIT_7
2309 #define DT_ISP2432 BIT_8
2310 #define DT_ISP5422 BIT_9
2311 #define DT_ISP5432 BIT_10
2312 #define DT_ISP2532 BIT_11
2313 #define DT_ISP8432 BIT_12
2314 #define DT_ISP8001 BIT_13
2315 #define DT_ISP_LAST (DT_ISP8001 << 1)
2317 #define DT_IIDMA BIT_26
2318 #define DT_FWI2 BIT_27
2319 #define DT_ZIO_SUPPORTED BIT_28
2320 #define DT_OEM_001 BIT_29
2321 #define DT_ISP2200A BIT_30
2322 #define DT_EXTENDED_IDS BIT_31
2323 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2324 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2325 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2326 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2327 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2328 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2329 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2330 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2331 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2332 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2333 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2334 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2335 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2336 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2337 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2339 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2340 IS_QLA6312(ha) || IS_QLA6322(ha))
2341 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2342 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2343 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2344 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2345 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2347 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2348 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2349 IS_QLA25XX(ha) || IS_QLA81XX(ha))
2350 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2351 (ha)->flags.msix_enabled)
2352 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2353 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2355 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2356 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2357 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2358 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2359 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2361 /* HBA serial number */
2366 /* NVRAM configuration data */
2367 #define MAX_NVRAM_SIZE 4096
2368 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2369 uint16_t nvram_size
;
2370 uint16_t nvram_base
;
2376 uint16_t loop_reset_delay
;
2377 uint8_t retry_count
;
2378 uint8_t login_timeout
;
2380 int port_down_retry_count
;
2383 uint32_t login_retry_count
;
2384 /* SNS command interfaces. */
2385 ms_iocb_entry_t
*ms_iocb
;
2386 dma_addr_t ms_iocb_dma
;
2387 struct ct_sns_pkt
*ct_sns
;
2388 dma_addr_t ct_sns_dma
;
2389 /* SNS command interfaces for 2200. */
2390 struct sns_cmd_pkt
*sns_cmd
;
2391 dma_addr_t sns_cmd_dma
;
2393 #define SFP_DEV_SIZE 256
2394 #define SFP_BLOCK_SIZE 64
2396 dma_addr_t sfp_data_dma
;
2399 dma_addr_t edc_data_dma
;
2400 uint16_t edc_data_len
;
2402 #define XGMAC_DATA_SIZE PAGE_SIZE
2404 dma_addr_t xgmac_data_dma
;
2406 #define DCBX_TLV_DATA_SIZE PAGE_SIZE
2408 dma_addr_t dcbx_tlv_dma
;
2410 struct task_struct
*dpc_thread
;
2411 uint8_t dpc_active
; /* DPC routine is active */
2413 dma_addr_t gid_list_dma
;
2414 struct gid_list_info
*gid_list
;
2415 int gid_list_info_size
;
2417 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2418 #define DMA_POOL_SIZE 256
2419 struct dma_pool
*s_dma_pool
;
2421 dma_addr_t init_cb_dma
;
2424 dma_addr_t ex_init_cb_dma
;
2425 struct ex_init_cb_81xx
*ex_init_cb
;
2427 /* These are used by mailbox operations. */
2428 volatile uint16_t mailbox_out
[MAILBOX_REGISTER_COUNT
];
2431 unsigned long mbx_cmd_flags
;
2432 #define MBX_INTERRUPT 1
2433 #define MBX_INTR_WAIT 2
2434 #define MBX_UPDATE_FLASH_ACTIVE 3
2436 struct mutex vport_lock
; /* Virtual port synchronization */
2437 struct completion mbx_cmd_comp
; /* Serialize mbx access */
2438 struct completion mbx_intr_comp
; /* Used for completion notification */
2440 /* Basic firmware related information. */
2441 uint16_t fw_major_version
;
2442 uint16_t fw_minor_version
;
2443 uint16_t fw_subminor_version
;
2444 uint16_t fw_attributes
;
2445 uint32_t fw_memory_size
;
2446 uint32_t fw_transfer_size
;
2447 uint32_t fw_srisc_address
;
2448 #define RISC_START_ADDRESS_2100 0x1000
2449 #define RISC_START_ADDRESS_2300 0x800
2450 #define RISC_START_ADDRESS_2400 0x100000
2451 uint16_t fw_xcb_count
;
2453 uint16_t fw_options
[16]; /* slots: 1,2,3,10,11 */
2454 uint8_t fw_seriallink_options
[4];
2455 uint16_t fw_seriallink_options24
[4];
2457 uint8_t mpi_version
[3];
2458 uint32_t mpi_capabilities
;
2459 uint8_t phy_version
[3];
2461 /* Firmware dump information. */
2462 struct qla2xxx_fw_dump
*fw_dump
;
2463 uint32_t fw_dump_len
;
2465 int fw_dump_reading
;
2469 uint32_t chain_offset
;
2470 struct dentry
*dfs_dir
;
2471 struct dentry
*dfs_fce
;
2476 uint64_t fce_wr
, fce_rd
;
2477 struct mutex fce_mutex
;
2480 uint16_t chip_revision
;
2482 uint16_t product_id
[4];
2484 uint8_t model_number
[16+1];
2485 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2486 char model_desc
[80];
2487 uint8_t adapter_id
[16+1];
2489 /* Option ROM information. */
2490 char *optrom_buffer
;
2491 uint32_t optrom_size
;
2493 #define QLA_SWAITING 0
2494 #define QLA_SREADING 1
2495 #define QLA_SWRITING 2
2496 uint32_t optrom_region_start
;
2497 uint32_t optrom_region_size
;
2499 /* PCI expansion ROM image information. */
2500 #define ROM_CODE_TYPE_BIOS 0
2501 #define ROM_CODE_TYPE_FCODE 1
2502 #define ROM_CODE_TYPE_EFI 3
2503 uint8_t bios_revision
[2];
2504 uint8_t efi_revision
[2];
2505 uint8_t fcode_revision
[16];
2506 uint32_t fw_revision
[4];
2508 /* Offsets for flash/nvram access (set to ~0 if not used). */
2509 uint32_t flash_conf_off
;
2510 uint32_t flash_data_off
;
2511 uint32_t nvram_conf_off
;
2512 uint32_t nvram_data_off
;
2514 uint32_t fdt_wrt_disable
;
2515 uint32_t fdt_erase_cmd
;
2516 uint32_t fdt_block_size
;
2517 uint32_t fdt_unprotect_sec_cmd
;
2518 uint32_t fdt_protect_sec_cmd
;
2520 uint32_t flt_region_flt
;
2521 uint32_t flt_region_fdt
;
2522 uint32_t flt_region_boot
;
2523 uint32_t flt_region_fw
;
2524 uint32_t flt_region_vpd_nvram
;
2525 uint32_t flt_region_vpd
;
2526 uint32_t flt_region_nvram
;
2527 uint32_t flt_region_npiv_conf
;
2528 uint32_t flt_region_gold_fw
;
2530 /* Needed for BEACON */
2531 uint16_t beacon_blink_led
;
2532 uint8_t beacon_color_state
;
2533 #define QLA_LED_GRN_ON 0x01
2534 #define QLA_LED_YLW_ON 0x02
2535 #define QLA_LED_ABR_ON 0x04
2536 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2537 /* ISP2322: red, green, amber. */
2540 struct fc_host_statistics fc_host_stat
;
2542 struct qla_msix_entry
*msix_entries
;
2544 struct list_head vp_list
; /* list of VP */
2545 unsigned long vp_idx_map
[(MAX_MULTI_ID_FABRIC
/ 8) /
2546 sizeof(unsigned long)];
2547 uint16_t num_vhosts
; /* number of vports created */
2548 uint16_t num_vsans
; /* number of vsan created */
2549 uint16_t max_npiv_vports
; /* 63 or 125 per topoloty */
2550 int cur_vport_count
;
2552 struct qla_chip_state_84xx
*cs84xx
;
2553 struct qla_statistics qla_stats
;
2554 struct isp_operations
*isp_ops
;
2555 struct workqueue_struct
*wq
;
2559 * Qlogic scsi host structure
2561 typedef struct scsi_qla_host
{
2562 struct list_head list
;
2563 struct list_head vp_fcports
; /* list of fcports */
2564 struct list_head work_list
;
2565 spinlock_t work_lock
;
2567 /* Commonly used flags and state information. */
2568 struct Scsi_Host
*host
;
2569 unsigned long host_no
;
2570 uint8_t host_str
[16];
2573 uint32_t init_done
:1;
2575 uint32_t rscn_queue_overflow
:1;
2576 uint32_t reset_active
:1;
2578 uint32_t management_server_logged_in
:1;
2579 uint32_t process_response_queue
:1;
2582 atomic_t loop_state
;
2583 #define LOOP_TIMEOUT 1
2586 #define LOOP_UPDATE 4
2587 #define LOOP_READY 5
2590 unsigned long dpc_flags
;
2591 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2592 #define RESET_ACTIVE 1
2593 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2594 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2595 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2596 #define LOOP_RESYNC_ACTIVE 5
2597 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2598 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2599 #define RELOGIN_NEEDED 8
2600 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2601 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2602 #define BEACON_BLINK_NEEDED 11
2603 #define REGISTER_FDMI_NEEDED 12
2604 #define FCPORT_UPDATE_NEEDED 13
2605 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2606 #define UNLOADING 15
2607 #define NPIV_CONFIG_NEEDED 16
2609 uint32_t device_flags
;
2610 #define SWITCH_FOUND BIT_0
2611 #define DFLG_NO_CABLE BIT_1
2613 /* ISP configuration data. */
2614 uint16_t loop_id
; /* Host adapter loop id */
2616 port_id_t d_id
; /* Host adapter port id */
2617 uint8_t marker_needed
;
2618 uint16_t mgmt_svr_loop_id
;
2623 uint32_t rscn_queue
[MAX_RSCN_COUNT
];
2624 uint8_t rscn_in_ptr
;
2625 uint8_t rscn_out_ptr
;
2627 /* Timeout timers. */
2628 uint8_t loop_down_abort_time
; /* port down timer */
2629 atomic_t loop_down_timer
; /* loop down timer */
2630 uint8_t link_down_timeout
; /* link down timeout */
2632 uint32_t timer_active
;
2633 struct timer_list timer
;
2635 uint8_t node_name
[WWN_SIZE
];
2636 uint8_t port_name
[WWN_SIZE
];
2637 uint8_t fabric_node_name
[WWN_SIZE
];
2639 uint16_t fcoe_vlan_id
;
2640 uint16_t fcoe_fcf_idx
;
2641 uint8_t fcoe_vn_port_mac
[6];
2643 uint32_t vp_abort_cnt
;
2645 struct fc_vport
*fc_vport
; /* holds fc_vport * for each vport */
2646 uint16_t vp_idx
; /* vport ID */
2648 unsigned long vp_flags
;
2649 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2650 #define VP_CREATE_NEEDED 1
2651 #define VP_BIND_NEEDED 2
2652 #define VP_DELETE_NEEDED 3
2653 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2655 #define VP_OFFLINE 0
2658 // #define VP_DISABLE 3
2659 uint16_t vp_err_state
;
2660 uint16_t vp_prev_err_state
;
2661 #define VP_ERR_UNKWN 0
2662 #define VP_ERR_PORTDWN 1
2663 #define VP_ERR_FAB_UNSUPPORTED 2
2664 #define VP_ERR_FAB_NORESOURCES 3
2665 #define VP_ERR_FAB_LOGOUT 4
2666 #define VP_ERR_ADAP_NORESOURCES 5
2667 struct qla_hw_data
*hw
;
2668 struct req_que
*req
;
2672 * Macros to help code, maintain, etc.
2674 #define LOOP_TRANSITION(ha) \
2675 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2676 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2677 atomic_read(&ha->loop_state) == LOOP_DOWN)
2679 #define qla_printk(level, ha, format, arg...) \
2680 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2683 * qla2x00 local function return status codes
2685 #define MBS_MASK 0x3fff
2687 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2688 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2689 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2690 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2691 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2692 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2693 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2694 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2695 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2696 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2698 #define QLA_FUNCTION_TIMEOUT 0x100
2699 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2700 #define QLA_FUNCTION_FAILED 0x102
2701 #define QLA_MEMORY_ALLOC_FAILED 0x103
2702 #define QLA_LOCK_TIMEOUT 0x104
2703 #define QLA_ABORTED 0x105
2704 #define QLA_SUSPENDED 0x106
2705 #define QLA_BUSY 0x107
2706 #define QLA_RSCNS_HANDLED 0x108
2707 #define QLA_ALREADY_REGISTERED 0x109
2709 #define NVRAM_DELAY() udelay(10)
2711 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2714 * Flash support definitions
2716 #define OPTROM_SIZE_2300 0x20000
2717 #define OPTROM_SIZE_2322 0x100000
2718 #define OPTROM_SIZE_24XX 0x100000
2719 #define OPTROM_SIZE_25XX 0x200000
2720 #define OPTROM_SIZE_81XX 0x400000
2722 #include "qla_gbl.h"
2723 #include "qla_dbg.h"
2724 #include "qla_inline.h"
2726 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)