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[mirror_ubuntu-hirsute-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35
36 #include "qla_bsg.h"
37 #include "qla_nx.h"
38 #define QLA2XXX_DRIVER_NAME "qla2xxx"
39 #define QLA2XXX_APIDEV "ql2xapidev"
40
41 /*
42 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
43 * but that's fine as we don't look at the last 24 ones for
44 * ISP2100 HBAs.
45 */
46 #define MAILBOX_REGISTER_COUNT_2100 8
47 #define MAILBOX_REGISTER_COUNT 32
48
49 #define QLA2200A_RISC_ROM_VER 4
50 #define FPM_2300 6
51 #define FPM_2310 7
52
53 #include "qla_settings.h"
54
55 /*
56 * Data bit definitions
57 */
58 #define BIT_0 0x1
59 #define BIT_1 0x2
60 #define BIT_2 0x4
61 #define BIT_3 0x8
62 #define BIT_4 0x10
63 #define BIT_5 0x20
64 #define BIT_6 0x40
65 #define BIT_7 0x80
66 #define BIT_8 0x100
67 #define BIT_9 0x200
68 #define BIT_10 0x400
69 #define BIT_11 0x800
70 #define BIT_12 0x1000
71 #define BIT_13 0x2000
72 #define BIT_14 0x4000
73 #define BIT_15 0x8000
74 #define BIT_16 0x10000
75 #define BIT_17 0x20000
76 #define BIT_18 0x40000
77 #define BIT_19 0x80000
78 #define BIT_20 0x100000
79 #define BIT_21 0x200000
80 #define BIT_22 0x400000
81 #define BIT_23 0x800000
82 #define BIT_24 0x1000000
83 #define BIT_25 0x2000000
84 #define BIT_26 0x4000000
85 #define BIT_27 0x8000000
86 #define BIT_28 0x10000000
87 #define BIT_29 0x20000000
88 #define BIT_30 0x40000000
89 #define BIT_31 0x80000000
90
91 #define LSB(x) ((uint8_t)(x))
92 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
93
94 #define LSW(x) ((uint16_t)(x))
95 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
96
97 #define LSD(x) ((uint32_t)((uint64_t)(x)))
98 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
99
100 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
101
102 /*
103 * I/O register
104 */
105
106 #define RD_REG_BYTE(addr) readb(addr)
107 #define RD_REG_WORD(addr) readw(addr)
108 #define RD_REG_DWORD(addr) readl(addr)
109 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
110 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
111 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
112 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
113 #define WRT_REG_WORD(addr, data) writew(data,addr)
114 #define WRT_REG_DWORD(addr, data) writel(data,addr)
115
116 /*
117 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
118 * 133Mhz slot.
119 */
120 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
121 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
122
123 /*
124 * Fibre Channel device definitions.
125 */
126 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
127 #define MAX_FIBRE_DEVICES 512
128 #define MAX_FIBRE_LUNS 0xFFFF
129 #define MAX_RSCN_COUNT 32
130 #define MAX_HOST_COUNT 16
131
132 /*
133 * Host adapter default definitions.
134 */
135 #define MAX_BUSES 1 /* We only have one bus today */
136 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
137 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
138 #define MIN_LUNS 8
139 #define MAX_LUNS MAX_FIBRE_LUNS
140 #define MAX_CMDS_PER_LUN 255
141
142 /*
143 * Fibre Channel device definitions.
144 */
145 #define SNS_LAST_LOOP_ID_2100 0xfe
146 #define SNS_LAST_LOOP_ID_2300 0x7ff
147
148 #define LAST_LOCAL_LOOP_ID 0x7d
149 #define SNS_FL_PORT 0x7e
150 #define FABRIC_CONTROLLER 0x7f
151 #define SIMPLE_NAME_SERVER 0x80
152 #define SNS_FIRST_LOOP_ID 0x81
153 #define MANAGEMENT_SERVER 0xfe
154 #define BROADCAST 0xff
155
156 /*
157 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
158 * valid range of an N-PORT id is 0 through 0x7ef.
159 */
160 #define NPH_LAST_HANDLE 0x7ef
161 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
162 #define NPH_SNS 0x7fc /* FFFFFC */
163 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
164 #define NPH_F_PORT 0x7fe /* FFFFFE */
165 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
166
167 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
168 #include "qla_fw.h"
169
170 /*
171 * Timeout timer counts in seconds
172 */
173 #define PORT_RETRY_TIME 1
174 #define LOOP_DOWN_TIMEOUT 60
175 #define LOOP_DOWN_TIME 255 /* 240 */
176 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
177
178 /* Maximum outstanding commands in ISP queues (1-65535) */
179 #define MAX_OUTSTANDING_COMMANDS 1024
180
181 /* ISP request and response entry counts (37-65535) */
182 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
183 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
184 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
185 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
186 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
187 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
188
189 struct req_que;
190
191 /*
192 * SCSI Request Block
193 */
194 typedef struct srb {
195 struct fc_port *fcport;
196 uint32_t handle;
197
198 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
199
200 uint16_t flags;
201
202 uint32_t request_sense_length;
203 uint8_t *request_sense_ptr;
204
205 void *ctx;
206 } srb_t;
207
208 /*
209 * SRB flag definitions
210 */
211 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
212 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* FCP command in IOCB */
213
214 /*
215 * SRB extensions.
216 */
217 struct srb_ctx {
218 #define SRB_LOGIN_CMD 1
219 #define SRB_LOGOUT_CMD 2
220 uint16_t type;
221 struct timer_list timer;
222
223 void (*free)(srb_t *sp);
224 void (*timeout)(srb_t *sp);
225 };
226
227 struct srb_logio {
228 struct srb_ctx ctx;
229
230 #define SRB_LOGIN_RETRIED BIT_0
231 #define SRB_LOGIN_COND_PLOGI BIT_1
232 #define SRB_LOGIN_SKIP_PRLI BIT_2
233 uint16_t flags;
234 };
235
236 struct srb_bsg_ctx {
237 #define SRB_ELS_CMD_RPT 3
238 #define SRB_ELS_CMD_HST 4
239 #define SRB_CT_CMD 5
240 uint16_t type;
241 };
242
243 struct srb_bsg {
244 struct srb_bsg_ctx ctx;
245 struct fc_bsg_job *bsg_job;
246 };
247
248 struct msg_echo_lb {
249 dma_addr_t send_dma;
250 dma_addr_t rcv_dma;
251 uint16_t req_sg_cnt;
252 uint16_t rsp_sg_cnt;
253 uint16_t options;
254 uint32_t transfer_size;
255 };
256
257 /*
258 * ISP I/O Register Set structure definitions.
259 */
260 struct device_reg_2xxx {
261 uint16_t flash_address; /* Flash BIOS address */
262 uint16_t flash_data; /* Flash BIOS data */
263 uint16_t unused_1[1]; /* Gap */
264 uint16_t ctrl_status; /* Control/Status */
265 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
266 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
267 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
268
269 uint16_t ictrl; /* Interrupt control */
270 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
271 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
272
273 uint16_t istatus; /* Interrupt status */
274 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
275
276 uint16_t semaphore; /* Semaphore */
277 uint16_t nvram; /* NVRAM register. */
278 #define NVR_DESELECT 0
279 #define NVR_BUSY BIT_15
280 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
281 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
282 #define NVR_DATA_IN BIT_3
283 #define NVR_DATA_OUT BIT_2
284 #define NVR_SELECT BIT_1
285 #define NVR_CLOCK BIT_0
286
287 #define NVR_WAIT_CNT 20000
288
289 union {
290 struct {
291 uint16_t mailbox0;
292 uint16_t mailbox1;
293 uint16_t mailbox2;
294 uint16_t mailbox3;
295 uint16_t mailbox4;
296 uint16_t mailbox5;
297 uint16_t mailbox6;
298 uint16_t mailbox7;
299 uint16_t unused_2[59]; /* Gap */
300 } __attribute__((packed)) isp2100;
301 struct {
302 /* Request Queue */
303 uint16_t req_q_in; /* In-Pointer */
304 uint16_t req_q_out; /* Out-Pointer */
305 /* Response Queue */
306 uint16_t rsp_q_in; /* In-Pointer */
307 uint16_t rsp_q_out; /* Out-Pointer */
308
309 /* RISC to Host Status */
310 uint32_t host_status;
311 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
312 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
313
314 /* Host to Host Semaphore */
315 uint16_t host_semaphore;
316 uint16_t unused_3[17]; /* Gap */
317 uint16_t mailbox0;
318 uint16_t mailbox1;
319 uint16_t mailbox2;
320 uint16_t mailbox3;
321 uint16_t mailbox4;
322 uint16_t mailbox5;
323 uint16_t mailbox6;
324 uint16_t mailbox7;
325 uint16_t mailbox8;
326 uint16_t mailbox9;
327 uint16_t mailbox10;
328 uint16_t mailbox11;
329 uint16_t mailbox12;
330 uint16_t mailbox13;
331 uint16_t mailbox14;
332 uint16_t mailbox15;
333 uint16_t mailbox16;
334 uint16_t mailbox17;
335 uint16_t mailbox18;
336 uint16_t mailbox19;
337 uint16_t mailbox20;
338 uint16_t mailbox21;
339 uint16_t mailbox22;
340 uint16_t mailbox23;
341 uint16_t mailbox24;
342 uint16_t mailbox25;
343 uint16_t mailbox26;
344 uint16_t mailbox27;
345 uint16_t mailbox28;
346 uint16_t mailbox29;
347 uint16_t mailbox30;
348 uint16_t mailbox31;
349 uint16_t fb_cmd;
350 uint16_t unused_4[10]; /* Gap */
351 } __attribute__((packed)) isp2300;
352 } u;
353
354 uint16_t fpm_diag_config;
355 uint16_t unused_5[0x4]; /* Gap */
356 uint16_t risc_hw;
357 uint16_t unused_5_1; /* Gap */
358 uint16_t pcr; /* Processor Control Register. */
359 uint16_t unused_6[0x5]; /* Gap */
360 uint16_t mctr; /* Memory Configuration and Timing. */
361 uint16_t unused_7[0x3]; /* Gap */
362 uint16_t fb_cmd_2100; /* Unused on 23XX */
363 uint16_t unused_8[0x3]; /* Gap */
364 uint16_t hccr; /* Host command & control register. */
365 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
366 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
367 /* HCCR commands */
368 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
369 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
370 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
371 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
372 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
373 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
374 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
375 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
376
377 uint16_t unused_9[5]; /* Gap */
378 uint16_t gpiod; /* GPIO Data register. */
379 uint16_t gpioe; /* GPIO Enable register. */
380 #define GPIO_LED_MASK 0x00C0
381 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
382 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
383 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
384 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
385 #define GPIO_LED_ALL_OFF 0x0000
386 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
387 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
388
389 union {
390 struct {
391 uint16_t unused_10[8]; /* Gap */
392 uint16_t mailbox8;
393 uint16_t mailbox9;
394 uint16_t mailbox10;
395 uint16_t mailbox11;
396 uint16_t mailbox12;
397 uint16_t mailbox13;
398 uint16_t mailbox14;
399 uint16_t mailbox15;
400 uint16_t mailbox16;
401 uint16_t mailbox17;
402 uint16_t mailbox18;
403 uint16_t mailbox19;
404 uint16_t mailbox20;
405 uint16_t mailbox21;
406 uint16_t mailbox22;
407 uint16_t mailbox23; /* Also probe reg. */
408 } __attribute__((packed)) isp2200;
409 } u_end;
410 };
411
412 struct device_reg_25xxmq {
413 uint32_t req_q_in;
414 uint32_t req_q_out;
415 uint32_t rsp_q_in;
416 uint32_t rsp_q_out;
417 };
418
419 typedef union {
420 struct device_reg_2xxx isp;
421 struct device_reg_24xx isp24;
422 struct device_reg_25xxmq isp25mq;
423 struct device_reg_82xx isp82;
424 } device_reg_t;
425
426 #define ISP_REQ_Q_IN(ha, reg) \
427 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
428 &(reg)->u.isp2100.mailbox4 : \
429 &(reg)->u.isp2300.req_q_in)
430 #define ISP_REQ_Q_OUT(ha, reg) \
431 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
432 &(reg)->u.isp2100.mailbox4 : \
433 &(reg)->u.isp2300.req_q_out)
434 #define ISP_RSP_Q_IN(ha, reg) \
435 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
436 &(reg)->u.isp2100.mailbox5 : \
437 &(reg)->u.isp2300.rsp_q_in)
438 #define ISP_RSP_Q_OUT(ha, reg) \
439 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
440 &(reg)->u.isp2100.mailbox5 : \
441 &(reg)->u.isp2300.rsp_q_out)
442
443 #define MAILBOX_REG(ha, reg, num) \
444 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
445 (num < 8 ? \
446 &(reg)->u.isp2100.mailbox0 + (num) : \
447 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
448 &(reg)->u.isp2300.mailbox0 + (num))
449 #define RD_MAILBOX_REG(ha, reg, num) \
450 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
451 #define WRT_MAILBOX_REG(ha, reg, num, data) \
452 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
453
454 #define FB_CMD_REG(ha, reg) \
455 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
456 &(reg)->fb_cmd_2100 : \
457 &(reg)->u.isp2300.fb_cmd)
458 #define RD_FB_CMD_REG(ha, reg) \
459 RD_REG_WORD(FB_CMD_REG(ha, reg))
460 #define WRT_FB_CMD_REG(ha, reg, data) \
461 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
462
463 typedef struct {
464 uint32_t out_mb; /* outbound from driver */
465 uint32_t in_mb; /* Incoming from RISC */
466 uint16_t mb[MAILBOX_REGISTER_COUNT];
467 long buf_size;
468 void *bufp;
469 uint32_t tov;
470 uint8_t flags;
471 #define MBX_DMA_IN BIT_0
472 #define MBX_DMA_OUT BIT_1
473 #define IOCTL_CMD BIT_2
474 } mbx_cmd_t;
475
476 #define MBX_TOV_SECONDS 30
477
478 /*
479 * ISP product identification definitions in mailboxes after reset.
480 */
481 #define PROD_ID_1 0x4953
482 #define PROD_ID_2 0x0000
483 #define PROD_ID_2a 0x5020
484 #define PROD_ID_3 0x2020
485
486 /*
487 * ISP mailbox Self-Test status codes
488 */
489 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
490 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
491 #define MBS_BUSY 4 /* Busy. */
492
493 /*
494 * ISP mailbox command complete status codes
495 */
496 #define MBS_COMMAND_COMPLETE 0x4000
497 #define MBS_INVALID_COMMAND 0x4001
498 #define MBS_HOST_INTERFACE_ERROR 0x4002
499 #define MBS_TEST_FAILED 0x4003
500 #define MBS_COMMAND_ERROR 0x4005
501 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
502 #define MBS_PORT_ID_USED 0x4007
503 #define MBS_LOOP_ID_USED 0x4008
504 #define MBS_ALL_IDS_IN_USE 0x4009
505 #define MBS_NOT_LOGGED_IN 0x400A
506 #define MBS_LINK_DOWN_ERROR 0x400B
507 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
508
509 /*
510 * ISP mailbox asynchronous event status codes
511 */
512 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
513 #define MBA_RESET 0x8001 /* Reset Detected. */
514 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
515 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
516 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
517 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
518 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
519 /* occurred. */
520 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
521 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
522 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
523 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
524 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
525 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
526 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
527 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
528 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
529 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
530 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
531 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
532 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
533 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
534 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
535 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
536 /* used. */
537 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
538 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
539 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
540 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
541 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
542 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
543 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
544 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
545 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
546 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
547 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
548 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
549 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
550 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
551
552 /* ISP mailbox loopback echo diagnostic error code */
553 #define MBS_LB_RESET 0x17
554 /*
555 * Firmware options 1, 2, 3.
556 */
557 #define FO1_AE_ON_LIPF8 BIT_0
558 #define FO1_AE_ALL_LIP_RESET BIT_1
559 #define FO1_CTIO_RETRY BIT_3
560 #define FO1_DISABLE_LIP_F7_SW BIT_4
561 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
562 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
563 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
564 #define FO1_SET_EMPHASIS_SWING BIT_8
565 #define FO1_AE_AUTO_BYPASS BIT_9
566 #define FO1_ENABLE_PURE_IOCB BIT_10
567 #define FO1_AE_PLOGI_RJT BIT_11
568 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
569 #define FO1_AE_QUEUE_FULL BIT_13
570
571 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
572 #define FO2_REV_LOOPBACK BIT_1
573
574 #define FO3_ENABLE_EMERG_IOCB BIT_0
575 #define FO3_AE_RND_ERROR BIT_1
576
577 /* 24XX additional firmware options */
578 #define ADD_FO_COUNT 3
579 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
580 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
581
582 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
583
584 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
585
586 /*
587 * ISP mailbox commands
588 */
589 #define MBC_LOAD_RAM 1 /* Load RAM. */
590 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
591 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
592 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
593 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
594 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
595 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
596 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
597 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
598 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
599 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
600 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
601 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
602 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
603 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
604 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
605 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
606 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
607 #define MBC_RESET 0x18 /* Reset. */
608 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
609 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
610 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
611 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
612 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
613 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
614 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
615 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
616 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
617 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
618 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
619 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
620 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
621 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
622 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
623 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
624 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
625 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
626 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
627 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
628 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
629 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
630 /* Initialization Procedure */
631 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
632 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
633 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
634 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
635 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
636 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
637 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
638 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
639 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
640 #define MBC_LIP_RESET 0x6c /* LIP reset. */
641 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
642 /* commandd. */
643 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
644 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
645 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
646 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
647 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
648 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
649 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
650 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
651 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
652 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
653 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
654
655 /*
656 * ISP24xx mailbox commands
657 */
658 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
659 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
660 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
661 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
662 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
663 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
664 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
665 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
666 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
667 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
668 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
669 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
670 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
671 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
672 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
673 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
674
675 /* Firmware return data sizes */
676 #define FCAL_MAP_SIZE 128
677
678 /* Mailbox bit definitions for out_mb and in_mb */
679 #define MBX_31 BIT_31
680 #define MBX_30 BIT_30
681 #define MBX_29 BIT_29
682 #define MBX_28 BIT_28
683 #define MBX_27 BIT_27
684 #define MBX_26 BIT_26
685 #define MBX_25 BIT_25
686 #define MBX_24 BIT_24
687 #define MBX_23 BIT_23
688 #define MBX_22 BIT_22
689 #define MBX_21 BIT_21
690 #define MBX_20 BIT_20
691 #define MBX_19 BIT_19
692 #define MBX_18 BIT_18
693 #define MBX_17 BIT_17
694 #define MBX_16 BIT_16
695 #define MBX_15 BIT_15
696 #define MBX_14 BIT_14
697 #define MBX_13 BIT_13
698 #define MBX_12 BIT_12
699 #define MBX_11 BIT_11
700 #define MBX_10 BIT_10
701 #define MBX_9 BIT_9
702 #define MBX_8 BIT_8
703 #define MBX_7 BIT_7
704 #define MBX_6 BIT_6
705 #define MBX_5 BIT_5
706 #define MBX_4 BIT_4
707 #define MBX_3 BIT_3
708 #define MBX_2 BIT_2
709 #define MBX_1 BIT_1
710 #define MBX_0 BIT_0
711
712 /*
713 * Firmware state codes from get firmware state mailbox command
714 */
715 #define FSTATE_CONFIG_WAIT 0
716 #define FSTATE_WAIT_AL_PA 1
717 #define FSTATE_WAIT_LOGIN 2
718 #define FSTATE_READY 3
719 #define FSTATE_LOSS_OF_SYNC 4
720 #define FSTATE_ERROR 5
721 #define FSTATE_REINIT 6
722 #define FSTATE_NON_PART 7
723
724 #define FSTATE_CONFIG_CORRECT 0
725 #define FSTATE_P2P_RCV_LIP 1
726 #define FSTATE_P2P_CHOOSE_LOOP 2
727 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
728 #define FSTATE_FATAL_ERROR 4
729 #define FSTATE_LOOP_BACK_CONN 5
730
731 /*
732 * Port Database structure definition
733 * Little endian except where noted.
734 */
735 #define PORT_DATABASE_SIZE 128 /* bytes */
736 typedef struct {
737 uint8_t options;
738 uint8_t control;
739 uint8_t master_state;
740 uint8_t slave_state;
741 uint8_t reserved[2];
742 uint8_t hard_address;
743 uint8_t reserved_1;
744 uint8_t port_id[4];
745 uint8_t node_name[WWN_SIZE];
746 uint8_t port_name[WWN_SIZE];
747 uint16_t execution_throttle;
748 uint16_t execution_count;
749 uint8_t reset_count;
750 uint8_t reserved_2;
751 uint16_t resource_allocation;
752 uint16_t current_allocation;
753 uint16_t queue_head;
754 uint16_t queue_tail;
755 uint16_t transmit_execution_list_next;
756 uint16_t transmit_execution_list_previous;
757 uint16_t common_features;
758 uint16_t total_concurrent_sequences;
759 uint16_t RO_by_information_category;
760 uint8_t recipient;
761 uint8_t initiator;
762 uint16_t receive_data_size;
763 uint16_t concurrent_sequences;
764 uint16_t open_sequences_per_exchange;
765 uint16_t lun_abort_flags;
766 uint16_t lun_stop_flags;
767 uint16_t stop_queue_head;
768 uint16_t stop_queue_tail;
769 uint16_t port_retry_timer;
770 uint16_t next_sequence_id;
771 uint16_t frame_count;
772 uint16_t PRLI_payload_length;
773 uint8_t prli_svc_param_word_0[2]; /* Big endian */
774 /* Bits 15-0 of word 0 */
775 uint8_t prli_svc_param_word_3[2]; /* Big endian */
776 /* Bits 15-0 of word 3 */
777 uint16_t loop_id;
778 uint16_t extended_lun_info_list_pointer;
779 uint16_t extended_lun_stop_list_pointer;
780 } port_database_t;
781
782 /*
783 * Port database slave/master states
784 */
785 #define PD_STATE_DISCOVERY 0
786 #define PD_STATE_WAIT_DISCOVERY_ACK 1
787 #define PD_STATE_PORT_LOGIN 2
788 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
789 #define PD_STATE_PROCESS_LOGIN 4
790 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
791 #define PD_STATE_PORT_LOGGED_IN 6
792 #define PD_STATE_PORT_UNAVAILABLE 7
793 #define PD_STATE_PROCESS_LOGOUT 8
794 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
795 #define PD_STATE_PORT_LOGOUT 10
796 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
797
798
799 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
800 #define QLA_ZIO_DISABLED 0
801 #define QLA_ZIO_DEFAULT_TIMER 2
802
803 /*
804 * ISP Initialization Control Block.
805 * Little endian except where noted.
806 */
807 #define ICB_VERSION 1
808 typedef struct {
809 uint8_t version;
810 uint8_t reserved_1;
811
812 /*
813 * LSB BIT 0 = Enable Hard Loop Id
814 * LSB BIT 1 = Enable Fairness
815 * LSB BIT 2 = Enable Full-Duplex
816 * LSB BIT 3 = Enable Fast Posting
817 * LSB BIT 4 = Enable Target Mode
818 * LSB BIT 5 = Disable Initiator Mode
819 * LSB BIT 6 = Enable ADISC
820 * LSB BIT 7 = Enable Target Inquiry Data
821 *
822 * MSB BIT 0 = Enable PDBC Notify
823 * MSB BIT 1 = Non Participating LIP
824 * MSB BIT 2 = Descending Loop ID Search
825 * MSB BIT 3 = Acquire Loop ID in LIPA
826 * MSB BIT 4 = Stop PortQ on Full Status
827 * MSB BIT 5 = Full Login after LIP
828 * MSB BIT 6 = Node Name Option
829 * MSB BIT 7 = Ext IFWCB enable bit
830 */
831 uint8_t firmware_options[2];
832
833 uint16_t frame_payload_size;
834 uint16_t max_iocb_allocation;
835 uint16_t execution_throttle;
836 uint8_t retry_count;
837 uint8_t retry_delay; /* unused */
838 uint8_t port_name[WWN_SIZE]; /* Big endian. */
839 uint16_t hard_address;
840 uint8_t inquiry_data;
841 uint8_t login_timeout;
842 uint8_t node_name[WWN_SIZE]; /* Big endian. */
843
844 uint16_t request_q_outpointer;
845 uint16_t response_q_inpointer;
846 uint16_t request_q_length;
847 uint16_t response_q_length;
848 uint32_t request_q_address[2];
849 uint32_t response_q_address[2];
850
851 uint16_t lun_enables;
852 uint8_t command_resource_count;
853 uint8_t immediate_notify_resource_count;
854 uint16_t timeout;
855 uint8_t reserved_2[2];
856
857 /*
858 * LSB BIT 0 = Timer Operation mode bit 0
859 * LSB BIT 1 = Timer Operation mode bit 1
860 * LSB BIT 2 = Timer Operation mode bit 2
861 * LSB BIT 3 = Timer Operation mode bit 3
862 * LSB BIT 4 = Init Config Mode bit 0
863 * LSB BIT 5 = Init Config Mode bit 1
864 * LSB BIT 6 = Init Config Mode bit 2
865 * LSB BIT 7 = Enable Non part on LIHA failure
866 *
867 * MSB BIT 0 = Enable class 2
868 * MSB BIT 1 = Enable ACK0
869 * MSB BIT 2 =
870 * MSB BIT 3 =
871 * MSB BIT 4 = FC Tape Enable
872 * MSB BIT 5 = Enable FC Confirm
873 * MSB BIT 6 = Enable command queuing in target mode
874 * MSB BIT 7 = No Logo On Link Down
875 */
876 uint8_t add_firmware_options[2];
877
878 uint8_t response_accumulation_timer;
879 uint8_t interrupt_delay_timer;
880
881 /*
882 * LSB BIT 0 = Enable Read xfr_rdy
883 * LSB BIT 1 = Soft ID only
884 * LSB BIT 2 =
885 * LSB BIT 3 =
886 * LSB BIT 4 = FCP RSP Payload [0]
887 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
888 * LSB BIT 6 = Enable Out-of-Order frame handling
889 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
890 *
891 * MSB BIT 0 = Sbus enable - 2300
892 * MSB BIT 1 =
893 * MSB BIT 2 =
894 * MSB BIT 3 =
895 * MSB BIT 4 = LED mode
896 * MSB BIT 5 = enable 50 ohm termination
897 * MSB BIT 6 = Data Rate (2300 only)
898 * MSB BIT 7 = Data Rate (2300 only)
899 */
900 uint8_t special_options[2];
901
902 uint8_t reserved_3[26];
903 } init_cb_t;
904
905 /*
906 * Get Link Status mailbox command return buffer.
907 */
908 #define GLSO_SEND_RPS BIT_0
909 #define GLSO_USE_DID BIT_3
910
911 struct link_statistics {
912 uint32_t link_fail_cnt;
913 uint32_t loss_sync_cnt;
914 uint32_t loss_sig_cnt;
915 uint32_t prim_seq_err_cnt;
916 uint32_t inval_xmit_word_cnt;
917 uint32_t inval_crc_cnt;
918 uint32_t lip_cnt;
919 uint32_t unused1[0x1a];
920 uint32_t tx_frames;
921 uint32_t rx_frames;
922 uint32_t dumped_frames;
923 uint32_t unused2[2];
924 uint32_t nos_rcvd;
925 };
926
927 /*
928 * NVRAM Command values.
929 */
930 #define NV_START_BIT BIT_2
931 #define NV_WRITE_OP (BIT_26+BIT_24)
932 #define NV_READ_OP (BIT_26+BIT_25)
933 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
934 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
935 #define NV_DELAY_COUNT 10
936
937 /*
938 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
939 */
940 typedef struct {
941 /*
942 * NVRAM header
943 */
944 uint8_t id[4];
945 uint8_t nvram_version;
946 uint8_t reserved_0;
947
948 /*
949 * NVRAM RISC parameter block
950 */
951 uint8_t parameter_block_version;
952 uint8_t reserved_1;
953
954 /*
955 * LSB BIT 0 = Enable Hard Loop Id
956 * LSB BIT 1 = Enable Fairness
957 * LSB BIT 2 = Enable Full-Duplex
958 * LSB BIT 3 = Enable Fast Posting
959 * LSB BIT 4 = Enable Target Mode
960 * LSB BIT 5 = Disable Initiator Mode
961 * LSB BIT 6 = Enable ADISC
962 * LSB BIT 7 = Enable Target Inquiry Data
963 *
964 * MSB BIT 0 = Enable PDBC Notify
965 * MSB BIT 1 = Non Participating LIP
966 * MSB BIT 2 = Descending Loop ID Search
967 * MSB BIT 3 = Acquire Loop ID in LIPA
968 * MSB BIT 4 = Stop PortQ on Full Status
969 * MSB BIT 5 = Full Login after LIP
970 * MSB BIT 6 = Node Name Option
971 * MSB BIT 7 = Ext IFWCB enable bit
972 */
973 uint8_t firmware_options[2];
974
975 uint16_t frame_payload_size;
976 uint16_t max_iocb_allocation;
977 uint16_t execution_throttle;
978 uint8_t retry_count;
979 uint8_t retry_delay; /* unused */
980 uint8_t port_name[WWN_SIZE]; /* Big endian. */
981 uint16_t hard_address;
982 uint8_t inquiry_data;
983 uint8_t login_timeout;
984 uint8_t node_name[WWN_SIZE]; /* Big endian. */
985
986 /*
987 * LSB BIT 0 = Timer Operation mode bit 0
988 * LSB BIT 1 = Timer Operation mode bit 1
989 * LSB BIT 2 = Timer Operation mode bit 2
990 * LSB BIT 3 = Timer Operation mode bit 3
991 * LSB BIT 4 = Init Config Mode bit 0
992 * LSB BIT 5 = Init Config Mode bit 1
993 * LSB BIT 6 = Init Config Mode bit 2
994 * LSB BIT 7 = Enable Non part on LIHA failure
995 *
996 * MSB BIT 0 = Enable class 2
997 * MSB BIT 1 = Enable ACK0
998 * MSB BIT 2 =
999 * MSB BIT 3 =
1000 * MSB BIT 4 = FC Tape Enable
1001 * MSB BIT 5 = Enable FC Confirm
1002 * MSB BIT 6 = Enable command queuing in target mode
1003 * MSB BIT 7 = No Logo On Link Down
1004 */
1005 uint8_t add_firmware_options[2];
1006
1007 uint8_t response_accumulation_timer;
1008 uint8_t interrupt_delay_timer;
1009
1010 /*
1011 * LSB BIT 0 = Enable Read xfr_rdy
1012 * LSB BIT 1 = Soft ID only
1013 * LSB BIT 2 =
1014 * LSB BIT 3 =
1015 * LSB BIT 4 = FCP RSP Payload [0]
1016 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1017 * LSB BIT 6 = Enable Out-of-Order frame handling
1018 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1019 *
1020 * MSB BIT 0 = Sbus enable - 2300
1021 * MSB BIT 1 =
1022 * MSB BIT 2 =
1023 * MSB BIT 3 =
1024 * MSB BIT 4 = LED mode
1025 * MSB BIT 5 = enable 50 ohm termination
1026 * MSB BIT 6 = Data Rate (2300 only)
1027 * MSB BIT 7 = Data Rate (2300 only)
1028 */
1029 uint8_t special_options[2];
1030
1031 /* Reserved for expanded RISC parameter block */
1032 uint8_t reserved_2[22];
1033
1034 /*
1035 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1036 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1037 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1038 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1039 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1040 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1041 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1042 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1043 *
1044 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1045 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1046 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1047 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1048 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1049 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1050 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1051 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1052 *
1053 * LSB BIT 0 = Output Swing 1G bit 0
1054 * LSB BIT 1 = Output Swing 1G bit 1
1055 * LSB BIT 2 = Output Swing 1G bit 2
1056 * LSB BIT 3 = Output Emphasis 1G bit 0
1057 * LSB BIT 4 = Output Emphasis 1G bit 1
1058 * LSB BIT 5 = Output Swing 2G bit 0
1059 * LSB BIT 6 = Output Swing 2G bit 1
1060 * LSB BIT 7 = Output Swing 2G bit 2
1061 *
1062 * MSB BIT 0 = Output Emphasis 2G bit 0
1063 * MSB BIT 1 = Output Emphasis 2G bit 1
1064 * MSB BIT 2 = Output Enable
1065 * MSB BIT 3 =
1066 * MSB BIT 4 =
1067 * MSB BIT 5 =
1068 * MSB BIT 6 =
1069 * MSB BIT 7 =
1070 */
1071 uint8_t seriallink_options[4];
1072
1073 /*
1074 * NVRAM host parameter block
1075 *
1076 * LSB BIT 0 = Enable spinup delay
1077 * LSB BIT 1 = Disable BIOS
1078 * LSB BIT 2 = Enable Memory Map BIOS
1079 * LSB BIT 3 = Enable Selectable Boot
1080 * LSB BIT 4 = Disable RISC code load
1081 * LSB BIT 5 = Set cache line size 1
1082 * LSB BIT 6 = PCI Parity Disable
1083 * LSB BIT 7 = Enable extended logging
1084 *
1085 * MSB BIT 0 = Enable 64bit addressing
1086 * MSB BIT 1 = Enable lip reset
1087 * MSB BIT 2 = Enable lip full login
1088 * MSB BIT 3 = Enable target reset
1089 * MSB BIT 4 = Enable database storage
1090 * MSB BIT 5 = Enable cache flush read
1091 * MSB BIT 6 = Enable database load
1092 * MSB BIT 7 = Enable alternate WWN
1093 */
1094 uint8_t host_p[2];
1095
1096 uint8_t boot_node_name[WWN_SIZE];
1097 uint8_t boot_lun_number;
1098 uint8_t reset_delay;
1099 uint8_t port_down_retry_count;
1100 uint8_t boot_id_number;
1101 uint16_t max_luns_per_target;
1102 uint8_t fcode_boot_port_name[WWN_SIZE];
1103 uint8_t alternate_port_name[WWN_SIZE];
1104 uint8_t alternate_node_name[WWN_SIZE];
1105
1106 /*
1107 * BIT 0 = Selective Login
1108 * BIT 1 = Alt-Boot Enable
1109 * BIT 2 =
1110 * BIT 3 = Boot Order List
1111 * BIT 4 =
1112 * BIT 5 = Selective LUN
1113 * BIT 6 =
1114 * BIT 7 = unused
1115 */
1116 uint8_t efi_parameters;
1117
1118 uint8_t link_down_timeout;
1119
1120 uint8_t adapter_id[16];
1121
1122 uint8_t alt1_boot_node_name[WWN_SIZE];
1123 uint16_t alt1_boot_lun_number;
1124 uint8_t alt2_boot_node_name[WWN_SIZE];
1125 uint16_t alt2_boot_lun_number;
1126 uint8_t alt3_boot_node_name[WWN_SIZE];
1127 uint16_t alt3_boot_lun_number;
1128 uint8_t alt4_boot_node_name[WWN_SIZE];
1129 uint16_t alt4_boot_lun_number;
1130 uint8_t alt5_boot_node_name[WWN_SIZE];
1131 uint16_t alt5_boot_lun_number;
1132 uint8_t alt6_boot_node_name[WWN_SIZE];
1133 uint16_t alt6_boot_lun_number;
1134 uint8_t alt7_boot_node_name[WWN_SIZE];
1135 uint16_t alt7_boot_lun_number;
1136
1137 uint8_t reserved_3[2];
1138
1139 /* Offset 200-215 : Model Number */
1140 uint8_t model_number[16];
1141
1142 /* OEM related items */
1143 uint8_t oem_specific[16];
1144
1145 /*
1146 * NVRAM Adapter Features offset 232-239
1147 *
1148 * LSB BIT 0 = External GBIC
1149 * LSB BIT 1 = Risc RAM parity
1150 * LSB BIT 2 = Buffer Plus Module
1151 * LSB BIT 3 = Multi Chip Adapter
1152 * LSB BIT 4 = Internal connector
1153 * LSB BIT 5 =
1154 * LSB BIT 6 =
1155 * LSB BIT 7 =
1156 *
1157 * MSB BIT 0 =
1158 * MSB BIT 1 =
1159 * MSB BIT 2 =
1160 * MSB BIT 3 =
1161 * MSB BIT 4 =
1162 * MSB BIT 5 =
1163 * MSB BIT 6 =
1164 * MSB BIT 7 =
1165 */
1166 uint8_t adapter_features[2];
1167
1168 uint8_t reserved_4[16];
1169
1170 /* Subsystem vendor ID for ISP2200 */
1171 uint16_t subsystem_vendor_id_2200;
1172
1173 /* Subsystem device ID for ISP2200 */
1174 uint16_t subsystem_device_id_2200;
1175
1176 uint8_t reserved_5;
1177 uint8_t checksum;
1178 } nvram_t;
1179
1180 /*
1181 * ISP queue - response queue entry definition.
1182 */
1183 typedef struct {
1184 uint8_t data[60];
1185 uint32_t signature;
1186 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1187 } response_t;
1188
1189 typedef union {
1190 uint16_t extended;
1191 struct {
1192 uint8_t reserved;
1193 uint8_t standard;
1194 } id;
1195 } target_id_t;
1196
1197 #define SET_TARGET_ID(ha, to, from) \
1198 do { \
1199 if (HAS_EXTENDED_IDS(ha)) \
1200 to.extended = cpu_to_le16(from); \
1201 else \
1202 to.id.standard = (uint8_t)from; \
1203 } while (0)
1204
1205 /*
1206 * ISP queue - command entry structure definition.
1207 */
1208 #define COMMAND_TYPE 0x11 /* Command entry */
1209 typedef struct {
1210 uint8_t entry_type; /* Entry type. */
1211 uint8_t entry_count; /* Entry count. */
1212 uint8_t sys_define; /* System defined. */
1213 uint8_t entry_status; /* Entry Status. */
1214 uint32_t handle; /* System handle. */
1215 target_id_t target; /* SCSI ID */
1216 uint16_t lun; /* SCSI LUN */
1217 uint16_t control_flags; /* Control flags. */
1218 #define CF_WRITE BIT_6
1219 #define CF_READ BIT_5
1220 #define CF_SIMPLE_TAG BIT_3
1221 #define CF_ORDERED_TAG BIT_2
1222 #define CF_HEAD_TAG BIT_1
1223 uint16_t reserved_1;
1224 uint16_t timeout; /* Command timeout. */
1225 uint16_t dseg_count; /* Data segment count. */
1226 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1227 uint32_t byte_count; /* Total byte count. */
1228 uint32_t dseg_0_address; /* Data segment 0 address. */
1229 uint32_t dseg_0_length; /* Data segment 0 length. */
1230 uint32_t dseg_1_address; /* Data segment 1 address. */
1231 uint32_t dseg_1_length; /* Data segment 1 length. */
1232 uint32_t dseg_2_address; /* Data segment 2 address. */
1233 uint32_t dseg_2_length; /* Data segment 2 length. */
1234 } cmd_entry_t;
1235
1236 /*
1237 * ISP queue - 64-Bit addressing, command entry structure definition.
1238 */
1239 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1240 typedef struct {
1241 uint8_t entry_type; /* Entry type. */
1242 uint8_t entry_count; /* Entry count. */
1243 uint8_t sys_define; /* System defined. */
1244 uint8_t entry_status; /* Entry Status. */
1245 uint32_t handle; /* System handle. */
1246 target_id_t target; /* SCSI ID */
1247 uint16_t lun; /* SCSI LUN */
1248 uint16_t control_flags; /* Control flags. */
1249 uint16_t reserved_1;
1250 uint16_t timeout; /* Command timeout. */
1251 uint16_t dseg_count; /* Data segment count. */
1252 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1253 uint32_t byte_count; /* Total byte count. */
1254 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1255 uint32_t dseg_0_length; /* Data segment 0 length. */
1256 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1257 uint32_t dseg_1_length; /* Data segment 1 length. */
1258 } cmd_a64_entry_t, request_t;
1259
1260 /*
1261 * ISP queue - continuation entry structure definition.
1262 */
1263 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1264 typedef struct {
1265 uint8_t entry_type; /* Entry type. */
1266 uint8_t entry_count; /* Entry count. */
1267 uint8_t sys_define; /* System defined. */
1268 uint8_t entry_status; /* Entry Status. */
1269 uint32_t reserved;
1270 uint32_t dseg_0_address; /* Data segment 0 address. */
1271 uint32_t dseg_0_length; /* Data segment 0 length. */
1272 uint32_t dseg_1_address; /* Data segment 1 address. */
1273 uint32_t dseg_1_length; /* Data segment 1 length. */
1274 uint32_t dseg_2_address; /* Data segment 2 address. */
1275 uint32_t dseg_2_length; /* Data segment 2 length. */
1276 uint32_t dseg_3_address; /* Data segment 3 address. */
1277 uint32_t dseg_3_length; /* Data segment 3 length. */
1278 uint32_t dseg_4_address; /* Data segment 4 address. */
1279 uint32_t dseg_4_length; /* Data segment 4 length. */
1280 uint32_t dseg_5_address; /* Data segment 5 address. */
1281 uint32_t dseg_5_length; /* Data segment 5 length. */
1282 uint32_t dseg_6_address; /* Data segment 6 address. */
1283 uint32_t dseg_6_length; /* Data segment 6 length. */
1284 } cont_entry_t;
1285
1286 /*
1287 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1288 */
1289 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1290 typedef struct {
1291 uint8_t entry_type; /* Entry type. */
1292 uint8_t entry_count; /* Entry count. */
1293 uint8_t sys_define; /* System defined. */
1294 uint8_t entry_status; /* Entry Status. */
1295 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1296 uint32_t dseg_0_length; /* Data segment 0 length. */
1297 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1298 uint32_t dseg_1_length; /* Data segment 1 length. */
1299 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1300 uint32_t dseg_2_length; /* Data segment 2 length. */
1301 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1302 uint32_t dseg_3_length; /* Data segment 3 length. */
1303 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1304 uint32_t dseg_4_length; /* Data segment 4 length. */
1305 } cont_a64_entry_t;
1306
1307 /*
1308 * ISP queue - status entry structure definition.
1309 */
1310 #define STATUS_TYPE 0x03 /* Status entry. */
1311 typedef struct {
1312 uint8_t entry_type; /* Entry type. */
1313 uint8_t entry_count; /* Entry count. */
1314 uint8_t sys_define; /* System defined. */
1315 uint8_t entry_status; /* Entry Status. */
1316 uint32_t handle; /* System handle. */
1317 uint16_t scsi_status; /* SCSI status. */
1318 uint16_t comp_status; /* Completion status. */
1319 uint16_t state_flags; /* State flags. */
1320 uint16_t status_flags; /* Status flags. */
1321 uint16_t rsp_info_len; /* Response Info Length. */
1322 uint16_t req_sense_length; /* Request sense data length. */
1323 uint32_t residual_length; /* Residual transfer length. */
1324 uint8_t rsp_info[8]; /* FCP response information. */
1325 uint8_t req_sense_data[32]; /* Request sense data. */
1326 } sts_entry_t;
1327
1328 /*
1329 * Status entry entry status
1330 */
1331 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1332 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1333 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1334 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1335 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1336 #define RF_BUSY BIT_1 /* Busy */
1337 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1338 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1339 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1340 RF_INV_E_TYPE)
1341
1342 /*
1343 * Status entry SCSI status bit definitions.
1344 */
1345 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1346 #define SS_RESIDUAL_UNDER BIT_11
1347 #define SS_RESIDUAL_OVER BIT_10
1348 #define SS_SENSE_LEN_VALID BIT_9
1349 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1350
1351 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1352 #define SS_BUSY_CONDITION BIT_3
1353 #define SS_CONDITION_MET BIT_2
1354 #define SS_CHECK_CONDITION BIT_1
1355
1356 /*
1357 * Status entry completion status
1358 */
1359 #define CS_COMPLETE 0x0 /* No errors */
1360 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1361 #define CS_DMA 0x2 /* A DMA direction error. */
1362 #define CS_TRANSPORT 0x3 /* Transport error. */
1363 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1364 #define CS_ABORTED 0x5 /* System aborted command. */
1365 #define CS_TIMEOUT 0x6 /* Timeout error. */
1366 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1367
1368 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1369 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1370 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1371 /* (selection timeout) */
1372 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1373 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1374 #define CS_PORT_BUSY 0x2B /* Port Busy */
1375 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1376 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1377 #define CS_UNKNOWN 0x81 /* Driver defined */
1378 #define CS_RETRY 0x82 /* Driver defined */
1379 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1380
1381 /*
1382 * Status entry status flags
1383 */
1384 #define SF_ABTS_TERMINATED BIT_10
1385 #define SF_LOGOUT_SENT BIT_13
1386
1387 /*
1388 * ISP queue - status continuation entry structure definition.
1389 */
1390 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1391 typedef struct {
1392 uint8_t entry_type; /* Entry type. */
1393 uint8_t entry_count; /* Entry count. */
1394 uint8_t sys_define; /* System defined. */
1395 uint8_t entry_status; /* Entry Status. */
1396 uint8_t data[60]; /* data */
1397 } sts_cont_entry_t;
1398
1399 /*
1400 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1401 * structure definition.
1402 */
1403 #define STATUS_TYPE_21 0x21 /* Status entry. */
1404 typedef struct {
1405 uint8_t entry_type; /* Entry type. */
1406 uint8_t entry_count; /* Entry count. */
1407 uint8_t handle_count; /* Handle count. */
1408 uint8_t entry_status; /* Entry Status. */
1409 uint32_t handle[15]; /* System handles. */
1410 } sts21_entry_t;
1411
1412 /*
1413 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1414 * structure definition.
1415 */
1416 #define STATUS_TYPE_22 0x22 /* Status entry. */
1417 typedef struct {
1418 uint8_t entry_type; /* Entry type. */
1419 uint8_t entry_count; /* Entry count. */
1420 uint8_t handle_count; /* Handle count. */
1421 uint8_t entry_status; /* Entry Status. */
1422 uint16_t handle[30]; /* System handles. */
1423 } sts22_entry_t;
1424
1425 /*
1426 * ISP queue - marker entry structure definition.
1427 */
1428 #define MARKER_TYPE 0x04 /* Marker entry. */
1429 typedef struct {
1430 uint8_t entry_type; /* Entry type. */
1431 uint8_t entry_count; /* Entry count. */
1432 uint8_t handle_count; /* Handle count. */
1433 uint8_t entry_status; /* Entry Status. */
1434 uint32_t sys_define_2; /* System defined. */
1435 target_id_t target; /* SCSI ID */
1436 uint8_t modifier; /* Modifier (7-0). */
1437 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1438 #define MK_SYNC_ID 1 /* Synchronize ID */
1439 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1440 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1441 /* clear port changed, */
1442 /* use sequence number. */
1443 uint8_t reserved_1;
1444 uint16_t sequence_number; /* Sequence number of event */
1445 uint16_t lun; /* SCSI LUN */
1446 uint8_t reserved_2[48];
1447 } mrk_entry_t;
1448
1449 /*
1450 * ISP queue - Management Server entry structure definition.
1451 */
1452 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1453 typedef struct {
1454 uint8_t entry_type; /* Entry type. */
1455 uint8_t entry_count; /* Entry count. */
1456 uint8_t handle_count; /* Handle count. */
1457 uint8_t entry_status; /* Entry Status. */
1458 uint32_t handle1; /* System handle. */
1459 target_id_t loop_id;
1460 uint16_t status;
1461 uint16_t control_flags; /* Control flags. */
1462 uint16_t reserved2;
1463 uint16_t timeout;
1464 uint16_t cmd_dsd_count;
1465 uint16_t total_dsd_count;
1466 uint8_t type;
1467 uint8_t r_ctl;
1468 uint16_t rx_id;
1469 uint16_t reserved3;
1470 uint32_t handle2;
1471 uint32_t rsp_bytecount;
1472 uint32_t req_bytecount;
1473 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1474 uint32_t dseg_req_length; /* Data segment 0 length. */
1475 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1476 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1477 } ms_iocb_entry_t;
1478
1479
1480 /*
1481 * ISP queue - Mailbox Command entry structure definition.
1482 */
1483 #define MBX_IOCB_TYPE 0x39
1484 struct mbx_entry {
1485 uint8_t entry_type;
1486 uint8_t entry_count;
1487 uint8_t sys_define1;
1488 /* Use sys_define1 for source type */
1489 #define SOURCE_SCSI 0x00
1490 #define SOURCE_IP 0x01
1491 #define SOURCE_VI 0x02
1492 #define SOURCE_SCTP 0x03
1493 #define SOURCE_MP 0x04
1494 #define SOURCE_MPIOCTL 0x05
1495 #define SOURCE_ASYNC_IOCB 0x07
1496
1497 uint8_t entry_status;
1498
1499 uint32_t handle;
1500 target_id_t loop_id;
1501
1502 uint16_t status;
1503 uint16_t state_flags;
1504 uint16_t status_flags;
1505
1506 uint32_t sys_define2[2];
1507
1508 uint16_t mb0;
1509 uint16_t mb1;
1510 uint16_t mb2;
1511 uint16_t mb3;
1512 uint16_t mb6;
1513 uint16_t mb7;
1514 uint16_t mb9;
1515 uint16_t mb10;
1516 uint32_t reserved_2[2];
1517 uint8_t node_name[WWN_SIZE];
1518 uint8_t port_name[WWN_SIZE];
1519 };
1520
1521 /*
1522 * ISP request and response queue entry sizes
1523 */
1524 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1525 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1526
1527
1528 /*
1529 * 24 bit port ID type definition.
1530 */
1531 typedef union {
1532 uint32_t b24 : 24;
1533
1534 struct {
1535 #ifdef __BIG_ENDIAN
1536 uint8_t domain;
1537 uint8_t area;
1538 uint8_t al_pa;
1539 #elif defined(__LITTLE_ENDIAN)
1540 uint8_t al_pa;
1541 uint8_t area;
1542 uint8_t domain;
1543 #else
1544 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1545 #endif
1546 uint8_t rsvd_1;
1547 } b;
1548 } port_id_t;
1549 #define INVALID_PORT_ID 0xFFFFFF
1550
1551 /*
1552 * Switch info gathering structure.
1553 */
1554 typedef struct {
1555 port_id_t d_id;
1556 uint8_t node_name[WWN_SIZE];
1557 uint8_t port_name[WWN_SIZE];
1558 uint8_t fabric_port_name[WWN_SIZE];
1559 uint16_t fp_speed;
1560 } sw_info_t;
1561
1562 /*
1563 * Fibre channel port type.
1564 */
1565 typedef enum {
1566 FCT_UNKNOWN,
1567 FCT_RSCN,
1568 FCT_SWITCH,
1569 FCT_BROADCAST,
1570 FCT_INITIATOR,
1571 FCT_TARGET
1572 } fc_port_type_t;
1573
1574 /*
1575 * Fibre channel port structure.
1576 */
1577 typedef struct fc_port {
1578 struct list_head list;
1579 struct scsi_qla_host *vha;
1580
1581 uint8_t node_name[WWN_SIZE];
1582 uint8_t port_name[WWN_SIZE];
1583 port_id_t d_id;
1584 uint16_t loop_id;
1585 uint16_t old_loop_id;
1586
1587 uint8_t fcp_prio;
1588
1589 uint8_t fabric_port_name[WWN_SIZE];
1590 uint16_t fp_speed;
1591
1592 fc_port_type_t port_type;
1593
1594 atomic_t state;
1595 uint32_t flags;
1596
1597 int port_login_retry_count;
1598 int login_retry;
1599 atomic_t port_down_timer;
1600
1601 struct fc_rport *rport, *drport;
1602 u32 supported_classes;
1603
1604 uint16_t vp_idx;
1605 } fc_port_t;
1606
1607 /*
1608 * Fibre channel port/lun states.
1609 */
1610 #define FCS_UNCONFIGURED 1
1611 #define FCS_DEVICE_DEAD 2
1612 #define FCS_DEVICE_LOST 3
1613 #define FCS_ONLINE 4
1614
1615 /*
1616 * FC port flags.
1617 */
1618 #define FCF_FABRIC_DEVICE BIT_0
1619 #define FCF_LOGIN_NEEDED BIT_1
1620 #define FCF_FCP2_DEVICE BIT_2
1621
1622 /* No loop ID flag. */
1623 #define FC_NO_LOOP_ID 0x1000
1624
1625 /*
1626 * FC-CT interface
1627 *
1628 * NOTE: All structures are big-endian in form.
1629 */
1630
1631 #define CT_REJECT_RESPONSE 0x8001
1632 #define CT_ACCEPT_RESPONSE 0x8002
1633 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1634 #define CT_REASON_CANNOT_PERFORM 0x09
1635 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1636 #define CT_EXPL_ALREADY_REGISTERED 0x10
1637
1638 #define NS_N_PORT_TYPE 0x01
1639 #define NS_NL_PORT_TYPE 0x02
1640 #define NS_NX_PORT_TYPE 0x7F
1641
1642 #define GA_NXT_CMD 0x100
1643 #define GA_NXT_REQ_SIZE (16 + 4)
1644 #define GA_NXT_RSP_SIZE (16 + 620)
1645
1646 #define GID_PT_CMD 0x1A1
1647 #define GID_PT_REQ_SIZE (16 + 4)
1648 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1649
1650 #define GPN_ID_CMD 0x112
1651 #define GPN_ID_REQ_SIZE (16 + 4)
1652 #define GPN_ID_RSP_SIZE (16 + 8)
1653
1654 #define GNN_ID_CMD 0x113
1655 #define GNN_ID_REQ_SIZE (16 + 4)
1656 #define GNN_ID_RSP_SIZE (16 + 8)
1657
1658 #define GFT_ID_CMD 0x117
1659 #define GFT_ID_REQ_SIZE (16 + 4)
1660 #define GFT_ID_RSP_SIZE (16 + 32)
1661
1662 #define RFT_ID_CMD 0x217
1663 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1664 #define RFT_ID_RSP_SIZE 16
1665
1666 #define RFF_ID_CMD 0x21F
1667 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1668 #define RFF_ID_RSP_SIZE 16
1669
1670 #define RNN_ID_CMD 0x213
1671 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1672 #define RNN_ID_RSP_SIZE 16
1673
1674 #define RSNN_NN_CMD 0x239
1675 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1676 #define RSNN_NN_RSP_SIZE 16
1677
1678 #define GFPN_ID_CMD 0x11C
1679 #define GFPN_ID_REQ_SIZE (16 + 4)
1680 #define GFPN_ID_RSP_SIZE (16 + 8)
1681
1682 #define GPSC_CMD 0x127
1683 #define GPSC_REQ_SIZE (16 + 8)
1684 #define GPSC_RSP_SIZE (16 + 2 + 2)
1685
1686
1687 /*
1688 * HBA attribute types.
1689 */
1690 #define FDMI_HBA_ATTR_COUNT 9
1691 #define FDMI_HBA_NODE_NAME 1
1692 #define FDMI_HBA_MANUFACTURER 2
1693 #define FDMI_HBA_SERIAL_NUMBER 3
1694 #define FDMI_HBA_MODEL 4
1695 #define FDMI_HBA_MODEL_DESCRIPTION 5
1696 #define FDMI_HBA_HARDWARE_VERSION 6
1697 #define FDMI_HBA_DRIVER_VERSION 7
1698 #define FDMI_HBA_OPTION_ROM_VERSION 8
1699 #define FDMI_HBA_FIRMWARE_VERSION 9
1700 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1701 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1702
1703 struct ct_fdmi_hba_attr {
1704 uint16_t type;
1705 uint16_t len;
1706 union {
1707 uint8_t node_name[WWN_SIZE];
1708 uint8_t manufacturer[32];
1709 uint8_t serial_num[8];
1710 uint8_t model[16];
1711 uint8_t model_desc[80];
1712 uint8_t hw_version[16];
1713 uint8_t driver_version[32];
1714 uint8_t orom_version[16];
1715 uint8_t fw_version[16];
1716 uint8_t os_version[128];
1717 uint8_t max_ct_len[4];
1718 } a;
1719 };
1720
1721 struct ct_fdmi_hba_attributes {
1722 uint32_t count;
1723 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1724 };
1725
1726 /*
1727 * Port attribute types.
1728 */
1729 #define FDMI_PORT_ATTR_COUNT 6
1730 #define FDMI_PORT_FC4_TYPES 1
1731 #define FDMI_PORT_SUPPORT_SPEED 2
1732 #define FDMI_PORT_CURRENT_SPEED 3
1733 #define FDMI_PORT_MAX_FRAME_SIZE 4
1734 #define FDMI_PORT_OS_DEVICE_NAME 5
1735 #define FDMI_PORT_HOST_NAME 6
1736
1737 #define FDMI_PORT_SPEED_1GB 0x1
1738 #define FDMI_PORT_SPEED_2GB 0x2
1739 #define FDMI_PORT_SPEED_10GB 0x4
1740 #define FDMI_PORT_SPEED_4GB 0x8
1741 #define FDMI_PORT_SPEED_8GB 0x10
1742 #define FDMI_PORT_SPEED_16GB 0x20
1743 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1744
1745 struct ct_fdmi_port_attr {
1746 uint16_t type;
1747 uint16_t len;
1748 union {
1749 uint8_t fc4_types[32];
1750 uint32_t sup_speed;
1751 uint32_t cur_speed;
1752 uint32_t max_frame_size;
1753 uint8_t os_dev_name[32];
1754 uint8_t host_name[32];
1755 } a;
1756 };
1757
1758 /*
1759 * Port Attribute Block.
1760 */
1761 struct ct_fdmi_port_attributes {
1762 uint32_t count;
1763 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1764 };
1765
1766 /* FDMI definitions. */
1767 #define GRHL_CMD 0x100
1768 #define GHAT_CMD 0x101
1769 #define GRPL_CMD 0x102
1770 #define GPAT_CMD 0x110
1771
1772 #define RHBA_CMD 0x200
1773 #define RHBA_RSP_SIZE 16
1774
1775 #define RHAT_CMD 0x201
1776 #define RPRT_CMD 0x210
1777
1778 #define RPA_CMD 0x211
1779 #define RPA_RSP_SIZE 16
1780
1781 #define DHBA_CMD 0x300
1782 #define DHBA_REQ_SIZE (16 + 8)
1783 #define DHBA_RSP_SIZE 16
1784
1785 #define DHAT_CMD 0x301
1786 #define DPRT_CMD 0x310
1787 #define DPA_CMD 0x311
1788
1789 /* CT command header -- request/response common fields */
1790 struct ct_cmd_hdr {
1791 uint8_t revision;
1792 uint8_t in_id[3];
1793 uint8_t gs_type;
1794 uint8_t gs_subtype;
1795 uint8_t options;
1796 uint8_t reserved;
1797 };
1798
1799 /* CT command request */
1800 struct ct_sns_req {
1801 struct ct_cmd_hdr header;
1802 uint16_t command;
1803 uint16_t max_rsp_size;
1804 uint8_t fragment_id;
1805 uint8_t reserved[3];
1806
1807 union {
1808 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1809 struct {
1810 uint8_t reserved;
1811 uint8_t port_id[3];
1812 } port_id;
1813
1814 struct {
1815 uint8_t port_type;
1816 uint8_t domain;
1817 uint8_t area;
1818 uint8_t reserved;
1819 } gid_pt;
1820
1821 struct {
1822 uint8_t reserved;
1823 uint8_t port_id[3];
1824 uint8_t fc4_types[32];
1825 } rft_id;
1826
1827 struct {
1828 uint8_t reserved;
1829 uint8_t port_id[3];
1830 uint16_t reserved2;
1831 uint8_t fc4_feature;
1832 uint8_t fc4_type;
1833 } rff_id;
1834
1835 struct {
1836 uint8_t reserved;
1837 uint8_t port_id[3];
1838 uint8_t node_name[8];
1839 } rnn_id;
1840
1841 struct {
1842 uint8_t node_name[8];
1843 uint8_t name_len;
1844 uint8_t sym_node_name[255];
1845 } rsnn_nn;
1846
1847 struct {
1848 uint8_t hba_indentifier[8];
1849 } ghat;
1850
1851 struct {
1852 uint8_t hba_identifier[8];
1853 uint32_t entry_count;
1854 uint8_t port_name[8];
1855 struct ct_fdmi_hba_attributes attrs;
1856 } rhba;
1857
1858 struct {
1859 uint8_t hba_identifier[8];
1860 struct ct_fdmi_hba_attributes attrs;
1861 } rhat;
1862
1863 struct {
1864 uint8_t port_name[8];
1865 struct ct_fdmi_port_attributes attrs;
1866 } rpa;
1867
1868 struct {
1869 uint8_t port_name[8];
1870 } dhba;
1871
1872 struct {
1873 uint8_t port_name[8];
1874 } dhat;
1875
1876 struct {
1877 uint8_t port_name[8];
1878 } dprt;
1879
1880 struct {
1881 uint8_t port_name[8];
1882 } dpa;
1883
1884 struct {
1885 uint8_t port_name[8];
1886 } gpsc;
1887 } req;
1888 };
1889
1890 /* CT command response header */
1891 struct ct_rsp_hdr {
1892 struct ct_cmd_hdr header;
1893 uint16_t response;
1894 uint16_t residual;
1895 uint8_t fragment_id;
1896 uint8_t reason_code;
1897 uint8_t explanation_code;
1898 uint8_t vendor_unique;
1899 };
1900
1901 struct ct_sns_gid_pt_data {
1902 uint8_t control_byte;
1903 uint8_t port_id[3];
1904 };
1905
1906 struct ct_sns_rsp {
1907 struct ct_rsp_hdr header;
1908
1909 union {
1910 struct {
1911 uint8_t port_type;
1912 uint8_t port_id[3];
1913 uint8_t port_name[8];
1914 uint8_t sym_port_name_len;
1915 uint8_t sym_port_name[255];
1916 uint8_t node_name[8];
1917 uint8_t sym_node_name_len;
1918 uint8_t sym_node_name[255];
1919 uint8_t init_proc_assoc[8];
1920 uint8_t node_ip_addr[16];
1921 uint8_t class_of_service[4];
1922 uint8_t fc4_types[32];
1923 uint8_t ip_address[16];
1924 uint8_t fabric_port_name[8];
1925 uint8_t reserved;
1926 uint8_t hard_address[3];
1927 } ga_nxt;
1928
1929 struct {
1930 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1931 } gid_pt;
1932
1933 struct {
1934 uint8_t port_name[8];
1935 } gpn_id;
1936
1937 struct {
1938 uint8_t node_name[8];
1939 } gnn_id;
1940
1941 struct {
1942 uint8_t fc4_types[32];
1943 } gft_id;
1944
1945 struct {
1946 uint32_t entry_count;
1947 uint8_t port_name[8];
1948 struct ct_fdmi_hba_attributes attrs;
1949 } ghat;
1950
1951 struct {
1952 uint8_t port_name[8];
1953 } gfpn_id;
1954
1955 struct {
1956 uint16_t speeds;
1957 uint16_t speed;
1958 } gpsc;
1959 } rsp;
1960 };
1961
1962 struct ct_sns_pkt {
1963 union {
1964 struct ct_sns_req req;
1965 struct ct_sns_rsp rsp;
1966 } p;
1967 };
1968
1969 /*
1970 * SNS command structures -- for 2200 compatability.
1971 */
1972 #define RFT_ID_SNS_SCMD_LEN 22
1973 #define RFT_ID_SNS_CMD_SIZE 60
1974 #define RFT_ID_SNS_DATA_SIZE 16
1975
1976 #define RNN_ID_SNS_SCMD_LEN 10
1977 #define RNN_ID_SNS_CMD_SIZE 36
1978 #define RNN_ID_SNS_DATA_SIZE 16
1979
1980 #define GA_NXT_SNS_SCMD_LEN 6
1981 #define GA_NXT_SNS_CMD_SIZE 28
1982 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1983
1984 #define GID_PT_SNS_SCMD_LEN 6
1985 #define GID_PT_SNS_CMD_SIZE 28
1986 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1987
1988 #define GPN_ID_SNS_SCMD_LEN 6
1989 #define GPN_ID_SNS_CMD_SIZE 28
1990 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1991
1992 #define GNN_ID_SNS_SCMD_LEN 6
1993 #define GNN_ID_SNS_CMD_SIZE 28
1994 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1995
1996 struct sns_cmd_pkt {
1997 union {
1998 struct {
1999 uint16_t buffer_length;
2000 uint16_t reserved_1;
2001 uint32_t buffer_address[2];
2002 uint16_t subcommand_length;
2003 uint16_t reserved_2;
2004 uint16_t subcommand;
2005 uint16_t size;
2006 uint32_t reserved_3;
2007 uint8_t param[36];
2008 } cmd;
2009
2010 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2011 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2012 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2013 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2014 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2015 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2016 } p;
2017 };
2018
2019 struct fw_blob {
2020 char *name;
2021 uint32_t segs[4];
2022 const struct firmware *fw;
2023 };
2024
2025 /* Return data from MBC_GET_ID_LIST call. */
2026 struct gid_list_info {
2027 uint8_t al_pa;
2028 uint8_t area;
2029 uint8_t domain;
2030 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2031 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2032 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2033 };
2034 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2035
2036 /* NPIV */
2037 typedef struct vport_info {
2038 uint8_t port_name[WWN_SIZE];
2039 uint8_t node_name[WWN_SIZE];
2040 int vp_id;
2041 uint16_t loop_id;
2042 unsigned long host_no;
2043 uint8_t port_id[3];
2044 int loop_state;
2045 } vport_info_t;
2046
2047 typedef struct vport_params {
2048 uint8_t port_name[WWN_SIZE];
2049 uint8_t node_name[WWN_SIZE];
2050 uint32_t options;
2051 #define VP_OPTS_RETRY_ENABLE BIT_0
2052 #define VP_OPTS_VP_DISABLE BIT_1
2053 } vport_params_t;
2054
2055 /* NPIV - return codes of VP create and modify */
2056 #define VP_RET_CODE_OK 0
2057 #define VP_RET_CODE_FATAL 1
2058 #define VP_RET_CODE_WRONG_ID 2
2059 #define VP_RET_CODE_WWPN 3
2060 #define VP_RET_CODE_RESOURCES 4
2061 #define VP_RET_CODE_NO_MEM 5
2062 #define VP_RET_CODE_NOT_FOUND 6
2063
2064 struct qla_hw_data;
2065 struct rsp_que;
2066 /*
2067 * ISP operations
2068 */
2069 struct isp_operations {
2070
2071 int (*pci_config) (struct scsi_qla_host *);
2072 void (*reset_chip) (struct scsi_qla_host *);
2073 int (*chip_diag) (struct scsi_qla_host *);
2074 void (*config_rings) (struct scsi_qla_host *);
2075 void (*reset_adapter) (struct scsi_qla_host *);
2076 int (*nvram_config) (struct scsi_qla_host *);
2077 void (*update_fw_options) (struct scsi_qla_host *);
2078 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2079
2080 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2081 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2082
2083 irq_handler_t intr_handler;
2084 void (*enable_intrs) (struct qla_hw_data *);
2085 void (*disable_intrs) (struct qla_hw_data *);
2086
2087 int (*abort_command) (srb_t *);
2088 int (*target_reset) (struct fc_port *, unsigned int, int);
2089 int (*lun_reset) (struct fc_port *, unsigned int, int);
2090 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2091 uint8_t, uint8_t, uint16_t *, uint8_t);
2092 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2093 uint8_t, uint8_t);
2094
2095 uint16_t (*calc_req_entries) (uint16_t);
2096 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2097 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2098 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2099 uint32_t);
2100
2101 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2102 uint32_t, uint32_t);
2103 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2104 uint32_t);
2105
2106 void (*fw_dump) (struct scsi_qla_host *, int);
2107
2108 int (*beacon_on) (struct scsi_qla_host *);
2109 int (*beacon_off) (struct scsi_qla_host *);
2110 void (*beacon_blink) (struct scsi_qla_host *);
2111
2112 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2113 uint32_t, uint32_t);
2114 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2115 uint32_t);
2116
2117 int (*get_flash_version) (struct scsi_qla_host *, void *);
2118 int (*start_scsi) (srb_t *);
2119 int (*abort_isp) (struct scsi_qla_host *);
2120 };
2121
2122 /* MSI-X Support *************************************************************/
2123
2124 #define QLA_MSIX_CHIP_REV_24XX 3
2125 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2126 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2127
2128 #define QLA_MSIX_DEFAULT 0x00
2129 #define QLA_MSIX_RSP_Q 0x01
2130
2131 #define QLA_MIDX_DEFAULT 0
2132 #define QLA_MIDX_RSP_Q 1
2133 #define QLA_PCI_MSIX_CONTROL 0xa2
2134
2135 struct scsi_qla_host;
2136
2137 struct qla_msix_entry {
2138 int have_irq;
2139 uint32_t vector;
2140 uint16_t entry;
2141 struct rsp_que *rsp;
2142 };
2143
2144 #define WATCH_INTERVAL 1 /* number of seconds */
2145
2146 /* Work events. */
2147 enum qla_work_type {
2148 QLA_EVT_AEN,
2149 QLA_EVT_IDC_ACK,
2150 QLA_EVT_ASYNC_LOGIN,
2151 QLA_EVT_ASYNC_LOGIN_DONE,
2152 QLA_EVT_ASYNC_LOGOUT,
2153 QLA_EVT_ASYNC_LOGOUT_DONE,
2154 QLA_EVT_UEVENT,
2155 };
2156
2157
2158 struct qla_work_evt {
2159 struct list_head list;
2160 enum qla_work_type type;
2161 u32 flags;
2162 #define QLA_EVT_FLAG_FREE 0x1
2163
2164 union {
2165 struct {
2166 enum fc_host_event_code code;
2167 u32 data;
2168 } aen;
2169 struct {
2170 #define QLA_IDC_ACK_REGS 7
2171 uint16_t mb[QLA_IDC_ACK_REGS];
2172 } idc_ack;
2173 struct {
2174 struct fc_port *fcport;
2175 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2176 u16 data[2];
2177 } logio;
2178 struct {
2179 u32 code;
2180 #define QLA_UEVENT_CODE_FW_DUMP 0
2181 } uevent;
2182 } u;
2183 };
2184
2185 struct qla_chip_state_84xx {
2186 struct list_head list;
2187 struct kref kref;
2188
2189 void *bus;
2190 spinlock_t access_lock;
2191 struct mutex fw_update_mutex;
2192 uint32_t fw_update;
2193 uint32_t op_fw_version;
2194 uint32_t op_fw_size;
2195 uint32_t op_fw_seq_size;
2196 uint32_t diag_fw_version;
2197 uint32_t gold_fw_version;
2198 };
2199
2200 struct qla_statistics {
2201 uint32_t total_isp_aborts;
2202 uint64_t input_bytes;
2203 uint64_t output_bytes;
2204 };
2205
2206 /* Multi queue support */
2207 #define MBC_INITIALIZE_MULTIQ 0x1f
2208 #define QLA_QUE_PAGE 0X1000
2209 #define QLA_MQ_SIZE 32
2210 #define QLA_MAX_QUEUES 256
2211 #define ISP_QUE_REG(ha, id) \
2212 ((ha->mqenable) ? \
2213 ((void *)(ha->mqiobase) +\
2214 (QLA_QUE_PAGE * id)) :\
2215 ((void *)(ha->iobase)))
2216 #define QLA_REQ_QUE_ID(tag) \
2217 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2218 #define QLA_DEFAULT_QUE_QOS 5
2219 #define QLA_PRECONFIG_VPORTS 32
2220 #define QLA_MAX_VPORTS_QLA24XX 128
2221 #define QLA_MAX_VPORTS_QLA25XX 256
2222 /* Response queue data structure */
2223 struct rsp_que {
2224 dma_addr_t dma;
2225 response_t *ring;
2226 response_t *ring_ptr;
2227 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2228 uint32_t __iomem *rsp_q_out;
2229 uint16_t ring_index;
2230 uint16_t out_ptr;
2231 uint16_t length;
2232 uint16_t options;
2233 uint16_t rid;
2234 uint16_t id;
2235 uint16_t vp_idx;
2236 struct qla_hw_data *hw;
2237 struct qla_msix_entry *msix;
2238 struct req_que *req;
2239 srb_t *status_srb; /* status continuation entry */
2240 struct work_struct q_work;
2241 };
2242
2243 /* Request queue data structure */
2244 struct req_que {
2245 dma_addr_t dma;
2246 request_t *ring;
2247 request_t *ring_ptr;
2248 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2249 uint32_t __iomem *req_q_out;
2250 uint16_t ring_index;
2251 uint16_t in_ptr;
2252 uint16_t cnt;
2253 uint16_t length;
2254 uint16_t options;
2255 uint16_t rid;
2256 uint16_t id;
2257 uint16_t qos;
2258 uint16_t vp_idx;
2259 struct rsp_que *rsp;
2260 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2261 uint32_t current_outstanding_cmd;
2262 int max_q_depth;
2263 };
2264
2265 /* Place holder for FW buffer parameters */
2266 struct qlfc_fw {
2267 void *fw_buf;
2268 dma_addr_t fw_dma;
2269 uint32_t len;
2270 };
2271
2272 /*
2273 * Qlogic host adapter specific data structure.
2274 */
2275 struct qla_hw_data {
2276 struct pci_dev *pdev;
2277 /* SRB cache. */
2278 #define SRB_MIN_REQ 128
2279 mempool_t *srb_mempool;
2280
2281 volatile struct {
2282 uint32_t mbox_int :1;
2283 uint32_t mbox_busy :1;
2284
2285 uint32_t disable_risc_code_load :1;
2286 uint32_t enable_64bit_addressing :1;
2287 uint32_t enable_lip_reset :1;
2288 uint32_t enable_target_reset :1;
2289 uint32_t enable_lip_full_login :1;
2290 uint32_t enable_led_scheme :1;
2291 uint32_t inta_enabled :1;
2292 uint32_t msi_enabled :1;
2293 uint32_t msix_enabled :1;
2294 uint32_t disable_serdes :1;
2295 uint32_t gpsc_supported :1;
2296 uint32_t npiv_supported :1;
2297 uint32_t pci_channel_io_perm_failure :1;
2298 uint32_t fce_enabled :1;
2299 uint32_t fac_supported :1;
2300 uint32_t chip_reset_done :1;
2301 uint32_t port0 :1;
2302 uint32_t running_gold_fw :1;
2303 uint32_t eeh_busy :1;
2304 uint32_t cpu_affinity_enabled :1;
2305 uint32_t disable_msix_handshake :1;
2306 uint32_t fcp_prio_enabled :1;
2307 } flags;
2308
2309 /* This spinlock is used to protect "io transactions", you must
2310 * acquire it before doing any IO to the card, eg with RD_REG*() and
2311 * WRT_REG*() for the duration of your entire commandtransaction.
2312 *
2313 * This spinlock is of lower priority than the io request lock.
2314 */
2315
2316 spinlock_t hardware_lock ____cacheline_aligned;
2317 int bars;
2318 int mem_only;
2319 device_reg_t __iomem *iobase; /* Base I/O address */
2320 resource_size_t pio_address;
2321
2322 #define MIN_IOBASE_LEN 0x100
2323 /* Multi queue data structs */
2324 device_reg_t __iomem *mqiobase;
2325 uint16_t msix_count;
2326 uint8_t mqenable;
2327 struct req_que **req_q_map;
2328 struct rsp_que **rsp_q_map;
2329 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2330 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2331 uint8_t max_req_queues;
2332 uint8_t max_rsp_queues;
2333 struct qla_npiv_entry *npiv_info;
2334 uint16_t nvram_npiv_size;
2335
2336 uint16_t switch_cap;
2337 #define FLOGI_SEQ_DEL BIT_8
2338 #define FLOGI_MID_SUPPORT BIT_10
2339 #define FLOGI_VSAN_SUPPORT BIT_12
2340 #define FLOGI_SP_SUPPORT BIT_13
2341
2342 uint8_t port_no; /* Physical port of adapter */
2343
2344 /* Timeout timers. */
2345 uint8_t loop_down_abort_time; /* port down timer */
2346 atomic_t loop_down_timer; /* loop down timer */
2347 uint8_t link_down_timeout; /* link down timeout */
2348 uint16_t max_loop_id;
2349
2350 uint16_t fb_rev;
2351 uint16_t min_external_loopid; /* First external loop Id */
2352
2353 #define PORT_SPEED_UNKNOWN 0xFFFF
2354 #define PORT_SPEED_1GB 0x00
2355 #define PORT_SPEED_2GB 0x01
2356 #define PORT_SPEED_4GB 0x03
2357 #define PORT_SPEED_8GB 0x04
2358 #define PORT_SPEED_10GB 0x13
2359 uint16_t link_data_rate; /* F/W operating speed */
2360
2361 uint8_t current_topology;
2362 uint8_t prev_topology;
2363 #define ISP_CFG_NL 1
2364 #define ISP_CFG_N 2
2365 #define ISP_CFG_FL 4
2366 #define ISP_CFG_F 8
2367
2368 uint8_t operating_mode; /* F/W operating mode */
2369 #define LOOP 0
2370 #define P2P 1
2371 #define LOOP_P2P 2
2372 #define P2P_LOOP 3
2373 uint8_t interrupts_on;
2374 uint32_t isp_abort_cnt;
2375
2376 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2377 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2378 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2379 uint32_t device_type;
2380 #define DT_ISP2100 BIT_0
2381 #define DT_ISP2200 BIT_1
2382 #define DT_ISP2300 BIT_2
2383 #define DT_ISP2312 BIT_3
2384 #define DT_ISP2322 BIT_4
2385 #define DT_ISP6312 BIT_5
2386 #define DT_ISP6322 BIT_6
2387 #define DT_ISP2422 BIT_7
2388 #define DT_ISP2432 BIT_8
2389 #define DT_ISP5422 BIT_9
2390 #define DT_ISP5432 BIT_10
2391 #define DT_ISP2532 BIT_11
2392 #define DT_ISP8432 BIT_12
2393 #define DT_ISP8001 BIT_13
2394 #define DT_ISP8021 BIT_14
2395 #define DT_ISP_LAST (DT_ISP8021 << 1)
2396
2397 #define DT_IIDMA BIT_26
2398 #define DT_FWI2 BIT_27
2399 #define DT_ZIO_SUPPORTED BIT_28
2400 #define DT_OEM_001 BIT_29
2401 #define DT_ISP2200A BIT_30
2402 #define DT_EXTENDED_IDS BIT_31
2403 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2404 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2405 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2406 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2407 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2408 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2409 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2410 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2411 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2412 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2413 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2414 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2415 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2416 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2417 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2418 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2419
2420 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2421 IS_QLA6312(ha) || IS_QLA6322(ha))
2422 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2423 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2424 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2425 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2426 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2427 IS_QLA84XX(ha))
2428 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2429 #define IS_QLA8XXX_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha))
2430 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2431 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2432 IS_QLA82XX(ha))
2433 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha))
2434 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2435 (ha)->flags.msix_enabled)
2436 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2437 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2438 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2439
2440 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2441 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2442 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2443 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2444 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2445
2446 /* HBA serial number */
2447 uint8_t serial0;
2448 uint8_t serial1;
2449 uint8_t serial2;
2450
2451 /* NVRAM configuration data */
2452 #define MAX_NVRAM_SIZE 4096
2453 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2454 uint16_t nvram_size;
2455 uint16_t nvram_base;
2456 void *nvram;
2457 uint16_t vpd_size;
2458 uint16_t vpd_base;
2459 void *vpd;
2460
2461 uint16_t loop_reset_delay;
2462 uint8_t retry_count;
2463 uint8_t login_timeout;
2464 uint16_t r_a_tov;
2465 int port_down_retry_count;
2466 uint8_t mbx_count;
2467
2468 uint32_t login_retry_count;
2469 /* SNS command interfaces. */
2470 ms_iocb_entry_t *ms_iocb;
2471 dma_addr_t ms_iocb_dma;
2472 struct ct_sns_pkt *ct_sns;
2473 dma_addr_t ct_sns_dma;
2474 /* SNS command interfaces for 2200. */
2475 struct sns_cmd_pkt *sns_cmd;
2476 dma_addr_t sns_cmd_dma;
2477
2478 #define SFP_DEV_SIZE 256
2479 #define SFP_BLOCK_SIZE 64
2480 void *sfp_data;
2481 dma_addr_t sfp_data_dma;
2482
2483 uint8_t *edc_data;
2484 dma_addr_t edc_data_dma;
2485 uint16_t edc_data_len;
2486
2487 #define XGMAC_DATA_SIZE 4096
2488 void *xgmac_data;
2489 dma_addr_t xgmac_data_dma;
2490
2491 #define DCBX_TLV_DATA_SIZE 4096
2492 void *dcbx_tlv;
2493 dma_addr_t dcbx_tlv_dma;
2494
2495 struct task_struct *dpc_thread;
2496 uint8_t dpc_active; /* DPC routine is active */
2497
2498 dma_addr_t gid_list_dma;
2499 struct gid_list_info *gid_list;
2500 int gid_list_info_size;
2501
2502 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2503 #define DMA_POOL_SIZE 256
2504 struct dma_pool *s_dma_pool;
2505
2506 dma_addr_t init_cb_dma;
2507 init_cb_t *init_cb;
2508 int init_cb_size;
2509 dma_addr_t ex_init_cb_dma;
2510 struct ex_init_cb_81xx *ex_init_cb;
2511
2512 /* These are used by mailbox operations. */
2513 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2514
2515 mbx_cmd_t *mcp;
2516 unsigned long mbx_cmd_flags;
2517 #define MBX_INTERRUPT 1
2518 #define MBX_INTR_WAIT 2
2519 #define MBX_UPDATE_FLASH_ACTIVE 3
2520
2521 struct mutex vport_lock; /* Virtual port synchronization */
2522 struct completion mbx_cmd_comp; /* Serialize mbx access */
2523 struct completion mbx_intr_comp; /* Used for completion notification */
2524
2525 /* Basic firmware related information. */
2526 uint16_t fw_major_version;
2527 uint16_t fw_minor_version;
2528 uint16_t fw_subminor_version;
2529 uint16_t fw_attributes;
2530 uint32_t fw_memory_size;
2531 uint32_t fw_transfer_size;
2532 uint32_t fw_srisc_address;
2533 #define RISC_START_ADDRESS_2100 0x1000
2534 #define RISC_START_ADDRESS_2300 0x800
2535 #define RISC_START_ADDRESS_2400 0x100000
2536 uint16_t fw_xcb_count;
2537
2538 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2539 uint8_t fw_seriallink_options[4];
2540 uint16_t fw_seriallink_options24[4];
2541
2542 uint8_t mpi_version[3];
2543 uint32_t mpi_capabilities;
2544 uint8_t phy_version[3];
2545
2546 /* Firmware dump information. */
2547 struct qla2xxx_fw_dump *fw_dump;
2548 uint32_t fw_dump_len;
2549 int fw_dumped;
2550 int fw_dump_reading;
2551 dma_addr_t eft_dma;
2552 void *eft;
2553
2554 uint32_t chain_offset;
2555 struct dentry *dfs_dir;
2556 struct dentry *dfs_fce;
2557 dma_addr_t fce_dma;
2558 void *fce;
2559 uint32_t fce_bufs;
2560 uint16_t fce_mb[8];
2561 uint64_t fce_wr, fce_rd;
2562 struct mutex fce_mutex;
2563
2564 uint32_t pci_attr;
2565 uint16_t chip_revision;
2566
2567 uint16_t product_id[4];
2568
2569 uint8_t model_number[16+1];
2570 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2571 char model_desc[80];
2572 uint8_t adapter_id[16+1];
2573
2574 /* Option ROM information. */
2575 char *optrom_buffer;
2576 uint32_t optrom_size;
2577 int optrom_state;
2578 #define QLA_SWAITING 0
2579 #define QLA_SREADING 1
2580 #define QLA_SWRITING 2
2581 uint32_t optrom_region_start;
2582 uint32_t optrom_region_size;
2583
2584 /* PCI expansion ROM image information. */
2585 #define ROM_CODE_TYPE_BIOS 0
2586 #define ROM_CODE_TYPE_FCODE 1
2587 #define ROM_CODE_TYPE_EFI 3
2588 uint8_t bios_revision[2];
2589 uint8_t efi_revision[2];
2590 uint8_t fcode_revision[16];
2591 uint32_t fw_revision[4];
2592
2593 /* Offsets for flash/nvram access (set to ~0 if not used). */
2594 uint32_t flash_conf_off;
2595 uint32_t flash_data_off;
2596 uint32_t nvram_conf_off;
2597 uint32_t nvram_data_off;
2598
2599 uint32_t fdt_wrt_disable;
2600 uint32_t fdt_erase_cmd;
2601 uint32_t fdt_block_size;
2602 uint32_t fdt_unprotect_sec_cmd;
2603 uint32_t fdt_protect_sec_cmd;
2604
2605 uint32_t flt_region_flt;
2606 uint32_t flt_region_fdt;
2607 uint32_t flt_region_boot;
2608 uint32_t flt_region_fw;
2609 uint32_t flt_region_vpd_nvram;
2610 uint32_t flt_region_vpd;
2611 uint32_t flt_region_nvram;
2612 uint32_t flt_region_npiv_conf;
2613 uint32_t flt_region_gold_fw;
2614 uint32_t flt_region_fcp_prio;
2615 uint32_t flt_region_bootload;
2616
2617 /* Needed for BEACON */
2618 uint16_t beacon_blink_led;
2619 uint8_t beacon_color_state;
2620 #define QLA_LED_GRN_ON 0x01
2621 #define QLA_LED_YLW_ON 0x02
2622 #define QLA_LED_ABR_ON 0x04
2623 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2624 /* ISP2322: red, green, amber. */
2625 uint16_t zio_mode;
2626 uint16_t zio_timer;
2627 struct fc_host_statistics fc_host_stat;
2628
2629 struct qla_msix_entry *msix_entries;
2630
2631 struct list_head vp_list; /* list of VP */
2632 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2633 sizeof(unsigned long)];
2634 uint16_t num_vhosts; /* number of vports created */
2635 uint16_t num_vsans; /* number of vsan created */
2636 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2637 int cur_vport_count;
2638
2639 struct qla_chip_state_84xx *cs84xx;
2640 struct qla_statistics qla_stats;
2641 struct isp_operations *isp_ops;
2642 struct workqueue_struct *wq;
2643 struct qlfc_fw fw_buf;
2644
2645 /* FCP_CMND priority support */
2646 struct qla_fcp_prio_cfg *fcp_prio_cfg;
2647
2648 struct dma_pool *dl_dma_pool;
2649 #define DSD_LIST_DMA_POOL_SIZE 512
2650
2651 struct dma_pool *fcp_cmnd_dma_pool;
2652 mempool_t *ctx_mempool;
2653 #define FCP_CMND_DMA_POOL_SIZE 512
2654
2655 unsigned long nx_pcibase; /* Base I/O address */
2656 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
2657 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
2658 unsigned long first_page_group_start;
2659 unsigned long first_page_group_end;
2660
2661 uint32_t crb_win;
2662 uint32_t curr_window;
2663 uint32_t ddr_mn_window;
2664 unsigned long mn_win_crb;
2665 unsigned long ms_win_crb;
2666 int qdr_sn_window;
2667 uint32_t nx_dev_init_timeout;
2668 uint32_t nx_reset_timeout;
2669 rwlock_t hw_lock;
2670 uint16_t portnum; /* port number */
2671 int link_width;
2672 struct fw_blob *hablob;
2673 struct qla82xx_legacy_intr_set nx_legacy_intr;
2674
2675 uint16_t gbl_dsd_inuse;
2676 uint16_t gbl_dsd_avail;
2677 struct list_head gbl_dsd_list;
2678 #define NUM_DSD_CHAIN 4096
2679 };
2680
2681 /*
2682 * Qlogic scsi host structure
2683 */
2684 typedef struct scsi_qla_host {
2685 struct list_head list;
2686 struct list_head vp_fcports; /* list of fcports */
2687 struct list_head work_list;
2688 spinlock_t work_lock;
2689
2690 /* Commonly used flags and state information. */
2691 struct Scsi_Host *host;
2692 unsigned long host_no;
2693 uint8_t host_str[16];
2694
2695 volatile struct {
2696 uint32_t init_done :1;
2697 uint32_t online :1;
2698 uint32_t rscn_queue_overflow :1;
2699 uint32_t reset_active :1;
2700
2701 uint32_t management_server_logged_in :1;
2702 uint32_t process_response_queue :1;
2703 } flags;
2704
2705 atomic_t loop_state;
2706 #define LOOP_TIMEOUT 1
2707 #define LOOP_DOWN 2
2708 #define LOOP_UP 3
2709 #define LOOP_UPDATE 4
2710 #define LOOP_READY 5
2711 #define LOOP_DEAD 6
2712
2713 unsigned long dpc_flags;
2714 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2715 #define RESET_ACTIVE 1
2716 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2717 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2718 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2719 #define LOOP_RESYNC_ACTIVE 5
2720 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2721 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2722 #define RELOGIN_NEEDED 8
2723 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2724 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2725 #define BEACON_BLINK_NEEDED 11
2726 #define REGISTER_FDMI_NEEDED 12
2727 #define FCPORT_UPDATE_NEEDED 13
2728 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2729 #define UNLOADING 15
2730 #define NPIV_CONFIG_NEEDED 16
2731 #define ISP_UNRECOVERABLE 17
2732 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
2733
2734 uint32_t device_flags;
2735 #define SWITCH_FOUND BIT_0
2736 #define DFLG_NO_CABLE BIT_1
2737 #define DFLG_DEV_FAILED BIT_5
2738
2739 /* ISP configuration data. */
2740 uint16_t loop_id; /* Host adapter loop id */
2741
2742 port_id_t d_id; /* Host adapter port id */
2743 uint8_t marker_needed;
2744 uint16_t mgmt_svr_loop_id;
2745
2746
2747
2748 /* RSCN queue. */
2749 uint32_t rscn_queue[MAX_RSCN_COUNT];
2750 uint8_t rscn_in_ptr;
2751 uint8_t rscn_out_ptr;
2752
2753 /* Timeout timers. */
2754 uint8_t loop_down_abort_time; /* port down timer */
2755 atomic_t loop_down_timer; /* loop down timer */
2756 uint8_t link_down_timeout; /* link down timeout */
2757
2758 uint32_t timer_active;
2759 struct timer_list timer;
2760
2761 uint8_t node_name[WWN_SIZE];
2762 uint8_t port_name[WWN_SIZE];
2763 uint8_t fabric_node_name[WWN_SIZE];
2764
2765 uint16_t fcoe_vlan_id;
2766 uint16_t fcoe_fcf_idx;
2767 uint8_t fcoe_vn_port_mac[6];
2768
2769 uint32_t vp_abort_cnt;
2770
2771 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2772 uint16_t vp_idx; /* vport ID */
2773
2774 unsigned long vp_flags;
2775 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2776 #define VP_CREATE_NEEDED 1
2777 #define VP_BIND_NEEDED 2
2778 #define VP_DELETE_NEEDED 3
2779 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2780 atomic_t vp_state;
2781 #define VP_OFFLINE 0
2782 #define VP_ACTIVE 1
2783 #define VP_FAILED 2
2784 // #define VP_DISABLE 3
2785 uint16_t vp_err_state;
2786 uint16_t vp_prev_err_state;
2787 #define VP_ERR_UNKWN 0
2788 #define VP_ERR_PORTDWN 1
2789 #define VP_ERR_FAB_UNSUPPORTED 2
2790 #define VP_ERR_FAB_NORESOURCES 3
2791 #define VP_ERR_FAB_LOGOUT 4
2792 #define VP_ERR_ADAP_NORESOURCES 5
2793 struct qla_hw_data *hw;
2794 struct req_que *req;
2795 int fw_heartbeat_counter;
2796 int seconds_since_last_heartbeat;
2797 } scsi_qla_host_t;
2798
2799 /*
2800 * Macros to help code, maintain, etc.
2801 */
2802 #define LOOP_TRANSITION(ha) \
2803 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2804 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2805 atomic_read(&ha->loop_state) == LOOP_DOWN)
2806
2807 #define qla_printk(level, ha, format, arg...) \
2808 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2809
2810 /*
2811 * qla2x00 local function return status codes
2812 */
2813 #define MBS_MASK 0x3fff
2814
2815 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2816 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2817 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2818 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2819 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2820 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2821 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2822 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2823 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2824 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2825
2826 #define QLA_FUNCTION_TIMEOUT 0x100
2827 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2828 #define QLA_FUNCTION_FAILED 0x102
2829 #define QLA_MEMORY_ALLOC_FAILED 0x103
2830 #define QLA_LOCK_TIMEOUT 0x104
2831 #define QLA_ABORTED 0x105
2832 #define QLA_SUSPENDED 0x106
2833 #define QLA_BUSY 0x107
2834 #define QLA_RSCNS_HANDLED 0x108
2835 #define QLA_ALREADY_REGISTERED 0x109
2836
2837 #define NVRAM_DELAY() udelay(10)
2838
2839 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2840
2841 /*
2842 * Flash support definitions
2843 */
2844 #define OPTROM_SIZE_2300 0x20000
2845 #define OPTROM_SIZE_2322 0x100000
2846 #define OPTROM_SIZE_24XX 0x100000
2847 #define OPTROM_SIZE_25XX 0x200000
2848 #define OPTROM_SIZE_81XX 0x400000
2849 #define OPTROM_SIZE_82XX 0x800000
2850
2851 #define OPTROM_BURST_SIZE 0x1000
2852 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
2853
2854 #include "qla_gbl.h"
2855 #include "qla_dbg.h"
2856 #include "qla_inline.h"
2857
2858 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2859 #endif
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