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Merge branch 'x86-ptrace-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35
36 #define QLA2XXX_DRIVER_NAME "qla2xxx"
37
38 /*
39 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
40 * but that's fine as we don't look at the last 24 ones for
41 * ISP2100 HBAs.
42 */
43 #define MAILBOX_REGISTER_COUNT_2100 8
44 #define MAILBOX_REGISTER_COUNT 32
45
46 #define QLA2200A_RISC_ROM_VER 4
47 #define FPM_2300 6
48 #define FPM_2310 7
49
50 #include "qla_settings.h"
51
52 /*
53 * Data bit definitions
54 */
55 #define BIT_0 0x1
56 #define BIT_1 0x2
57 #define BIT_2 0x4
58 #define BIT_3 0x8
59 #define BIT_4 0x10
60 #define BIT_5 0x20
61 #define BIT_6 0x40
62 #define BIT_7 0x80
63 #define BIT_8 0x100
64 #define BIT_9 0x200
65 #define BIT_10 0x400
66 #define BIT_11 0x800
67 #define BIT_12 0x1000
68 #define BIT_13 0x2000
69 #define BIT_14 0x4000
70 #define BIT_15 0x8000
71 #define BIT_16 0x10000
72 #define BIT_17 0x20000
73 #define BIT_18 0x40000
74 #define BIT_19 0x80000
75 #define BIT_20 0x100000
76 #define BIT_21 0x200000
77 #define BIT_22 0x400000
78 #define BIT_23 0x800000
79 #define BIT_24 0x1000000
80 #define BIT_25 0x2000000
81 #define BIT_26 0x4000000
82 #define BIT_27 0x8000000
83 #define BIT_28 0x10000000
84 #define BIT_29 0x20000000
85 #define BIT_30 0x40000000
86 #define BIT_31 0x80000000
87
88 #define LSB(x) ((uint8_t)(x))
89 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
90
91 #define LSW(x) ((uint16_t)(x))
92 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
93
94 #define LSD(x) ((uint32_t)((uint64_t)(x)))
95 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
96
97 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
98
99 /*
100 * I/O register
101 */
102
103 #define RD_REG_BYTE(addr) readb(addr)
104 #define RD_REG_WORD(addr) readw(addr)
105 #define RD_REG_DWORD(addr) readl(addr)
106 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
107 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
108 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
109 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
110 #define WRT_REG_WORD(addr, data) writew(data,addr)
111 #define WRT_REG_DWORD(addr, data) writel(data,addr)
112
113 /*
114 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
115 * 133Mhz slot.
116 */
117 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
118 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
119
120 /*
121 * Fibre Channel device definitions.
122 */
123 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
124 #define MAX_FIBRE_DEVICES 512
125 #define MAX_FIBRE_LUNS 0xFFFF
126 #define MAX_RSCN_COUNT 32
127 #define MAX_HOST_COUNT 16
128
129 /*
130 * Host adapter default definitions.
131 */
132 #define MAX_BUSES 1 /* We only have one bus today */
133 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
134 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
135 #define MIN_LUNS 8
136 #define MAX_LUNS MAX_FIBRE_LUNS
137 #define MAX_CMDS_PER_LUN 255
138
139 /*
140 * Fibre Channel device definitions.
141 */
142 #define SNS_LAST_LOOP_ID_2100 0xfe
143 #define SNS_LAST_LOOP_ID_2300 0x7ff
144
145 #define LAST_LOCAL_LOOP_ID 0x7d
146 #define SNS_FL_PORT 0x7e
147 #define FABRIC_CONTROLLER 0x7f
148 #define SIMPLE_NAME_SERVER 0x80
149 #define SNS_FIRST_LOOP_ID 0x81
150 #define MANAGEMENT_SERVER 0xfe
151 #define BROADCAST 0xff
152
153 /*
154 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
155 * valid range of an N-PORT id is 0 through 0x7ef.
156 */
157 #define NPH_LAST_HANDLE 0x7ef
158 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
159 #define NPH_SNS 0x7fc /* FFFFFC */
160 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
161 #define NPH_F_PORT 0x7fe /* FFFFFE */
162 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
163
164 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
165 #include "qla_fw.h"
166
167 /*
168 * Timeout timer counts in seconds
169 */
170 #define PORT_RETRY_TIME 1
171 #define LOOP_DOWN_TIMEOUT 60
172 #define LOOP_DOWN_TIME 255 /* 240 */
173 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
174
175 /* Maximum outstanding commands in ISP queues (1-65535) */
176 #define MAX_OUTSTANDING_COMMANDS 1024
177
178 /* ISP request and response entry counts (37-65535) */
179 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
180 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
181 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
182 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
183 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
184 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
185
186 struct req_que;
187
188 /*
189 * SCSI Request Block
190 */
191 typedef struct srb {
192 struct fc_port *fcport;
193 uint32_t handle;
194
195 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
196
197 uint16_t flags;
198
199 uint32_t request_sense_length;
200 uint8_t *request_sense_ptr;
201
202 void *ctx;
203 } srb_t;
204
205 /*
206 * SRB flag definitions
207 */
208 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
209
210 /*
211 * SRB extensions.
212 */
213 struct srb_ctx {
214 #define SRB_LOGIN_CMD 1
215 #define SRB_LOGOUT_CMD 2
216 uint16_t type;
217 struct timer_list timer;
218
219 void (*free)(srb_t *sp);
220 void (*timeout)(srb_t *sp);
221 };
222
223 struct srb_logio {
224 struct srb_ctx ctx;
225
226 #define SRB_LOGIN_RETRIED BIT_0
227 #define SRB_LOGIN_COND_PLOGI BIT_1
228 #define SRB_LOGIN_SKIP_PRLI BIT_2
229 uint16_t flags;
230 };
231
232 struct srb_bsg_ctx {
233 #define SRB_ELS_CMD_RPT 3
234 #define SRB_ELS_CMD_HST 4
235 #define SRB_CT_CMD 5
236 uint16_t type;
237 };
238
239 struct srb_bsg {
240 struct srb_bsg_ctx ctx;
241 struct fc_bsg_job *bsg_job;
242 };
243
244 struct msg_echo_lb {
245 dma_addr_t send_dma;
246 dma_addr_t rcv_dma;
247 uint16_t req_sg_cnt;
248 uint16_t rsp_sg_cnt;
249 uint16_t options;
250 uint32_t transfer_size;
251 };
252
253 /*
254 * ISP I/O Register Set structure definitions.
255 */
256 struct device_reg_2xxx {
257 uint16_t flash_address; /* Flash BIOS address */
258 uint16_t flash_data; /* Flash BIOS data */
259 uint16_t unused_1[1]; /* Gap */
260 uint16_t ctrl_status; /* Control/Status */
261 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
262 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
263 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
264
265 uint16_t ictrl; /* Interrupt control */
266 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
267 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
268
269 uint16_t istatus; /* Interrupt status */
270 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
271
272 uint16_t semaphore; /* Semaphore */
273 uint16_t nvram; /* NVRAM register. */
274 #define NVR_DESELECT 0
275 #define NVR_BUSY BIT_15
276 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
277 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
278 #define NVR_DATA_IN BIT_3
279 #define NVR_DATA_OUT BIT_2
280 #define NVR_SELECT BIT_1
281 #define NVR_CLOCK BIT_0
282
283 #define NVR_WAIT_CNT 20000
284
285 union {
286 struct {
287 uint16_t mailbox0;
288 uint16_t mailbox1;
289 uint16_t mailbox2;
290 uint16_t mailbox3;
291 uint16_t mailbox4;
292 uint16_t mailbox5;
293 uint16_t mailbox6;
294 uint16_t mailbox7;
295 uint16_t unused_2[59]; /* Gap */
296 } __attribute__((packed)) isp2100;
297 struct {
298 /* Request Queue */
299 uint16_t req_q_in; /* In-Pointer */
300 uint16_t req_q_out; /* Out-Pointer */
301 /* Response Queue */
302 uint16_t rsp_q_in; /* In-Pointer */
303 uint16_t rsp_q_out; /* Out-Pointer */
304
305 /* RISC to Host Status */
306 uint32_t host_status;
307 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
308 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
309
310 /* Host to Host Semaphore */
311 uint16_t host_semaphore;
312 uint16_t unused_3[17]; /* Gap */
313 uint16_t mailbox0;
314 uint16_t mailbox1;
315 uint16_t mailbox2;
316 uint16_t mailbox3;
317 uint16_t mailbox4;
318 uint16_t mailbox5;
319 uint16_t mailbox6;
320 uint16_t mailbox7;
321 uint16_t mailbox8;
322 uint16_t mailbox9;
323 uint16_t mailbox10;
324 uint16_t mailbox11;
325 uint16_t mailbox12;
326 uint16_t mailbox13;
327 uint16_t mailbox14;
328 uint16_t mailbox15;
329 uint16_t mailbox16;
330 uint16_t mailbox17;
331 uint16_t mailbox18;
332 uint16_t mailbox19;
333 uint16_t mailbox20;
334 uint16_t mailbox21;
335 uint16_t mailbox22;
336 uint16_t mailbox23;
337 uint16_t mailbox24;
338 uint16_t mailbox25;
339 uint16_t mailbox26;
340 uint16_t mailbox27;
341 uint16_t mailbox28;
342 uint16_t mailbox29;
343 uint16_t mailbox30;
344 uint16_t mailbox31;
345 uint16_t fb_cmd;
346 uint16_t unused_4[10]; /* Gap */
347 } __attribute__((packed)) isp2300;
348 } u;
349
350 uint16_t fpm_diag_config;
351 uint16_t unused_5[0x4]; /* Gap */
352 uint16_t risc_hw;
353 uint16_t unused_5_1; /* Gap */
354 uint16_t pcr; /* Processor Control Register. */
355 uint16_t unused_6[0x5]; /* Gap */
356 uint16_t mctr; /* Memory Configuration and Timing. */
357 uint16_t unused_7[0x3]; /* Gap */
358 uint16_t fb_cmd_2100; /* Unused on 23XX */
359 uint16_t unused_8[0x3]; /* Gap */
360 uint16_t hccr; /* Host command & control register. */
361 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
362 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
363 /* HCCR commands */
364 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
365 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
366 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
367 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
368 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
369 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
370 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
371 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
372
373 uint16_t unused_9[5]; /* Gap */
374 uint16_t gpiod; /* GPIO Data register. */
375 uint16_t gpioe; /* GPIO Enable register. */
376 #define GPIO_LED_MASK 0x00C0
377 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
378 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
379 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
380 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
381 #define GPIO_LED_ALL_OFF 0x0000
382 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
383 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
384
385 union {
386 struct {
387 uint16_t unused_10[8]; /* Gap */
388 uint16_t mailbox8;
389 uint16_t mailbox9;
390 uint16_t mailbox10;
391 uint16_t mailbox11;
392 uint16_t mailbox12;
393 uint16_t mailbox13;
394 uint16_t mailbox14;
395 uint16_t mailbox15;
396 uint16_t mailbox16;
397 uint16_t mailbox17;
398 uint16_t mailbox18;
399 uint16_t mailbox19;
400 uint16_t mailbox20;
401 uint16_t mailbox21;
402 uint16_t mailbox22;
403 uint16_t mailbox23; /* Also probe reg. */
404 } __attribute__((packed)) isp2200;
405 } u_end;
406 };
407
408 struct device_reg_25xxmq {
409 uint32_t req_q_in;
410 uint32_t req_q_out;
411 uint32_t rsp_q_in;
412 uint32_t rsp_q_out;
413 };
414
415 typedef union {
416 struct device_reg_2xxx isp;
417 struct device_reg_24xx isp24;
418 struct device_reg_25xxmq isp25mq;
419 } device_reg_t;
420
421 #define ISP_REQ_Q_IN(ha, reg) \
422 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
423 &(reg)->u.isp2100.mailbox4 : \
424 &(reg)->u.isp2300.req_q_in)
425 #define ISP_REQ_Q_OUT(ha, reg) \
426 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
427 &(reg)->u.isp2100.mailbox4 : \
428 &(reg)->u.isp2300.req_q_out)
429 #define ISP_RSP_Q_IN(ha, reg) \
430 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
431 &(reg)->u.isp2100.mailbox5 : \
432 &(reg)->u.isp2300.rsp_q_in)
433 #define ISP_RSP_Q_OUT(ha, reg) \
434 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
435 &(reg)->u.isp2100.mailbox5 : \
436 &(reg)->u.isp2300.rsp_q_out)
437
438 #define MAILBOX_REG(ha, reg, num) \
439 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
440 (num < 8 ? \
441 &(reg)->u.isp2100.mailbox0 + (num) : \
442 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
443 &(reg)->u.isp2300.mailbox0 + (num))
444 #define RD_MAILBOX_REG(ha, reg, num) \
445 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
446 #define WRT_MAILBOX_REG(ha, reg, num, data) \
447 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
448
449 #define FB_CMD_REG(ha, reg) \
450 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
451 &(reg)->fb_cmd_2100 : \
452 &(reg)->u.isp2300.fb_cmd)
453 #define RD_FB_CMD_REG(ha, reg) \
454 RD_REG_WORD(FB_CMD_REG(ha, reg))
455 #define WRT_FB_CMD_REG(ha, reg, data) \
456 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
457
458 typedef struct {
459 uint32_t out_mb; /* outbound from driver */
460 uint32_t in_mb; /* Incoming from RISC */
461 uint16_t mb[MAILBOX_REGISTER_COUNT];
462 long buf_size;
463 void *bufp;
464 uint32_t tov;
465 uint8_t flags;
466 #define MBX_DMA_IN BIT_0
467 #define MBX_DMA_OUT BIT_1
468 #define IOCTL_CMD BIT_2
469 } mbx_cmd_t;
470
471 #define MBX_TOV_SECONDS 30
472
473 /*
474 * ISP product identification definitions in mailboxes after reset.
475 */
476 #define PROD_ID_1 0x4953
477 #define PROD_ID_2 0x0000
478 #define PROD_ID_2a 0x5020
479 #define PROD_ID_3 0x2020
480
481 /*
482 * ISP mailbox Self-Test status codes
483 */
484 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
485 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
486 #define MBS_BUSY 4 /* Busy. */
487
488 /*
489 * ISP mailbox command complete status codes
490 */
491 #define MBS_COMMAND_COMPLETE 0x4000
492 #define MBS_INVALID_COMMAND 0x4001
493 #define MBS_HOST_INTERFACE_ERROR 0x4002
494 #define MBS_TEST_FAILED 0x4003
495 #define MBS_COMMAND_ERROR 0x4005
496 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
497 #define MBS_PORT_ID_USED 0x4007
498 #define MBS_LOOP_ID_USED 0x4008
499 #define MBS_ALL_IDS_IN_USE 0x4009
500 #define MBS_NOT_LOGGED_IN 0x400A
501 #define MBS_LINK_DOWN_ERROR 0x400B
502 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
503
504 /*
505 * ISP mailbox asynchronous event status codes
506 */
507 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
508 #define MBA_RESET 0x8001 /* Reset Detected. */
509 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
510 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
511 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
512 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
513 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
514 /* occurred. */
515 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
516 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
517 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
518 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
519 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
520 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
521 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
522 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
523 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
524 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
525 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
526 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
527 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
528 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
529 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
530 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
531 /* used. */
532 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
533 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
534 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
535 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
536 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
537 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
538 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
539 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
540 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
541 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
542 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
543 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
544 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
545 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
546
547 /* ISP mailbox loopback echo diagnostic error code */
548 #define MBS_LB_RESET 0x17
549 /*
550 * Firmware options 1, 2, 3.
551 */
552 #define FO1_AE_ON_LIPF8 BIT_0
553 #define FO1_AE_ALL_LIP_RESET BIT_1
554 #define FO1_CTIO_RETRY BIT_3
555 #define FO1_DISABLE_LIP_F7_SW BIT_4
556 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
557 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
558 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
559 #define FO1_SET_EMPHASIS_SWING BIT_8
560 #define FO1_AE_AUTO_BYPASS BIT_9
561 #define FO1_ENABLE_PURE_IOCB BIT_10
562 #define FO1_AE_PLOGI_RJT BIT_11
563 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
564 #define FO1_AE_QUEUE_FULL BIT_13
565
566 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
567 #define FO2_REV_LOOPBACK BIT_1
568
569 #define FO3_ENABLE_EMERG_IOCB BIT_0
570 #define FO3_AE_RND_ERROR BIT_1
571
572 /* 24XX additional firmware options */
573 #define ADD_FO_COUNT 3
574 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
575 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
576
577 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
578
579 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
580
581 /*
582 * ISP mailbox commands
583 */
584 #define MBC_LOAD_RAM 1 /* Load RAM. */
585 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
586 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
587 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
588 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
589 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
590 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
591 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
592 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
593 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
594 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
595 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
596 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
597 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
598 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
599 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
600 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
601 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
602 #define MBC_RESET 0x18 /* Reset. */
603 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
604 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
605 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
606 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
607 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
608 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
609 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
610 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
611 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
612 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
613 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
614 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
615 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
616 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
617 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
618 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
619 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
620 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
621 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
622 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
623 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
624 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
625 /* Initialization Procedure */
626 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
627 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
628 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
629 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
630 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
631 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
632 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
633 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
634 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
635 #define MBC_LIP_RESET 0x6c /* LIP reset. */
636 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
637 /* commandd. */
638 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
639 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
640 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
641 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
642 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
643 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
644 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
645 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
646 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
647 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
648 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
649
650 /*
651 * ISP24xx mailbox commands
652 */
653 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
654 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
655 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
656 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
657 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
658 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
659 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
660 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
661 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
662 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
663 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
664 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
665 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
666 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
667 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
668 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
669
670 /* Firmware return data sizes */
671 #define FCAL_MAP_SIZE 128
672
673 /* Mailbox bit definitions for out_mb and in_mb */
674 #define MBX_31 BIT_31
675 #define MBX_30 BIT_30
676 #define MBX_29 BIT_29
677 #define MBX_28 BIT_28
678 #define MBX_27 BIT_27
679 #define MBX_26 BIT_26
680 #define MBX_25 BIT_25
681 #define MBX_24 BIT_24
682 #define MBX_23 BIT_23
683 #define MBX_22 BIT_22
684 #define MBX_21 BIT_21
685 #define MBX_20 BIT_20
686 #define MBX_19 BIT_19
687 #define MBX_18 BIT_18
688 #define MBX_17 BIT_17
689 #define MBX_16 BIT_16
690 #define MBX_15 BIT_15
691 #define MBX_14 BIT_14
692 #define MBX_13 BIT_13
693 #define MBX_12 BIT_12
694 #define MBX_11 BIT_11
695 #define MBX_10 BIT_10
696 #define MBX_9 BIT_9
697 #define MBX_8 BIT_8
698 #define MBX_7 BIT_7
699 #define MBX_6 BIT_6
700 #define MBX_5 BIT_5
701 #define MBX_4 BIT_4
702 #define MBX_3 BIT_3
703 #define MBX_2 BIT_2
704 #define MBX_1 BIT_1
705 #define MBX_0 BIT_0
706
707 /*
708 * Firmware state codes from get firmware state mailbox command
709 */
710 #define FSTATE_CONFIG_WAIT 0
711 #define FSTATE_WAIT_AL_PA 1
712 #define FSTATE_WAIT_LOGIN 2
713 #define FSTATE_READY 3
714 #define FSTATE_LOSS_OF_SYNC 4
715 #define FSTATE_ERROR 5
716 #define FSTATE_REINIT 6
717 #define FSTATE_NON_PART 7
718
719 #define FSTATE_CONFIG_CORRECT 0
720 #define FSTATE_P2P_RCV_LIP 1
721 #define FSTATE_P2P_CHOOSE_LOOP 2
722 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
723 #define FSTATE_FATAL_ERROR 4
724 #define FSTATE_LOOP_BACK_CONN 5
725
726 /*
727 * Port Database structure definition
728 * Little endian except where noted.
729 */
730 #define PORT_DATABASE_SIZE 128 /* bytes */
731 typedef struct {
732 uint8_t options;
733 uint8_t control;
734 uint8_t master_state;
735 uint8_t slave_state;
736 uint8_t reserved[2];
737 uint8_t hard_address;
738 uint8_t reserved_1;
739 uint8_t port_id[4];
740 uint8_t node_name[WWN_SIZE];
741 uint8_t port_name[WWN_SIZE];
742 uint16_t execution_throttle;
743 uint16_t execution_count;
744 uint8_t reset_count;
745 uint8_t reserved_2;
746 uint16_t resource_allocation;
747 uint16_t current_allocation;
748 uint16_t queue_head;
749 uint16_t queue_tail;
750 uint16_t transmit_execution_list_next;
751 uint16_t transmit_execution_list_previous;
752 uint16_t common_features;
753 uint16_t total_concurrent_sequences;
754 uint16_t RO_by_information_category;
755 uint8_t recipient;
756 uint8_t initiator;
757 uint16_t receive_data_size;
758 uint16_t concurrent_sequences;
759 uint16_t open_sequences_per_exchange;
760 uint16_t lun_abort_flags;
761 uint16_t lun_stop_flags;
762 uint16_t stop_queue_head;
763 uint16_t stop_queue_tail;
764 uint16_t port_retry_timer;
765 uint16_t next_sequence_id;
766 uint16_t frame_count;
767 uint16_t PRLI_payload_length;
768 uint8_t prli_svc_param_word_0[2]; /* Big endian */
769 /* Bits 15-0 of word 0 */
770 uint8_t prli_svc_param_word_3[2]; /* Big endian */
771 /* Bits 15-0 of word 3 */
772 uint16_t loop_id;
773 uint16_t extended_lun_info_list_pointer;
774 uint16_t extended_lun_stop_list_pointer;
775 } port_database_t;
776
777 /*
778 * Port database slave/master states
779 */
780 #define PD_STATE_DISCOVERY 0
781 #define PD_STATE_WAIT_DISCOVERY_ACK 1
782 #define PD_STATE_PORT_LOGIN 2
783 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
784 #define PD_STATE_PROCESS_LOGIN 4
785 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
786 #define PD_STATE_PORT_LOGGED_IN 6
787 #define PD_STATE_PORT_UNAVAILABLE 7
788 #define PD_STATE_PROCESS_LOGOUT 8
789 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
790 #define PD_STATE_PORT_LOGOUT 10
791 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
792
793
794 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
795 #define QLA_ZIO_DISABLED 0
796 #define QLA_ZIO_DEFAULT_TIMER 2
797
798 /*
799 * ISP Initialization Control Block.
800 * Little endian except where noted.
801 */
802 #define ICB_VERSION 1
803 typedef struct {
804 uint8_t version;
805 uint8_t reserved_1;
806
807 /*
808 * LSB BIT 0 = Enable Hard Loop Id
809 * LSB BIT 1 = Enable Fairness
810 * LSB BIT 2 = Enable Full-Duplex
811 * LSB BIT 3 = Enable Fast Posting
812 * LSB BIT 4 = Enable Target Mode
813 * LSB BIT 5 = Disable Initiator Mode
814 * LSB BIT 6 = Enable ADISC
815 * LSB BIT 7 = Enable Target Inquiry Data
816 *
817 * MSB BIT 0 = Enable PDBC Notify
818 * MSB BIT 1 = Non Participating LIP
819 * MSB BIT 2 = Descending Loop ID Search
820 * MSB BIT 3 = Acquire Loop ID in LIPA
821 * MSB BIT 4 = Stop PortQ on Full Status
822 * MSB BIT 5 = Full Login after LIP
823 * MSB BIT 6 = Node Name Option
824 * MSB BIT 7 = Ext IFWCB enable bit
825 */
826 uint8_t firmware_options[2];
827
828 uint16_t frame_payload_size;
829 uint16_t max_iocb_allocation;
830 uint16_t execution_throttle;
831 uint8_t retry_count;
832 uint8_t retry_delay; /* unused */
833 uint8_t port_name[WWN_SIZE]; /* Big endian. */
834 uint16_t hard_address;
835 uint8_t inquiry_data;
836 uint8_t login_timeout;
837 uint8_t node_name[WWN_SIZE]; /* Big endian. */
838
839 uint16_t request_q_outpointer;
840 uint16_t response_q_inpointer;
841 uint16_t request_q_length;
842 uint16_t response_q_length;
843 uint32_t request_q_address[2];
844 uint32_t response_q_address[2];
845
846 uint16_t lun_enables;
847 uint8_t command_resource_count;
848 uint8_t immediate_notify_resource_count;
849 uint16_t timeout;
850 uint8_t reserved_2[2];
851
852 /*
853 * LSB BIT 0 = Timer Operation mode bit 0
854 * LSB BIT 1 = Timer Operation mode bit 1
855 * LSB BIT 2 = Timer Operation mode bit 2
856 * LSB BIT 3 = Timer Operation mode bit 3
857 * LSB BIT 4 = Init Config Mode bit 0
858 * LSB BIT 5 = Init Config Mode bit 1
859 * LSB BIT 6 = Init Config Mode bit 2
860 * LSB BIT 7 = Enable Non part on LIHA failure
861 *
862 * MSB BIT 0 = Enable class 2
863 * MSB BIT 1 = Enable ACK0
864 * MSB BIT 2 =
865 * MSB BIT 3 =
866 * MSB BIT 4 = FC Tape Enable
867 * MSB BIT 5 = Enable FC Confirm
868 * MSB BIT 6 = Enable command queuing in target mode
869 * MSB BIT 7 = No Logo On Link Down
870 */
871 uint8_t add_firmware_options[2];
872
873 uint8_t response_accumulation_timer;
874 uint8_t interrupt_delay_timer;
875
876 /*
877 * LSB BIT 0 = Enable Read xfr_rdy
878 * LSB BIT 1 = Soft ID only
879 * LSB BIT 2 =
880 * LSB BIT 3 =
881 * LSB BIT 4 = FCP RSP Payload [0]
882 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
883 * LSB BIT 6 = Enable Out-of-Order frame handling
884 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
885 *
886 * MSB BIT 0 = Sbus enable - 2300
887 * MSB BIT 1 =
888 * MSB BIT 2 =
889 * MSB BIT 3 =
890 * MSB BIT 4 = LED mode
891 * MSB BIT 5 = enable 50 ohm termination
892 * MSB BIT 6 = Data Rate (2300 only)
893 * MSB BIT 7 = Data Rate (2300 only)
894 */
895 uint8_t special_options[2];
896
897 uint8_t reserved_3[26];
898 } init_cb_t;
899
900 /*
901 * Get Link Status mailbox command return buffer.
902 */
903 #define GLSO_SEND_RPS BIT_0
904 #define GLSO_USE_DID BIT_3
905
906 struct link_statistics {
907 uint32_t link_fail_cnt;
908 uint32_t loss_sync_cnt;
909 uint32_t loss_sig_cnt;
910 uint32_t prim_seq_err_cnt;
911 uint32_t inval_xmit_word_cnt;
912 uint32_t inval_crc_cnt;
913 uint32_t lip_cnt;
914 uint32_t unused1[0x1a];
915 uint32_t tx_frames;
916 uint32_t rx_frames;
917 uint32_t dumped_frames;
918 uint32_t unused2[2];
919 uint32_t nos_rcvd;
920 };
921
922 /*
923 * NVRAM Command values.
924 */
925 #define NV_START_BIT BIT_2
926 #define NV_WRITE_OP (BIT_26+BIT_24)
927 #define NV_READ_OP (BIT_26+BIT_25)
928 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
929 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
930 #define NV_DELAY_COUNT 10
931
932 /*
933 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
934 */
935 typedef struct {
936 /*
937 * NVRAM header
938 */
939 uint8_t id[4];
940 uint8_t nvram_version;
941 uint8_t reserved_0;
942
943 /*
944 * NVRAM RISC parameter block
945 */
946 uint8_t parameter_block_version;
947 uint8_t reserved_1;
948
949 /*
950 * LSB BIT 0 = Enable Hard Loop Id
951 * LSB BIT 1 = Enable Fairness
952 * LSB BIT 2 = Enable Full-Duplex
953 * LSB BIT 3 = Enable Fast Posting
954 * LSB BIT 4 = Enable Target Mode
955 * LSB BIT 5 = Disable Initiator Mode
956 * LSB BIT 6 = Enable ADISC
957 * LSB BIT 7 = Enable Target Inquiry Data
958 *
959 * MSB BIT 0 = Enable PDBC Notify
960 * MSB BIT 1 = Non Participating LIP
961 * MSB BIT 2 = Descending Loop ID Search
962 * MSB BIT 3 = Acquire Loop ID in LIPA
963 * MSB BIT 4 = Stop PortQ on Full Status
964 * MSB BIT 5 = Full Login after LIP
965 * MSB BIT 6 = Node Name Option
966 * MSB BIT 7 = Ext IFWCB enable bit
967 */
968 uint8_t firmware_options[2];
969
970 uint16_t frame_payload_size;
971 uint16_t max_iocb_allocation;
972 uint16_t execution_throttle;
973 uint8_t retry_count;
974 uint8_t retry_delay; /* unused */
975 uint8_t port_name[WWN_SIZE]; /* Big endian. */
976 uint16_t hard_address;
977 uint8_t inquiry_data;
978 uint8_t login_timeout;
979 uint8_t node_name[WWN_SIZE]; /* Big endian. */
980
981 /*
982 * LSB BIT 0 = Timer Operation mode bit 0
983 * LSB BIT 1 = Timer Operation mode bit 1
984 * LSB BIT 2 = Timer Operation mode bit 2
985 * LSB BIT 3 = Timer Operation mode bit 3
986 * LSB BIT 4 = Init Config Mode bit 0
987 * LSB BIT 5 = Init Config Mode bit 1
988 * LSB BIT 6 = Init Config Mode bit 2
989 * LSB BIT 7 = Enable Non part on LIHA failure
990 *
991 * MSB BIT 0 = Enable class 2
992 * MSB BIT 1 = Enable ACK0
993 * MSB BIT 2 =
994 * MSB BIT 3 =
995 * MSB BIT 4 = FC Tape Enable
996 * MSB BIT 5 = Enable FC Confirm
997 * MSB BIT 6 = Enable command queuing in target mode
998 * MSB BIT 7 = No Logo On Link Down
999 */
1000 uint8_t add_firmware_options[2];
1001
1002 uint8_t response_accumulation_timer;
1003 uint8_t interrupt_delay_timer;
1004
1005 /*
1006 * LSB BIT 0 = Enable Read xfr_rdy
1007 * LSB BIT 1 = Soft ID only
1008 * LSB BIT 2 =
1009 * LSB BIT 3 =
1010 * LSB BIT 4 = FCP RSP Payload [0]
1011 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1012 * LSB BIT 6 = Enable Out-of-Order frame handling
1013 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1014 *
1015 * MSB BIT 0 = Sbus enable - 2300
1016 * MSB BIT 1 =
1017 * MSB BIT 2 =
1018 * MSB BIT 3 =
1019 * MSB BIT 4 = LED mode
1020 * MSB BIT 5 = enable 50 ohm termination
1021 * MSB BIT 6 = Data Rate (2300 only)
1022 * MSB BIT 7 = Data Rate (2300 only)
1023 */
1024 uint8_t special_options[2];
1025
1026 /* Reserved for expanded RISC parameter block */
1027 uint8_t reserved_2[22];
1028
1029 /*
1030 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1031 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1032 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1033 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1034 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1035 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1036 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1037 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1038 *
1039 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1040 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1041 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1042 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1043 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1044 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1045 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1046 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1047 *
1048 * LSB BIT 0 = Output Swing 1G bit 0
1049 * LSB BIT 1 = Output Swing 1G bit 1
1050 * LSB BIT 2 = Output Swing 1G bit 2
1051 * LSB BIT 3 = Output Emphasis 1G bit 0
1052 * LSB BIT 4 = Output Emphasis 1G bit 1
1053 * LSB BIT 5 = Output Swing 2G bit 0
1054 * LSB BIT 6 = Output Swing 2G bit 1
1055 * LSB BIT 7 = Output Swing 2G bit 2
1056 *
1057 * MSB BIT 0 = Output Emphasis 2G bit 0
1058 * MSB BIT 1 = Output Emphasis 2G bit 1
1059 * MSB BIT 2 = Output Enable
1060 * MSB BIT 3 =
1061 * MSB BIT 4 =
1062 * MSB BIT 5 =
1063 * MSB BIT 6 =
1064 * MSB BIT 7 =
1065 */
1066 uint8_t seriallink_options[4];
1067
1068 /*
1069 * NVRAM host parameter block
1070 *
1071 * LSB BIT 0 = Enable spinup delay
1072 * LSB BIT 1 = Disable BIOS
1073 * LSB BIT 2 = Enable Memory Map BIOS
1074 * LSB BIT 3 = Enable Selectable Boot
1075 * LSB BIT 4 = Disable RISC code load
1076 * LSB BIT 5 = Set cache line size 1
1077 * LSB BIT 6 = PCI Parity Disable
1078 * LSB BIT 7 = Enable extended logging
1079 *
1080 * MSB BIT 0 = Enable 64bit addressing
1081 * MSB BIT 1 = Enable lip reset
1082 * MSB BIT 2 = Enable lip full login
1083 * MSB BIT 3 = Enable target reset
1084 * MSB BIT 4 = Enable database storage
1085 * MSB BIT 5 = Enable cache flush read
1086 * MSB BIT 6 = Enable database load
1087 * MSB BIT 7 = Enable alternate WWN
1088 */
1089 uint8_t host_p[2];
1090
1091 uint8_t boot_node_name[WWN_SIZE];
1092 uint8_t boot_lun_number;
1093 uint8_t reset_delay;
1094 uint8_t port_down_retry_count;
1095 uint8_t boot_id_number;
1096 uint16_t max_luns_per_target;
1097 uint8_t fcode_boot_port_name[WWN_SIZE];
1098 uint8_t alternate_port_name[WWN_SIZE];
1099 uint8_t alternate_node_name[WWN_SIZE];
1100
1101 /*
1102 * BIT 0 = Selective Login
1103 * BIT 1 = Alt-Boot Enable
1104 * BIT 2 =
1105 * BIT 3 = Boot Order List
1106 * BIT 4 =
1107 * BIT 5 = Selective LUN
1108 * BIT 6 =
1109 * BIT 7 = unused
1110 */
1111 uint8_t efi_parameters;
1112
1113 uint8_t link_down_timeout;
1114
1115 uint8_t adapter_id[16];
1116
1117 uint8_t alt1_boot_node_name[WWN_SIZE];
1118 uint16_t alt1_boot_lun_number;
1119 uint8_t alt2_boot_node_name[WWN_SIZE];
1120 uint16_t alt2_boot_lun_number;
1121 uint8_t alt3_boot_node_name[WWN_SIZE];
1122 uint16_t alt3_boot_lun_number;
1123 uint8_t alt4_boot_node_name[WWN_SIZE];
1124 uint16_t alt4_boot_lun_number;
1125 uint8_t alt5_boot_node_name[WWN_SIZE];
1126 uint16_t alt5_boot_lun_number;
1127 uint8_t alt6_boot_node_name[WWN_SIZE];
1128 uint16_t alt6_boot_lun_number;
1129 uint8_t alt7_boot_node_name[WWN_SIZE];
1130 uint16_t alt7_boot_lun_number;
1131
1132 uint8_t reserved_3[2];
1133
1134 /* Offset 200-215 : Model Number */
1135 uint8_t model_number[16];
1136
1137 /* OEM related items */
1138 uint8_t oem_specific[16];
1139
1140 /*
1141 * NVRAM Adapter Features offset 232-239
1142 *
1143 * LSB BIT 0 = External GBIC
1144 * LSB BIT 1 = Risc RAM parity
1145 * LSB BIT 2 = Buffer Plus Module
1146 * LSB BIT 3 = Multi Chip Adapter
1147 * LSB BIT 4 = Internal connector
1148 * LSB BIT 5 =
1149 * LSB BIT 6 =
1150 * LSB BIT 7 =
1151 *
1152 * MSB BIT 0 =
1153 * MSB BIT 1 =
1154 * MSB BIT 2 =
1155 * MSB BIT 3 =
1156 * MSB BIT 4 =
1157 * MSB BIT 5 =
1158 * MSB BIT 6 =
1159 * MSB BIT 7 =
1160 */
1161 uint8_t adapter_features[2];
1162
1163 uint8_t reserved_4[16];
1164
1165 /* Subsystem vendor ID for ISP2200 */
1166 uint16_t subsystem_vendor_id_2200;
1167
1168 /* Subsystem device ID for ISP2200 */
1169 uint16_t subsystem_device_id_2200;
1170
1171 uint8_t reserved_5;
1172 uint8_t checksum;
1173 } nvram_t;
1174
1175 /*
1176 * ISP queue - response queue entry definition.
1177 */
1178 typedef struct {
1179 uint8_t data[60];
1180 uint32_t signature;
1181 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1182 } response_t;
1183
1184 typedef union {
1185 uint16_t extended;
1186 struct {
1187 uint8_t reserved;
1188 uint8_t standard;
1189 } id;
1190 } target_id_t;
1191
1192 #define SET_TARGET_ID(ha, to, from) \
1193 do { \
1194 if (HAS_EXTENDED_IDS(ha)) \
1195 to.extended = cpu_to_le16(from); \
1196 else \
1197 to.id.standard = (uint8_t)from; \
1198 } while (0)
1199
1200 /*
1201 * ISP queue - command entry structure definition.
1202 */
1203 #define COMMAND_TYPE 0x11 /* Command entry */
1204 typedef struct {
1205 uint8_t entry_type; /* Entry type. */
1206 uint8_t entry_count; /* Entry count. */
1207 uint8_t sys_define; /* System defined. */
1208 uint8_t entry_status; /* Entry Status. */
1209 uint32_t handle; /* System handle. */
1210 target_id_t target; /* SCSI ID */
1211 uint16_t lun; /* SCSI LUN */
1212 uint16_t control_flags; /* Control flags. */
1213 #define CF_WRITE BIT_6
1214 #define CF_READ BIT_5
1215 #define CF_SIMPLE_TAG BIT_3
1216 #define CF_ORDERED_TAG BIT_2
1217 #define CF_HEAD_TAG BIT_1
1218 uint16_t reserved_1;
1219 uint16_t timeout; /* Command timeout. */
1220 uint16_t dseg_count; /* Data segment count. */
1221 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1222 uint32_t byte_count; /* Total byte count. */
1223 uint32_t dseg_0_address; /* Data segment 0 address. */
1224 uint32_t dseg_0_length; /* Data segment 0 length. */
1225 uint32_t dseg_1_address; /* Data segment 1 address. */
1226 uint32_t dseg_1_length; /* Data segment 1 length. */
1227 uint32_t dseg_2_address; /* Data segment 2 address. */
1228 uint32_t dseg_2_length; /* Data segment 2 length. */
1229 } cmd_entry_t;
1230
1231 /*
1232 * ISP queue - 64-Bit addressing, command entry structure definition.
1233 */
1234 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1235 typedef struct {
1236 uint8_t entry_type; /* Entry type. */
1237 uint8_t entry_count; /* Entry count. */
1238 uint8_t sys_define; /* System defined. */
1239 uint8_t entry_status; /* Entry Status. */
1240 uint32_t handle; /* System handle. */
1241 target_id_t target; /* SCSI ID */
1242 uint16_t lun; /* SCSI LUN */
1243 uint16_t control_flags; /* Control flags. */
1244 uint16_t reserved_1;
1245 uint16_t timeout; /* Command timeout. */
1246 uint16_t dseg_count; /* Data segment count. */
1247 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1248 uint32_t byte_count; /* Total byte count. */
1249 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1250 uint32_t dseg_0_length; /* Data segment 0 length. */
1251 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1252 uint32_t dseg_1_length; /* Data segment 1 length. */
1253 } cmd_a64_entry_t, request_t;
1254
1255 /*
1256 * ISP queue - continuation entry structure definition.
1257 */
1258 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1259 typedef struct {
1260 uint8_t entry_type; /* Entry type. */
1261 uint8_t entry_count; /* Entry count. */
1262 uint8_t sys_define; /* System defined. */
1263 uint8_t entry_status; /* Entry Status. */
1264 uint32_t reserved;
1265 uint32_t dseg_0_address; /* Data segment 0 address. */
1266 uint32_t dseg_0_length; /* Data segment 0 length. */
1267 uint32_t dseg_1_address; /* Data segment 1 address. */
1268 uint32_t dseg_1_length; /* Data segment 1 length. */
1269 uint32_t dseg_2_address; /* Data segment 2 address. */
1270 uint32_t dseg_2_length; /* Data segment 2 length. */
1271 uint32_t dseg_3_address; /* Data segment 3 address. */
1272 uint32_t dseg_3_length; /* Data segment 3 length. */
1273 uint32_t dseg_4_address; /* Data segment 4 address. */
1274 uint32_t dseg_4_length; /* Data segment 4 length. */
1275 uint32_t dseg_5_address; /* Data segment 5 address. */
1276 uint32_t dseg_5_length; /* Data segment 5 length. */
1277 uint32_t dseg_6_address; /* Data segment 6 address. */
1278 uint32_t dseg_6_length; /* Data segment 6 length. */
1279 } cont_entry_t;
1280
1281 /*
1282 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1283 */
1284 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1285 typedef struct {
1286 uint8_t entry_type; /* Entry type. */
1287 uint8_t entry_count; /* Entry count. */
1288 uint8_t sys_define; /* System defined. */
1289 uint8_t entry_status; /* Entry Status. */
1290 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1291 uint32_t dseg_0_length; /* Data segment 0 length. */
1292 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1293 uint32_t dseg_1_length; /* Data segment 1 length. */
1294 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1295 uint32_t dseg_2_length; /* Data segment 2 length. */
1296 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1297 uint32_t dseg_3_length; /* Data segment 3 length. */
1298 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1299 uint32_t dseg_4_length; /* Data segment 4 length. */
1300 } cont_a64_entry_t;
1301
1302 /*
1303 * ISP queue - status entry structure definition.
1304 */
1305 #define STATUS_TYPE 0x03 /* Status entry. */
1306 typedef struct {
1307 uint8_t entry_type; /* Entry type. */
1308 uint8_t entry_count; /* Entry count. */
1309 uint8_t sys_define; /* System defined. */
1310 uint8_t entry_status; /* Entry Status. */
1311 uint32_t handle; /* System handle. */
1312 uint16_t scsi_status; /* SCSI status. */
1313 uint16_t comp_status; /* Completion status. */
1314 uint16_t state_flags; /* State flags. */
1315 uint16_t status_flags; /* Status flags. */
1316 uint16_t rsp_info_len; /* Response Info Length. */
1317 uint16_t req_sense_length; /* Request sense data length. */
1318 uint32_t residual_length; /* Residual transfer length. */
1319 uint8_t rsp_info[8]; /* FCP response information. */
1320 uint8_t req_sense_data[32]; /* Request sense data. */
1321 } sts_entry_t;
1322
1323 /*
1324 * Status entry entry status
1325 */
1326 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1327 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1328 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1329 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1330 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1331 #define RF_BUSY BIT_1 /* Busy */
1332 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1333 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1334 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1335 RF_INV_E_TYPE)
1336
1337 /*
1338 * Status entry SCSI status bit definitions.
1339 */
1340 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1341 #define SS_RESIDUAL_UNDER BIT_11
1342 #define SS_RESIDUAL_OVER BIT_10
1343 #define SS_SENSE_LEN_VALID BIT_9
1344 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1345
1346 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1347 #define SS_BUSY_CONDITION BIT_3
1348 #define SS_CONDITION_MET BIT_2
1349 #define SS_CHECK_CONDITION BIT_1
1350
1351 /*
1352 * Status entry completion status
1353 */
1354 #define CS_COMPLETE 0x0 /* No errors */
1355 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1356 #define CS_DMA 0x2 /* A DMA direction error. */
1357 #define CS_TRANSPORT 0x3 /* Transport error. */
1358 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1359 #define CS_ABORTED 0x5 /* System aborted command. */
1360 #define CS_TIMEOUT 0x6 /* Timeout error. */
1361 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1362
1363 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1364 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1365 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1366 /* (selection timeout) */
1367 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1368 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1369 #define CS_PORT_BUSY 0x2B /* Port Busy */
1370 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1371 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1372 #define CS_UNKNOWN 0x81 /* Driver defined */
1373 #define CS_RETRY 0x82 /* Driver defined */
1374 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1375
1376 /*
1377 * Status entry status flags
1378 */
1379 #define SF_ABTS_TERMINATED BIT_10
1380 #define SF_LOGOUT_SENT BIT_13
1381
1382 /*
1383 * ISP queue - status continuation entry structure definition.
1384 */
1385 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1386 typedef struct {
1387 uint8_t entry_type; /* Entry type. */
1388 uint8_t entry_count; /* Entry count. */
1389 uint8_t sys_define; /* System defined. */
1390 uint8_t entry_status; /* Entry Status. */
1391 uint8_t data[60]; /* data */
1392 } sts_cont_entry_t;
1393
1394 /*
1395 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1396 * structure definition.
1397 */
1398 #define STATUS_TYPE_21 0x21 /* Status entry. */
1399 typedef struct {
1400 uint8_t entry_type; /* Entry type. */
1401 uint8_t entry_count; /* Entry count. */
1402 uint8_t handle_count; /* Handle count. */
1403 uint8_t entry_status; /* Entry Status. */
1404 uint32_t handle[15]; /* System handles. */
1405 } sts21_entry_t;
1406
1407 /*
1408 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1409 * structure definition.
1410 */
1411 #define STATUS_TYPE_22 0x22 /* Status entry. */
1412 typedef struct {
1413 uint8_t entry_type; /* Entry type. */
1414 uint8_t entry_count; /* Entry count. */
1415 uint8_t handle_count; /* Handle count. */
1416 uint8_t entry_status; /* Entry Status. */
1417 uint16_t handle[30]; /* System handles. */
1418 } sts22_entry_t;
1419
1420 /*
1421 * ISP queue - marker entry structure definition.
1422 */
1423 #define MARKER_TYPE 0x04 /* Marker entry. */
1424 typedef struct {
1425 uint8_t entry_type; /* Entry type. */
1426 uint8_t entry_count; /* Entry count. */
1427 uint8_t handle_count; /* Handle count. */
1428 uint8_t entry_status; /* Entry Status. */
1429 uint32_t sys_define_2; /* System defined. */
1430 target_id_t target; /* SCSI ID */
1431 uint8_t modifier; /* Modifier (7-0). */
1432 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1433 #define MK_SYNC_ID 1 /* Synchronize ID */
1434 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1435 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1436 /* clear port changed, */
1437 /* use sequence number. */
1438 uint8_t reserved_1;
1439 uint16_t sequence_number; /* Sequence number of event */
1440 uint16_t lun; /* SCSI LUN */
1441 uint8_t reserved_2[48];
1442 } mrk_entry_t;
1443
1444 /*
1445 * ISP queue - Management Server entry structure definition.
1446 */
1447 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1448 typedef struct {
1449 uint8_t entry_type; /* Entry type. */
1450 uint8_t entry_count; /* Entry count. */
1451 uint8_t handle_count; /* Handle count. */
1452 uint8_t entry_status; /* Entry Status. */
1453 uint32_t handle1; /* System handle. */
1454 target_id_t loop_id;
1455 uint16_t status;
1456 uint16_t control_flags; /* Control flags. */
1457 uint16_t reserved2;
1458 uint16_t timeout;
1459 uint16_t cmd_dsd_count;
1460 uint16_t total_dsd_count;
1461 uint8_t type;
1462 uint8_t r_ctl;
1463 uint16_t rx_id;
1464 uint16_t reserved3;
1465 uint32_t handle2;
1466 uint32_t rsp_bytecount;
1467 uint32_t req_bytecount;
1468 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1469 uint32_t dseg_req_length; /* Data segment 0 length. */
1470 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1471 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1472 } ms_iocb_entry_t;
1473
1474
1475 /*
1476 * ISP queue - Mailbox Command entry structure definition.
1477 */
1478 #define MBX_IOCB_TYPE 0x39
1479 struct mbx_entry {
1480 uint8_t entry_type;
1481 uint8_t entry_count;
1482 uint8_t sys_define1;
1483 /* Use sys_define1 for source type */
1484 #define SOURCE_SCSI 0x00
1485 #define SOURCE_IP 0x01
1486 #define SOURCE_VI 0x02
1487 #define SOURCE_SCTP 0x03
1488 #define SOURCE_MP 0x04
1489 #define SOURCE_MPIOCTL 0x05
1490 #define SOURCE_ASYNC_IOCB 0x07
1491
1492 uint8_t entry_status;
1493
1494 uint32_t handle;
1495 target_id_t loop_id;
1496
1497 uint16_t status;
1498 uint16_t state_flags;
1499 uint16_t status_flags;
1500
1501 uint32_t sys_define2[2];
1502
1503 uint16_t mb0;
1504 uint16_t mb1;
1505 uint16_t mb2;
1506 uint16_t mb3;
1507 uint16_t mb6;
1508 uint16_t mb7;
1509 uint16_t mb9;
1510 uint16_t mb10;
1511 uint32_t reserved_2[2];
1512 uint8_t node_name[WWN_SIZE];
1513 uint8_t port_name[WWN_SIZE];
1514 };
1515
1516 /*
1517 * ISP request and response queue entry sizes
1518 */
1519 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1520 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1521
1522
1523 /*
1524 * 24 bit port ID type definition.
1525 */
1526 typedef union {
1527 uint32_t b24 : 24;
1528
1529 struct {
1530 #ifdef __BIG_ENDIAN
1531 uint8_t domain;
1532 uint8_t area;
1533 uint8_t al_pa;
1534 #elif defined(__LITTLE_ENDIAN)
1535 uint8_t al_pa;
1536 uint8_t area;
1537 uint8_t domain;
1538 #else
1539 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1540 #endif
1541 uint8_t rsvd_1;
1542 } b;
1543 } port_id_t;
1544 #define INVALID_PORT_ID 0xFFFFFF
1545
1546 /*
1547 * Switch info gathering structure.
1548 */
1549 typedef struct {
1550 port_id_t d_id;
1551 uint8_t node_name[WWN_SIZE];
1552 uint8_t port_name[WWN_SIZE];
1553 uint8_t fabric_port_name[WWN_SIZE];
1554 uint16_t fp_speed;
1555 } sw_info_t;
1556
1557 /*
1558 * Fibre channel port type.
1559 */
1560 typedef enum {
1561 FCT_UNKNOWN,
1562 FCT_RSCN,
1563 FCT_SWITCH,
1564 FCT_BROADCAST,
1565 FCT_INITIATOR,
1566 FCT_TARGET
1567 } fc_port_type_t;
1568
1569 /*
1570 * Fibre channel port structure.
1571 */
1572 typedef struct fc_port {
1573 struct list_head list;
1574 struct scsi_qla_host *vha;
1575
1576 uint8_t node_name[WWN_SIZE];
1577 uint8_t port_name[WWN_SIZE];
1578 port_id_t d_id;
1579 uint16_t loop_id;
1580 uint16_t old_loop_id;
1581
1582 uint8_t fabric_port_name[WWN_SIZE];
1583 uint16_t fp_speed;
1584
1585 fc_port_type_t port_type;
1586
1587 atomic_t state;
1588 uint32_t flags;
1589
1590 int port_login_retry_count;
1591 int login_retry;
1592 atomic_t port_down_timer;
1593
1594 struct fc_rport *rport, *drport;
1595 u32 supported_classes;
1596
1597 uint16_t vp_idx;
1598 } fc_port_t;
1599
1600 /*
1601 * Fibre channel port/lun states.
1602 */
1603 #define FCS_UNCONFIGURED 1
1604 #define FCS_DEVICE_DEAD 2
1605 #define FCS_DEVICE_LOST 3
1606 #define FCS_ONLINE 4
1607
1608 /*
1609 * FC port flags.
1610 */
1611 #define FCF_FABRIC_DEVICE BIT_0
1612 #define FCF_LOGIN_NEEDED BIT_1
1613 #define FCF_FCP2_DEVICE BIT_2
1614
1615 /* No loop ID flag. */
1616 #define FC_NO_LOOP_ID 0x1000
1617
1618 /*
1619 * FC-CT interface
1620 *
1621 * NOTE: All structures are big-endian in form.
1622 */
1623
1624 #define CT_REJECT_RESPONSE 0x8001
1625 #define CT_ACCEPT_RESPONSE 0x8002
1626 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1627 #define CT_REASON_CANNOT_PERFORM 0x09
1628 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1629 #define CT_EXPL_ALREADY_REGISTERED 0x10
1630
1631 #define NS_N_PORT_TYPE 0x01
1632 #define NS_NL_PORT_TYPE 0x02
1633 #define NS_NX_PORT_TYPE 0x7F
1634
1635 #define GA_NXT_CMD 0x100
1636 #define GA_NXT_REQ_SIZE (16 + 4)
1637 #define GA_NXT_RSP_SIZE (16 + 620)
1638
1639 #define GID_PT_CMD 0x1A1
1640 #define GID_PT_REQ_SIZE (16 + 4)
1641 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1642
1643 #define GPN_ID_CMD 0x112
1644 #define GPN_ID_REQ_SIZE (16 + 4)
1645 #define GPN_ID_RSP_SIZE (16 + 8)
1646
1647 #define GNN_ID_CMD 0x113
1648 #define GNN_ID_REQ_SIZE (16 + 4)
1649 #define GNN_ID_RSP_SIZE (16 + 8)
1650
1651 #define GFT_ID_CMD 0x117
1652 #define GFT_ID_REQ_SIZE (16 + 4)
1653 #define GFT_ID_RSP_SIZE (16 + 32)
1654
1655 #define RFT_ID_CMD 0x217
1656 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1657 #define RFT_ID_RSP_SIZE 16
1658
1659 #define RFF_ID_CMD 0x21F
1660 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1661 #define RFF_ID_RSP_SIZE 16
1662
1663 #define RNN_ID_CMD 0x213
1664 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1665 #define RNN_ID_RSP_SIZE 16
1666
1667 #define RSNN_NN_CMD 0x239
1668 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1669 #define RSNN_NN_RSP_SIZE 16
1670
1671 #define GFPN_ID_CMD 0x11C
1672 #define GFPN_ID_REQ_SIZE (16 + 4)
1673 #define GFPN_ID_RSP_SIZE (16 + 8)
1674
1675 #define GPSC_CMD 0x127
1676 #define GPSC_REQ_SIZE (16 + 8)
1677 #define GPSC_RSP_SIZE (16 + 2 + 2)
1678
1679
1680 /*
1681 * HBA attribute types.
1682 */
1683 #define FDMI_HBA_ATTR_COUNT 9
1684 #define FDMI_HBA_NODE_NAME 1
1685 #define FDMI_HBA_MANUFACTURER 2
1686 #define FDMI_HBA_SERIAL_NUMBER 3
1687 #define FDMI_HBA_MODEL 4
1688 #define FDMI_HBA_MODEL_DESCRIPTION 5
1689 #define FDMI_HBA_HARDWARE_VERSION 6
1690 #define FDMI_HBA_DRIVER_VERSION 7
1691 #define FDMI_HBA_OPTION_ROM_VERSION 8
1692 #define FDMI_HBA_FIRMWARE_VERSION 9
1693 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1694 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1695
1696 struct ct_fdmi_hba_attr {
1697 uint16_t type;
1698 uint16_t len;
1699 union {
1700 uint8_t node_name[WWN_SIZE];
1701 uint8_t manufacturer[32];
1702 uint8_t serial_num[8];
1703 uint8_t model[16];
1704 uint8_t model_desc[80];
1705 uint8_t hw_version[16];
1706 uint8_t driver_version[32];
1707 uint8_t orom_version[16];
1708 uint8_t fw_version[16];
1709 uint8_t os_version[128];
1710 uint8_t max_ct_len[4];
1711 } a;
1712 };
1713
1714 struct ct_fdmi_hba_attributes {
1715 uint32_t count;
1716 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1717 };
1718
1719 /*
1720 * Port attribute types.
1721 */
1722 #define FDMI_PORT_ATTR_COUNT 6
1723 #define FDMI_PORT_FC4_TYPES 1
1724 #define FDMI_PORT_SUPPORT_SPEED 2
1725 #define FDMI_PORT_CURRENT_SPEED 3
1726 #define FDMI_PORT_MAX_FRAME_SIZE 4
1727 #define FDMI_PORT_OS_DEVICE_NAME 5
1728 #define FDMI_PORT_HOST_NAME 6
1729
1730 #define FDMI_PORT_SPEED_1GB 0x1
1731 #define FDMI_PORT_SPEED_2GB 0x2
1732 #define FDMI_PORT_SPEED_10GB 0x4
1733 #define FDMI_PORT_SPEED_4GB 0x8
1734 #define FDMI_PORT_SPEED_8GB 0x10
1735 #define FDMI_PORT_SPEED_16GB 0x20
1736 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1737
1738 struct ct_fdmi_port_attr {
1739 uint16_t type;
1740 uint16_t len;
1741 union {
1742 uint8_t fc4_types[32];
1743 uint32_t sup_speed;
1744 uint32_t cur_speed;
1745 uint32_t max_frame_size;
1746 uint8_t os_dev_name[32];
1747 uint8_t host_name[32];
1748 } a;
1749 };
1750
1751 /*
1752 * Port Attribute Block.
1753 */
1754 struct ct_fdmi_port_attributes {
1755 uint32_t count;
1756 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1757 };
1758
1759 /* FDMI definitions. */
1760 #define GRHL_CMD 0x100
1761 #define GHAT_CMD 0x101
1762 #define GRPL_CMD 0x102
1763 #define GPAT_CMD 0x110
1764
1765 #define RHBA_CMD 0x200
1766 #define RHBA_RSP_SIZE 16
1767
1768 #define RHAT_CMD 0x201
1769 #define RPRT_CMD 0x210
1770
1771 #define RPA_CMD 0x211
1772 #define RPA_RSP_SIZE 16
1773
1774 #define DHBA_CMD 0x300
1775 #define DHBA_REQ_SIZE (16 + 8)
1776 #define DHBA_RSP_SIZE 16
1777
1778 #define DHAT_CMD 0x301
1779 #define DPRT_CMD 0x310
1780 #define DPA_CMD 0x311
1781
1782 /* CT command header -- request/response common fields */
1783 struct ct_cmd_hdr {
1784 uint8_t revision;
1785 uint8_t in_id[3];
1786 uint8_t gs_type;
1787 uint8_t gs_subtype;
1788 uint8_t options;
1789 uint8_t reserved;
1790 };
1791
1792 /* CT command request */
1793 struct ct_sns_req {
1794 struct ct_cmd_hdr header;
1795 uint16_t command;
1796 uint16_t max_rsp_size;
1797 uint8_t fragment_id;
1798 uint8_t reserved[3];
1799
1800 union {
1801 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1802 struct {
1803 uint8_t reserved;
1804 uint8_t port_id[3];
1805 } port_id;
1806
1807 struct {
1808 uint8_t port_type;
1809 uint8_t domain;
1810 uint8_t area;
1811 uint8_t reserved;
1812 } gid_pt;
1813
1814 struct {
1815 uint8_t reserved;
1816 uint8_t port_id[3];
1817 uint8_t fc4_types[32];
1818 } rft_id;
1819
1820 struct {
1821 uint8_t reserved;
1822 uint8_t port_id[3];
1823 uint16_t reserved2;
1824 uint8_t fc4_feature;
1825 uint8_t fc4_type;
1826 } rff_id;
1827
1828 struct {
1829 uint8_t reserved;
1830 uint8_t port_id[3];
1831 uint8_t node_name[8];
1832 } rnn_id;
1833
1834 struct {
1835 uint8_t node_name[8];
1836 uint8_t name_len;
1837 uint8_t sym_node_name[255];
1838 } rsnn_nn;
1839
1840 struct {
1841 uint8_t hba_indentifier[8];
1842 } ghat;
1843
1844 struct {
1845 uint8_t hba_identifier[8];
1846 uint32_t entry_count;
1847 uint8_t port_name[8];
1848 struct ct_fdmi_hba_attributes attrs;
1849 } rhba;
1850
1851 struct {
1852 uint8_t hba_identifier[8];
1853 struct ct_fdmi_hba_attributes attrs;
1854 } rhat;
1855
1856 struct {
1857 uint8_t port_name[8];
1858 struct ct_fdmi_port_attributes attrs;
1859 } rpa;
1860
1861 struct {
1862 uint8_t port_name[8];
1863 } dhba;
1864
1865 struct {
1866 uint8_t port_name[8];
1867 } dhat;
1868
1869 struct {
1870 uint8_t port_name[8];
1871 } dprt;
1872
1873 struct {
1874 uint8_t port_name[8];
1875 } dpa;
1876
1877 struct {
1878 uint8_t port_name[8];
1879 } gpsc;
1880 } req;
1881 };
1882
1883 /* CT command response header */
1884 struct ct_rsp_hdr {
1885 struct ct_cmd_hdr header;
1886 uint16_t response;
1887 uint16_t residual;
1888 uint8_t fragment_id;
1889 uint8_t reason_code;
1890 uint8_t explanation_code;
1891 uint8_t vendor_unique;
1892 };
1893
1894 struct ct_sns_gid_pt_data {
1895 uint8_t control_byte;
1896 uint8_t port_id[3];
1897 };
1898
1899 struct ct_sns_rsp {
1900 struct ct_rsp_hdr header;
1901
1902 union {
1903 struct {
1904 uint8_t port_type;
1905 uint8_t port_id[3];
1906 uint8_t port_name[8];
1907 uint8_t sym_port_name_len;
1908 uint8_t sym_port_name[255];
1909 uint8_t node_name[8];
1910 uint8_t sym_node_name_len;
1911 uint8_t sym_node_name[255];
1912 uint8_t init_proc_assoc[8];
1913 uint8_t node_ip_addr[16];
1914 uint8_t class_of_service[4];
1915 uint8_t fc4_types[32];
1916 uint8_t ip_address[16];
1917 uint8_t fabric_port_name[8];
1918 uint8_t reserved;
1919 uint8_t hard_address[3];
1920 } ga_nxt;
1921
1922 struct {
1923 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1924 } gid_pt;
1925
1926 struct {
1927 uint8_t port_name[8];
1928 } gpn_id;
1929
1930 struct {
1931 uint8_t node_name[8];
1932 } gnn_id;
1933
1934 struct {
1935 uint8_t fc4_types[32];
1936 } gft_id;
1937
1938 struct {
1939 uint32_t entry_count;
1940 uint8_t port_name[8];
1941 struct ct_fdmi_hba_attributes attrs;
1942 } ghat;
1943
1944 struct {
1945 uint8_t port_name[8];
1946 } gfpn_id;
1947
1948 struct {
1949 uint16_t speeds;
1950 uint16_t speed;
1951 } gpsc;
1952 } rsp;
1953 };
1954
1955 struct ct_sns_pkt {
1956 union {
1957 struct ct_sns_req req;
1958 struct ct_sns_rsp rsp;
1959 } p;
1960 };
1961
1962 /*
1963 * SNS command structures -- for 2200 compatability.
1964 */
1965 #define RFT_ID_SNS_SCMD_LEN 22
1966 #define RFT_ID_SNS_CMD_SIZE 60
1967 #define RFT_ID_SNS_DATA_SIZE 16
1968
1969 #define RNN_ID_SNS_SCMD_LEN 10
1970 #define RNN_ID_SNS_CMD_SIZE 36
1971 #define RNN_ID_SNS_DATA_SIZE 16
1972
1973 #define GA_NXT_SNS_SCMD_LEN 6
1974 #define GA_NXT_SNS_CMD_SIZE 28
1975 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1976
1977 #define GID_PT_SNS_SCMD_LEN 6
1978 #define GID_PT_SNS_CMD_SIZE 28
1979 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1980
1981 #define GPN_ID_SNS_SCMD_LEN 6
1982 #define GPN_ID_SNS_CMD_SIZE 28
1983 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1984
1985 #define GNN_ID_SNS_SCMD_LEN 6
1986 #define GNN_ID_SNS_CMD_SIZE 28
1987 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1988
1989 struct sns_cmd_pkt {
1990 union {
1991 struct {
1992 uint16_t buffer_length;
1993 uint16_t reserved_1;
1994 uint32_t buffer_address[2];
1995 uint16_t subcommand_length;
1996 uint16_t reserved_2;
1997 uint16_t subcommand;
1998 uint16_t size;
1999 uint32_t reserved_3;
2000 uint8_t param[36];
2001 } cmd;
2002
2003 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2004 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2005 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2006 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2007 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2008 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2009 } p;
2010 };
2011
2012 struct fw_blob {
2013 char *name;
2014 uint32_t segs[4];
2015 const struct firmware *fw;
2016 };
2017
2018 /* Return data from MBC_GET_ID_LIST call. */
2019 struct gid_list_info {
2020 uint8_t al_pa;
2021 uint8_t area;
2022 uint8_t domain;
2023 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2024 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2025 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2026 };
2027 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2028
2029 /* NPIV */
2030 typedef struct vport_info {
2031 uint8_t port_name[WWN_SIZE];
2032 uint8_t node_name[WWN_SIZE];
2033 int vp_id;
2034 uint16_t loop_id;
2035 unsigned long host_no;
2036 uint8_t port_id[3];
2037 int loop_state;
2038 } vport_info_t;
2039
2040 typedef struct vport_params {
2041 uint8_t port_name[WWN_SIZE];
2042 uint8_t node_name[WWN_SIZE];
2043 uint32_t options;
2044 #define VP_OPTS_RETRY_ENABLE BIT_0
2045 #define VP_OPTS_VP_DISABLE BIT_1
2046 } vport_params_t;
2047
2048 /* NPIV - return codes of VP create and modify */
2049 #define VP_RET_CODE_OK 0
2050 #define VP_RET_CODE_FATAL 1
2051 #define VP_RET_CODE_WRONG_ID 2
2052 #define VP_RET_CODE_WWPN 3
2053 #define VP_RET_CODE_RESOURCES 4
2054 #define VP_RET_CODE_NO_MEM 5
2055 #define VP_RET_CODE_NOT_FOUND 6
2056
2057 struct qla_hw_data;
2058 struct rsp_que;
2059 /*
2060 * ISP operations
2061 */
2062 struct isp_operations {
2063
2064 int (*pci_config) (struct scsi_qla_host *);
2065 void (*reset_chip) (struct scsi_qla_host *);
2066 int (*chip_diag) (struct scsi_qla_host *);
2067 void (*config_rings) (struct scsi_qla_host *);
2068 void (*reset_adapter) (struct scsi_qla_host *);
2069 int (*nvram_config) (struct scsi_qla_host *);
2070 void (*update_fw_options) (struct scsi_qla_host *);
2071 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2072
2073 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2074 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2075
2076 irq_handler_t intr_handler;
2077 void (*enable_intrs) (struct qla_hw_data *);
2078 void (*disable_intrs) (struct qla_hw_data *);
2079
2080 int (*abort_command) (srb_t *);
2081 int (*target_reset) (struct fc_port *, unsigned int, int);
2082 int (*lun_reset) (struct fc_port *, unsigned int, int);
2083 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2084 uint8_t, uint8_t, uint16_t *, uint8_t);
2085 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2086 uint8_t, uint8_t);
2087
2088 uint16_t (*calc_req_entries) (uint16_t);
2089 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2090 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2091 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2092 uint32_t);
2093
2094 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2095 uint32_t, uint32_t);
2096 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2097 uint32_t);
2098
2099 void (*fw_dump) (struct scsi_qla_host *, int);
2100
2101 int (*beacon_on) (struct scsi_qla_host *);
2102 int (*beacon_off) (struct scsi_qla_host *);
2103 void (*beacon_blink) (struct scsi_qla_host *);
2104
2105 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2106 uint32_t, uint32_t);
2107 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2108 uint32_t);
2109
2110 int (*get_flash_version) (struct scsi_qla_host *, void *);
2111 int (*start_scsi) (srb_t *);
2112 };
2113
2114 /* MSI-X Support *************************************************************/
2115
2116 #define QLA_MSIX_CHIP_REV_24XX 3
2117 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2118 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2119
2120 #define QLA_MSIX_DEFAULT 0x00
2121 #define QLA_MSIX_RSP_Q 0x01
2122
2123 #define QLA_MIDX_DEFAULT 0
2124 #define QLA_MIDX_RSP_Q 1
2125 #define QLA_PCI_MSIX_CONTROL 0xa2
2126
2127 struct scsi_qla_host;
2128
2129 struct qla_msix_entry {
2130 int have_irq;
2131 uint32_t vector;
2132 uint16_t entry;
2133 struct rsp_que *rsp;
2134 };
2135
2136 #define WATCH_INTERVAL 1 /* number of seconds */
2137
2138 /* Work events. */
2139 enum qla_work_type {
2140 QLA_EVT_AEN,
2141 QLA_EVT_IDC_ACK,
2142 QLA_EVT_ASYNC_LOGIN,
2143 QLA_EVT_ASYNC_LOGIN_DONE,
2144 QLA_EVT_ASYNC_LOGOUT,
2145 QLA_EVT_ASYNC_LOGOUT_DONE,
2146 QLA_EVT_UEVENT,
2147 };
2148
2149
2150 struct qla_work_evt {
2151 struct list_head list;
2152 enum qla_work_type type;
2153 u32 flags;
2154 #define QLA_EVT_FLAG_FREE 0x1
2155
2156 union {
2157 struct {
2158 enum fc_host_event_code code;
2159 u32 data;
2160 } aen;
2161 struct {
2162 #define QLA_IDC_ACK_REGS 7
2163 uint16_t mb[QLA_IDC_ACK_REGS];
2164 } idc_ack;
2165 struct {
2166 struct fc_port *fcport;
2167 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2168 u16 data[2];
2169 } logio;
2170 struct {
2171 u32 code;
2172 #define QLA_UEVENT_CODE_FW_DUMP 0
2173 } uevent;
2174 } u;
2175 };
2176
2177 struct qla_chip_state_84xx {
2178 struct list_head list;
2179 struct kref kref;
2180
2181 void *bus;
2182 spinlock_t access_lock;
2183 struct mutex fw_update_mutex;
2184 uint32_t fw_update;
2185 uint32_t op_fw_version;
2186 uint32_t op_fw_size;
2187 uint32_t op_fw_seq_size;
2188 uint32_t diag_fw_version;
2189 uint32_t gold_fw_version;
2190 };
2191
2192 struct qla_statistics {
2193 uint32_t total_isp_aborts;
2194 uint64_t input_bytes;
2195 uint64_t output_bytes;
2196 };
2197
2198 /* Multi queue support */
2199 #define MBC_INITIALIZE_MULTIQ 0x1f
2200 #define QLA_QUE_PAGE 0X1000
2201 #define QLA_MQ_SIZE 32
2202 #define QLA_MAX_QUEUES 256
2203 #define ISP_QUE_REG(ha, id) \
2204 ((ha->mqenable) ? \
2205 ((void *)(ha->mqiobase) +\
2206 (QLA_QUE_PAGE * id)) :\
2207 ((void *)(ha->iobase)))
2208 #define QLA_REQ_QUE_ID(tag) \
2209 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2210 #define QLA_DEFAULT_QUE_QOS 5
2211 #define QLA_PRECONFIG_VPORTS 32
2212 #define QLA_MAX_VPORTS_QLA24XX 128
2213 #define QLA_MAX_VPORTS_QLA25XX 256
2214 /* Response queue data structure */
2215 struct rsp_que {
2216 dma_addr_t dma;
2217 response_t *ring;
2218 response_t *ring_ptr;
2219 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2220 uint32_t __iomem *rsp_q_out;
2221 uint16_t ring_index;
2222 uint16_t out_ptr;
2223 uint16_t length;
2224 uint16_t options;
2225 uint16_t rid;
2226 uint16_t id;
2227 uint16_t vp_idx;
2228 struct qla_hw_data *hw;
2229 struct qla_msix_entry *msix;
2230 struct req_que *req;
2231 srb_t *status_srb; /* status continuation entry */
2232 struct work_struct q_work;
2233 };
2234
2235 /* Request queue data structure */
2236 struct req_que {
2237 dma_addr_t dma;
2238 request_t *ring;
2239 request_t *ring_ptr;
2240 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2241 uint32_t __iomem *req_q_out;
2242 uint16_t ring_index;
2243 uint16_t in_ptr;
2244 uint16_t cnt;
2245 uint16_t length;
2246 uint16_t options;
2247 uint16_t rid;
2248 uint16_t id;
2249 uint16_t qos;
2250 uint16_t vp_idx;
2251 struct rsp_que *rsp;
2252 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2253 uint32_t current_outstanding_cmd;
2254 int max_q_depth;
2255 };
2256
2257 /* Place holder for FW buffer parameters */
2258 struct qlfc_fw {
2259 void *fw_buf;
2260 dma_addr_t fw_dma;
2261 uint32_t len;
2262 };
2263
2264 /*
2265 * Qlogic host adapter specific data structure.
2266 */
2267 struct qla_hw_data {
2268 struct pci_dev *pdev;
2269 /* SRB cache. */
2270 #define SRB_MIN_REQ 128
2271 mempool_t *srb_mempool;
2272
2273 volatile struct {
2274 uint32_t mbox_int :1;
2275 uint32_t mbox_busy :1;
2276
2277 uint32_t disable_risc_code_load :1;
2278 uint32_t enable_64bit_addressing :1;
2279 uint32_t enable_lip_reset :1;
2280 uint32_t enable_target_reset :1;
2281 uint32_t enable_lip_full_login :1;
2282 uint32_t enable_led_scheme :1;
2283 uint32_t inta_enabled :1;
2284 uint32_t msi_enabled :1;
2285 uint32_t msix_enabled :1;
2286 uint32_t disable_serdes :1;
2287 uint32_t gpsc_supported :1;
2288 uint32_t npiv_supported :1;
2289 uint32_t pci_channel_io_perm_failure :1;
2290 uint32_t fce_enabled :1;
2291 uint32_t fac_supported :1;
2292 uint32_t chip_reset_done :1;
2293 uint32_t port0 :1;
2294 uint32_t running_gold_fw :1;
2295 uint32_t eeh_busy :1;
2296 uint32_t cpu_affinity_enabled :1;
2297 uint32_t disable_msix_handshake :1;
2298 } flags;
2299
2300 /* This spinlock is used to protect "io transactions", you must
2301 * acquire it before doing any IO to the card, eg with RD_REG*() and
2302 * WRT_REG*() for the duration of your entire commandtransaction.
2303 *
2304 * This spinlock is of lower priority than the io request lock.
2305 */
2306
2307 spinlock_t hardware_lock ____cacheline_aligned;
2308 int bars;
2309 int mem_only;
2310 device_reg_t __iomem *iobase; /* Base I/O address */
2311 resource_size_t pio_address;
2312
2313 #define MIN_IOBASE_LEN 0x100
2314 /* Multi queue data structs */
2315 device_reg_t __iomem *mqiobase;
2316 uint16_t msix_count;
2317 uint8_t mqenable;
2318 struct req_que **req_q_map;
2319 struct rsp_que **rsp_q_map;
2320 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2321 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2322 uint8_t max_req_queues;
2323 uint8_t max_rsp_queues;
2324 struct qla_npiv_entry *npiv_info;
2325 uint16_t nvram_npiv_size;
2326
2327 uint16_t switch_cap;
2328 #define FLOGI_SEQ_DEL BIT_8
2329 #define FLOGI_MID_SUPPORT BIT_10
2330 #define FLOGI_VSAN_SUPPORT BIT_12
2331 #define FLOGI_SP_SUPPORT BIT_13
2332
2333 uint8_t port_no; /* Physical port of adapter */
2334
2335 /* Timeout timers. */
2336 uint8_t loop_down_abort_time; /* port down timer */
2337 atomic_t loop_down_timer; /* loop down timer */
2338 uint8_t link_down_timeout; /* link down timeout */
2339 uint16_t max_loop_id;
2340
2341 uint16_t fb_rev;
2342 uint16_t min_external_loopid; /* First external loop Id */
2343
2344 #define PORT_SPEED_UNKNOWN 0xFFFF
2345 #define PORT_SPEED_1GB 0x00
2346 #define PORT_SPEED_2GB 0x01
2347 #define PORT_SPEED_4GB 0x03
2348 #define PORT_SPEED_8GB 0x04
2349 #define PORT_SPEED_10GB 0x13
2350 uint16_t link_data_rate; /* F/W operating speed */
2351
2352 uint8_t current_topology;
2353 uint8_t prev_topology;
2354 #define ISP_CFG_NL 1
2355 #define ISP_CFG_N 2
2356 #define ISP_CFG_FL 4
2357 #define ISP_CFG_F 8
2358
2359 uint8_t operating_mode; /* F/W operating mode */
2360 #define LOOP 0
2361 #define P2P 1
2362 #define LOOP_P2P 2
2363 #define P2P_LOOP 3
2364 uint8_t interrupts_on;
2365 uint32_t isp_abort_cnt;
2366
2367 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2368 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2369 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2370 uint32_t device_type;
2371 #define DT_ISP2100 BIT_0
2372 #define DT_ISP2200 BIT_1
2373 #define DT_ISP2300 BIT_2
2374 #define DT_ISP2312 BIT_3
2375 #define DT_ISP2322 BIT_4
2376 #define DT_ISP6312 BIT_5
2377 #define DT_ISP6322 BIT_6
2378 #define DT_ISP2422 BIT_7
2379 #define DT_ISP2432 BIT_8
2380 #define DT_ISP5422 BIT_9
2381 #define DT_ISP5432 BIT_10
2382 #define DT_ISP2532 BIT_11
2383 #define DT_ISP8432 BIT_12
2384 #define DT_ISP8001 BIT_13
2385 #define DT_ISP_LAST (DT_ISP8001 << 1)
2386
2387 #define DT_IIDMA BIT_26
2388 #define DT_FWI2 BIT_27
2389 #define DT_ZIO_SUPPORTED BIT_28
2390 #define DT_OEM_001 BIT_29
2391 #define DT_ISP2200A BIT_30
2392 #define DT_EXTENDED_IDS BIT_31
2393 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2394 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2395 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2396 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2397 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2398 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2399 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2400 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2401 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2402 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2403 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2404 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2405 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2406 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2407 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2408
2409 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2410 IS_QLA6312(ha) || IS_QLA6322(ha))
2411 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2412 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2413 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2414 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2415 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2416 IS_QLA84XX(ha))
2417 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2418 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2419 IS_QLA25XX(ha) || IS_QLA81XX(ha))
2420 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha))
2421 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2422 (ha)->flags.msix_enabled)
2423 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2424 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2425 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2426
2427 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2428 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2429 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2430 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2431 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2432
2433 /* HBA serial number */
2434 uint8_t serial0;
2435 uint8_t serial1;
2436 uint8_t serial2;
2437
2438 /* NVRAM configuration data */
2439 #define MAX_NVRAM_SIZE 4096
2440 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2441 uint16_t nvram_size;
2442 uint16_t nvram_base;
2443 void *nvram;
2444 uint16_t vpd_size;
2445 uint16_t vpd_base;
2446 void *vpd;
2447
2448 uint16_t loop_reset_delay;
2449 uint8_t retry_count;
2450 uint8_t login_timeout;
2451 uint16_t r_a_tov;
2452 int port_down_retry_count;
2453 uint8_t mbx_count;
2454
2455 uint32_t login_retry_count;
2456 /* SNS command interfaces. */
2457 ms_iocb_entry_t *ms_iocb;
2458 dma_addr_t ms_iocb_dma;
2459 struct ct_sns_pkt *ct_sns;
2460 dma_addr_t ct_sns_dma;
2461 /* SNS command interfaces for 2200. */
2462 struct sns_cmd_pkt *sns_cmd;
2463 dma_addr_t sns_cmd_dma;
2464
2465 #define SFP_DEV_SIZE 256
2466 #define SFP_BLOCK_SIZE 64
2467 void *sfp_data;
2468 dma_addr_t sfp_data_dma;
2469
2470 uint8_t *edc_data;
2471 dma_addr_t edc_data_dma;
2472 uint16_t edc_data_len;
2473
2474 #define XGMAC_DATA_SIZE 4096
2475 void *xgmac_data;
2476 dma_addr_t xgmac_data_dma;
2477
2478 #define DCBX_TLV_DATA_SIZE 4096
2479 void *dcbx_tlv;
2480 dma_addr_t dcbx_tlv_dma;
2481
2482 struct task_struct *dpc_thread;
2483 uint8_t dpc_active; /* DPC routine is active */
2484
2485 dma_addr_t gid_list_dma;
2486 struct gid_list_info *gid_list;
2487 int gid_list_info_size;
2488
2489 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2490 #define DMA_POOL_SIZE 256
2491 struct dma_pool *s_dma_pool;
2492
2493 dma_addr_t init_cb_dma;
2494 init_cb_t *init_cb;
2495 int init_cb_size;
2496 dma_addr_t ex_init_cb_dma;
2497 struct ex_init_cb_81xx *ex_init_cb;
2498
2499 /* These are used by mailbox operations. */
2500 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2501
2502 mbx_cmd_t *mcp;
2503 unsigned long mbx_cmd_flags;
2504 #define MBX_INTERRUPT 1
2505 #define MBX_INTR_WAIT 2
2506 #define MBX_UPDATE_FLASH_ACTIVE 3
2507
2508 struct mutex vport_lock; /* Virtual port synchronization */
2509 struct completion mbx_cmd_comp; /* Serialize mbx access */
2510 struct completion mbx_intr_comp; /* Used for completion notification */
2511
2512 /* Basic firmware related information. */
2513 uint16_t fw_major_version;
2514 uint16_t fw_minor_version;
2515 uint16_t fw_subminor_version;
2516 uint16_t fw_attributes;
2517 uint32_t fw_memory_size;
2518 uint32_t fw_transfer_size;
2519 uint32_t fw_srisc_address;
2520 #define RISC_START_ADDRESS_2100 0x1000
2521 #define RISC_START_ADDRESS_2300 0x800
2522 #define RISC_START_ADDRESS_2400 0x100000
2523 uint16_t fw_xcb_count;
2524
2525 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2526 uint8_t fw_seriallink_options[4];
2527 uint16_t fw_seriallink_options24[4];
2528
2529 uint8_t mpi_version[3];
2530 uint32_t mpi_capabilities;
2531 uint8_t phy_version[3];
2532
2533 /* Firmware dump information. */
2534 struct qla2xxx_fw_dump *fw_dump;
2535 uint32_t fw_dump_len;
2536 int fw_dumped;
2537 int fw_dump_reading;
2538 dma_addr_t eft_dma;
2539 void *eft;
2540
2541 uint32_t chain_offset;
2542 struct dentry *dfs_dir;
2543 struct dentry *dfs_fce;
2544 dma_addr_t fce_dma;
2545 void *fce;
2546 uint32_t fce_bufs;
2547 uint16_t fce_mb[8];
2548 uint64_t fce_wr, fce_rd;
2549 struct mutex fce_mutex;
2550
2551 uint32_t pci_attr;
2552 uint16_t chip_revision;
2553
2554 uint16_t product_id[4];
2555
2556 uint8_t model_number[16+1];
2557 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2558 char model_desc[80];
2559 uint8_t adapter_id[16+1];
2560
2561 /* Option ROM information. */
2562 char *optrom_buffer;
2563 uint32_t optrom_size;
2564 int optrom_state;
2565 #define QLA_SWAITING 0
2566 #define QLA_SREADING 1
2567 #define QLA_SWRITING 2
2568 uint32_t optrom_region_start;
2569 uint32_t optrom_region_size;
2570
2571 /* PCI expansion ROM image information. */
2572 #define ROM_CODE_TYPE_BIOS 0
2573 #define ROM_CODE_TYPE_FCODE 1
2574 #define ROM_CODE_TYPE_EFI 3
2575 uint8_t bios_revision[2];
2576 uint8_t efi_revision[2];
2577 uint8_t fcode_revision[16];
2578 uint32_t fw_revision[4];
2579
2580 /* Offsets for flash/nvram access (set to ~0 if not used). */
2581 uint32_t flash_conf_off;
2582 uint32_t flash_data_off;
2583 uint32_t nvram_conf_off;
2584 uint32_t nvram_data_off;
2585
2586 uint32_t fdt_wrt_disable;
2587 uint32_t fdt_erase_cmd;
2588 uint32_t fdt_block_size;
2589 uint32_t fdt_unprotect_sec_cmd;
2590 uint32_t fdt_protect_sec_cmd;
2591
2592 uint32_t flt_region_flt;
2593 uint32_t flt_region_fdt;
2594 uint32_t flt_region_boot;
2595 uint32_t flt_region_fw;
2596 uint32_t flt_region_vpd_nvram;
2597 uint32_t flt_region_vpd;
2598 uint32_t flt_region_nvram;
2599 uint32_t flt_region_npiv_conf;
2600 uint32_t flt_region_gold_fw;
2601
2602 /* Needed for BEACON */
2603 uint16_t beacon_blink_led;
2604 uint8_t beacon_color_state;
2605 #define QLA_LED_GRN_ON 0x01
2606 #define QLA_LED_YLW_ON 0x02
2607 #define QLA_LED_ABR_ON 0x04
2608 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2609 /* ISP2322: red, green, amber. */
2610 uint16_t zio_mode;
2611 uint16_t zio_timer;
2612 struct fc_host_statistics fc_host_stat;
2613
2614 struct qla_msix_entry *msix_entries;
2615
2616 struct list_head vp_list; /* list of VP */
2617 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2618 sizeof(unsigned long)];
2619 uint16_t num_vhosts; /* number of vports created */
2620 uint16_t num_vsans; /* number of vsan created */
2621 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2622 int cur_vport_count;
2623
2624 struct qla_chip_state_84xx *cs84xx;
2625 struct qla_statistics qla_stats;
2626 struct isp_operations *isp_ops;
2627 struct workqueue_struct *wq;
2628 struct qlfc_fw fw_buf;
2629 };
2630
2631 /*
2632 * Qlogic scsi host structure
2633 */
2634 typedef struct scsi_qla_host {
2635 struct list_head list;
2636 struct list_head vp_fcports; /* list of fcports */
2637 struct list_head work_list;
2638 spinlock_t work_lock;
2639
2640 /* Commonly used flags and state information. */
2641 struct Scsi_Host *host;
2642 unsigned long host_no;
2643 uint8_t host_str[16];
2644
2645 volatile struct {
2646 uint32_t init_done :1;
2647 uint32_t online :1;
2648 uint32_t rscn_queue_overflow :1;
2649 uint32_t reset_active :1;
2650
2651 uint32_t management_server_logged_in :1;
2652 uint32_t process_response_queue :1;
2653 } flags;
2654
2655 atomic_t loop_state;
2656 #define LOOP_TIMEOUT 1
2657 #define LOOP_DOWN 2
2658 #define LOOP_UP 3
2659 #define LOOP_UPDATE 4
2660 #define LOOP_READY 5
2661 #define LOOP_DEAD 6
2662
2663 unsigned long dpc_flags;
2664 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2665 #define RESET_ACTIVE 1
2666 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2667 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2668 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2669 #define LOOP_RESYNC_ACTIVE 5
2670 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2671 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2672 #define RELOGIN_NEEDED 8
2673 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2674 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2675 #define BEACON_BLINK_NEEDED 11
2676 #define REGISTER_FDMI_NEEDED 12
2677 #define FCPORT_UPDATE_NEEDED 13
2678 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2679 #define UNLOADING 15
2680 #define NPIV_CONFIG_NEEDED 16
2681
2682 uint32_t device_flags;
2683 #define SWITCH_FOUND BIT_0
2684 #define DFLG_NO_CABLE BIT_1
2685
2686 /* ISP configuration data. */
2687 uint16_t loop_id; /* Host adapter loop id */
2688
2689 port_id_t d_id; /* Host adapter port id */
2690 uint8_t marker_needed;
2691 uint16_t mgmt_svr_loop_id;
2692
2693
2694
2695 /* RSCN queue. */
2696 uint32_t rscn_queue[MAX_RSCN_COUNT];
2697 uint8_t rscn_in_ptr;
2698 uint8_t rscn_out_ptr;
2699
2700 /* Timeout timers. */
2701 uint8_t loop_down_abort_time; /* port down timer */
2702 atomic_t loop_down_timer; /* loop down timer */
2703 uint8_t link_down_timeout; /* link down timeout */
2704
2705 uint32_t timer_active;
2706 struct timer_list timer;
2707
2708 uint8_t node_name[WWN_SIZE];
2709 uint8_t port_name[WWN_SIZE];
2710 uint8_t fabric_node_name[WWN_SIZE];
2711
2712 uint16_t fcoe_vlan_id;
2713 uint16_t fcoe_fcf_idx;
2714 uint8_t fcoe_vn_port_mac[6];
2715
2716 uint32_t vp_abort_cnt;
2717
2718 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2719 uint16_t vp_idx; /* vport ID */
2720
2721 unsigned long vp_flags;
2722 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2723 #define VP_CREATE_NEEDED 1
2724 #define VP_BIND_NEEDED 2
2725 #define VP_DELETE_NEEDED 3
2726 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2727 atomic_t vp_state;
2728 #define VP_OFFLINE 0
2729 #define VP_ACTIVE 1
2730 #define VP_FAILED 2
2731 // #define VP_DISABLE 3
2732 uint16_t vp_err_state;
2733 uint16_t vp_prev_err_state;
2734 #define VP_ERR_UNKWN 0
2735 #define VP_ERR_PORTDWN 1
2736 #define VP_ERR_FAB_UNSUPPORTED 2
2737 #define VP_ERR_FAB_NORESOURCES 3
2738 #define VP_ERR_FAB_LOGOUT 4
2739 #define VP_ERR_ADAP_NORESOURCES 5
2740 struct qla_hw_data *hw;
2741 struct req_que *req;
2742 } scsi_qla_host_t;
2743
2744 /*
2745 * Macros to help code, maintain, etc.
2746 */
2747 #define LOOP_TRANSITION(ha) \
2748 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2749 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2750 atomic_read(&ha->loop_state) == LOOP_DOWN)
2751
2752 #define qla_printk(level, ha, format, arg...) \
2753 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2754
2755 /*
2756 * qla2x00 local function return status codes
2757 */
2758 #define MBS_MASK 0x3fff
2759
2760 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2761 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2762 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2763 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2764 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2765 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2766 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2767 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2768 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2769 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2770
2771 #define QLA_FUNCTION_TIMEOUT 0x100
2772 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2773 #define QLA_FUNCTION_FAILED 0x102
2774 #define QLA_MEMORY_ALLOC_FAILED 0x103
2775 #define QLA_LOCK_TIMEOUT 0x104
2776 #define QLA_ABORTED 0x105
2777 #define QLA_SUSPENDED 0x106
2778 #define QLA_BUSY 0x107
2779 #define QLA_RSCNS_HANDLED 0x108
2780 #define QLA_ALREADY_REGISTERED 0x109
2781
2782 #define NVRAM_DELAY() udelay(10)
2783
2784 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2785
2786 /*
2787 * Flash support definitions
2788 */
2789 #define OPTROM_SIZE_2300 0x20000
2790 #define OPTROM_SIZE_2322 0x100000
2791 #define OPTROM_SIZE_24XX 0x100000
2792 #define OPTROM_SIZE_25XX 0x200000
2793 #define OPTROM_SIZE_81XX 0x400000
2794
2795 #include "qla_gbl.h"
2796 #include "qla_dbg.h"
2797 #include "qla_inline.h"
2798
2799 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2800
2801 /*
2802 * BSG Vendor specific commands
2803 */
2804
2805 #define QL_VND_LOOPBACK 0x01
2806 #define QLA84_RESET 0x02
2807 #define QLA84_UPDATE_FW 0x03
2808 #define QLA84_MGMT_CMD 0x04
2809
2810 /* BSG definations for interpreting CommandSent field */
2811 #define INT_DEF_LB_LOOPBACK_CMD 0
2812 #define INT_DEF_LB_ECHO_CMD 1
2813
2814 /* BSG Vendor specific definations */
2815 typedef struct _A84_RESET {
2816 uint16_t Flags;
2817 uint16_t Reserved;
2818 #define A84_RESET_FLAG_ENABLE_DIAG_FW 1
2819 } __attribute__((packed)) A84_RESET, *PA84_RESET;
2820
2821 #define A84_ISSUE_WRITE_TYPE_CMD 0
2822 #define A84_ISSUE_READ_TYPE_CMD 1
2823 #define A84_CLEANUP_CMD 2
2824 #define A84_ISSUE_RESET_OP_FW 3
2825 #define A84_ISSUE_RESET_DIAG_FW 4
2826 #define A84_ISSUE_UPDATE_OPFW_CMD 5
2827 #define A84_ISSUE_UPDATE_DIAGFW_CMD 6
2828
2829 struct qla84_mgmt_param {
2830 union {
2831 struct {
2832 uint32_t start_addr;
2833 } mem; /* for QLA84_MGMT_READ/WRITE_MEM */
2834 struct {
2835 uint32_t id;
2836 #define QLA84_MGMT_CONFIG_ID_UIF 1
2837 #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
2838 #define QLA84_MGMT_CONFIG_ID_PAUSE 3
2839 #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
2840
2841 uint32_t param0;
2842 uint32_t param1;
2843 } config; /* for QLA84_MGMT_CHNG_CONFIG */
2844
2845 struct {
2846 uint32_t type;
2847 #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
2848 #define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
2849 #define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
2850 #define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
2851 #define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
2852 #define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
2853 #define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
2854
2855 uint32_t context;
2856 /*
2857 * context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
2858 */
2859 #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
2860 #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
2861 #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
2862 #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
2863 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
2864 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
2865 #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
2866 #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
2867 #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
2868 #define IC_LOG_DATA_LOG_ID_DCX_LOG 9
2869
2870 /*
2871 * context definitions for QLA84_MGMT_INFO_PORT_STAT
2872 */
2873 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
2874 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
2875 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
2876 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
2877 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
2878 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
2879
2880
2881 /*
2882 * context definitions for QLA84_MGMT_INFO_LIF_STAT
2883 */
2884 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
2885 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
2886 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
2887 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
2888 #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
2889
2890 } info; /* for QLA84_MGMT_GET_INFO */
2891 } u;
2892 };
2893
2894 struct qla84_msg_mgmt {
2895 uint16_t cmd;
2896 #define QLA84_MGMT_READ_MEM 0x00
2897 #define QLA84_MGMT_WRITE_MEM 0x01
2898 #define QLA84_MGMT_CHNG_CONFIG 0x02
2899 #define QLA84_MGMT_GET_INFO 0x03
2900 uint16_t rsrvd;
2901 struct qla84_mgmt_param mgmtp;/* parameters for cmd */
2902 uint32_t len; /* bytes in payload following this struct */
2903 uint8_t payload[0]; /* payload for cmd */
2904 };
2905
2906 struct msg_update_fw {
2907 /*
2908 * diag_fw = 0 operational fw
2909 * otherwise diagnostic fw
2910 * offset, len, fw_len are present to overcome the current limitation
2911 * of 128Kb xfer size. The fw is sent in smaller chunks. Each chunk
2912 * specifies the byte "offset" where it fits in the fw buffer. The
2913 * number of bytes in each chunk is specified in "len". "fw_len"
2914 * is the total size of fw. The first chunk should start at offset = 0.
2915 * When offset+len == fw_len, the fw is written to the HBA.
2916 */
2917 uint32_t diag_fw;
2918 uint32_t offset;/* start offset */
2919 uint32_t len; /* num bytes in cur xfer */
2920 uint32_t fw_len; /* size of fw in bytes */
2921 uint8_t fw_bytes[0];
2922 };
2923
2924 #endif
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