2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/nvme.h>
11 #include <linux/nvme-fc.h>
15 #define MBS_CHECKSUM_ERROR 0x4010
16 #define MBS_INVALID_PRODUCT_KEY 0x4020
21 #define FO1_ENABLE_PUREX BIT_10
22 #define FO1_DISABLE_LED_CTRL BIT_6
23 #define FO1_ENABLE_8016 BIT_0
24 #define FO2_ENABLE_SEL_CLASS2 BIT_5
25 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
26 #define FO3_HOLD_STS_IOCB BIT_12
29 * Port Database structure definition for ISP 24xx.
31 #define PDO_FORCE_ADISC BIT_1
32 #define PDO_FORCE_PLOGI BIT_0
34 struct buffer_credit_24xx
{
38 #define PORT_DATABASE_24XX_SIZE 64
39 struct port_database_24xx
{
41 #define PDF_TASK_RETRY_ID BIT_14
42 #define PDF_FC_TAPE BIT_7
43 #define PDF_ACK0_CAPABLE BIT_6
44 #define PDF_FCP2_CONF BIT_5
45 #define PDF_CLASS_2 BIT_4
46 #define PDF_HARD_ADDR BIT_1
49 * for NVMe, the login_state field has been
51 * The lower nibble is for FCP.
52 * The upper nibble is for NVMe.
54 uint8_t current_login_state
;
55 uint8_t last_login_state
;
56 #define PDS_PLOGI_PENDING 0x03
57 #define PDS_PLOGI_COMPLETE 0x04
58 #define PDS_PRLI_PENDING 0x05
59 #define PDS_PRLI_COMPLETE 0x06
60 #define PDS_PORT_UNAVAILABLE 0x07
61 #define PDS_PRLO_PENDING 0x09
62 #define PDS_LOGO_PENDING 0x11
63 #define PDS_PRLI2_PENDING 0x12
65 uint8_t hard_address
[3];
73 uint16_t nport_handle
; /* N_PORT handle. */
75 uint16_t receive_data_size
;
78 uint8_t prli_svc_param_word_0
[2]; /* Big endian */
79 /* Bits 15-0 of word 0 */
80 uint8_t prli_svc_param_word_3
[2]; /* Big endian */
81 /* Bits 15-0 of word 3 */
83 uint8_t port_name
[WWN_SIZE
];
84 uint8_t node_name
[WWN_SIZE
];
86 uint8_t reserved_3
[4];
87 uint16_t prli_nvme_svc_param_word_0
; /* Bits 15-0 of word 0 */
88 uint16_t prli_nvme_svc_param_word_3
; /* Bits 15-0 of word 3 */
89 uint16_t nvme_first_burst_size
;
90 uint8_t reserved_4
[14];
94 * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
95 * However, in this case it returns 1st 40 bytes.
97 struct get_name_list_extended
{
99 u8 current_login_state
;
106 __le16 nport_handle
; /* N_PORT handle. */
107 __le16 receive_data_size
;
110 /* PRLI SVC Param are Big endian */
111 u8 prli_svc_param_word_0
[2]; /* Bits 15-0 of word 0 */
112 u8 prli_svc_param_word_3
[2]; /* Bits 15-0 of word 3 */
113 u8 port_name
[WWN_SIZE
];
114 u8 node_name
[WWN_SIZE
];
117 /* MB 75h: This is the short version of the database */
118 struct get_name_list
{
119 u8 port_node_name
[WWN_SIZE
]; /* B7 most sig, B0 least sig */
124 struct vp_database_24xx
{
128 uint8_t port_name
[WWN_SIZE
];
129 uint8_t node_name
[WWN_SIZE
];
130 uint16_t port_id_low
;
131 uint16_t port_id_high
;
137 __le16 nvram_version
;
140 /* Firmware Initialization Control Block. */
143 __le16 frame_payload_size
;
144 __le16 execution_throttle
;
145 __le16 exchange_count
;
148 uint8_t port_name
[WWN_SIZE
];
149 uint8_t node_name
[WWN_SIZE
];
151 __le16 login_retry_count
;
152 __le16 link_down_on_nos
;
153 __le16 interrupt_delay_timer
;
154 __le16 login_timeout
;
156 __le32 firmware_options_1
;
157 __le32 firmware_options_2
;
158 __le32 firmware_options_3
;
163 * BIT 0 = Control Enable
167 * BIT 8-10 = Output Swing 1G
168 * BIT 11-13 = Output Emphasis 1G
169 * BIT 14-15 = Reserved
172 * BIT 8-10 = Output Swing 2G
173 * BIT 11-13 = Output Emphasis 2G
174 * BIT 14-15 = Reserved
177 * BIT 8-10 = Output Swing 4G
178 * BIT 11-13 = Output Emphasis 4G
179 * BIT 14-15 = Reserved
181 __le16 seriallink_options
[4];
183 uint16_t reserved_2
[16];
186 uint16_t reserved_3
[16];
188 /* PCIe table entries. */
189 uint16_t reserved_4
[16];
192 uint16_t reserved_5
[16];
195 uint16_t reserved_6
[16];
198 uint16_t reserved_7
[16];
201 * BIT 0 = Enable spinup delay
202 * BIT 1 = Disable BIOS
203 * BIT 2 = Enable Memory Map BIOS
204 * BIT 3 = Enable Selectable Boot
205 * BIT 4 = Disable RISC code load
206 * BIT 5 = Disable Serdes
212 * BIT 10 = Enable lip full login
213 * BIT 11 = Enable target reset
217 * BIT 15 = Enable alternate WWN
223 uint8_t alternate_port_name
[WWN_SIZE
];
224 uint8_t alternate_node_name
[WWN_SIZE
];
226 uint8_t boot_port_name
[WWN_SIZE
];
227 __le16 boot_lun_number
;
230 uint8_t alt1_boot_port_name
[WWN_SIZE
];
231 __le16 alt1_boot_lun_number
;
234 uint8_t alt2_boot_port_name
[WWN_SIZE
];
235 __le16 alt2_boot_lun_number
;
236 uint16_t reserved_10
;
238 uint8_t alt3_boot_port_name
[WWN_SIZE
];
239 __le16 alt3_boot_lun_number
;
240 uint16_t reserved_11
;
243 * BIT 0 = Selective Login
244 * BIT 1 = Alt-Boot Enable
246 * BIT 3 = Boot Order List
248 * BIT 5 = Selective LUN
252 __le32 efi_parameters
;
256 uint16_t reserved_13
;
258 __le16 boot_id_number
;
259 uint16_t reserved_14
;
261 __le16 max_luns_per_target
;
262 uint16_t reserved_15
;
264 __le16 port_down_retry_count
;
265 __le16 link_down_timeout
;
267 /* FCode parameters. */
268 __le16 fcode_parameter
;
270 uint16_t reserved_16
[3];
273 uint8_t prev_drv_ver_major
;
274 uint8_t prev_drv_ver_submajob
;
275 uint8_t prev_drv_ver_minor
;
276 uint8_t prev_drv_ver_subminor
;
278 __le16 prev_bios_ver_major
;
279 __le16 prev_bios_ver_minor
;
281 __le16 prev_efi_ver_major
;
282 __le16 prev_efi_ver_minor
;
284 __le16 prev_fw_ver_major
;
285 uint8_t prev_fw_ver_minor
;
286 uint8_t prev_fw_ver_subminor
;
288 uint16_t reserved_17
[8];
291 uint16_t reserved_18
[16];
294 uint16_t reserved_19
[16];
297 uint16_t reserved_20
[16];
300 uint8_t model_name
[16];
302 uint16_t reserved_21
[2];
305 /* HW Parameter Block. */
306 uint16_t pcie_table_sig
;
307 uint16_t pcie_table_offset
;
309 uint16_t subsystem_vendor_id
;
310 uint16_t subsystem_device_id
;
316 * ISP Initialization Control Block.
317 * Little endian except where noted.
319 #define ICB_VERSION 1
320 struct init_cb_24xx
{
324 __le16 frame_payload_size
;
325 __le16 execution_throttle
;
326 __le16 exchange_count
;
330 uint8_t port_name
[WWN_SIZE
]; /* Big endian. */
331 uint8_t node_name
[WWN_SIZE
]; /* Big endian. */
333 __le16 response_q_inpointer
;
334 __le16 request_q_outpointer
;
336 __le16 login_retry_count
;
338 __le16 prio_request_q_outpointer
;
340 __le16 response_q_length
;
341 __le16 request_q_length
;
343 __le16 link_down_on_nos
; /* Milliseconds. */
345 __le16 prio_request_q_length
;
347 __le64 request_q_address __packed
;
348 __le64 response_q_address __packed
;
349 __le64 prio_request_q_address __packed
;
353 uint8_t reserved_2
[4];
355 __le16 atio_q_inpointer
;
356 __le16 atio_q_length
;
357 __le64 atio_q_address __packed
;
359 __le16 interrupt_delay_timer
; /* 100us increments. */
360 __le16 login_timeout
;
363 * BIT 0 = Enable Hard Loop Id
364 * BIT 1 = Enable Fairness
365 * BIT 2 = Enable Full-Duplex
367 * BIT 4 = Enable Target Mode
368 * BIT 5 = Disable Initiator Mode
369 * BIT 6 = Acquire FA-WWN
370 * BIT 7 = Enable D-port Diagnostics
373 * BIT 9 = Non Participating LIP
374 * BIT 10 = Descending Loop ID Search
375 * BIT 11 = Acquire Loop ID in LIPA
377 * BIT 13 = Full Login after LIP
378 * BIT 14 = Node Name Option
379 * BIT 15-31 = Reserved
381 __le32 firmware_options_1
;
384 * BIT 0 = Operation Mode bit 0
385 * BIT 1 = Operation Mode bit 1
386 * BIT 2 = Operation Mode bit 2
387 * BIT 3 = Operation Mode bit 3
388 * BIT 4 = Connection Options bit 0
389 * BIT 5 = Connection Options bit 1
390 * BIT 6 = Connection Options bit 2
391 * BIT 7 = Enable Non part on LIHA failure
393 * BIT 8 = Enable Class 2
394 * BIT 9 = Enable ACK0
396 * BIT 11 = Enable FC-SP Security
397 * BIT 12 = FC Tape Enable
399 * BIT 14 = Enable Target PRLI Control
400 * BIT 15-31 = Reserved
402 __le32 firmware_options_2
;
406 * BIT 1 = Soft ID only
409 * BIT 4 = FCP RSP Payload bit 0
410 * BIT 5 = FCP RSP Payload bit 1
411 * BIT 6 = Enable Receive Out-of-Order data frame handling
412 * BIT 7 = Disable Automatic PLOGI on Local Loop
415 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
419 * BIT 13 = Data Rate bit 0
420 * BIT 14 = Data Rate bit 1
421 * BIT 15 = Data Rate bit 2
422 * BIT 16 = Enable 75 ohm Termination Select
423 * BIT 17-28 = Reserved
424 * BIT 29 = Enable response queue 0 in index shadowing
425 * BIT 30 = Enable request queue 0 out index shadowing
428 __le32 firmware_options_3
;
431 uint8_t reserved_3
[20];
435 * ISP queue - command entry structure definition.
437 #define COMMAND_BIDIRECTIONAL 0x75
439 uint8_t entry_type
; /* Entry type. */
440 uint8_t entry_count
; /* Entry count. */
441 uint8_t sys_define
; /* System defined */
442 uint8_t entry_status
; /* Entry status. */
444 uint32_t handle
; /* System handle. */
446 __le16 nport_handle
; /* N_PORT handle. */
448 __le16 timeout
; /* Command timeout. */
450 __le16 wr_dseg_count
; /* Write Data segment count. */
451 __le16 rd_dseg_count
; /* Read Data segment count. */
453 struct scsi_lun lun
; /* FCP LUN (BE). */
455 __le16 control_flags
; /* Control flags. */
456 #define BD_WRAP_BACK BIT_3
457 #define BD_READ_DATA BIT_1
458 #define BD_WRITE_DATA BIT_0
460 __le16 fcp_cmnd_dseg_len
; /* Data segment length. */
461 __le64 fcp_cmnd_dseg_address __packed
;/* Data segment address. */
463 uint16_t reserved
[2]; /* Reserved */
465 __le32 rd_byte_count
; /* Total Byte count Read. */
466 __le32 wr_byte_count
; /* Total Byte count write. */
468 uint8_t port_id
[3]; /* PortID of destination port.*/
471 struct dsd64 fcp_dsd
;
474 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
476 uint8_t entry_type
; /* Entry type. */
477 uint8_t entry_count
; /* Entry count. */
478 uint8_t sys_define
; /* System defined. */
479 uint8_t entry_status
; /* Entry Status. */
481 uint32_t handle
; /* System handle. */
483 __le16 nport_handle
; /* N_PORT handle. */
484 __le16 timeout
; /* Command timeout. */
486 __le16 dseg_count
; /* Data segment count. */
488 __le16 fcp_rsp_dsd_len
; /* FCP_RSP DSD length. */
490 struct scsi_lun lun
; /* FCP LUN (BE). */
492 __le16 control_flags
; /* Control flags. */
493 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
494 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
495 #define CF_READ_DATA BIT_1
496 #define CF_WRITE_DATA BIT_0
498 __le16 fcp_cmnd_dseg_len
; /* Data segment length. */
499 /* Data segment address. */
500 __le64 fcp_cmnd_dseg_address __packed
;
501 /* Data segment address. */
502 __le64 fcp_rsp_dseg_address __packed
;
504 __le32 byte_count
; /* Total byte count. */
506 uint8_t port_id
[3]; /* PortID of destination port. */
509 struct dsd64 fcp_dsd
;
512 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
514 uint8_t entry_type
; /* Entry type. */
515 uint8_t entry_count
; /* Entry count. */
516 uint8_t sys_define
; /* System defined. */
517 uint8_t entry_status
; /* Entry Status. */
519 uint32_t handle
; /* System handle. */
521 __le16 nport_handle
; /* N_PORT handle. */
522 __le16 timeout
; /* Command timeout. */
523 #define FW_MAX_TIMEOUT 0x1999
525 __le16 dseg_count
; /* Data segment count. */
528 struct scsi_lun lun
; /* FCP LUN (BE). */
530 __le16 task_mgmt_flags
; /* Task management flags. */
531 #define TMF_CLEAR_ACA BIT_14
532 #define TMF_TARGET_RESET BIT_13
533 #define TMF_LUN_RESET BIT_12
534 #define TMF_CLEAR_TASK_SET BIT_10
535 #define TMF_ABORT_TASK_SET BIT_9
536 #define TMF_DSD_LIST_ENABLE BIT_2
537 #define TMF_READ_DATA BIT_1
538 #define TMF_WRITE_DATA BIT_0
542 #define TSK_HEAD_OF_QUEUE 1
543 #define TSK_ORDERED 2
545 #define TSK_UNTAGGED 5
549 uint8_t fcp_cdb
[MAX_CMDSZ
]; /* SCSI command words. */
550 __le32 byte_count
; /* Total byte count. */
552 uint8_t port_id
[3]; /* PortID of destination port. */
558 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
560 struct cmd_type_crc_2
{
561 uint8_t entry_type
; /* Entry type. */
562 uint8_t entry_count
; /* Entry count. */
563 uint8_t sys_define
; /* System defined. */
564 uint8_t entry_status
; /* Entry Status. */
566 uint32_t handle
; /* System handle. */
568 __le16 nport_handle
; /* N_PORT handle. */
569 __le16 timeout
; /* Command timeout. */
571 __le16 dseg_count
; /* Data segment count. */
573 __le16 fcp_rsp_dseg_len
; /* FCP_RSP DSD length. */
575 struct scsi_lun lun
; /* FCP LUN (BE). */
577 __le16 control_flags
; /* Control flags. */
579 __le16 fcp_cmnd_dseg_len
; /* Data segment length. */
580 __le64 fcp_cmnd_dseg_address __packed
;
581 /* Data segment address. */
582 __le64 fcp_rsp_dseg_address __packed
;
584 __le32 byte_count
; /* Total byte count. */
586 uint8_t port_id
[3]; /* PortID of destination port. */
589 __le64 crc_context_address __packed
; /* Data segment address. */
590 __le16 crc_context_len
; /* Data segment length. */
591 uint16_t reserved_1
; /* MUST be set to 0. */
596 * ISP queue - status entry structure definition.
598 #define STATUS_TYPE 0x03 /* Status entry. */
599 struct sts_entry_24xx
{
600 uint8_t entry_type
; /* Entry type. */
601 uint8_t entry_count
; /* Entry count. */
602 uint8_t sys_define
; /* System defined. */
603 uint8_t entry_status
; /* Entry Status. */
605 uint32_t handle
; /* System handle. */
607 __le16 comp_status
; /* Completion status. */
608 __le16 ox_id
; /* OX_ID used by the firmware. */
610 __le32 residual_len
; /* FW calc residual transfer length. */
614 __le16 nvme_rsp_pyld_len
;
617 __le16 state_flags
; /* State flags. */
618 #define SF_TRANSFERRED_DATA BIT_11
619 #define SF_NVME_ERSP BIT_6
620 #define SF_FCP_RSP_DMA BIT_0
623 __le16 scsi_status
; /* SCSI status. */
624 #define SS_CONFIRMATION_REQ BIT_12
626 __le32 rsp_residual_count
; /* FCP RSP residual count. */
628 __le32 sense_len
; /* FCP SENSE length. */
632 __le32 rsp_data_len
; /* FCP response data length */
633 uint8_t data
[28]; /* FCP rsp/sense information */
635 struct nvme_fc_ersp_iu nvme_ersp
;
636 uint8_t nvme_ersp_data
[32];
640 * If DIF Error is set in comp_status, these additional fields are
643 * !!! NOTE: Firmware sends expected/actual DIF data in big endian
644 * format; but all of the "data" field gets swab32-d in the beginning
645 * of qla2x00_status_entry().
647 * &data[10] : uint8_t report_runt_bg[2]; - computed guard
648 * &data[12] : uint8_t actual_dif[8]; - DIF Data received
649 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed
655 * Status entry completion status
657 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
658 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
659 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
660 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
661 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
664 * ISP queue - marker entry structure definition.
666 #define MARKER_TYPE 0x04 /* Marker entry. */
667 struct mrk_entry_24xx
{
668 uint8_t entry_type
; /* Entry type. */
669 uint8_t entry_count
; /* Entry count. */
670 uint8_t handle_count
; /* Handle count. */
671 uint8_t entry_status
; /* Entry Status. */
673 uint32_t handle
; /* System handle. */
675 __le16 nport_handle
; /* N_PORT handle. */
677 uint8_t modifier
; /* Modifier (7-0). */
678 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
679 #define MK_SYNC_ID 1 /* Synchronize ID */
680 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
688 uint8_t lun
[8]; /* FCP LUN (BE). */
689 uint8_t reserved_4
[40];
693 * ISP queue - CT Pass-Through entry structure definition.
695 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
696 struct ct_entry_24xx
{
697 uint8_t entry_type
; /* Entry type. */
698 uint8_t entry_count
; /* Entry count. */
699 uint8_t sys_define
; /* System Defined. */
700 uint8_t entry_status
; /* Entry Status. */
702 uint32_t handle
; /* System handle. */
704 __le16 comp_status
; /* Completion status. */
706 __le16 nport_handle
; /* N_PORT handle. */
708 __le16 cmd_dsd_count
;
713 __le16 timeout
; /* Command timeout. */
716 __le16 rsp_dsd_count
;
718 uint8_t reserved_3
[10];
720 __le32 rsp_byte_count
;
721 __le32 cmd_byte_count
;
726 #define PURX_ELS_HEADER_SIZE 0x18
729 * ISP queue - PUREX IOCB entry structure definition
731 #define PUREX_IOCB_TYPE 0x51 /* CT Pass Through IOCB entry */
732 struct purex_entry_24xx
{
733 uint8_t entry_type
; /* Entry type. */
734 uint8_t entry_count
; /* Entry count. */
735 uint8_t sys_define
; /* System defined. */
736 uint8_t entry_status
; /* Entry Status. */
746 __le16 trunc_frame_size
;
767 uint8_t els_frame_payload
[20];
771 * ISP queue - ELS Pass-Through entry structure definition.
773 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
774 struct els_entry_24xx
{
775 uint8_t entry_type
; /* Entry type. */
776 uint8_t entry_count
; /* Entry count. */
777 uint8_t sys_define
; /* System Defined. */
778 uint8_t entry_status
; /* Entry Status. */
780 uint32_t handle
; /* System handle. */
782 __le16 comp_status
; /* response only */
789 #define EST_SOFI3 (1 << 4)
790 #define EST_SOFI2 (3 << 4)
792 __le32 rx_xchg_address
; /* Receive exchange address. */
801 __le16 control_flags
; /* Control flags. */
802 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
803 #define EPD_ELS_COMMAND (0 << 13)
804 #define EPD_ELS_ACC (1 << 13)
805 #define EPD_ELS_RJT (2 << 13)
806 #define EPD_RX_XCHG (3 << 13)
807 #define ECF_CLR_PASSTHRU_PEND BIT_12
808 #define ECF_INCL_FRAME_HDR BIT_11
812 __le32 rx_byte_count
;
813 __le32 tx_byte_count
;
815 __le64 tx_address __packed
; /* DSD 0 address. */
816 __le32 tx_len
; /* DSD 0 length. */
818 __le64 rx_address __packed
; /* DSD 1 address. */
819 __le32 rx_len
; /* DSD 1 length. */
822 __le32 total_byte_count
;
823 __le32 error_subcode_1
;
824 __le32 error_subcode_2
;
825 __le32 error_subcode_3
;
830 struct els_sts_entry_24xx
{
831 uint8_t entry_type
; /* Entry type. */
832 uint8_t entry_count
; /* Entry count. */
833 uint8_t sys_define
; /* System Defined. */
834 uint8_t entry_status
; /* Entry Status. */
836 __le32 handle
; /* System handle. */
840 __le16 nport_handle
; /* N_PORT handle. */
847 __le32 rx_xchg_address
; /* Receive exchange address. */
856 __le16 control_flags
; /* Control flags. */
857 __le32 total_byte_count
;
858 __le32 error_subcode_1
;
859 __le32 error_subcode_2
;
860 __le32 error_subcode_3
;
862 __le32 reserved_4
[4];
865 * ISP queue - Mailbox Command entry structure definition.
867 #define MBX_IOCB_TYPE 0x39
868 struct mbx_entry_24xx
{
869 uint8_t entry_type
; /* Entry type. */
870 uint8_t entry_count
; /* Entry count. */
871 uint8_t handle_count
; /* Handle count. */
872 uint8_t entry_status
; /* Entry Status. */
874 uint32_t handle
; /* System handle. */
880 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
881 struct logio_entry_24xx
{
882 uint8_t entry_type
; /* Entry type. */
883 uint8_t entry_count
; /* Entry count. */
884 uint8_t sys_define
; /* System defined. */
885 uint8_t entry_status
; /* Entry Status. */
887 uint32_t handle
; /* System handle. */
889 __le16 comp_status
; /* Completion status. */
890 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
892 __le16 nport_handle
; /* N_PORT handle. */
894 __le16 control_flags
; /* Control flags. */
896 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */
897 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
898 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
899 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
900 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
901 #define LCF_NVME_PRLI BIT_6 /* Perform NVME FC4 PRLI */
902 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
903 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
904 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
905 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
906 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
908 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
909 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
910 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
911 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
912 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
913 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
914 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
919 uint8_t port_id
[3]; /* PortID of destination port. */
921 uint8_t rsp_size
; /* Response size in 32bit words. */
923 __le32 io_parameter
[11]; /* General I/O parameters. */
924 #define LSC_SCODE_NOLINK 0x01
925 #define LSC_SCODE_NOIOCB 0x02
926 #define LSC_SCODE_NOXCB 0x03
927 #define LSC_SCODE_CMD_FAILED 0x04
928 #define LSC_SCODE_NOFABRIC 0x05
929 #define LSC_SCODE_FW_NOT_READY 0x07
930 #define LSC_SCODE_NOT_LOGGED_IN 0x09
931 #define LSC_SCODE_NOPCB 0x0A
933 #define LSC_SCODE_ELS_REJECT 0x18
934 #define LSC_SCODE_CMD_PARAM_ERR 0x19
935 #define LSC_SCODE_PORTID_USED 0x1A
936 #define LSC_SCODE_NPORT_USED 0x1B
937 #define LSC_SCODE_NONPORT 0x1C
938 #define LSC_SCODE_LOGGED_IN 0x1D
939 #define LSC_SCODE_NOFLOGI_ACC 0x1F
942 #define TSK_MGMT_IOCB_TYPE 0x14
943 struct tsk_mgmt_entry
{
944 uint8_t entry_type
; /* Entry type. */
945 uint8_t entry_count
; /* Entry count. */
946 uint8_t handle_count
; /* Handle count. */
947 uint8_t entry_status
; /* Entry Status. */
949 uint32_t handle
; /* System handle. */
951 __le16 nport_handle
; /* N_PORT handle. */
955 __le16 delay
; /* Activity delay in seconds. */
957 __le16 timeout
; /* Command timeout. */
959 struct scsi_lun lun
; /* FCP LUN (BE). */
961 __le32 control_flags
; /* Control Flags. */
962 #define TCF_NOTMCMD_TO_TARGET BIT_31
963 #define TCF_LUN_RESET BIT_4
964 #define TCF_ABORT_TASK_SET BIT_3
965 #define TCF_CLEAR_TASK_SET BIT_2
966 #define TCF_TARGET_RESET BIT_1
967 #define TCF_CLEAR_ACA BIT_0
969 uint8_t reserved_2
[20];
971 uint8_t port_id
[3]; /* PortID of destination port. */
974 uint8_t reserved_3
[12];
977 #define ABORT_IOCB_TYPE 0x33
978 struct abort_entry_24xx
{
979 uint8_t entry_type
; /* Entry type. */
980 uint8_t entry_count
; /* Entry count. */
981 uint8_t handle_count
; /* Handle count. */
982 uint8_t entry_status
; /* Entry Status. */
984 uint32_t handle
; /* System handle. */
986 __le16 nport_handle
; /* N_PORT handle. */
987 /* or Completion status. */
989 __le16 options
; /* Options. */
990 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
992 uint32_t handle_to_abort
; /* System handle to abort. */
995 uint8_t reserved_1
[30];
997 uint8_t port_id
[3]; /* PortID of destination port. */
1000 uint8_t reserved_2
[12];
1003 #define ABTS_RCV_TYPE 0x54
1004 #define ABTS_RSP_TYPE 0x55
1005 struct abts_entry_24xx
{
1007 uint8_t entry_count
;
1008 uint8_t handle_count
;
1009 uint8_t entry_status
;
1011 __le32 handle
; /* type 0x55 only */
1013 __le16 comp_status
; /* type 0x55 only */
1014 __le16 nport_handle
; /* type 0x54 only */
1016 __le16 control_flags
; /* type 0x55 only */
1018 uint8_t sof_type
; /* sof_type is upper nibble */
1049 uint8_t last_seq_id
;
1050 uint8_t seq_id_valid
;
1051 __le16 aborted_rx_id
;
1052 __le16 aborted_ox_id
;
1053 __le16 high_seq_cnt
;
1057 uint8_t vendor_unique
;
1058 uint8_t explanation
;
1063 __le32 rx_xch_addr_to_abort
;
1066 /* ABTS payload explanation values */
1067 #define BA_RJT_EXP_NO_ADDITIONAL 0
1068 #define BA_RJT_EXP_INV_OX_RX_ID 3
1069 #define BA_RJT_EXP_SEQ_ABORTED 5
1071 /* ABTS payload reason values */
1072 #define BA_RJT_RSN_INV_CMD_CODE 1
1073 #define BA_RJT_RSN_LOGICAL_ERROR 3
1074 #define BA_RJT_RSN_LOGICAL_BUSY 5
1075 #define BA_RJT_RSN_PROTOCOL_ERROR 7
1076 #define BA_RJT_RSN_UNABLE_TO_PERFORM 9
1077 #define BA_RJT_RSN_VENDOR_SPECIFIC 0xff
1080 #define FC_TYPE_BLD 0x000 /* Basic link data */
1081 #define FC_F_CTL_RSP_CNTXT 0x800000 /* Responder of exchange */
1082 #define FC_F_CTL_LAST_SEQ 0x100000 /* Last sequence */
1083 #define FC_F_CTL_END_SEQ 0x80000 /* Last sequence */
1084 #define FC_F_CTL_SEQ_INIT 0x010000 /* Sequence initiative */
1085 #define FC_ROUTING_BLD 0x80 /* Basic link data frame */
1086 #define FC_R_CTL_BLD_BA_ACC 0x04 /* BA_ACC (basic accept) */
1089 * ISP I/O Register Set structure definitions.
1091 struct device_reg_24xx
{
1092 __le32 flash_addr
; /* Flash/NVRAM BIOS address. */
1093 #define FARX_DATA_FLAG BIT_31
1094 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
1095 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
1096 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
1097 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
1099 #define FA_NVRAM_FUNC0_ADDR 0x80
1100 #define FA_NVRAM_FUNC1_ADDR 0x180
1102 #define FA_NVRAM_VPD_SIZE 0x200
1103 #define FA_NVRAM_VPD0_ADDR 0x00
1104 #define FA_NVRAM_VPD1_ADDR 0x100
1106 #define FA_BOOT_CODE_ADDR 0x00000
1108 * RISC code begins at offset 512KB
1109 * within flash. Consisting of two
1110 * contiguous RISC code segments.
1112 #define FA_RISC_CODE_ADDR 0x20000
1113 #define FA_RISC_CODE_SEGMENTS 2
1115 #define FA_FLASH_DESCR_ADDR_24 0x11000
1116 #define FA_FLASH_LAYOUT_ADDR_24 0x11400
1117 #define FA_NPIV_CONF0_ADDR_24 0x16000
1118 #define FA_NPIV_CONF1_ADDR_24 0x17000
1120 #define FA_FW_AREA_ADDR 0x40000
1121 #define FA_VPD_NVRAM_ADDR 0x48000
1122 #define FA_FEATURE_ADDR 0x4C000
1123 #define FA_FLASH_DESCR_ADDR 0x50000
1124 #define FA_FLASH_LAYOUT_ADDR 0x50400
1125 #define FA_HW_EVENT0_ADDR 0x54000
1126 #define FA_HW_EVENT1_ADDR 0x54400
1127 #define FA_HW_EVENT_SIZE 0x200
1128 #define FA_HW_EVENT_ENTRY_SIZE 4
1129 #define FA_NPIV_CONF0_ADDR 0x5C000
1130 #define FA_NPIV_CONF1_ADDR 0x5D000
1131 #define FA_FCP_PRIO0_ADDR 0x10000
1132 #define FA_FCP_PRIO1_ADDR 0x12000
1135 * Flash Error Log Event Codes.
1137 #define HW_EVENT_RESET_ERR 0xF00B
1138 #define HW_EVENT_ISP_ERR 0xF020
1139 #define HW_EVENT_PARITY_ERR 0xF022
1140 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
1141 #define HW_EVENT_FLASH_FW_ERR 0xF024
1143 __le32 flash_data
; /* Flash/NVRAM BIOS data. */
1145 __le32 ctrl_status
; /* Control/Status. */
1146 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
1147 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
1148 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
1149 #define CSRX_FUNCTION BIT_15 /* Function number. */
1150 /* PCI-X Bus Mode. */
1151 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
1152 #define PBM_PCI_33MHZ (0 << 8)
1153 #define PBM_PCIX_M1_66MHZ (1 << 8)
1154 #define PBM_PCIX_M1_100MHZ (2 << 8)
1155 #define PBM_PCIX_M1_133MHZ (3 << 8)
1156 #define PBM_PCIX_M2_66MHZ (5 << 8)
1157 #define PBM_PCIX_M2_100MHZ (6 << 8)
1158 #define PBM_PCIX_M2_133MHZ (7 << 8)
1159 #define PBM_PCI_66MHZ (8 << 8)
1160 /* Max Write Burst byte count. */
1161 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
1162 #define MWB_512_BYTES (0 << 4)
1163 #define MWB_1024_BYTES (1 << 4)
1164 #define MWB_2048_BYTES (2 << 4)
1165 #define MWB_4096_BYTES (3 << 4)
1167 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
1168 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1169 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
1171 __le32 ictrl
; /* Interrupt control. */
1172 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
1174 __le32 istatus
; /* Interrupt status. */
1175 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
1177 __le32 unused_1
[2]; /* Gap. */
1179 /* Request Queue. */
1180 __le32 req_q_in
; /* In-Pointer. */
1181 __le32 req_q_out
; /* Out-Pointer. */
1182 /* Response Queue. */
1183 __le32 rsp_q_in
; /* In-Pointer. */
1184 __le32 rsp_q_out
; /* Out-Pointer. */
1185 /* Priority Request Queue. */
1186 __le32 preq_q_in
; /* In-Pointer. */
1187 __le32 preq_q_out
; /* Out-Pointer. */
1189 __le32 unused_2
[2]; /* Gap. */
1192 __le32 atio_q_in
; /* In-Pointer. */
1193 __le32 atio_q_out
; /* Out-Pointer. */
1196 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
1197 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
1199 __le32 hccr
; /* Host command & control register. */
1200 /* HCCR statuses. */
1201 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
1202 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
1203 /* HCCR commands. */
1205 #define HCCRX_NOOP 0x00000000
1206 /* Set RISC Reset. */
1207 #define HCCRX_SET_RISC_RESET 0x10000000
1208 /* Clear RISC Reset. */
1209 #define HCCRX_CLR_RISC_RESET 0x20000000
1210 /* Set RISC Pause. */
1211 #define HCCRX_SET_RISC_PAUSE 0x30000000
1212 /* Releases RISC Pause. */
1213 #define HCCRX_REL_RISC_PAUSE 0x40000000
1214 /* Set HOST to RISC interrupt. */
1215 #define HCCRX_SET_HOST_INT 0x50000000
1216 /* Clear HOST to RISC interrupt. */
1217 #define HCCRX_CLR_HOST_INT 0x60000000
1218 /* Clear RISC to PCI interrupt. */
1219 #define HCCRX_CLR_RISC_INT 0xA0000000
1221 __le32 gpiod
; /* GPIO Data register. */
1223 /* LED update mask. */
1224 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
1225 /* Data update mask. */
1226 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
1227 /* Data update mask. */
1228 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1229 /* LED control mask. */
1230 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
1231 /* LED bit values. Color names as
1232 * referenced in fw spec.
1234 #define GPDX_LED_YELLOW_ON BIT_2
1235 #define GPDX_LED_GREEN_ON BIT_3
1236 #define GPDX_LED_AMBER_ON BIT_4
1238 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1240 __le32 gpioe
; /* GPIO Enable register. */
1241 /* Enable update mask. */
1242 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1243 /* Enable update mask. */
1244 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1246 #define GPEX_ENABLE (BIT_1|BIT_0)
1248 __le32 iobase_addr
; /* I/O Bus Base Address register. */
1250 __le32 unused_3
[10]; /* Gap. */
1285 __le32 iobase_window
;
1288 __le32 unused_4_1
[6]; /* Gap. */
1290 __le32 unused_5
[2]; /* Gap. */
1291 __le32 iobase_select
;
1292 __le32 unused_6
[2]; /* Gap. */
1293 __le32 iobase_sdata
;
1295 /* RISC-RISC semaphore register PCI offet */
1296 #define RISC_REGISTER_BASE_OFFSET 0x7010
1297 #define RISC_REGISTER_WINDOW_OFFSET 0x6
1299 /* RISC-RISC semaphore/flag register (risc address 0x7016) */
1301 #define RISC_SEMAPHORE 0x1UL
1302 #define RISC_SEMAPHORE_WE (RISC_SEMAPHORE << 16)
1303 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL)
1304 #define RISC_SEMAPHORE_SET (RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
1306 #define RISC_SEMAPHORE_FORCE 0x8000UL
1307 #define RISC_SEMAPHORE_FORCE_WE (RISC_SEMAPHORE_FORCE << 16)
1308 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1309 #define RISC_SEMAPHORE_FORCE_SET \
1310 (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
1312 /* RISC semaphore timeouts (ms) */
1313 #define TIMEOUT_SEMAPHORE 2500
1314 #define TIMEOUT_SEMAPHORE_FORCE 2000
1315 #define TIMEOUT_TOTAL_ELAPSED 4500
1317 /* Trace Control *************************************************************/
1319 #define TC_AEN_DISABLE 0
1321 #define TC_EFT_ENABLE 4
1322 #define TC_EFT_DISABLE 5
1324 #define TC_FCE_ENABLE 8
1325 #define TC_FCE_OPTIONS 0
1326 #define TC_FCE_DEFAULT_RX_SIZE 2112
1327 #define TC_FCE_DEFAULT_TX_SIZE 2112
1328 #define TC_FCE_DISABLE 9
1329 #define TC_FCE_DISABLE_TRACE BIT_0
1331 /* MID Support ***************************************************************/
1333 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */
1334 #define MAX_MULTI_ID_FABRIC 256 /* ... */
1336 struct mid_conf_entry_24xx
{
1337 uint16_t reserved_1
;
1340 * BIT 0 = Enable Hard Loop Id
1341 * BIT 1 = Acquire Loop ID in LIPA
1342 * BIT 2 = ID not Acquired
1344 * BIT 4 = Enable Initiator Mode
1345 * BIT 5 = Disable Target Mode
1346 * BIT 6-7 = Reserved
1350 uint8_t hard_address
;
1352 uint8_t port_name
[WWN_SIZE
];
1353 uint8_t node_name
[WWN_SIZE
];
1356 struct mid_init_cb_24xx
{
1357 struct init_cb_24xx init_cb
;
1362 struct mid_conf_entry_24xx entries
[MAX_MULTI_ID_FABRIC
];
1366 struct mid_db_entry_24xx
{
1368 #define MDBS_NON_PARTIC BIT_3
1369 #define MDBS_ID_ACQUIRED BIT_1
1370 #define MDBS_ENABLED BIT_0
1373 uint8_t hard_address
;
1375 uint8_t port_name
[WWN_SIZE
];
1376 uint8_t node_name
[WWN_SIZE
];
1383 * Virtual Port Control IOCB
1385 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */
1386 struct vp_ctrl_entry_24xx
{
1387 uint8_t entry_type
; /* Entry type. */
1388 uint8_t entry_count
; /* Entry count. */
1389 uint8_t sys_define
; /* System defined. */
1390 uint8_t entry_status
; /* Entry Status. */
1392 uint32_t handle
; /* System handle. */
1394 __le16 vp_idx_failed
;
1396 __le16 comp_status
; /* Completion status. */
1397 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1398 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1399 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1402 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1403 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1404 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1405 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1406 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1410 uint8_t vp_idx_map
[16];
1413 uint16_t reserved_4
;
1415 uint8_t reserved_5
[24];
1419 * Modify Virtual Port Configuration IOCB
1421 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */
1422 struct vp_config_entry_24xx
{
1423 uint8_t entry_type
; /* Entry type. */
1424 uint8_t entry_count
; /* Entry count. */
1425 uint8_t handle_count
;
1426 uint8_t entry_status
; /* Entry Status. */
1428 uint32_t handle
; /* System handle. */
1431 #define CS_VF_BIND_VPORTS_TO_VF BIT_0
1432 #define CS_VF_SET_QOS_OF_VPORTS BIT_1
1433 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1435 __le16 comp_status
; /* Completion status. */
1436 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1437 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1438 #define CS_VCT_ERROR 0x03 /* Unknown error. */
1439 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1440 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1443 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
1444 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1451 uint8_t options_idx1
;
1452 uint8_t hard_address_idx1
;
1453 uint16_t reserved_vp1
;
1454 uint8_t port_name_idx1
[WWN_SIZE
];
1455 uint8_t node_name_idx1
[WWN_SIZE
];
1457 uint8_t options_idx2
;
1458 uint8_t hard_address_idx2
;
1459 uint16_t reserved_vp2
;
1460 uint8_t port_name_idx2
[WWN_SIZE
];
1461 uint8_t node_name_idx2
[WWN_SIZE
];
1463 uint16_t reserved_4
;
1465 uint8_t reserved_5
[2];
1468 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1473 VP_STAT_SNS_TO
, /* timeout */
1475 VP_STAT_SCR_TO
, /* timeout */
1480 VP_FLAGS_CON_FLOOP
= 1,
1481 VP_FLAGS_CON_P2P
= 2,
1482 VP_FLAGS_CON_FABRIC
= 3,
1483 VP_FLAGS_NAME_VALID
= BIT_5
,
1486 struct vp_rpt_id_entry_24xx
{
1487 uint8_t entry_type
; /* Entry type. */
1488 uint8_t entry_count
; /* Entry count. */
1489 uint8_t sys_define
; /* System defined. */
1490 uint8_t entry_status
; /* Entry Status. */
1492 uint8_t vp_acquired
;
1494 uint8_t vp_idx
; /* Format 0=reserved */
1495 uint8_t vp_status
; /* Format 0=reserved */
1502 uint8_t vp_idx_map
[16];
1503 uint8_t reserved_4
[32];
1506 /* format 1 fabric */
1507 uint8_t vpstat1_subcode
; /* vp_status=1 subcode */
1509 #define TOPO_MASK 0xE
1511 #define TOPO_N2N 0x4
1517 uint8_t ls_rjt_vendor
;
1518 uint8_t ls_rjt_explanation
;
1519 uint8_t ls_rjt_reason
;
1522 uint8_t port_name
[8];
1523 uint8_t node_name
[8];
1525 uint8_t reserved_5
[6];
1527 struct _f2
{ /* format 2: N2N direct connect */
1528 uint8_t vpstat1_subcode
;
1533 uint8_t ls_rjt_vendor
;
1534 uint8_t ls_rjt_explanation
;
1535 uint8_t ls_rjt_reason
;
1538 uint8_t port_name
[8];
1539 uint8_t node_name
[8];
1541 uint8_t reserved_5
[2];
1542 uint8_t remote_nport_id
[4];
1547 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
1548 struct vf_evfp_entry_24xx
{
1549 uint8_t entry_type
; /* Entry type. */
1550 uint8_t entry_count
; /* Entry count. */
1551 uint8_t sys_define
; /* System defined. */
1552 uint8_t entry_status
; /* Entry Status. */
1554 uint32_t handle
; /* System handle. */
1555 __le16 comp_status
; /* Completion status. */
1556 __le16 timeout
; /* timeout */
1557 __le16 adim_tagging_mode
;
1562 __le16 nport_handle
; /* N_PORT handle. */
1563 __le16 control_flags
;
1564 uint32_t io_parameter_0
;
1565 uint32_t io_parameter_1
;
1566 __le64 tx_address __packed
; /* Data segment 0 address. */
1567 uint32_t tx_len
; /* Data segment 0 length. */
1568 __le64 rx_address __packed
; /* Data segment 1 address. */
1569 uint32_t rx_len
; /* Data segment 1 length. */
1572 /* END MID Support ***********************************************************/
1574 /* Flash Description Table ***************************************************/
1576 struct qla_fdt_layout
{
1587 uint8_t alt_erase_cmd
;
1588 uint8_t wrt_enable_cmd
;
1589 uint8_t wrt_enable_bits
;
1590 uint8_t wrt_sts_reg_cmd
;
1591 uint8_t unprotect_sec_cmd
;
1592 uint8_t read_man_id_cmd
;
1594 __le32 alt_block_size
;
1596 __le32 wrt_enable_data
;
1597 uint8_t read_id_addr_len
;
1598 uint8_t wrt_disable_bits
;
1599 uint8_t read_dev_id_len
;
1600 uint8_t chip_erase_cmd
;
1601 __le16 read_timeout
;
1602 uint8_t protect_sec_cmd
;
1603 uint8_t unused2
[65];
1606 /* Flash Layout Table ********************************************************/
1608 struct qla_flt_location
{
1617 #define FLT_REG_FW 0x01
1618 #define FLT_REG_BOOT_CODE 0x07
1619 #define FLT_REG_VPD_0 0x14
1620 #define FLT_REG_NVRAM_0 0x15
1621 #define FLT_REG_VPD_1 0x16
1622 #define FLT_REG_NVRAM_1 0x17
1623 #define FLT_REG_VPD_2 0xD4
1624 #define FLT_REG_NVRAM_2 0xD5
1625 #define FLT_REG_VPD_3 0xD6
1626 #define FLT_REG_NVRAM_3 0xD7
1627 #define FLT_REG_FDT 0x1a
1628 #define FLT_REG_FLT 0x1c
1629 #define FLT_REG_HW_EVENT_0 0x1d
1630 #define FLT_REG_HW_EVENT_1 0x1f
1631 #define FLT_REG_NPIV_CONF_0 0x29
1632 #define FLT_REG_NPIV_CONF_1 0x2a
1633 #define FLT_REG_GOLD_FW 0x2f
1634 #define FLT_REG_FCP_PRIO_0 0x87
1635 #define FLT_REG_FCP_PRIO_1 0x88
1636 #define FLT_REG_CNA_FW 0x97
1637 #define FLT_REG_BOOT_CODE_8044 0xA2
1638 #define FLT_REG_FCOE_FW 0xA4
1639 #define FLT_REG_FCOE_NVRAM_0 0xAA
1640 #define FLT_REG_FCOE_NVRAM_1 0xAC
1643 #define FLT_REG_IMG_PRI_27XX 0x95
1644 #define FLT_REG_IMG_SEC_27XX 0x96
1645 #define FLT_REG_FW_SEC_27XX 0x02
1646 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9
1647 #define FLT_REG_VPD_SEC_27XX_0 0x50
1648 #define FLT_REG_VPD_SEC_27XX_1 0x52
1649 #define FLT_REG_VPD_SEC_27XX_2 0xD8
1650 #define FLT_REG_VPD_SEC_27XX_3 0xDA
1653 #define FLT_REG_AUX_IMG_PRI_28XX 0x125
1654 #define FLT_REG_AUX_IMG_SEC_28XX 0x126
1655 #define FLT_REG_VPD_SEC_28XX_0 0x10C
1656 #define FLT_REG_VPD_SEC_28XX_1 0x10E
1657 #define FLT_REG_VPD_SEC_28XX_2 0x110
1658 #define FLT_REG_VPD_SEC_28XX_3 0x112
1659 #define FLT_REG_NVRAM_SEC_28XX_0 0x10D
1660 #define FLT_REG_NVRAM_SEC_28XX_1 0x10F
1661 #define FLT_REG_NVRAM_SEC_28XX_2 0x111
1662 #define FLT_REG_NVRAM_SEC_28XX_3 0x113
1663 #define FLT_REG_MPI_PRI_28XX 0xD3
1664 #define FLT_REG_MPI_SEC_28XX 0xF0
1665 #define FLT_REG_PEP_PRI_28XX 0xD1
1666 #define FLT_REG_PEP_SEC_28XX 0xF1
1668 struct qla_flt_region
{
1677 struct qla_flt_header
{
1682 struct qla_flt_region region
[0];
1685 #define FLT_REGION_SIZE 16
1686 #define FLT_MAX_REGIONS 0xFF
1687 #define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS)
1689 /* Flash NPIV Configuration Table ********************************************/
1691 struct qla_npiv_header
{
1699 struct qla_npiv_entry
{
1705 uint8_t port_name
[WWN_SIZE
];
1706 uint8_t node_name
[WWN_SIZE
];
1709 /* 84XX Support **************************************************************/
1711 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
1712 #define A84_PANIC_RECOVERY 0x1
1713 #define A84_OP_LOGIN_COMPLETE 0x2
1714 #define A84_DIAG_LOGIN_COMPLETE 0x3
1715 #define A84_GOLD_LOGIN_COMPLETE 0x4
1717 #define MBC_ISP84XX_RESET 0x3a /* Reset. */
1719 #define FSTATE_REMOTE_FC_DOWN BIT_0
1720 #define FSTATE_NSL_LINK_DOWN BIT_1
1721 #define FSTATE_IS_DIAG_FW BIT_2
1722 #define FSTATE_LOGGED_IN BIT_3
1723 #define FSTATE_WAITING_FOR_VERIFY BIT_4
1725 #define VERIFY_CHIP_IOCB_TYPE 0x1B
1726 struct verify_chip_entry_84xx
{
1728 uint8_t entry_count
;
1729 uint8_t sys_defined
;
1730 uint8_t entry_status
;
1735 #define VCO_DONT_UPDATE_FW BIT_0
1736 #define VCO_FORCE_UPDATE BIT_1
1737 #define VCO_DONT_RESET_UPDATE BIT_2
1738 #define VCO_DIAG_FW BIT_3
1739 #define VCO_END_OF_DATA BIT_14
1740 #define VCO_ENABLE_DSD BIT_15
1744 __le16 data_seg_cnt
;
1745 __le16 reserved_2
[3];
1748 __le32 exchange_address
;
1750 __le32 reserved_3
[3];
1753 __le32 relative_offset
;
1758 struct verify_chip_rsp_84xx
{
1760 uint8_t entry_count
;
1761 uint8_t sys_defined
;
1762 uint8_t entry_status
;
1767 #define CS_VCS_CHIP_FAILURE 0x3
1768 #define CS_VCS_BAD_EXCHANGE 0x8
1769 #define CS_VCS_SEQ_COMPLETEi 0x40
1771 __le16 failure_code
;
1772 #define VFC_CHECKSUM_ERROR 0x1
1773 #define VFC_INVALID_LEN 0x2
1774 #define VFC_ALREADY_IN_PROGRESS 0x8
1776 __le16 reserved_1
[4];
1779 __le32 exchange_address
;
1781 __le32 reserved_2
[6];
1784 #define ACCESS_CHIP_IOCB_TYPE 0x2B
1785 struct access_chip_84xx
{
1787 uint8_t entry_count
;
1788 uint8_t sys_defined
;
1789 uint8_t entry_status
;
1794 #define ACO_DUMP_MEMORY 0x0
1795 #define ACO_LOAD_MEMORY 0x1
1796 #define ACO_CHANGE_CONFIG_PARAM 0x2
1797 #define ACO_REQUEST_INFO 0x3
1802 __le16 reserved2
[3];
1808 __le32 reserved3
[3];
1809 __le32 total_byte_cnt
;
1815 struct access_chip_rsp_84xx
{
1817 uint8_t entry_count
;
1818 uint8_t sys_defined
;
1819 uint8_t entry_status
;
1824 __le16 failure_code
;
1825 __le32 residual_count
;
1827 __le32 reserved
[12];
1830 /* 81XX Support **************************************************************/
1832 #define MBA_DCBX_START 0x8016
1833 #define MBA_DCBX_COMPLETE 0x8030
1834 #define MBA_FCF_CONF_ERR 0x8031
1835 #define MBA_DCBX_PARAM_UPDATE 0x8032
1836 #define MBA_IDC_COMPLETE 0x8100
1837 #define MBA_IDC_NOTIFY 0x8101
1838 #define MBA_IDC_TIME_EXT 0x8102
1840 #define MBC_IDC_ACK 0x101
1841 #define MBC_RESTART_MPI_FW 0x3d
1842 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
1843 #define MBC_GET_XGMAC_STATS 0x7a
1844 #define MBC_GET_DCBX_PARAMS 0x51
1847 * ISP83xx mailbox commands
1849 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
1850 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */
1851 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */
1852 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */
1854 /* Flash access control option field bit definitions */
1855 #define FAC_OPT_FORCE_SEMAPHORE BIT_15
1856 #define FAC_OPT_REQUESTOR_ID BIT_14
1857 #define FAC_OPT_CMD_SUBCODE 0xff
1859 /* Flash access control command subcodes */
1860 #define FAC_OPT_CMD_WRITE_PROTECT 0x00
1861 #define FAC_OPT_CMD_WRITE_ENABLE 0x01
1862 #define FAC_OPT_CMD_ERASE_SECTOR 0x02
1863 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
1864 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
1865 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
1867 /* enhanced features bit definitions */
1868 #define NEF_LR_DIST_ENABLE BIT_0
1870 /* LR Distance bit positions */
1871 #define LR_DIST_NV_POS 2
1872 #define LR_DIST_NV_MASK 0xf
1873 #define LR_DIST_FW_POS 12
1875 /* FAC semaphore defines */
1876 #define FAC_SEMAPHORE_UNLOCK 0
1877 #define FAC_SEMAPHORE_LOCK 1
1882 __le16 nvram_version
;
1885 /* Firmware Initialization Control Block. */
1888 __le16 frame_payload_size
;
1889 __le16 execution_throttle
;
1890 __le16 exchange_count
;
1893 uint8_t port_name
[WWN_SIZE
];
1894 uint8_t node_name
[WWN_SIZE
];
1896 __le16 login_retry_count
;
1898 __le16 interrupt_delay_timer
;
1899 __le16 login_timeout
;
1901 __le32 firmware_options_1
;
1902 __le32 firmware_options_2
;
1903 __le32 firmware_options_3
;
1905 __le16 reserved_4
[4];
1908 uint8_t enode_mac
[6];
1909 __le16 reserved_5
[5];
1912 __le16 reserved_6
[24];
1916 uint8_t prio_fcf_matching_flags
;
1917 uint8_t reserved_6_1
[3];
1918 __le16 pri_fcf_vlan_id
;
1919 uint8_t pri_fcf_fabric_name
[8];
1920 __le16 reserved_6_2
[7];
1921 uint8_t spma_mac_addr
[6];
1922 __le16 reserved_6_3
[14];
1925 uint8_t min_supported_speed
;
1926 uint8_t reserved_7_0
;
1927 __le16 reserved_7
[31];
1930 * BIT 0 = Enable spinup delay
1931 * BIT 1 = Disable BIOS
1932 * BIT 2 = Enable Memory Map BIOS
1933 * BIT 3 = Enable Selectable Boot
1934 * BIT 4 = Disable RISC code load
1935 * BIT 5 = Disable Serdes
1936 * BIT 6 = Opt boot mode
1937 * BIT 7 = Interrupt enable
1939 * BIT 8 = EV Control enable
1940 * BIT 9 = Enable lip reset
1941 * BIT 10 = Enable lip full login
1942 * BIT 11 = Enable target reset
1943 * BIT 12 = Stop firmware
1944 * BIT 13 = Enable nodename option
1945 * BIT 14 = Default WWPN valid
1946 * BIT 15 = Enable alternate WWN
1948 * BIT 16 = CLP LUN string
1949 * BIT 17 = CLP Target string
1950 * BIT 18 = CLP BIOS enable string
1951 * BIT 19 = CLP Serdes string
1952 * BIT 20 = CLP WWPN string
1953 * BIT 21 = CLP WWNN string
1956 * BIT 24 = Keep WWPN
1957 * BIT 25 = Temp WWPN
1962 uint8_t alternate_port_name
[WWN_SIZE
];
1963 uint8_t alternate_node_name
[WWN_SIZE
];
1965 uint8_t boot_port_name
[WWN_SIZE
];
1966 __le16 boot_lun_number
;
1969 uint8_t alt1_boot_port_name
[WWN_SIZE
];
1970 __le16 alt1_boot_lun_number
;
1973 uint8_t alt2_boot_port_name
[WWN_SIZE
];
1974 __le16 alt2_boot_lun_number
;
1977 uint8_t alt3_boot_port_name
[WWN_SIZE
];
1978 __le16 alt3_boot_lun_number
;
1982 * BIT 0 = Selective Login
1983 * BIT 1 = Alt-Boot Enable
1985 * BIT 3 = Boot Order List
1987 * BIT 5 = Selective LUN
1991 __le32 efi_parameters
;
1993 uint8_t reset_delay
;
1994 uint8_t reserved_12
;
1997 __le16 boot_id_number
;
2000 __le16 max_luns_per_target
;
2003 __le16 port_down_retry_count
;
2004 __le16 link_down_timeout
;
2006 /* FCode parameters. */
2007 __le16 fcode_parameter
;
2009 __le16 reserved_16
[3];
2012 uint8_t reserved_17
[4];
2013 __le16 reserved_18
[5];
2014 uint8_t reserved_19
[2];
2015 __le16 reserved_20
[8];
2018 uint8_t reserved_21
[16];
2019 __le16 reserved_22
[3];
2021 /* Offset 406 (0x196) Enhanced Features
2022 * BIT 0 = Extended BB credits for LR
2023 * BIT 1 = Virtual Fabric Enable
2024 * BIT 2-5 = Distance Support if BIT 0 is on
2025 * BIT 6 = Prefer FCP
2026 * BIT 7 = SCM Disabled if BIT is set (1)
2029 uint16_t enhanced_features
;
2031 uint16_t reserved_24
[4];
2034 __le16 reserved_25
[32];
2037 uint8_t model_name
[16];
2040 __le16 feature_mask_l
;
2041 __le16 feature_mask_h
;
2042 __le16 reserved_26
[2];
2044 __le16 subsystem_vendor_id
;
2045 __le16 subsystem_device_id
;
2051 * ISP Initialization Control Block.
2052 * Little endian except where noted.
2054 #define ICB_VERSION 1
2055 struct init_cb_81xx
{
2059 __le16 frame_payload_size
;
2060 __le16 execution_throttle
;
2061 __le16 exchange_count
;
2065 uint8_t port_name
[WWN_SIZE
]; /* Big endian. */
2066 uint8_t node_name
[WWN_SIZE
]; /* Big endian. */
2068 __le16 response_q_inpointer
;
2069 __le16 request_q_outpointer
;
2071 __le16 login_retry_count
;
2073 __le16 prio_request_q_outpointer
;
2075 __le16 response_q_length
;
2076 __le16 request_q_length
;
2080 __le16 prio_request_q_length
;
2082 __le64 request_q_address __packed
;
2083 __le64 response_q_address __packed
;
2084 __le64 prio_request_q_address __packed
;
2086 uint8_t reserved_4
[8];
2088 __le16 atio_q_inpointer
;
2089 __le16 atio_q_length
;
2090 __le64 atio_q_address __packed
;
2092 __le16 interrupt_delay_timer
; /* 100us increments. */
2093 __le16 login_timeout
;
2096 * BIT 0-3 = Reserved
2097 * BIT 4 = Enable Target Mode
2098 * BIT 5 = Disable Initiator Mode
2102 * BIT 8-13 = Reserved
2103 * BIT 14 = Node Name Option
2104 * BIT 15-31 = Reserved
2106 __le32 firmware_options_1
;
2109 * BIT 0 = Operation Mode bit 0
2110 * BIT 1 = Operation Mode bit 1
2111 * BIT 2 = Operation Mode bit 2
2112 * BIT 3 = Operation Mode bit 3
2113 * BIT 4-7 = Reserved
2115 * BIT 8 = Enable Class 2
2116 * BIT 9 = Enable ACK0
2118 * BIT 11 = Enable FC-SP Security
2119 * BIT 12 = FC Tape Enable
2121 * BIT 14 = Enable Target PRLI Control
2122 * BIT 15-31 = Reserved
2124 __le32 firmware_options_2
;
2127 * BIT 0-3 = Reserved
2128 * BIT 4 = FCP RSP Payload bit 0
2129 * BIT 5 = FCP RSP Payload bit 1
2130 * BIT 6 = Enable Receive Out-of-Order data frame handling
2134 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
2135 * BIT 10-16 = Reserved
2136 * BIT 17 = Enable multiple FCFs
2137 * BIT 18-20 = MAC addressing mode
2138 * BIT 21-25 = Ethernet data rate
2139 * BIT 26 = Enable ethernet header rx IOCB for ATIO q
2140 * BIT 27 = Enable ethernet header rx IOCB for response q
2141 * BIT 28 = SPMA selection bit 0
2142 * BIT 28 = SPMA selection bit 1
2143 * BIT 30-31 = Reserved
2145 __le32 firmware_options_3
;
2147 uint8_t reserved_5
[8];
2149 uint8_t enode_mac
[6];
2151 uint8_t reserved_6
[10];
2154 struct mid_init_cb_81xx
{
2155 struct init_cb_81xx init_cb
;
2160 struct mid_conf_entry_24xx entries
[MAX_MULTI_ID_FABRIC
];
2163 struct ex_init_cb_81xx
{
2164 uint16_t ex_version
;
2165 uint8_t prio_fcf_matching_flags
;
2166 uint8_t reserved_1
[3];
2167 uint16_t pri_fcf_vlan_id
;
2168 uint8_t pri_fcf_fabric_name
[8];
2169 uint16_t reserved_2
[7];
2170 uint8_t spma_mac_addr
[6];
2171 uint16_t reserved_3
[14];
2174 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
2175 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
2176 #define FARX_ACCESS_FLASH_CONF_28XX 0x7FFD0000
2177 #define FARX_ACCESS_FLASH_DATA_28XX 0x7F7D0000
2179 /* FCP priority config defines *************************************/
2181 #define QLFC_FCP_PRIO_DISABLE 0x0
2182 #define QLFC_FCP_PRIO_ENABLE 0x1
2183 #define QLFC_FCP_PRIO_GET_CONFIG 0x2
2184 #define QLFC_FCP_PRIO_SET_CONFIG 0x3
2186 struct qla_fcp_prio_entry
{
2187 uint16_t flags
; /* Describes parameter(s) in FCP */
2188 /* priority entry that are valid */
2189 #define FCP_PRIO_ENTRY_VALID 0x1
2190 #define FCP_PRIO_ENTRY_TAG_VALID 0x2
2191 #define FCP_PRIO_ENTRY_SPID_VALID 0x4
2192 #define FCP_PRIO_ENTRY_DPID_VALID 0x8
2193 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10
2194 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20
2195 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40
2196 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80
2197 uint8_t tag
; /* Priority value */
2198 uint8_t reserved
; /* Reserved for future use */
2199 uint32_t src_pid
; /* Src port id. high order byte */
2200 /* unused; -1 (wild card) */
2201 uint32_t dst_pid
; /* Src port id. high order byte */
2202 /* unused; -1 (wild card) */
2203 uint16_t lun_beg
; /* 1st lun num of lun range. */
2204 /* -1 (wild card) */
2205 uint16_t lun_end
; /* 2nd lun num of lun range. */
2206 /* -1 (wild card) */
2207 uint8_t src_wwpn
[8]; /* Source WWPN: -1 (wild card) */
2208 uint8_t dst_wwpn
[8]; /* Destination WWPN: -1 (wild card) */
2211 struct qla_fcp_prio_cfg
{
2212 uint8_t signature
[4]; /* "HQOS" signature of config data */
2213 uint16_t version
; /* 1: Initial version */
2214 uint16_t length
; /* config data size in num bytes */
2215 uint16_t checksum
; /* config data bytes checksum */
2216 uint16_t num_entries
; /* Number of entries */
2217 uint16_t size_of_entry
; /* Size of each entry in num bytes */
2218 uint8_t attributes
; /* enable/disable, persistence */
2219 #define FCP_PRIO_ATTR_DISABLE 0x0
2220 #define FCP_PRIO_ATTR_ENABLE 0x1
2221 #define FCP_PRIO_ATTR_PERSIST 0x2
2222 uint8_t reserved
; /* Reserved for future use */
2223 #define FCP_PRIO_CFG_HDR_SIZE offsetof(struct qla_fcp_prio_cfg, entry)
2224 struct qla_fcp_prio_entry entry
[1023]; /* fcp priority entries */
2225 uint8_t reserved2
[16];
2228 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/
2230 /* 25XX Support ****************************************************/
2231 #define FA_FCP_PRIO0_ADDR_25 0x3C000
2232 #define FA_FCP_PRIO1_ADDR_25 0x3E000
2234 /* 81XX Flash locations -- occupies second 2MB region. */
2235 #define FA_BOOT_CODE_ADDR_81 0x80000
2236 #define FA_RISC_CODE_ADDR_81 0xA0000
2237 #define FA_FW_AREA_ADDR_81 0xC0000
2238 #define FA_VPD_NVRAM_ADDR_81 0xD0000
2239 #define FA_VPD0_ADDR_81 0xD0000
2240 #define FA_VPD1_ADDR_81 0xD0400
2241 #define FA_NVRAM0_ADDR_81 0xD0080
2242 #define FA_NVRAM1_ADDR_81 0xD0180
2243 #define FA_FEATURE_ADDR_81 0xD4000
2244 #define FA_FLASH_DESCR_ADDR_81 0xD8000
2245 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2246 #define FA_HW_EVENT0_ADDR_81 0xDC000
2247 #define FA_HW_EVENT1_ADDR_81 0xDC400
2248 #define FA_NPIV_CONF0_ADDR_81 0xD1000
2249 #define FA_NPIV_CONF1_ADDR_81 0xD2000
2251 /* 83XX Flash locations -- occupies second 8MB region. */
2252 #define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
2253 #define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
2255 #define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196