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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / qla2xxx / qla_mbx.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include "qla_target.h"
9
10 #include <linux/delay.h>
11 #include <linux/gfp.h>
12
13 static struct rom_cmd {
14 uint16_t cmd;
15 } rom_cmds[] = {
16 { MBC_LOAD_RAM },
17 { MBC_EXECUTE_FIRMWARE },
18 { MBC_READ_RAM_WORD },
19 { MBC_MAILBOX_REGISTER_TEST },
20 { MBC_VERIFY_CHECKSUM },
21 { MBC_GET_FIRMWARE_VERSION },
22 { MBC_LOAD_RISC_RAM },
23 { MBC_DUMP_RISC_RAM },
24 { MBC_LOAD_RISC_RAM_EXTENDED },
25 { MBC_DUMP_RISC_RAM_EXTENDED },
26 { MBC_WRITE_RAM_WORD_EXTENDED },
27 { MBC_READ_RAM_EXTENDED },
28 { MBC_GET_RESOURCE_COUNTS },
29 { MBC_SET_FIRMWARE_OPTION },
30 { MBC_MID_INITIALIZE_FIRMWARE },
31 { MBC_GET_FIRMWARE_STATE },
32 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
33 { MBC_GET_RETRY_COUNT },
34 { MBC_TRACE_CONTROL },
35 };
36
37 static int is_rom_cmd(uint16_t cmd)
38 {
39 int i;
40 struct rom_cmd *wc;
41
42 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
43 wc = rom_cmds + i;
44 if (wc->cmd == cmd)
45 return 1;
46 }
47
48 return 0;
49 }
50
51 /*
52 * qla2x00_mailbox_command
53 * Issue mailbox command and waits for completion.
54 *
55 * Input:
56 * ha = adapter block pointer.
57 * mcp = driver internal mbx struct pointer.
58 *
59 * Output:
60 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
61 *
62 * Returns:
63 * 0 : QLA_SUCCESS = cmd performed success
64 * 1 : QLA_FUNCTION_FAILED (error encountered)
65 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
66 *
67 * Context:
68 * Kernel context.
69 */
70 static int
71 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
72 {
73 int rval, i;
74 unsigned long flags = 0;
75 device_reg_t *reg;
76 uint8_t abort_active;
77 uint8_t io_lock_on;
78 uint16_t command = 0;
79 uint16_t *iptr;
80 uint16_t __iomem *optr;
81 uint32_t cnt;
82 uint32_t mboxes;
83 uint16_t __iomem *mbx_reg;
84 unsigned long wait_time;
85 struct qla_hw_data *ha = vha->hw;
86 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
87
88
89 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
90
91 if (ha->pdev->error_state > pci_channel_io_frozen) {
92 ql_log(ql_log_warn, vha, 0x1001,
93 "error_state is greater than pci_channel_io_frozen, "
94 "exiting.\n");
95 return QLA_FUNCTION_TIMEOUT;
96 }
97
98 if (vha->device_flags & DFLG_DEV_FAILED) {
99 ql_log(ql_log_warn, vha, 0x1002,
100 "Device in failed state, exiting.\n");
101 return QLA_FUNCTION_TIMEOUT;
102 }
103
104 /* if PCI error, then avoid mbx processing.*/
105 if (test_bit(PCI_ERR, &base_vha->dpc_flags)) {
106 ql_log(ql_log_warn, vha, 0x1191,
107 "PCI error, exiting.\n");
108 return QLA_FUNCTION_TIMEOUT;
109 }
110
111 reg = ha->iobase;
112 io_lock_on = base_vha->flags.init_done;
113
114 rval = QLA_SUCCESS;
115 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
116
117
118 if (ha->flags.pci_channel_io_perm_failure) {
119 ql_log(ql_log_warn, vha, 0x1003,
120 "Perm failure on EEH timeout MBX, exiting.\n");
121 return QLA_FUNCTION_TIMEOUT;
122 }
123
124 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
125 /* Setting Link-Down error */
126 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
127 ql_log(ql_log_warn, vha, 0x1004,
128 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
129 return QLA_FUNCTION_TIMEOUT;
130 }
131
132 /* check if ISP abort is active and return cmd with timeout */
133 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
134 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
135 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
136 !is_rom_cmd(mcp->mb[0])) {
137 ql_log(ql_log_info, vha, 0x1005,
138 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
139 mcp->mb[0]);
140 return QLA_FUNCTION_TIMEOUT;
141 }
142
143 /*
144 * Wait for active mailbox commands to finish by waiting at most tov
145 * seconds. This is to serialize actual issuing of mailbox cmds during
146 * non ISP abort time.
147 */
148 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
149 /* Timeout occurred. Return error. */
150 ql_log(ql_log_warn, vha, 0x1005,
151 "Cmd access timeout, cmd=0x%x, Exiting.\n",
152 mcp->mb[0]);
153 return QLA_FUNCTION_TIMEOUT;
154 }
155
156 ha->flags.mbox_busy = 1;
157 /* Save mailbox command for debug */
158 ha->mcp = mcp;
159
160 ql_dbg(ql_dbg_mbx, vha, 0x1006,
161 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
162
163 spin_lock_irqsave(&ha->hardware_lock, flags);
164
165 /* Load mailbox registers. */
166 if (IS_P3P_TYPE(ha))
167 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
168 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
169 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
170 else
171 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
172
173 iptr = mcp->mb;
174 command = mcp->mb[0];
175 mboxes = mcp->out_mb;
176
177 ql_dbg(ql_dbg_mbx, vha, 0x1111,
178 "Mailbox registers (OUT):\n");
179 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
180 if (IS_QLA2200(ha) && cnt == 8)
181 optr =
182 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
183 if (mboxes & BIT_0) {
184 ql_dbg(ql_dbg_mbx, vha, 0x1112,
185 "mbox[%d]<-0x%04x\n", cnt, *iptr);
186 WRT_REG_WORD(optr, *iptr);
187 }
188
189 mboxes >>= 1;
190 optr++;
191 iptr++;
192 }
193
194 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
195 "I/O Address = %p.\n", optr);
196
197 /* Issue set host interrupt command to send cmd out. */
198 ha->flags.mbox_int = 0;
199 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
200
201 /* Unlock mbx registers and wait for interrupt */
202 ql_dbg(ql_dbg_mbx, vha, 0x100f,
203 "Going to unlock irq & waiting for interrupts. "
204 "jiffies=%lx.\n", jiffies);
205
206 /* Wait for mbx cmd completion until timeout */
207
208 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
209 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
210
211 if (IS_P3P_TYPE(ha)) {
212 if (RD_REG_DWORD(&reg->isp82.hint) &
213 HINT_MBX_INT_PENDING) {
214 spin_unlock_irqrestore(&ha->hardware_lock,
215 flags);
216 ha->flags.mbox_busy = 0;
217 ql_dbg(ql_dbg_mbx, vha, 0x1010,
218 "Pending mailbox timeout, exiting.\n");
219 rval = QLA_FUNCTION_TIMEOUT;
220 goto premature_exit;
221 }
222 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
223 } else if (IS_FWI2_CAPABLE(ha))
224 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
225 else
226 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
227 spin_unlock_irqrestore(&ha->hardware_lock, flags);
228
229 wait_time = jiffies;
230 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
231 mcp->tov * HZ)) {
232 ql_dbg(ql_dbg_mbx, vha, 0x117a,
233 "cmd=%x Timeout.\n", command);
234 spin_lock_irqsave(&ha->hardware_lock, flags);
235 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
236 spin_unlock_irqrestore(&ha->hardware_lock, flags);
237 }
238 if (time_after(jiffies, wait_time + 5 * HZ))
239 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
240 command, jiffies_to_msecs(jiffies - wait_time));
241 } else {
242 ql_dbg(ql_dbg_mbx, vha, 0x1011,
243 "Cmd=%x Polling Mode.\n", command);
244
245 if (IS_P3P_TYPE(ha)) {
246 if (RD_REG_DWORD(&reg->isp82.hint) &
247 HINT_MBX_INT_PENDING) {
248 spin_unlock_irqrestore(&ha->hardware_lock,
249 flags);
250 ha->flags.mbox_busy = 0;
251 ql_dbg(ql_dbg_mbx, vha, 0x1012,
252 "Pending mailbox timeout, exiting.\n");
253 rval = QLA_FUNCTION_TIMEOUT;
254 goto premature_exit;
255 }
256 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
257 } else if (IS_FWI2_CAPABLE(ha))
258 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
259 else
260 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
261 spin_unlock_irqrestore(&ha->hardware_lock, flags);
262
263 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
264 while (!ha->flags.mbox_int) {
265 if (time_after(jiffies, wait_time))
266 break;
267
268 /* Check for pending interrupts. */
269 qla2x00_poll(ha->rsp_q_map[0]);
270
271 if (!ha->flags.mbox_int &&
272 !(IS_QLA2200(ha) &&
273 command == MBC_LOAD_RISC_RAM_EXTENDED))
274 msleep(10);
275 } /* while */
276 ql_dbg(ql_dbg_mbx, vha, 0x1013,
277 "Waited %d sec.\n",
278 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
279 }
280
281 /* Check whether we timed out */
282 if (ha->flags.mbox_int) {
283 uint16_t *iptr2;
284
285 ql_dbg(ql_dbg_mbx, vha, 0x1014,
286 "Cmd=%x completed.\n", command);
287
288 /* Got interrupt. Clear the flag. */
289 ha->flags.mbox_int = 0;
290 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
291
292 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
293 ha->flags.mbox_busy = 0;
294 /* Setting Link-Down error */
295 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
296 ha->mcp = NULL;
297 rval = QLA_FUNCTION_FAILED;
298 ql_log(ql_log_warn, vha, 0x1015,
299 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
300 goto premature_exit;
301 }
302
303 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
304 rval = QLA_FUNCTION_FAILED;
305
306 /* Load return mailbox registers. */
307 iptr2 = mcp->mb;
308 iptr = (uint16_t *)&ha->mailbox_out[0];
309 mboxes = mcp->in_mb;
310
311 ql_dbg(ql_dbg_mbx, vha, 0x1113,
312 "Mailbox registers (IN):\n");
313 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
314 if (mboxes & BIT_0) {
315 *iptr2 = *iptr;
316 ql_dbg(ql_dbg_mbx, vha, 0x1114,
317 "mbox[%d]->0x%04x\n", cnt, *iptr2);
318 }
319
320 mboxes >>= 1;
321 iptr2++;
322 iptr++;
323 }
324 } else {
325
326 uint16_t mb[8];
327 uint32_t ictrl, host_status, hccr;
328 uint16_t w;
329
330 if (IS_FWI2_CAPABLE(ha)) {
331 mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
332 mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
333 mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
334 mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
335 mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
336 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
337 host_status = RD_REG_DWORD(&reg->isp24.host_status);
338 hccr = RD_REG_DWORD(&reg->isp24.hccr);
339
340 ql_log(ql_log_warn, vha, 0x1119,
341 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
342 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
343 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
344 mb[7], host_status, hccr);
345
346 } else {
347 mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
348 ictrl = RD_REG_WORD(&reg->isp.ictrl);
349 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
350 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
351 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
352 }
353 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
354
355 /* Capture FW dump only, if PCI device active */
356 if (!pci_channel_offline(vha->hw->pdev)) {
357 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
358 if (w == 0xffff || ictrl == 0xffffffff) {
359 /* This is special case if there is unload
360 * of driver happening and if PCI device go
361 * into bad state due to PCI error condition
362 * then only PCI ERR flag would be set.
363 * we will do premature exit for above case.
364 */
365 if (test_bit(UNLOADING, &base_vha->dpc_flags))
366 set_bit(PCI_ERR, &base_vha->dpc_flags);
367 ha->flags.mbox_busy = 0;
368 rval = QLA_FUNCTION_TIMEOUT;
369 goto premature_exit;
370 }
371
372 /* Attempt to capture firmware dump for further
373 * anallysis of the current formware state. we do not
374 * need to do this if we are intentionally generating
375 * a dump
376 */
377 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
378 ha->isp_ops->fw_dump(vha, 0);
379 rval = QLA_FUNCTION_TIMEOUT;
380 }
381 }
382
383 ha->flags.mbox_busy = 0;
384
385 /* Clean up */
386 ha->mcp = NULL;
387
388 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
389 ql_dbg(ql_dbg_mbx, vha, 0x101a,
390 "Checking for additional resp interrupt.\n");
391
392 /* polling mode for non isp_abort commands. */
393 qla2x00_poll(ha->rsp_q_map[0]);
394 }
395
396 if (rval == QLA_FUNCTION_TIMEOUT &&
397 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
398 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
399 ha->flags.eeh_busy) {
400 /* not in dpc. schedule it for dpc to take over. */
401 ql_dbg(ql_dbg_mbx, vha, 0x101b,
402 "Timeout, schedule isp_abort_needed.\n");
403
404 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
405 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
406 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
407 if (IS_QLA82XX(ha)) {
408 ql_dbg(ql_dbg_mbx, vha, 0x112a,
409 "disabling pause transmit on port "
410 "0 & 1.\n");
411 qla82xx_wr_32(ha,
412 QLA82XX_CRB_NIU + 0x98,
413 CRB_NIU_XG_PAUSE_CTL_P0|
414 CRB_NIU_XG_PAUSE_CTL_P1);
415 }
416 ql_log(ql_log_info, base_vha, 0x101c,
417 "Mailbox cmd timeout occurred, cmd=0x%x, "
418 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
419 "abort.\n", command, mcp->mb[0],
420 ha->flags.eeh_busy);
421 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
422 qla2xxx_wake_dpc(vha);
423 }
424 } else if (!abort_active) {
425 /* call abort directly since we are in the DPC thread */
426 ql_dbg(ql_dbg_mbx, vha, 0x101d,
427 "Timeout, calling abort_isp.\n");
428
429 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
430 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
431 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
432 if (IS_QLA82XX(ha)) {
433 ql_dbg(ql_dbg_mbx, vha, 0x112b,
434 "disabling pause transmit on port "
435 "0 & 1.\n");
436 qla82xx_wr_32(ha,
437 QLA82XX_CRB_NIU + 0x98,
438 CRB_NIU_XG_PAUSE_CTL_P0|
439 CRB_NIU_XG_PAUSE_CTL_P1);
440 }
441 ql_log(ql_log_info, base_vha, 0x101e,
442 "Mailbox cmd timeout occurred, cmd=0x%x, "
443 "mb[0]=0x%x. Scheduling ISP abort ",
444 command, mcp->mb[0]);
445 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
446 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
447 /* Allow next mbx cmd to come in. */
448 complete(&ha->mbx_cmd_comp);
449 if (ha->isp_ops->abort_isp(vha)) {
450 /* Failed. retry later. */
451 set_bit(ISP_ABORT_NEEDED,
452 &vha->dpc_flags);
453 }
454 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
455 ql_dbg(ql_dbg_mbx, vha, 0x101f,
456 "Finished abort_isp.\n");
457 goto mbx_done;
458 }
459 }
460 }
461
462 premature_exit:
463 /* Allow next mbx cmd to come in. */
464 complete(&ha->mbx_cmd_comp);
465
466 mbx_done:
467 if (rval) {
468 ql_dbg(ql_dbg_disc, base_vha, 0x1020,
469 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
470 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
471
472 ql_dbg(ql_dbg_mbx, vha, 0x1198,
473 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n",
474 RD_REG_DWORD(&reg->isp24.host_status),
475 ha->fw_dump_cap_flags,
476 RD_REG_DWORD(&reg->isp24.ictrl),
477 RD_REG_DWORD(&reg->isp24.istatus));
478
479 mbx_reg = &reg->isp24.mailbox0;
480 for (i = 0; i < 6; i++)
481 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1199,
482 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
483 } else {
484 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
485 }
486
487 return rval;
488 }
489
490 int
491 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
492 uint32_t risc_code_size)
493 {
494 int rval;
495 struct qla_hw_data *ha = vha->hw;
496 mbx_cmd_t mc;
497 mbx_cmd_t *mcp = &mc;
498
499 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
500 "Entered %s.\n", __func__);
501
502 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
503 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
504 mcp->mb[8] = MSW(risc_addr);
505 mcp->out_mb = MBX_8|MBX_0;
506 } else {
507 mcp->mb[0] = MBC_LOAD_RISC_RAM;
508 mcp->out_mb = MBX_0;
509 }
510 mcp->mb[1] = LSW(risc_addr);
511 mcp->mb[2] = MSW(req_dma);
512 mcp->mb[3] = LSW(req_dma);
513 mcp->mb[6] = MSW(MSD(req_dma));
514 mcp->mb[7] = LSW(MSD(req_dma));
515 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
516 if (IS_FWI2_CAPABLE(ha)) {
517 mcp->mb[4] = MSW(risc_code_size);
518 mcp->mb[5] = LSW(risc_code_size);
519 mcp->out_mb |= MBX_5|MBX_4;
520 } else {
521 mcp->mb[4] = LSW(risc_code_size);
522 mcp->out_mb |= MBX_4;
523 }
524
525 mcp->in_mb = MBX_0;
526 mcp->tov = MBX_TOV_SECONDS;
527 mcp->flags = 0;
528 rval = qla2x00_mailbox_command(vha, mcp);
529
530 if (rval != QLA_SUCCESS) {
531 ql_dbg(ql_dbg_mbx, vha, 0x1023,
532 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
533 } else {
534 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
535 "Done %s.\n", __func__);
536 }
537
538 return rval;
539 }
540
541 #define EXTENDED_BB_CREDITS BIT_0
542 /*
543 * qla2x00_execute_fw
544 * Start adapter firmware.
545 *
546 * Input:
547 * ha = adapter block pointer.
548 * TARGET_QUEUE_LOCK must be released.
549 * ADAPTER_STATE_LOCK must be released.
550 *
551 * Returns:
552 * qla2x00 local function return status code.
553 *
554 * Context:
555 * Kernel context.
556 */
557 int
558 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
559 {
560 int rval;
561 struct qla_hw_data *ha = vha->hw;
562 mbx_cmd_t mc;
563 mbx_cmd_t *mcp = &mc;
564
565 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
566 "Entered %s.\n", __func__);
567
568 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
569 mcp->out_mb = MBX_0;
570 mcp->in_mb = MBX_0;
571 if (IS_FWI2_CAPABLE(ha)) {
572 mcp->mb[1] = MSW(risc_addr);
573 mcp->mb[2] = LSW(risc_addr);
574 mcp->mb[3] = 0;
575 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
576 IS_QLA27XX(ha)) {
577 struct nvram_81xx *nv = ha->nvram;
578 mcp->mb[4] = (nv->enhanced_features &
579 EXTENDED_BB_CREDITS);
580 } else
581 mcp->mb[4] = 0;
582
583 if (ha->flags.exlogins_enabled)
584 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
585
586 if (ha->flags.exchoffld_enabled)
587 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
588
589 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
590 mcp->in_mb |= MBX_1;
591 } else {
592 mcp->mb[1] = LSW(risc_addr);
593 mcp->out_mb |= MBX_1;
594 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
595 mcp->mb[2] = 0;
596 mcp->out_mb |= MBX_2;
597 }
598 }
599
600 mcp->tov = MBX_TOV_SECONDS;
601 mcp->flags = 0;
602 rval = qla2x00_mailbox_command(vha, mcp);
603
604 if (rval != QLA_SUCCESS) {
605 ql_dbg(ql_dbg_mbx, vha, 0x1026,
606 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
607 } else {
608 if (IS_FWI2_CAPABLE(ha)) {
609 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
610 "Done exchanges=%x.\n", mcp->mb[1]);
611 } else {
612 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
613 "Done %s.\n", __func__);
614 }
615 }
616
617 return rval;
618 }
619
620 /*
621 * qla_get_exlogin_status
622 * Get extended login status
623 * uses the memory offload control/status Mailbox
624 *
625 * Input:
626 * ha: adapter state pointer.
627 * fwopt: firmware options
628 *
629 * Returns:
630 * qla2x00 local function status
631 *
632 * Context:
633 * Kernel context.
634 */
635 #define FETCH_XLOGINS_STAT 0x8
636 int
637 qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
638 uint16_t *ex_logins_cnt)
639 {
640 int rval;
641 mbx_cmd_t mc;
642 mbx_cmd_t *mcp = &mc;
643
644 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
645 "Entered %s\n", __func__);
646
647 memset(mcp->mb, 0 , sizeof(mcp->mb));
648 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
649 mcp->mb[1] = FETCH_XLOGINS_STAT;
650 mcp->out_mb = MBX_1|MBX_0;
651 mcp->in_mb = MBX_10|MBX_4|MBX_0;
652 mcp->tov = MBX_TOV_SECONDS;
653 mcp->flags = 0;
654
655 rval = qla2x00_mailbox_command(vha, mcp);
656 if (rval != QLA_SUCCESS) {
657 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
658 } else {
659 *buf_sz = mcp->mb[4];
660 *ex_logins_cnt = mcp->mb[10];
661
662 ql_log(ql_log_info, vha, 0x1190,
663 "buffer size 0x%x, exchange login count=%d\n",
664 mcp->mb[4], mcp->mb[10]);
665
666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
667 "Done %s.\n", __func__);
668 }
669
670 return rval;
671 }
672
673 /*
674 * qla_set_exlogin_mem_cfg
675 * set extended login memory configuration
676 * Mbx needs to be issues before init_cb is set
677 *
678 * Input:
679 * ha: adapter state pointer.
680 * buffer: buffer pointer
681 * phys_addr: physical address of buffer
682 * size: size of buffer
683 * TARGET_QUEUE_LOCK must be released
684 * ADAPTER_STATE_LOCK must be release
685 *
686 * Returns:
687 * qla2x00 local funxtion status code.
688 *
689 * Context:
690 * Kernel context.
691 */
692 #define CONFIG_XLOGINS_MEM 0x3
693 int
694 qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
695 {
696 int rval;
697 mbx_cmd_t mc;
698 mbx_cmd_t *mcp = &mc;
699 struct qla_hw_data *ha = vha->hw;
700
701 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
702 "Entered %s.\n", __func__);
703
704 memset(mcp->mb, 0 , sizeof(mcp->mb));
705 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
706 mcp->mb[1] = CONFIG_XLOGINS_MEM;
707 mcp->mb[2] = MSW(phys_addr);
708 mcp->mb[3] = LSW(phys_addr);
709 mcp->mb[6] = MSW(MSD(phys_addr));
710 mcp->mb[7] = LSW(MSD(phys_addr));
711 mcp->mb[8] = MSW(ha->exlogin_size);
712 mcp->mb[9] = LSW(ha->exlogin_size);
713 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
714 mcp->in_mb = MBX_11|MBX_0;
715 mcp->tov = MBX_TOV_SECONDS;
716 mcp->flags = 0;
717 rval = qla2x00_mailbox_command(vha, mcp);
718 if (rval != QLA_SUCCESS) {
719 /*EMPTY*/
720 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
721 } else {
722 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
723 "Done %s.\n", __func__);
724 }
725
726 return rval;
727 }
728
729 /*
730 * qla_get_exchoffld_status
731 * Get exchange offload status
732 * uses the memory offload control/status Mailbox
733 *
734 * Input:
735 * ha: adapter state pointer.
736 * fwopt: firmware options
737 *
738 * Returns:
739 * qla2x00 local function status
740 *
741 * Context:
742 * Kernel context.
743 */
744 #define FETCH_XCHOFFLD_STAT 0x2
745 int
746 qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
747 uint16_t *ex_logins_cnt)
748 {
749 int rval;
750 mbx_cmd_t mc;
751 mbx_cmd_t *mcp = &mc;
752
753 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
754 "Entered %s\n", __func__);
755
756 memset(mcp->mb, 0 , sizeof(mcp->mb));
757 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
758 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
759 mcp->out_mb = MBX_1|MBX_0;
760 mcp->in_mb = MBX_10|MBX_4|MBX_0;
761 mcp->tov = MBX_TOV_SECONDS;
762 mcp->flags = 0;
763
764 rval = qla2x00_mailbox_command(vha, mcp);
765 if (rval != QLA_SUCCESS) {
766 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
767 } else {
768 *buf_sz = mcp->mb[4];
769 *ex_logins_cnt = mcp->mb[10];
770
771 ql_log(ql_log_info, vha, 0x118e,
772 "buffer size 0x%x, exchange offload count=%d\n",
773 mcp->mb[4], mcp->mb[10]);
774
775 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
776 "Done %s.\n", __func__);
777 }
778
779 return rval;
780 }
781
782 /*
783 * qla_set_exchoffld_mem_cfg
784 * Set exchange offload memory configuration
785 * Mbx needs to be issues before init_cb is set
786 *
787 * Input:
788 * ha: adapter state pointer.
789 * buffer: buffer pointer
790 * phys_addr: physical address of buffer
791 * size: size of buffer
792 * TARGET_QUEUE_LOCK must be released
793 * ADAPTER_STATE_LOCK must be release
794 *
795 * Returns:
796 * qla2x00 local funxtion status code.
797 *
798 * Context:
799 * Kernel context.
800 */
801 #define CONFIG_XCHOFFLD_MEM 0x3
802 int
803 qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
804 {
805 int rval;
806 mbx_cmd_t mc;
807 mbx_cmd_t *mcp = &mc;
808 struct qla_hw_data *ha = vha->hw;
809
810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
811 "Entered %s.\n", __func__);
812
813 memset(mcp->mb, 0 , sizeof(mcp->mb));
814 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
815 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
816 mcp->mb[2] = MSW(phys_addr);
817 mcp->mb[3] = LSW(phys_addr);
818 mcp->mb[6] = MSW(MSD(phys_addr));
819 mcp->mb[7] = LSW(MSD(phys_addr));
820 mcp->mb[8] = MSW(ha->exlogin_size);
821 mcp->mb[9] = LSW(ha->exlogin_size);
822 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
823 mcp->in_mb = MBX_11|MBX_0;
824 mcp->tov = MBX_TOV_SECONDS;
825 mcp->flags = 0;
826 rval = qla2x00_mailbox_command(vha, mcp);
827 if (rval != QLA_SUCCESS) {
828 /*EMPTY*/
829 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
830 } else {
831 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
832 "Done %s.\n", __func__);
833 }
834
835 return rval;
836 }
837
838 /*
839 * qla2x00_get_fw_version
840 * Get firmware version.
841 *
842 * Input:
843 * ha: adapter state pointer.
844 * major: pointer for major number.
845 * minor: pointer for minor number.
846 * subminor: pointer for subminor number.
847 *
848 * Returns:
849 * qla2x00 local function return status code.
850 *
851 * Context:
852 * Kernel context.
853 */
854 int
855 qla2x00_get_fw_version(scsi_qla_host_t *vha)
856 {
857 int rval;
858 mbx_cmd_t mc;
859 mbx_cmd_t *mcp = &mc;
860 struct qla_hw_data *ha = vha->hw;
861
862 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
863 "Entered %s.\n", __func__);
864
865 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
866 mcp->out_mb = MBX_0;
867 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
868 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
869 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
870 if (IS_FWI2_CAPABLE(ha))
871 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
872 if (IS_QLA27XX(ha))
873 mcp->in_mb |=
874 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
875 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8;
876
877 mcp->flags = 0;
878 mcp->tov = MBX_TOV_SECONDS;
879 rval = qla2x00_mailbox_command(vha, mcp);
880 if (rval != QLA_SUCCESS)
881 goto failed;
882
883 /* Return mailbox data. */
884 ha->fw_major_version = mcp->mb[1];
885 ha->fw_minor_version = mcp->mb[2];
886 ha->fw_subminor_version = mcp->mb[3];
887 ha->fw_attributes = mcp->mb[6];
888 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
889 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
890 else
891 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
892
893 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
894 ha->mpi_version[0] = mcp->mb[10] & 0xff;
895 ha->mpi_version[1] = mcp->mb[11] >> 8;
896 ha->mpi_version[2] = mcp->mb[11] & 0xff;
897 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
898 ha->phy_version[0] = mcp->mb[8] & 0xff;
899 ha->phy_version[1] = mcp->mb[9] >> 8;
900 ha->phy_version[2] = mcp->mb[9] & 0xff;
901 }
902
903 if (IS_FWI2_CAPABLE(ha)) {
904 ha->fw_attributes_h = mcp->mb[15];
905 ha->fw_attributes_ext[0] = mcp->mb[16];
906 ha->fw_attributes_ext[1] = mcp->mb[17];
907 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
908 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
909 __func__, mcp->mb[15], mcp->mb[6]);
910 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
911 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
912 __func__, mcp->mb[17], mcp->mb[16]);
913
914 if (ha->fw_attributes_h & 0x4)
915 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
916 "%s: Firmware supports Extended Login 0x%x\n",
917 __func__, ha->fw_attributes_h);
918
919 if (ha->fw_attributes_h & 0x8)
920 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
921 "%s: Firmware supports Exchange Offload 0x%x\n",
922 __func__, ha->fw_attributes_h);
923 }
924
925 if (IS_QLA27XX(ha)) {
926 ha->mpi_version[0] = mcp->mb[10] & 0xff;
927 ha->mpi_version[1] = mcp->mb[11] >> 8;
928 ha->mpi_version[2] = mcp->mb[11] & 0xff;
929 ha->pep_version[0] = mcp->mb[13] & 0xff;
930 ha->pep_version[1] = mcp->mb[14] >> 8;
931 ha->pep_version[2] = mcp->mb[14] & 0xff;
932 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
933 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
934 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
935 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
936 }
937
938 failed:
939 if (rval != QLA_SUCCESS) {
940 /*EMPTY*/
941 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
942 } else {
943 /*EMPTY*/
944 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
945 "Done %s.\n", __func__);
946 }
947 return rval;
948 }
949
950 /*
951 * qla2x00_get_fw_options
952 * Set firmware options.
953 *
954 * Input:
955 * ha = adapter block pointer.
956 * fwopt = pointer for firmware options.
957 *
958 * Returns:
959 * qla2x00 local function return status code.
960 *
961 * Context:
962 * Kernel context.
963 */
964 int
965 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
966 {
967 int rval;
968 mbx_cmd_t mc;
969 mbx_cmd_t *mcp = &mc;
970
971 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
972 "Entered %s.\n", __func__);
973
974 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
975 mcp->out_mb = MBX_0;
976 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
977 mcp->tov = MBX_TOV_SECONDS;
978 mcp->flags = 0;
979 rval = qla2x00_mailbox_command(vha, mcp);
980
981 if (rval != QLA_SUCCESS) {
982 /*EMPTY*/
983 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
984 } else {
985 fwopts[0] = mcp->mb[0];
986 fwopts[1] = mcp->mb[1];
987 fwopts[2] = mcp->mb[2];
988 fwopts[3] = mcp->mb[3];
989
990 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
991 "Done %s.\n", __func__);
992 }
993
994 return rval;
995 }
996
997
998 /*
999 * qla2x00_set_fw_options
1000 * Set firmware options.
1001 *
1002 * Input:
1003 * ha = adapter block pointer.
1004 * fwopt = pointer for firmware options.
1005 *
1006 * Returns:
1007 * qla2x00 local function return status code.
1008 *
1009 * Context:
1010 * Kernel context.
1011 */
1012 int
1013 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1014 {
1015 int rval;
1016 mbx_cmd_t mc;
1017 mbx_cmd_t *mcp = &mc;
1018
1019 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1020 "Entered %s.\n", __func__);
1021
1022 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1023 mcp->mb[1] = fwopts[1];
1024 mcp->mb[2] = fwopts[2];
1025 mcp->mb[3] = fwopts[3];
1026 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1027 mcp->in_mb = MBX_0;
1028 if (IS_FWI2_CAPABLE(vha->hw)) {
1029 mcp->in_mb |= MBX_1;
1030 } else {
1031 mcp->mb[10] = fwopts[10];
1032 mcp->mb[11] = fwopts[11];
1033 mcp->mb[12] = 0; /* Undocumented, but used */
1034 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1035 }
1036 mcp->tov = MBX_TOV_SECONDS;
1037 mcp->flags = 0;
1038 rval = qla2x00_mailbox_command(vha, mcp);
1039
1040 fwopts[0] = mcp->mb[0];
1041
1042 if (rval != QLA_SUCCESS) {
1043 /*EMPTY*/
1044 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1045 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1046 } else {
1047 /*EMPTY*/
1048 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1049 "Done %s.\n", __func__);
1050 }
1051
1052 return rval;
1053 }
1054
1055 /*
1056 * qla2x00_mbx_reg_test
1057 * Mailbox register wrap test.
1058 *
1059 * Input:
1060 * ha = adapter block pointer.
1061 * TARGET_QUEUE_LOCK must be released.
1062 * ADAPTER_STATE_LOCK must be released.
1063 *
1064 * Returns:
1065 * qla2x00 local function return status code.
1066 *
1067 * Context:
1068 * Kernel context.
1069 */
1070 int
1071 qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1072 {
1073 int rval;
1074 mbx_cmd_t mc;
1075 mbx_cmd_t *mcp = &mc;
1076
1077 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1078 "Entered %s.\n", __func__);
1079
1080 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1081 mcp->mb[1] = 0xAAAA;
1082 mcp->mb[2] = 0x5555;
1083 mcp->mb[3] = 0xAA55;
1084 mcp->mb[4] = 0x55AA;
1085 mcp->mb[5] = 0xA5A5;
1086 mcp->mb[6] = 0x5A5A;
1087 mcp->mb[7] = 0x2525;
1088 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1089 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1090 mcp->tov = MBX_TOV_SECONDS;
1091 mcp->flags = 0;
1092 rval = qla2x00_mailbox_command(vha, mcp);
1093
1094 if (rval == QLA_SUCCESS) {
1095 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1096 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1097 rval = QLA_FUNCTION_FAILED;
1098 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1099 mcp->mb[7] != 0x2525)
1100 rval = QLA_FUNCTION_FAILED;
1101 }
1102
1103 if (rval != QLA_SUCCESS) {
1104 /*EMPTY*/
1105 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1106 } else {
1107 /*EMPTY*/
1108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1109 "Done %s.\n", __func__);
1110 }
1111
1112 return rval;
1113 }
1114
1115 /*
1116 * qla2x00_verify_checksum
1117 * Verify firmware checksum.
1118 *
1119 * Input:
1120 * ha = adapter block pointer.
1121 * TARGET_QUEUE_LOCK must be released.
1122 * ADAPTER_STATE_LOCK must be released.
1123 *
1124 * Returns:
1125 * qla2x00 local function return status code.
1126 *
1127 * Context:
1128 * Kernel context.
1129 */
1130 int
1131 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1132 {
1133 int rval;
1134 mbx_cmd_t mc;
1135 mbx_cmd_t *mcp = &mc;
1136
1137 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1138 "Entered %s.\n", __func__);
1139
1140 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1141 mcp->out_mb = MBX_0;
1142 mcp->in_mb = MBX_0;
1143 if (IS_FWI2_CAPABLE(vha->hw)) {
1144 mcp->mb[1] = MSW(risc_addr);
1145 mcp->mb[2] = LSW(risc_addr);
1146 mcp->out_mb |= MBX_2|MBX_1;
1147 mcp->in_mb |= MBX_2|MBX_1;
1148 } else {
1149 mcp->mb[1] = LSW(risc_addr);
1150 mcp->out_mb |= MBX_1;
1151 mcp->in_mb |= MBX_1;
1152 }
1153
1154 mcp->tov = MBX_TOV_SECONDS;
1155 mcp->flags = 0;
1156 rval = qla2x00_mailbox_command(vha, mcp);
1157
1158 if (rval != QLA_SUCCESS) {
1159 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1160 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1161 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1162 } else {
1163 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1164 "Done %s.\n", __func__);
1165 }
1166
1167 return rval;
1168 }
1169
1170 /*
1171 * qla2x00_issue_iocb
1172 * Issue IOCB using mailbox command
1173 *
1174 * Input:
1175 * ha = adapter state pointer.
1176 * buffer = buffer pointer.
1177 * phys_addr = physical address of buffer.
1178 * size = size of buffer.
1179 * TARGET_QUEUE_LOCK must be released.
1180 * ADAPTER_STATE_LOCK must be released.
1181 *
1182 * Returns:
1183 * qla2x00 local function return status code.
1184 *
1185 * Context:
1186 * Kernel context.
1187 */
1188 int
1189 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
1190 dma_addr_t phys_addr, size_t size, uint32_t tov)
1191 {
1192 int rval;
1193 mbx_cmd_t mc;
1194 mbx_cmd_t *mcp = &mc;
1195
1196 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1197 "Entered %s.\n", __func__);
1198
1199 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1200 mcp->mb[1] = 0;
1201 mcp->mb[2] = MSW(phys_addr);
1202 mcp->mb[3] = LSW(phys_addr);
1203 mcp->mb[6] = MSW(MSD(phys_addr));
1204 mcp->mb[7] = LSW(MSD(phys_addr));
1205 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1206 mcp->in_mb = MBX_2|MBX_0;
1207 mcp->tov = tov;
1208 mcp->flags = 0;
1209 rval = qla2x00_mailbox_command(vha, mcp);
1210
1211 if (rval != QLA_SUCCESS) {
1212 /*EMPTY*/
1213 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1214 } else {
1215 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
1216
1217 /* Mask reserved bits. */
1218 sts_entry->entry_status &=
1219 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
1220 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1221 "Done %s.\n", __func__);
1222 }
1223
1224 return rval;
1225 }
1226
1227 int
1228 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
1229 size_t size)
1230 {
1231 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
1232 MBX_TOV_SECONDS);
1233 }
1234
1235 /*
1236 * qla2x00_abort_command
1237 * Abort command aborts a specified IOCB.
1238 *
1239 * Input:
1240 * ha = adapter block pointer.
1241 * sp = SB structure pointer.
1242 *
1243 * Returns:
1244 * qla2x00 local function return status code.
1245 *
1246 * Context:
1247 * Kernel context.
1248 */
1249 int
1250 qla2x00_abort_command(srb_t *sp)
1251 {
1252 unsigned long flags = 0;
1253 int rval;
1254 uint32_t handle = 0;
1255 mbx_cmd_t mc;
1256 mbx_cmd_t *mcp = &mc;
1257 fc_port_t *fcport = sp->fcport;
1258 scsi_qla_host_t *vha = fcport->vha;
1259 struct qla_hw_data *ha = vha->hw;
1260 struct req_que *req;
1261 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1262
1263 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1264 "Entered %s.\n", __func__);
1265
1266 if (vha->flags.qpairs_available && sp->qpair)
1267 req = sp->qpair->req;
1268 else
1269 req = vha->req;
1270
1271 spin_lock_irqsave(&ha->hardware_lock, flags);
1272 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1273 if (req->outstanding_cmds[handle] == sp)
1274 break;
1275 }
1276 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1277
1278 if (handle == req->num_outstanding_cmds) {
1279 /* command not found */
1280 return QLA_FUNCTION_FAILED;
1281 }
1282
1283 mcp->mb[0] = MBC_ABORT_COMMAND;
1284 if (HAS_EXTENDED_IDS(ha))
1285 mcp->mb[1] = fcport->loop_id;
1286 else
1287 mcp->mb[1] = fcport->loop_id << 8;
1288 mcp->mb[2] = (uint16_t)handle;
1289 mcp->mb[3] = (uint16_t)(handle >> 16);
1290 mcp->mb[6] = (uint16_t)cmd->device->lun;
1291 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1292 mcp->in_mb = MBX_0;
1293 mcp->tov = MBX_TOV_SECONDS;
1294 mcp->flags = 0;
1295 rval = qla2x00_mailbox_command(vha, mcp);
1296
1297 if (rval != QLA_SUCCESS) {
1298 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1299 } else {
1300 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1301 "Done %s.\n", __func__);
1302 }
1303
1304 return rval;
1305 }
1306
1307 int
1308 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1309 {
1310 int rval, rval2;
1311 mbx_cmd_t mc;
1312 mbx_cmd_t *mcp = &mc;
1313 scsi_qla_host_t *vha;
1314 struct req_que *req;
1315 struct rsp_que *rsp;
1316
1317 l = l;
1318 vha = fcport->vha;
1319
1320 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1321 "Entered %s.\n", __func__);
1322
1323 req = vha->hw->req_q_map[0];
1324 rsp = req->rsp;
1325 mcp->mb[0] = MBC_ABORT_TARGET;
1326 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
1327 if (HAS_EXTENDED_IDS(vha->hw)) {
1328 mcp->mb[1] = fcport->loop_id;
1329 mcp->mb[10] = 0;
1330 mcp->out_mb |= MBX_10;
1331 } else {
1332 mcp->mb[1] = fcport->loop_id << 8;
1333 }
1334 mcp->mb[2] = vha->hw->loop_reset_delay;
1335 mcp->mb[9] = vha->vp_idx;
1336
1337 mcp->in_mb = MBX_0;
1338 mcp->tov = MBX_TOV_SECONDS;
1339 mcp->flags = 0;
1340 rval = qla2x00_mailbox_command(vha, mcp);
1341 if (rval != QLA_SUCCESS) {
1342 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1343 "Failed=%x.\n", rval);
1344 }
1345
1346 /* Issue marker IOCB. */
1347 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
1348 MK_SYNC_ID);
1349 if (rval2 != QLA_SUCCESS) {
1350 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1351 "Failed to issue marker IOCB (%x).\n", rval2);
1352 } else {
1353 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1354 "Done %s.\n", __func__);
1355 }
1356
1357 return rval;
1358 }
1359
1360 int
1361 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
1362 {
1363 int rval, rval2;
1364 mbx_cmd_t mc;
1365 mbx_cmd_t *mcp = &mc;
1366 scsi_qla_host_t *vha;
1367 struct req_que *req;
1368 struct rsp_que *rsp;
1369
1370 vha = fcport->vha;
1371
1372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1373 "Entered %s.\n", __func__);
1374
1375 req = vha->hw->req_q_map[0];
1376 rsp = req->rsp;
1377 mcp->mb[0] = MBC_LUN_RESET;
1378 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
1379 if (HAS_EXTENDED_IDS(vha->hw))
1380 mcp->mb[1] = fcport->loop_id;
1381 else
1382 mcp->mb[1] = fcport->loop_id << 8;
1383 mcp->mb[2] = (u32)l;
1384 mcp->mb[3] = 0;
1385 mcp->mb[9] = vha->vp_idx;
1386
1387 mcp->in_mb = MBX_0;
1388 mcp->tov = MBX_TOV_SECONDS;
1389 mcp->flags = 0;
1390 rval = qla2x00_mailbox_command(vha, mcp);
1391 if (rval != QLA_SUCCESS) {
1392 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
1393 }
1394
1395 /* Issue marker IOCB. */
1396 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1397 MK_SYNC_ID_LUN);
1398 if (rval2 != QLA_SUCCESS) {
1399 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1400 "Failed to issue marker IOCB (%x).\n", rval2);
1401 } else {
1402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1403 "Done %s.\n", __func__);
1404 }
1405
1406 return rval;
1407 }
1408
1409 /*
1410 * qla2x00_get_adapter_id
1411 * Get adapter ID and topology.
1412 *
1413 * Input:
1414 * ha = adapter block pointer.
1415 * id = pointer for loop ID.
1416 * al_pa = pointer for AL_PA.
1417 * area = pointer for area.
1418 * domain = pointer for domain.
1419 * top = pointer for topology.
1420 * TARGET_QUEUE_LOCK must be released.
1421 * ADAPTER_STATE_LOCK must be released.
1422 *
1423 * Returns:
1424 * qla2x00 local function return status code.
1425 *
1426 * Context:
1427 * Kernel context.
1428 */
1429 int
1430 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1431 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1432 {
1433 int rval;
1434 mbx_cmd_t mc;
1435 mbx_cmd_t *mcp = &mc;
1436
1437 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1438 "Entered %s.\n", __func__);
1439
1440 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
1441 mcp->mb[9] = vha->vp_idx;
1442 mcp->out_mb = MBX_9|MBX_0;
1443 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1444 if (IS_CNA_CAPABLE(vha->hw))
1445 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
1446 if (IS_FWI2_CAPABLE(vha->hw))
1447 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
1448 if (IS_QLA27XX(vha->hw))
1449 mcp->in_mb |= MBX_15;
1450 mcp->tov = MBX_TOV_SECONDS;
1451 mcp->flags = 0;
1452 rval = qla2x00_mailbox_command(vha, mcp);
1453 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1454 rval = QLA_COMMAND_ERROR;
1455 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1456 rval = QLA_INVALID_COMMAND;
1457
1458 /* Return data. */
1459 *id = mcp->mb[1];
1460 *al_pa = LSB(mcp->mb[2]);
1461 *area = MSB(mcp->mb[2]);
1462 *domain = LSB(mcp->mb[3]);
1463 *top = mcp->mb[6];
1464 *sw_cap = mcp->mb[7];
1465
1466 if (rval != QLA_SUCCESS) {
1467 /*EMPTY*/
1468 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1469 } else {
1470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1471 "Done %s.\n", __func__);
1472
1473 if (IS_CNA_CAPABLE(vha->hw)) {
1474 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1475 vha->fcoe_fcf_idx = mcp->mb[10];
1476 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1477 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1478 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1479 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1480 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1481 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1482 }
1483 /* If FA-WWN supported */
1484 if (IS_FAWWN_CAPABLE(vha->hw)) {
1485 if (mcp->mb[7] & BIT_14) {
1486 vha->port_name[0] = MSB(mcp->mb[16]);
1487 vha->port_name[1] = LSB(mcp->mb[16]);
1488 vha->port_name[2] = MSB(mcp->mb[17]);
1489 vha->port_name[3] = LSB(mcp->mb[17]);
1490 vha->port_name[4] = MSB(mcp->mb[18]);
1491 vha->port_name[5] = LSB(mcp->mb[18]);
1492 vha->port_name[6] = MSB(mcp->mb[19]);
1493 vha->port_name[7] = LSB(mcp->mb[19]);
1494 fc_host_port_name(vha->host) =
1495 wwn_to_u64(vha->port_name);
1496 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1497 "FA-WWN acquired %016llx\n",
1498 wwn_to_u64(vha->port_name));
1499 }
1500 }
1501
1502 if (IS_QLA27XX(vha->hw))
1503 vha->bbcr = mcp->mb[15];
1504 }
1505
1506 return rval;
1507 }
1508
1509 /*
1510 * qla2x00_get_retry_cnt
1511 * Get current firmware login retry count and delay.
1512 *
1513 * Input:
1514 * ha = adapter block pointer.
1515 * retry_cnt = pointer to login retry count.
1516 * tov = pointer to login timeout value.
1517 *
1518 * Returns:
1519 * qla2x00 local function return status code.
1520 *
1521 * Context:
1522 * Kernel context.
1523 */
1524 int
1525 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1526 uint16_t *r_a_tov)
1527 {
1528 int rval;
1529 uint16_t ratov;
1530 mbx_cmd_t mc;
1531 mbx_cmd_t *mcp = &mc;
1532
1533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1534 "Entered %s.\n", __func__);
1535
1536 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1537 mcp->out_mb = MBX_0;
1538 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1539 mcp->tov = MBX_TOV_SECONDS;
1540 mcp->flags = 0;
1541 rval = qla2x00_mailbox_command(vha, mcp);
1542
1543 if (rval != QLA_SUCCESS) {
1544 /*EMPTY*/
1545 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1546 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1547 } else {
1548 /* Convert returned data and check our values. */
1549 *r_a_tov = mcp->mb[3] / 2;
1550 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1551 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1552 /* Update to the larger values */
1553 *retry_cnt = (uint8_t)mcp->mb[1];
1554 *tov = ratov;
1555 }
1556
1557 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
1558 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1559 }
1560
1561 return rval;
1562 }
1563
1564 /*
1565 * qla2x00_init_firmware
1566 * Initialize adapter firmware.
1567 *
1568 * Input:
1569 * ha = adapter block pointer.
1570 * dptr = Initialization control block pointer.
1571 * size = size of initialization control block.
1572 * TARGET_QUEUE_LOCK must be released.
1573 * ADAPTER_STATE_LOCK must be released.
1574 *
1575 * Returns:
1576 * qla2x00 local function return status code.
1577 *
1578 * Context:
1579 * Kernel context.
1580 */
1581 int
1582 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1583 {
1584 int rval;
1585 mbx_cmd_t mc;
1586 mbx_cmd_t *mcp = &mc;
1587 struct qla_hw_data *ha = vha->hw;
1588
1589 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1590 "Entered %s.\n", __func__);
1591
1592 if (IS_P3P_TYPE(ha) && ql2xdbwr)
1593 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
1594 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1595
1596 if (ha->flags.npiv_supported)
1597 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1598 else
1599 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1600
1601 mcp->mb[1] = 0;
1602 mcp->mb[2] = MSW(ha->init_cb_dma);
1603 mcp->mb[3] = LSW(ha->init_cb_dma);
1604 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1605 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
1606 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1607 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1608 mcp->mb[1] = BIT_0;
1609 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1610 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1611 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1612 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1613 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1614 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1615 }
1616 /* 1 and 2 should normally be captured. */
1617 mcp->in_mb = MBX_2|MBX_1|MBX_0;
1618 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
1619 /* mb3 is additional info about the installed SFP. */
1620 mcp->in_mb |= MBX_3;
1621 mcp->buf_size = size;
1622 mcp->flags = MBX_DMA_OUT;
1623 mcp->tov = MBX_TOV_SECONDS;
1624 rval = qla2x00_mailbox_command(vha, mcp);
1625
1626 if (rval != QLA_SUCCESS) {
1627 /*EMPTY*/
1628 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1629 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1630 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1631 } else {
1632 /*EMPTY*/
1633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1634 "Done %s.\n", __func__);
1635 }
1636
1637 return rval;
1638 }
1639
1640 /*
1641 * qla2x00_get_node_name_list
1642 * Issue get node name list mailbox command, kmalloc()
1643 * and return the resulting list. Caller must kfree() it!
1644 *
1645 * Input:
1646 * ha = adapter state pointer.
1647 * out_data = resulting list
1648 * out_len = length of the resulting list
1649 *
1650 * Returns:
1651 * qla2x00 local function return status code.
1652 *
1653 * Context:
1654 * Kernel context.
1655 */
1656 int
1657 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
1658 {
1659 struct qla_hw_data *ha = vha->hw;
1660 struct qla_port_24xx_data *list = NULL;
1661 void *pmap;
1662 mbx_cmd_t mc;
1663 dma_addr_t pmap_dma;
1664 ulong dma_size;
1665 int rval, left;
1666
1667 left = 1;
1668 while (left > 0) {
1669 dma_size = left * sizeof(*list);
1670 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
1671 &pmap_dma, GFP_KERNEL);
1672 if (!pmap) {
1673 ql_log(ql_log_warn, vha, 0x113f,
1674 "%s(%ld): DMA Alloc failed of %ld\n",
1675 __func__, vha->host_no, dma_size);
1676 rval = QLA_MEMORY_ALLOC_FAILED;
1677 goto out;
1678 }
1679
1680 mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
1681 mc.mb[1] = BIT_1 | BIT_3;
1682 mc.mb[2] = MSW(pmap_dma);
1683 mc.mb[3] = LSW(pmap_dma);
1684 mc.mb[6] = MSW(MSD(pmap_dma));
1685 mc.mb[7] = LSW(MSD(pmap_dma));
1686 mc.mb[8] = dma_size;
1687 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
1688 mc.in_mb = MBX_0|MBX_1;
1689 mc.tov = 30;
1690 mc.flags = MBX_DMA_IN;
1691
1692 rval = qla2x00_mailbox_command(vha, &mc);
1693 if (rval != QLA_SUCCESS) {
1694 if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
1695 (mc.mb[1] == 0xA)) {
1696 left += le16_to_cpu(mc.mb[2]) /
1697 sizeof(struct qla_port_24xx_data);
1698 goto restart;
1699 }
1700 goto out_free;
1701 }
1702
1703 left = 0;
1704
1705 list = kmemdup(pmap, dma_size, GFP_KERNEL);
1706 if (!list) {
1707 ql_log(ql_log_warn, vha, 0x1140,
1708 "%s(%ld): failed to allocate node names list "
1709 "structure.\n", __func__, vha->host_no);
1710 rval = QLA_MEMORY_ALLOC_FAILED;
1711 goto out_free;
1712 }
1713
1714 restart:
1715 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1716 }
1717
1718 *out_data = list;
1719 *out_len = dma_size;
1720
1721 out:
1722 return rval;
1723
1724 out_free:
1725 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1726 return rval;
1727 }
1728
1729 /*
1730 * qla2x00_get_port_database
1731 * Issue normal/enhanced get port database mailbox command
1732 * and copy device name as necessary.
1733 *
1734 * Input:
1735 * ha = adapter state pointer.
1736 * dev = structure pointer.
1737 * opt = enhanced cmd option byte.
1738 *
1739 * Returns:
1740 * qla2x00 local function return status code.
1741 *
1742 * Context:
1743 * Kernel context.
1744 */
1745 int
1746 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1747 {
1748 int rval;
1749 mbx_cmd_t mc;
1750 mbx_cmd_t *mcp = &mc;
1751 port_database_t *pd;
1752 struct port_database_24xx *pd24;
1753 dma_addr_t pd_dma;
1754 struct qla_hw_data *ha = vha->hw;
1755
1756 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1757 "Entered %s.\n", __func__);
1758
1759 pd24 = NULL;
1760 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1761 if (pd == NULL) {
1762 ql_log(ql_log_warn, vha, 0x1050,
1763 "Failed to allocate port database structure.\n");
1764 return QLA_MEMORY_ALLOC_FAILED;
1765 }
1766 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1767
1768 mcp->mb[0] = MBC_GET_PORT_DATABASE;
1769 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1770 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1771 mcp->mb[2] = MSW(pd_dma);
1772 mcp->mb[3] = LSW(pd_dma);
1773 mcp->mb[6] = MSW(MSD(pd_dma));
1774 mcp->mb[7] = LSW(MSD(pd_dma));
1775 mcp->mb[9] = vha->vp_idx;
1776 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1777 mcp->in_mb = MBX_0;
1778 if (IS_FWI2_CAPABLE(ha)) {
1779 mcp->mb[1] = fcport->loop_id;
1780 mcp->mb[10] = opt;
1781 mcp->out_mb |= MBX_10|MBX_1;
1782 mcp->in_mb |= MBX_1;
1783 } else if (HAS_EXTENDED_IDS(ha)) {
1784 mcp->mb[1] = fcport->loop_id;
1785 mcp->mb[10] = opt;
1786 mcp->out_mb |= MBX_10|MBX_1;
1787 } else {
1788 mcp->mb[1] = fcport->loop_id << 8 | opt;
1789 mcp->out_mb |= MBX_1;
1790 }
1791 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1792 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1793 mcp->flags = MBX_DMA_IN;
1794 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1795 rval = qla2x00_mailbox_command(vha, mcp);
1796 if (rval != QLA_SUCCESS)
1797 goto gpd_error_out;
1798
1799 if (IS_FWI2_CAPABLE(ha)) {
1800 uint64_t zero = 0;
1801 pd24 = (struct port_database_24xx *) pd;
1802
1803 /* Check for logged in state. */
1804 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1805 pd24->last_login_state != PDS_PRLI_COMPLETE) {
1806 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1807 "Unable to verify login-state (%x/%x) for "
1808 "loop_id %x.\n", pd24->current_login_state,
1809 pd24->last_login_state, fcport->loop_id);
1810 rval = QLA_FUNCTION_FAILED;
1811 goto gpd_error_out;
1812 }
1813
1814 if (fcport->loop_id == FC_NO_LOOP_ID ||
1815 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1816 memcmp(fcport->port_name, pd24->port_name, 8))) {
1817 /* We lost the device mid way. */
1818 rval = QLA_NOT_LOGGED_IN;
1819 goto gpd_error_out;
1820 }
1821
1822 /* Names are little-endian. */
1823 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1824 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1825
1826 /* Get port_id of device. */
1827 fcport->d_id.b.domain = pd24->port_id[0];
1828 fcport->d_id.b.area = pd24->port_id[1];
1829 fcport->d_id.b.al_pa = pd24->port_id[2];
1830 fcport->d_id.b.rsvd_1 = 0;
1831
1832 /* If not target must be initiator or unknown type. */
1833 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1834 fcport->port_type = FCT_INITIATOR;
1835 else
1836 fcport->port_type = FCT_TARGET;
1837
1838 /* Passback COS information. */
1839 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1840 FC_COS_CLASS2 : FC_COS_CLASS3;
1841
1842 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1843 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1844 } else {
1845 uint64_t zero = 0;
1846
1847 /* Check for logged in state. */
1848 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1849 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
1850 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1851 "Unable to verify login-state (%x/%x) - "
1852 "portid=%02x%02x%02x.\n", pd->master_state,
1853 pd->slave_state, fcport->d_id.b.domain,
1854 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1855 rval = QLA_FUNCTION_FAILED;
1856 goto gpd_error_out;
1857 }
1858
1859 if (fcport->loop_id == FC_NO_LOOP_ID ||
1860 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1861 memcmp(fcport->port_name, pd->port_name, 8))) {
1862 /* We lost the device mid way. */
1863 rval = QLA_NOT_LOGGED_IN;
1864 goto gpd_error_out;
1865 }
1866
1867 /* Names are little-endian. */
1868 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1869 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1870
1871 /* Get port_id of device. */
1872 fcport->d_id.b.domain = pd->port_id[0];
1873 fcport->d_id.b.area = pd->port_id[3];
1874 fcport->d_id.b.al_pa = pd->port_id[2];
1875 fcport->d_id.b.rsvd_1 = 0;
1876
1877 /* If not target must be initiator or unknown type. */
1878 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1879 fcport->port_type = FCT_INITIATOR;
1880 else
1881 fcport->port_type = FCT_TARGET;
1882
1883 /* Passback COS information. */
1884 fcport->supported_classes = (pd->options & BIT_4) ?
1885 FC_COS_CLASS2: FC_COS_CLASS3;
1886 }
1887
1888 gpd_error_out:
1889 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1890
1891 if (rval != QLA_SUCCESS) {
1892 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1893 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1894 mcp->mb[0], mcp->mb[1]);
1895 } else {
1896 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1897 "Done %s.\n", __func__);
1898 }
1899
1900 return rval;
1901 }
1902
1903 /*
1904 * qla2x00_get_firmware_state
1905 * Get adapter firmware state.
1906 *
1907 * Input:
1908 * ha = adapter block pointer.
1909 * dptr = pointer for firmware state.
1910 * TARGET_QUEUE_LOCK must be released.
1911 * ADAPTER_STATE_LOCK must be released.
1912 *
1913 * Returns:
1914 * qla2x00 local function return status code.
1915 *
1916 * Context:
1917 * Kernel context.
1918 */
1919 int
1920 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1921 {
1922 int rval;
1923 mbx_cmd_t mc;
1924 mbx_cmd_t *mcp = &mc;
1925
1926 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1927 "Entered %s.\n", __func__);
1928
1929 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1930 mcp->out_mb = MBX_0;
1931 if (IS_FWI2_CAPABLE(vha->hw))
1932 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1933 else
1934 mcp->in_mb = MBX_1|MBX_0;
1935 mcp->tov = MBX_TOV_SECONDS;
1936 mcp->flags = 0;
1937 rval = qla2x00_mailbox_command(vha, mcp);
1938
1939 /* Return firmware states. */
1940 states[0] = mcp->mb[1];
1941 if (IS_FWI2_CAPABLE(vha->hw)) {
1942 states[1] = mcp->mb[2];
1943 states[2] = mcp->mb[3]; /* SFP info */
1944 states[3] = mcp->mb[4];
1945 states[4] = mcp->mb[5];
1946 states[5] = mcp->mb[6]; /* DPORT status */
1947 }
1948
1949 if (rval != QLA_SUCCESS) {
1950 /*EMPTY*/
1951 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1952 } else {
1953 /*EMPTY*/
1954 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1955 "Done %s.\n", __func__);
1956 }
1957
1958 return rval;
1959 }
1960
1961 /*
1962 * qla2x00_get_port_name
1963 * Issue get port name mailbox command.
1964 * Returned name is in big endian format.
1965 *
1966 * Input:
1967 * ha = adapter block pointer.
1968 * loop_id = loop ID of device.
1969 * name = pointer for name.
1970 * TARGET_QUEUE_LOCK must be released.
1971 * ADAPTER_STATE_LOCK must be released.
1972 *
1973 * Returns:
1974 * qla2x00 local function return status code.
1975 *
1976 * Context:
1977 * Kernel context.
1978 */
1979 int
1980 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1981 uint8_t opt)
1982 {
1983 int rval;
1984 mbx_cmd_t mc;
1985 mbx_cmd_t *mcp = &mc;
1986
1987 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1988 "Entered %s.\n", __func__);
1989
1990 mcp->mb[0] = MBC_GET_PORT_NAME;
1991 mcp->mb[9] = vha->vp_idx;
1992 mcp->out_mb = MBX_9|MBX_1|MBX_0;
1993 if (HAS_EXTENDED_IDS(vha->hw)) {
1994 mcp->mb[1] = loop_id;
1995 mcp->mb[10] = opt;
1996 mcp->out_mb |= MBX_10;
1997 } else {
1998 mcp->mb[1] = loop_id << 8 | opt;
1999 }
2000
2001 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2002 mcp->tov = MBX_TOV_SECONDS;
2003 mcp->flags = 0;
2004 rval = qla2x00_mailbox_command(vha, mcp);
2005
2006 if (rval != QLA_SUCCESS) {
2007 /*EMPTY*/
2008 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
2009 } else {
2010 if (name != NULL) {
2011 /* This function returns name in big endian. */
2012 name[0] = MSB(mcp->mb[2]);
2013 name[1] = LSB(mcp->mb[2]);
2014 name[2] = MSB(mcp->mb[3]);
2015 name[3] = LSB(mcp->mb[3]);
2016 name[4] = MSB(mcp->mb[6]);
2017 name[5] = LSB(mcp->mb[6]);
2018 name[6] = MSB(mcp->mb[7]);
2019 name[7] = LSB(mcp->mb[7]);
2020 }
2021
2022 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
2023 "Done %s.\n", __func__);
2024 }
2025
2026 return rval;
2027 }
2028
2029 /*
2030 * qla24xx_link_initialization
2031 * Issue link initialization mailbox command.
2032 *
2033 * Input:
2034 * ha = adapter block pointer.
2035 * TARGET_QUEUE_LOCK must be released.
2036 * ADAPTER_STATE_LOCK must be released.
2037 *
2038 * Returns:
2039 * qla2x00 local function return status code.
2040 *
2041 * Context:
2042 * Kernel context.
2043 */
2044 int
2045 qla24xx_link_initialize(scsi_qla_host_t *vha)
2046 {
2047 int rval;
2048 mbx_cmd_t mc;
2049 mbx_cmd_t *mcp = &mc;
2050
2051 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
2052 "Entered %s.\n", __func__);
2053
2054 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
2055 return QLA_FUNCTION_FAILED;
2056
2057 mcp->mb[0] = MBC_LINK_INITIALIZATION;
2058 mcp->mb[1] = BIT_4;
2059 if (vha->hw->operating_mode == LOOP)
2060 mcp->mb[1] |= BIT_6;
2061 else
2062 mcp->mb[1] |= BIT_5;
2063 mcp->mb[2] = 0;
2064 mcp->mb[3] = 0;
2065 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2066 mcp->in_mb = MBX_0;
2067 mcp->tov = MBX_TOV_SECONDS;
2068 mcp->flags = 0;
2069 rval = qla2x00_mailbox_command(vha, mcp);
2070
2071 if (rval != QLA_SUCCESS) {
2072 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2073 } else {
2074 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2075 "Done %s.\n", __func__);
2076 }
2077
2078 return rval;
2079 }
2080
2081 /*
2082 * qla2x00_lip_reset
2083 * Issue LIP reset mailbox command.
2084 *
2085 * Input:
2086 * ha = adapter block pointer.
2087 * TARGET_QUEUE_LOCK must be released.
2088 * ADAPTER_STATE_LOCK must be released.
2089 *
2090 * Returns:
2091 * qla2x00 local function return status code.
2092 *
2093 * Context:
2094 * Kernel context.
2095 */
2096 int
2097 qla2x00_lip_reset(scsi_qla_host_t *vha)
2098 {
2099 int rval;
2100 mbx_cmd_t mc;
2101 mbx_cmd_t *mcp = &mc;
2102
2103 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
2104 "Entered %s.\n", __func__);
2105
2106 if (IS_CNA_CAPABLE(vha->hw)) {
2107 /* Logout across all FCFs. */
2108 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2109 mcp->mb[1] = BIT_1;
2110 mcp->mb[2] = 0;
2111 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2112 } else if (IS_FWI2_CAPABLE(vha->hw)) {
2113 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2114 mcp->mb[1] = BIT_6;
2115 mcp->mb[2] = 0;
2116 mcp->mb[3] = vha->hw->loop_reset_delay;
2117 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2118 } else {
2119 mcp->mb[0] = MBC_LIP_RESET;
2120 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2121 if (HAS_EXTENDED_IDS(vha->hw)) {
2122 mcp->mb[1] = 0x00ff;
2123 mcp->mb[10] = 0;
2124 mcp->out_mb |= MBX_10;
2125 } else {
2126 mcp->mb[1] = 0xff00;
2127 }
2128 mcp->mb[2] = vha->hw->loop_reset_delay;
2129 mcp->mb[3] = 0;
2130 }
2131 mcp->in_mb = MBX_0;
2132 mcp->tov = MBX_TOV_SECONDS;
2133 mcp->flags = 0;
2134 rval = qla2x00_mailbox_command(vha, mcp);
2135
2136 if (rval != QLA_SUCCESS) {
2137 /*EMPTY*/
2138 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
2139 } else {
2140 /*EMPTY*/
2141 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2142 "Done %s.\n", __func__);
2143 }
2144
2145 return rval;
2146 }
2147
2148 /*
2149 * qla2x00_send_sns
2150 * Send SNS command.
2151 *
2152 * Input:
2153 * ha = adapter block pointer.
2154 * sns = pointer for command.
2155 * cmd_size = command size.
2156 * buf_size = response/command size.
2157 * TARGET_QUEUE_LOCK must be released.
2158 * ADAPTER_STATE_LOCK must be released.
2159 *
2160 * Returns:
2161 * qla2x00 local function return status code.
2162 *
2163 * Context:
2164 * Kernel context.
2165 */
2166 int
2167 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
2168 uint16_t cmd_size, size_t buf_size)
2169 {
2170 int rval;
2171 mbx_cmd_t mc;
2172 mbx_cmd_t *mcp = &mc;
2173
2174 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2175 "Entered %s.\n", __func__);
2176
2177 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
2178 "Retry cnt=%d ratov=%d total tov=%d.\n",
2179 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
2180
2181 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2182 mcp->mb[1] = cmd_size;
2183 mcp->mb[2] = MSW(sns_phys_address);
2184 mcp->mb[3] = LSW(sns_phys_address);
2185 mcp->mb[6] = MSW(MSD(sns_phys_address));
2186 mcp->mb[7] = LSW(MSD(sns_phys_address));
2187 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2188 mcp->in_mb = MBX_0|MBX_1;
2189 mcp->buf_size = buf_size;
2190 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
2191 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2192 rval = qla2x00_mailbox_command(vha, mcp);
2193
2194 if (rval != QLA_SUCCESS) {
2195 /*EMPTY*/
2196 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2197 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2198 rval, mcp->mb[0], mcp->mb[1]);
2199 } else {
2200 /*EMPTY*/
2201 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2202 "Done %s.\n", __func__);
2203 }
2204
2205 return rval;
2206 }
2207
2208 int
2209 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2210 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2211 {
2212 int rval;
2213
2214 struct logio_entry_24xx *lg;
2215 dma_addr_t lg_dma;
2216 uint32_t iop[2];
2217 struct qla_hw_data *ha = vha->hw;
2218 struct req_que *req;
2219
2220 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2221 "Entered %s.\n", __func__);
2222
2223 if (vha->vp_idx && vha->qpair)
2224 req = vha->qpair->req;
2225 else
2226 req = ha->req_q_map[0];
2227
2228 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2229 if (lg == NULL) {
2230 ql_log(ql_log_warn, vha, 0x1062,
2231 "Failed to allocate login IOCB.\n");
2232 return QLA_MEMORY_ALLOC_FAILED;
2233 }
2234 memset(lg, 0, sizeof(struct logio_entry_24xx));
2235
2236 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2237 lg->entry_count = 1;
2238 lg->handle = MAKE_HANDLE(req->id, lg->handle);
2239 lg->nport_handle = cpu_to_le16(loop_id);
2240 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
2241 if (opt & BIT_0)
2242 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
2243 if (opt & BIT_1)
2244 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
2245 lg->port_id[0] = al_pa;
2246 lg->port_id[1] = area;
2247 lg->port_id[2] = domain;
2248 lg->vp_index = vha->vp_idx;
2249 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2250 (ha->r_a_tov / 10 * 2) + 2);
2251 if (rval != QLA_SUCCESS) {
2252 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2253 "Failed to issue login IOCB (%x).\n", rval);
2254 } else if (lg->entry_status != 0) {
2255 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2256 "Failed to complete IOCB -- error status (%x).\n",
2257 lg->entry_status);
2258 rval = QLA_FUNCTION_FAILED;
2259 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
2260 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2261 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2262
2263 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2264 "Failed to complete IOCB -- completion status (%x) "
2265 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2266 iop[0], iop[1]);
2267
2268 switch (iop[0]) {
2269 case LSC_SCODE_PORTID_USED:
2270 mb[0] = MBS_PORT_ID_USED;
2271 mb[1] = LSW(iop[1]);
2272 break;
2273 case LSC_SCODE_NPORT_USED:
2274 mb[0] = MBS_LOOP_ID_USED;
2275 break;
2276 case LSC_SCODE_NOLINK:
2277 case LSC_SCODE_NOIOCB:
2278 case LSC_SCODE_NOXCB:
2279 case LSC_SCODE_CMD_FAILED:
2280 case LSC_SCODE_NOFABRIC:
2281 case LSC_SCODE_FW_NOT_READY:
2282 case LSC_SCODE_NOT_LOGGED_IN:
2283 case LSC_SCODE_NOPCB:
2284 case LSC_SCODE_ELS_REJECT:
2285 case LSC_SCODE_CMD_PARAM_ERR:
2286 case LSC_SCODE_NONPORT:
2287 case LSC_SCODE_LOGGED_IN:
2288 case LSC_SCODE_NOFLOGI_ACC:
2289 default:
2290 mb[0] = MBS_COMMAND_ERROR;
2291 break;
2292 }
2293 } else {
2294 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2295 "Done %s.\n", __func__);
2296
2297 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2298
2299 mb[0] = MBS_COMMAND_COMPLETE;
2300 mb[1] = 0;
2301 if (iop[0] & BIT_4) {
2302 if (iop[0] & BIT_8)
2303 mb[1] |= BIT_1;
2304 } else
2305 mb[1] = BIT_0;
2306
2307 /* Passback COS information. */
2308 mb[10] = 0;
2309 if (lg->io_parameter[7] || lg->io_parameter[8])
2310 mb[10] |= BIT_0; /* Class 2. */
2311 if (lg->io_parameter[9] || lg->io_parameter[10])
2312 mb[10] |= BIT_1; /* Class 3. */
2313 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2314 mb[10] |= BIT_7; /* Confirmed Completion
2315 * Allowed
2316 */
2317 }
2318
2319 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2320
2321 return rval;
2322 }
2323
2324 /*
2325 * qla2x00_login_fabric
2326 * Issue login fabric port mailbox command.
2327 *
2328 * Input:
2329 * ha = adapter block pointer.
2330 * loop_id = device loop ID.
2331 * domain = device domain.
2332 * area = device area.
2333 * al_pa = device AL_PA.
2334 * status = pointer for return status.
2335 * opt = command options.
2336 * TARGET_QUEUE_LOCK must be released.
2337 * ADAPTER_STATE_LOCK must be released.
2338 *
2339 * Returns:
2340 * qla2x00 local function return status code.
2341 *
2342 * Context:
2343 * Kernel context.
2344 */
2345 int
2346 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2347 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2348 {
2349 int rval;
2350 mbx_cmd_t mc;
2351 mbx_cmd_t *mcp = &mc;
2352 struct qla_hw_data *ha = vha->hw;
2353
2354 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2355 "Entered %s.\n", __func__);
2356
2357 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2358 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2359 if (HAS_EXTENDED_IDS(ha)) {
2360 mcp->mb[1] = loop_id;
2361 mcp->mb[10] = opt;
2362 mcp->out_mb |= MBX_10;
2363 } else {
2364 mcp->mb[1] = (loop_id << 8) | opt;
2365 }
2366 mcp->mb[2] = domain;
2367 mcp->mb[3] = area << 8 | al_pa;
2368
2369 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2370 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2371 mcp->flags = 0;
2372 rval = qla2x00_mailbox_command(vha, mcp);
2373
2374 /* Return mailbox statuses. */
2375 if (mb != NULL) {
2376 mb[0] = mcp->mb[0];
2377 mb[1] = mcp->mb[1];
2378 mb[2] = mcp->mb[2];
2379 mb[6] = mcp->mb[6];
2380 mb[7] = mcp->mb[7];
2381 /* COS retrieved from Get-Port-Database mailbox command. */
2382 mb[10] = 0;
2383 }
2384
2385 if (rval != QLA_SUCCESS) {
2386 /* RLU tmp code: need to change main mailbox_command function to
2387 * return ok even when the mailbox completion value is not
2388 * SUCCESS. The caller needs to be responsible to interpret
2389 * the return values of this mailbox command if we're not
2390 * to change too much of the existing code.
2391 */
2392 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2393 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2394 mcp->mb[0] == 0x4006)
2395 rval = QLA_SUCCESS;
2396
2397 /*EMPTY*/
2398 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2399 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2400 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
2401 } else {
2402 /*EMPTY*/
2403 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2404 "Done %s.\n", __func__);
2405 }
2406
2407 return rval;
2408 }
2409
2410 /*
2411 * qla2x00_login_local_device
2412 * Issue login loop port mailbox command.
2413 *
2414 * Input:
2415 * ha = adapter block pointer.
2416 * loop_id = device loop ID.
2417 * opt = command options.
2418 *
2419 * Returns:
2420 * Return status code.
2421 *
2422 * Context:
2423 * Kernel context.
2424 *
2425 */
2426 int
2427 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
2428 uint16_t *mb_ret, uint8_t opt)
2429 {
2430 int rval;
2431 mbx_cmd_t mc;
2432 mbx_cmd_t *mcp = &mc;
2433 struct qla_hw_data *ha = vha->hw;
2434
2435 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2436 "Entered %s.\n", __func__);
2437
2438 if (IS_FWI2_CAPABLE(ha))
2439 return qla24xx_login_fabric(vha, fcport->loop_id,
2440 fcport->d_id.b.domain, fcport->d_id.b.area,
2441 fcport->d_id.b.al_pa, mb_ret, opt);
2442
2443 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2444 if (HAS_EXTENDED_IDS(ha))
2445 mcp->mb[1] = fcport->loop_id;
2446 else
2447 mcp->mb[1] = fcport->loop_id << 8;
2448 mcp->mb[2] = opt;
2449 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2450 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2451 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2452 mcp->flags = 0;
2453 rval = qla2x00_mailbox_command(vha, mcp);
2454
2455 /* Return mailbox statuses. */
2456 if (mb_ret != NULL) {
2457 mb_ret[0] = mcp->mb[0];
2458 mb_ret[1] = mcp->mb[1];
2459 mb_ret[6] = mcp->mb[6];
2460 mb_ret[7] = mcp->mb[7];
2461 }
2462
2463 if (rval != QLA_SUCCESS) {
2464 /* AV tmp code: need to change main mailbox_command function to
2465 * return ok even when the mailbox completion value is not
2466 * SUCCESS. The caller needs to be responsible to interpret
2467 * the return values of this mailbox command if we're not
2468 * to change too much of the existing code.
2469 */
2470 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2471 rval = QLA_SUCCESS;
2472
2473 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2474 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2475 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
2476 } else {
2477 /*EMPTY*/
2478 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2479 "Done %s.\n", __func__);
2480 }
2481
2482 return (rval);
2483 }
2484
2485 int
2486 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2487 uint8_t area, uint8_t al_pa)
2488 {
2489 int rval;
2490 struct logio_entry_24xx *lg;
2491 dma_addr_t lg_dma;
2492 struct qla_hw_data *ha = vha->hw;
2493 struct req_que *req;
2494
2495 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2496 "Entered %s.\n", __func__);
2497
2498 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2499 if (lg == NULL) {
2500 ql_log(ql_log_warn, vha, 0x106e,
2501 "Failed to allocate logout IOCB.\n");
2502 return QLA_MEMORY_ALLOC_FAILED;
2503 }
2504 memset(lg, 0, sizeof(struct logio_entry_24xx));
2505
2506 req = vha->req;
2507 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2508 lg->entry_count = 1;
2509 lg->handle = MAKE_HANDLE(req->id, lg->handle);
2510 lg->nport_handle = cpu_to_le16(loop_id);
2511 lg->control_flags =
2512 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
2513 LCF_FREE_NPORT);
2514 lg->port_id[0] = al_pa;
2515 lg->port_id[1] = area;
2516 lg->port_id[2] = domain;
2517 lg->vp_index = vha->vp_idx;
2518 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2519 (ha->r_a_tov / 10 * 2) + 2);
2520 if (rval != QLA_SUCCESS) {
2521 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2522 "Failed to issue logout IOCB (%x).\n", rval);
2523 } else if (lg->entry_status != 0) {
2524 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2525 "Failed to complete IOCB -- error status (%x).\n",
2526 lg->entry_status);
2527 rval = QLA_FUNCTION_FAILED;
2528 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
2529 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2530 "Failed to complete IOCB -- completion status (%x) "
2531 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2532 le32_to_cpu(lg->io_parameter[0]),
2533 le32_to_cpu(lg->io_parameter[1]));
2534 } else {
2535 /*EMPTY*/
2536 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2537 "Done %s.\n", __func__);
2538 }
2539
2540 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2541
2542 return rval;
2543 }
2544
2545 /*
2546 * qla2x00_fabric_logout
2547 * Issue logout fabric port mailbox command.
2548 *
2549 * Input:
2550 * ha = adapter block pointer.
2551 * loop_id = device loop ID.
2552 * TARGET_QUEUE_LOCK must be released.
2553 * ADAPTER_STATE_LOCK must be released.
2554 *
2555 * Returns:
2556 * qla2x00 local function return status code.
2557 *
2558 * Context:
2559 * Kernel context.
2560 */
2561 int
2562 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2563 uint8_t area, uint8_t al_pa)
2564 {
2565 int rval;
2566 mbx_cmd_t mc;
2567 mbx_cmd_t *mcp = &mc;
2568
2569 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2570 "Entered %s.\n", __func__);
2571
2572 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2573 mcp->out_mb = MBX_1|MBX_0;
2574 if (HAS_EXTENDED_IDS(vha->hw)) {
2575 mcp->mb[1] = loop_id;
2576 mcp->mb[10] = 0;
2577 mcp->out_mb |= MBX_10;
2578 } else {
2579 mcp->mb[1] = loop_id << 8;
2580 }
2581
2582 mcp->in_mb = MBX_1|MBX_0;
2583 mcp->tov = MBX_TOV_SECONDS;
2584 mcp->flags = 0;
2585 rval = qla2x00_mailbox_command(vha, mcp);
2586
2587 if (rval != QLA_SUCCESS) {
2588 /*EMPTY*/
2589 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2590 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
2591 } else {
2592 /*EMPTY*/
2593 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2594 "Done %s.\n", __func__);
2595 }
2596
2597 return rval;
2598 }
2599
2600 /*
2601 * qla2x00_full_login_lip
2602 * Issue full login LIP mailbox command.
2603 *
2604 * Input:
2605 * ha = adapter block pointer.
2606 * TARGET_QUEUE_LOCK must be released.
2607 * ADAPTER_STATE_LOCK must be released.
2608 *
2609 * Returns:
2610 * qla2x00 local function return status code.
2611 *
2612 * Context:
2613 * Kernel context.
2614 */
2615 int
2616 qla2x00_full_login_lip(scsi_qla_host_t *vha)
2617 {
2618 int rval;
2619 mbx_cmd_t mc;
2620 mbx_cmd_t *mcp = &mc;
2621
2622 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2623 "Entered %s.\n", __func__);
2624
2625 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2626 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
2627 mcp->mb[2] = 0;
2628 mcp->mb[3] = 0;
2629 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2630 mcp->in_mb = MBX_0;
2631 mcp->tov = MBX_TOV_SECONDS;
2632 mcp->flags = 0;
2633 rval = qla2x00_mailbox_command(vha, mcp);
2634
2635 if (rval != QLA_SUCCESS) {
2636 /*EMPTY*/
2637 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
2638 } else {
2639 /*EMPTY*/
2640 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2641 "Done %s.\n", __func__);
2642 }
2643
2644 return rval;
2645 }
2646
2647 /*
2648 * qla2x00_get_id_list
2649 *
2650 * Input:
2651 * ha = adapter block pointer.
2652 *
2653 * Returns:
2654 * qla2x00 local function return status code.
2655 *
2656 * Context:
2657 * Kernel context.
2658 */
2659 int
2660 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
2661 uint16_t *entries)
2662 {
2663 int rval;
2664 mbx_cmd_t mc;
2665 mbx_cmd_t *mcp = &mc;
2666
2667 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2668 "Entered %s.\n", __func__);
2669
2670 if (id_list == NULL)
2671 return QLA_FUNCTION_FAILED;
2672
2673 mcp->mb[0] = MBC_GET_ID_LIST;
2674 mcp->out_mb = MBX_0;
2675 if (IS_FWI2_CAPABLE(vha->hw)) {
2676 mcp->mb[2] = MSW(id_list_dma);
2677 mcp->mb[3] = LSW(id_list_dma);
2678 mcp->mb[6] = MSW(MSD(id_list_dma));
2679 mcp->mb[7] = LSW(MSD(id_list_dma));
2680 mcp->mb[8] = 0;
2681 mcp->mb[9] = vha->vp_idx;
2682 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
2683 } else {
2684 mcp->mb[1] = MSW(id_list_dma);
2685 mcp->mb[2] = LSW(id_list_dma);
2686 mcp->mb[3] = MSW(MSD(id_list_dma));
2687 mcp->mb[6] = LSW(MSD(id_list_dma));
2688 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2689 }
2690 mcp->in_mb = MBX_1|MBX_0;
2691 mcp->tov = MBX_TOV_SECONDS;
2692 mcp->flags = 0;
2693 rval = qla2x00_mailbox_command(vha, mcp);
2694
2695 if (rval != QLA_SUCCESS) {
2696 /*EMPTY*/
2697 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
2698 } else {
2699 *entries = mcp->mb[1];
2700 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2701 "Done %s.\n", __func__);
2702 }
2703
2704 return rval;
2705 }
2706
2707 /*
2708 * qla2x00_get_resource_cnts
2709 * Get current firmware resource counts.
2710 *
2711 * Input:
2712 * ha = adapter block pointer.
2713 *
2714 * Returns:
2715 * qla2x00 local function return status code.
2716 *
2717 * Context:
2718 * Kernel context.
2719 */
2720 int
2721 qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
2722 {
2723 struct qla_hw_data *ha = vha->hw;
2724 int rval;
2725 mbx_cmd_t mc;
2726 mbx_cmd_t *mcp = &mc;
2727
2728 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2729 "Entered %s.\n", __func__);
2730
2731 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2732 mcp->out_mb = MBX_0;
2733 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2734 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
2735 mcp->in_mb |= MBX_12;
2736 mcp->tov = MBX_TOV_SECONDS;
2737 mcp->flags = 0;
2738 rval = qla2x00_mailbox_command(vha, mcp);
2739
2740 if (rval != QLA_SUCCESS) {
2741 /*EMPTY*/
2742 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2743 "Failed mb[0]=%x.\n", mcp->mb[0]);
2744 } else {
2745 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
2746 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2747 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2748 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2749 mcp->mb[11], mcp->mb[12]);
2750
2751 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2752 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2753 ha->cur_fw_xcb_count = mcp->mb[3];
2754 ha->orig_fw_xcb_count = mcp->mb[6];
2755 ha->cur_fw_iocb_count = mcp->mb[7];
2756 ha->orig_fw_iocb_count = mcp->mb[10];
2757 if (ha->flags.npiv_supported)
2758 ha->max_npiv_vports = mcp->mb[11];
2759 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
2760 ha->fw_max_fcf_count = mcp->mb[12];
2761 }
2762
2763 return (rval);
2764 }
2765
2766 /*
2767 * qla2x00_get_fcal_position_map
2768 * Get FCAL (LILP) position map using mailbox command
2769 *
2770 * Input:
2771 * ha = adapter state pointer.
2772 * pos_map = buffer pointer (can be NULL).
2773 *
2774 * Returns:
2775 * qla2x00 local function return status code.
2776 *
2777 * Context:
2778 * Kernel context.
2779 */
2780 int
2781 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
2782 {
2783 int rval;
2784 mbx_cmd_t mc;
2785 mbx_cmd_t *mcp = &mc;
2786 char *pmap;
2787 dma_addr_t pmap_dma;
2788 struct qla_hw_data *ha = vha->hw;
2789
2790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2791 "Entered %s.\n", __func__);
2792
2793 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
2794 if (pmap == NULL) {
2795 ql_log(ql_log_warn, vha, 0x1080,
2796 "Memory alloc failed.\n");
2797 return QLA_MEMORY_ALLOC_FAILED;
2798 }
2799 memset(pmap, 0, FCAL_MAP_SIZE);
2800
2801 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2802 mcp->mb[2] = MSW(pmap_dma);
2803 mcp->mb[3] = LSW(pmap_dma);
2804 mcp->mb[6] = MSW(MSD(pmap_dma));
2805 mcp->mb[7] = LSW(MSD(pmap_dma));
2806 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2807 mcp->in_mb = MBX_1|MBX_0;
2808 mcp->buf_size = FCAL_MAP_SIZE;
2809 mcp->flags = MBX_DMA_IN;
2810 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2811 rval = qla2x00_mailbox_command(vha, mcp);
2812
2813 if (rval == QLA_SUCCESS) {
2814 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
2815 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2816 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2817 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2818 pmap, pmap[0] + 1);
2819
2820 if (pos_map)
2821 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2822 }
2823 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2824
2825 if (rval != QLA_SUCCESS) {
2826 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
2827 } else {
2828 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2829 "Done %s.\n", __func__);
2830 }
2831
2832 return rval;
2833 }
2834
2835 /*
2836 * qla2x00_get_link_status
2837 *
2838 * Input:
2839 * ha = adapter block pointer.
2840 * loop_id = device loop ID.
2841 * ret_buf = pointer to link status return buffer.
2842 *
2843 * Returns:
2844 * 0 = success.
2845 * BIT_0 = mem alloc error.
2846 * BIT_1 = mailbox error.
2847 */
2848 int
2849 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
2850 struct link_statistics *stats, dma_addr_t stats_dma)
2851 {
2852 int rval;
2853 mbx_cmd_t mc;
2854 mbx_cmd_t *mcp = &mc;
2855 uint32_t *iter = (void *)stats;
2856 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
2857 struct qla_hw_data *ha = vha->hw;
2858
2859 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2860 "Entered %s.\n", __func__);
2861
2862 mcp->mb[0] = MBC_GET_LINK_STATUS;
2863 mcp->mb[2] = MSW(LSD(stats_dma));
2864 mcp->mb[3] = LSW(LSD(stats_dma));
2865 mcp->mb[6] = MSW(MSD(stats_dma));
2866 mcp->mb[7] = LSW(MSD(stats_dma));
2867 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2868 mcp->in_mb = MBX_0;
2869 if (IS_FWI2_CAPABLE(ha)) {
2870 mcp->mb[1] = loop_id;
2871 mcp->mb[4] = 0;
2872 mcp->mb[10] = 0;
2873 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2874 mcp->in_mb |= MBX_1;
2875 } else if (HAS_EXTENDED_IDS(ha)) {
2876 mcp->mb[1] = loop_id;
2877 mcp->mb[10] = 0;
2878 mcp->out_mb |= MBX_10|MBX_1;
2879 } else {
2880 mcp->mb[1] = loop_id << 8;
2881 mcp->out_mb |= MBX_1;
2882 }
2883 mcp->tov = MBX_TOV_SECONDS;
2884 mcp->flags = IOCTL_CMD;
2885 rval = qla2x00_mailbox_command(vha, mcp);
2886
2887 if (rval == QLA_SUCCESS) {
2888 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2889 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2890 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2891 rval = QLA_FUNCTION_FAILED;
2892 } else {
2893 /* Re-endianize - firmware data is le32. */
2894 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2895 "Done %s.\n", __func__);
2896 for ( ; dwords--; iter++)
2897 le32_to_cpus(iter);
2898 }
2899 } else {
2900 /* Failed. */
2901 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
2902 }
2903
2904 return rval;
2905 }
2906
2907 int
2908 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
2909 dma_addr_t stats_dma, uint options)
2910 {
2911 int rval;
2912 mbx_cmd_t mc;
2913 mbx_cmd_t *mcp = &mc;
2914 uint32_t *iter, dwords;
2915
2916 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2917 "Entered %s.\n", __func__);
2918
2919 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
2920 mcp->mb[2] = MSW(stats_dma);
2921 mcp->mb[3] = LSW(stats_dma);
2922 mcp->mb[6] = MSW(MSD(stats_dma));
2923 mcp->mb[7] = LSW(MSD(stats_dma));
2924 mcp->mb[8] = sizeof(struct link_statistics) / 4;
2925 mcp->mb[9] = vha->vp_idx;
2926 mcp->mb[10] = options;
2927 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2928 mcp->in_mb = MBX_2|MBX_1|MBX_0;
2929 mcp->tov = MBX_TOV_SECONDS;
2930 mcp->flags = IOCTL_CMD;
2931 rval = qla2x00_mailbox_command(vha, mcp);
2932
2933 if (rval == QLA_SUCCESS) {
2934 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2935 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2936 "Failed mb[0]=%x.\n", mcp->mb[0]);
2937 rval = QLA_FUNCTION_FAILED;
2938 } else {
2939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2940 "Done %s.\n", __func__);
2941 /* Re-endianize - firmware data is le32. */
2942 dwords = sizeof(struct link_statistics) / 4;
2943 iter = &stats->link_fail_cnt;
2944 for ( ; dwords--; iter++)
2945 le32_to_cpus(iter);
2946 }
2947 } else {
2948 /* Failed. */
2949 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
2950 }
2951
2952 return rval;
2953 }
2954
2955 int
2956 qla24xx_abort_command(srb_t *sp)
2957 {
2958 int rval;
2959 unsigned long flags = 0;
2960
2961 struct abort_entry_24xx *abt;
2962 dma_addr_t abt_dma;
2963 uint32_t handle;
2964 fc_port_t *fcport = sp->fcport;
2965 struct scsi_qla_host *vha = fcport->vha;
2966 struct qla_hw_data *ha = vha->hw;
2967 struct req_que *req = vha->req;
2968
2969 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2970 "Entered %s.\n", __func__);
2971
2972 if (vha->flags.qpairs_available && sp->qpair)
2973 req = sp->qpair->req;
2974
2975 if (ql2xasynctmfenable)
2976 return qla24xx_async_abort_command(sp);
2977
2978 spin_lock_irqsave(&ha->hardware_lock, flags);
2979 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
2980 if (req->outstanding_cmds[handle] == sp)
2981 break;
2982 }
2983 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2984 if (handle == req->num_outstanding_cmds) {
2985 /* Command not found. */
2986 return QLA_FUNCTION_FAILED;
2987 }
2988
2989 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2990 if (abt == NULL) {
2991 ql_log(ql_log_warn, vha, 0x108d,
2992 "Failed to allocate abort IOCB.\n");
2993 return QLA_MEMORY_ALLOC_FAILED;
2994 }
2995 memset(abt, 0, sizeof(struct abort_entry_24xx));
2996
2997 abt->entry_type = ABORT_IOCB_TYPE;
2998 abt->entry_count = 1;
2999 abt->handle = MAKE_HANDLE(req->id, abt->handle);
3000 abt->nport_handle = cpu_to_le16(fcport->loop_id);
3001 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
3002 abt->port_id[0] = fcport->d_id.b.al_pa;
3003 abt->port_id[1] = fcport->d_id.b.area;
3004 abt->port_id[2] = fcport->d_id.b.domain;
3005 abt->vp_index = fcport->vha->vp_idx;
3006
3007 abt->req_que_no = cpu_to_le16(req->id);
3008
3009 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
3010 if (rval != QLA_SUCCESS) {
3011 ql_dbg(ql_dbg_mbx, vha, 0x108e,
3012 "Failed to issue IOCB (%x).\n", rval);
3013 } else if (abt->entry_status != 0) {
3014 ql_dbg(ql_dbg_mbx, vha, 0x108f,
3015 "Failed to complete IOCB -- error status (%x).\n",
3016 abt->entry_status);
3017 rval = QLA_FUNCTION_FAILED;
3018 } else if (abt->nport_handle != cpu_to_le16(0)) {
3019 ql_dbg(ql_dbg_mbx, vha, 0x1090,
3020 "Failed to complete IOCB -- completion status (%x).\n",
3021 le16_to_cpu(abt->nport_handle));
3022 if (abt->nport_handle == CS_IOCB_ERROR)
3023 rval = QLA_FUNCTION_PARAMETER_ERROR;
3024 else
3025 rval = QLA_FUNCTION_FAILED;
3026 } else {
3027 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
3028 "Done %s.\n", __func__);
3029 }
3030
3031 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
3032
3033 return rval;
3034 }
3035
3036 struct tsk_mgmt_cmd {
3037 union {
3038 struct tsk_mgmt_entry tsk;
3039 struct sts_entry_24xx sts;
3040 } p;
3041 };
3042
3043 static int
3044 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
3045 uint64_t l, int tag)
3046 {
3047 int rval, rval2;
3048 struct tsk_mgmt_cmd *tsk;
3049 struct sts_entry_24xx *sts;
3050 dma_addr_t tsk_dma;
3051 scsi_qla_host_t *vha;
3052 struct qla_hw_data *ha;
3053 struct req_que *req;
3054 struct rsp_que *rsp;
3055 struct qla_qpair *qpair;
3056
3057 vha = fcport->vha;
3058 ha = vha->hw;
3059 req = vha->req;
3060
3061 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
3062 "Entered %s.\n", __func__);
3063
3064 if (vha->vp_idx && vha->qpair) {
3065 /* NPIV port */
3066 qpair = vha->qpair;
3067 rsp = qpair->rsp;
3068 req = qpair->req;
3069 } else {
3070 rsp = req->rsp;
3071 }
3072
3073 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
3074 if (tsk == NULL) {
3075 ql_log(ql_log_warn, vha, 0x1093,
3076 "Failed to allocate task management IOCB.\n");
3077 return QLA_MEMORY_ALLOC_FAILED;
3078 }
3079 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
3080
3081 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3082 tsk->p.tsk.entry_count = 1;
3083 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
3084 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
3085 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
3086 tsk->p.tsk.control_flags = cpu_to_le32(type);
3087 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3088 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3089 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
3090 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
3091 if (type == TCF_LUN_RESET) {
3092 int_to_scsilun(l, &tsk->p.tsk.lun);
3093 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3094 sizeof(tsk->p.tsk.lun));
3095 }
3096
3097 sts = &tsk->p.sts;
3098 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
3099 if (rval != QLA_SUCCESS) {
3100 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3101 "Failed to issue %s reset IOCB (%x).\n", name, rval);
3102 } else if (sts->entry_status != 0) {
3103 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3104 "Failed to complete IOCB -- error status (%x).\n",
3105 sts->entry_status);
3106 rval = QLA_FUNCTION_FAILED;
3107 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
3108 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3109 "Failed to complete IOCB -- completion status (%x).\n",
3110 le16_to_cpu(sts->comp_status));
3111 rval = QLA_FUNCTION_FAILED;
3112 } else if (le16_to_cpu(sts->scsi_status) &
3113 SS_RESPONSE_INFO_LEN_VALID) {
3114 if (le32_to_cpu(sts->rsp_data_len) < 4) {
3115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
3116 "Ignoring inconsistent data length -- not enough "
3117 "response info (%d).\n",
3118 le32_to_cpu(sts->rsp_data_len));
3119 } else if (sts->data[3]) {
3120 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3121 "Failed to complete IOCB -- response (%x).\n",
3122 sts->data[3]);
3123 rval = QLA_FUNCTION_FAILED;
3124 }
3125 }
3126
3127 /* Issue marker IOCB. */
3128 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
3129 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
3130 if (rval2 != QLA_SUCCESS) {
3131 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3132 "Failed to issue marker IOCB (%x).\n", rval2);
3133 } else {
3134 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3135 "Done %s.\n", __func__);
3136 }
3137
3138 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
3139
3140 return rval;
3141 }
3142
3143 int
3144 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
3145 {
3146 struct qla_hw_data *ha = fcport->vha->hw;
3147
3148 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3149 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3150
3151 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
3152 }
3153
3154 int
3155 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
3156 {
3157 struct qla_hw_data *ha = fcport->vha->hw;
3158
3159 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3160 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3161
3162 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
3163 }
3164
3165 int
3166 qla2x00_system_error(scsi_qla_host_t *vha)
3167 {
3168 int rval;
3169 mbx_cmd_t mc;
3170 mbx_cmd_t *mcp = &mc;
3171 struct qla_hw_data *ha = vha->hw;
3172
3173 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
3174 return QLA_FUNCTION_FAILED;
3175
3176 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3177 "Entered %s.\n", __func__);
3178
3179 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3180 mcp->out_mb = MBX_0;
3181 mcp->in_mb = MBX_0;
3182 mcp->tov = 5;
3183 mcp->flags = 0;
3184 rval = qla2x00_mailbox_command(vha, mcp);
3185
3186 if (rval != QLA_SUCCESS) {
3187 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
3188 } else {
3189 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3190 "Done %s.\n", __func__);
3191 }
3192
3193 return rval;
3194 }
3195
3196 int
3197 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3198 {
3199 int rval;
3200 mbx_cmd_t mc;
3201 mbx_cmd_t *mcp = &mc;
3202
3203 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3204 !IS_QLA27XX(vha->hw))
3205 return QLA_FUNCTION_FAILED;
3206
3207 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3208 "Entered %s.\n", __func__);
3209
3210 mcp->mb[0] = MBC_WRITE_SERDES;
3211 mcp->mb[1] = addr;
3212 if (IS_QLA2031(vha->hw))
3213 mcp->mb[2] = data & 0xff;
3214 else
3215 mcp->mb[2] = data;
3216
3217 mcp->mb[3] = 0;
3218 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3219 mcp->in_mb = MBX_0;
3220 mcp->tov = MBX_TOV_SECONDS;
3221 mcp->flags = 0;
3222 rval = qla2x00_mailbox_command(vha, mcp);
3223
3224 if (rval != QLA_SUCCESS) {
3225 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3226 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3227 } else {
3228 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3229 "Done %s.\n", __func__);
3230 }
3231
3232 return rval;
3233 }
3234
3235 int
3236 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3237 {
3238 int rval;
3239 mbx_cmd_t mc;
3240 mbx_cmd_t *mcp = &mc;
3241
3242 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3243 !IS_QLA27XX(vha->hw))
3244 return QLA_FUNCTION_FAILED;
3245
3246 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3247 "Entered %s.\n", __func__);
3248
3249 mcp->mb[0] = MBC_READ_SERDES;
3250 mcp->mb[1] = addr;
3251 mcp->mb[3] = 0;
3252 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3253 mcp->in_mb = MBX_1|MBX_0;
3254 mcp->tov = MBX_TOV_SECONDS;
3255 mcp->flags = 0;
3256 rval = qla2x00_mailbox_command(vha, mcp);
3257
3258 if (IS_QLA2031(vha->hw))
3259 *data = mcp->mb[1] & 0xff;
3260 else
3261 *data = mcp->mb[1];
3262
3263 if (rval != QLA_SUCCESS) {
3264 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3265 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3266 } else {
3267 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3268 "Done %s.\n", __func__);
3269 }
3270
3271 return rval;
3272 }
3273
3274 int
3275 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3276 {
3277 int rval;
3278 mbx_cmd_t mc;
3279 mbx_cmd_t *mcp = &mc;
3280
3281 if (!IS_QLA8044(vha->hw))
3282 return QLA_FUNCTION_FAILED;
3283
3284 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186,
3285 "Entered %s.\n", __func__);
3286
3287 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3288 mcp->mb[1] = HCS_WRITE_SERDES;
3289 mcp->mb[3] = LSW(addr);
3290 mcp->mb[4] = MSW(addr);
3291 mcp->mb[5] = LSW(data);
3292 mcp->mb[6] = MSW(data);
3293 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3294 mcp->in_mb = MBX_0;
3295 mcp->tov = MBX_TOV_SECONDS;
3296 mcp->flags = 0;
3297 rval = qla2x00_mailbox_command(vha, mcp);
3298
3299 if (rval != QLA_SUCCESS) {
3300 ql_dbg(ql_dbg_mbx, vha, 0x1187,
3301 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3302 } else {
3303 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3304 "Done %s.\n", __func__);
3305 }
3306
3307 return rval;
3308 }
3309
3310 int
3311 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3312 {
3313 int rval;
3314 mbx_cmd_t mc;
3315 mbx_cmd_t *mcp = &mc;
3316
3317 if (!IS_QLA8044(vha->hw))
3318 return QLA_FUNCTION_FAILED;
3319
3320 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3321 "Entered %s.\n", __func__);
3322
3323 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3324 mcp->mb[1] = HCS_READ_SERDES;
3325 mcp->mb[3] = LSW(addr);
3326 mcp->mb[4] = MSW(addr);
3327 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3328 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3329 mcp->tov = MBX_TOV_SECONDS;
3330 mcp->flags = 0;
3331 rval = qla2x00_mailbox_command(vha, mcp);
3332
3333 *data = mcp->mb[2] << 16 | mcp->mb[1];
3334
3335 if (rval != QLA_SUCCESS) {
3336 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3337 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3338 } else {
3339 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3340 "Done %s.\n", __func__);
3341 }
3342
3343 return rval;
3344 }
3345
3346 /**
3347 * qla2x00_set_serdes_params() -
3348 * @ha: HA context
3349 *
3350 * Returns
3351 */
3352 int
3353 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
3354 uint16_t sw_em_2g, uint16_t sw_em_4g)
3355 {
3356 int rval;
3357 mbx_cmd_t mc;
3358 mbx_cmd_t *mcp = &mc;
3359
3360 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3361 "Entered %s.\n", __func__);
3362
3363 mcp->mb[0] = MBC_SERDES_PARAMS;
3364 mcp->mb[1] = BIT_0;
3365 mcp->mb[2] = sw_em_1g | BIT_15;
3366 mcp->mb[3] = sw_em_2g | BIT_15;
3367 mcp->mb[4] = sw_em_4g | BIT_15;
3368 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3369 mcp->in_mb = MBX_0;
3370 mcp->tov = MBX_TOV_SECONDS;
3371 mcp->flags = 0;
3372 rval = qla2x00_mailbox_command(vha, mcp);
3373
3374 if (rval != QLA_SUCCESS) {
3375 /*EMPTY*/
3376 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3377 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3378 } else {
3379 /*EMPTY*/
3380 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3381 "Done %s.\n", __func__);
3382 }
3383
3384 return rval;
3385 }
3386
3387 int
3388 qla2x00_stop_firmware(scsi_qla_host_t *vha)
3389 {
3390 int rval;
3391 mbx_cmd_t mc;
3392 mbx_cmd_t *mcp = &mc;
3393
3394 if (!IS_FWI2_CAPABLE(vha->hw))
3395 return QLA_FUNCTION_FAILED;
3396
3397 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3398 "Entered %s.\n", __func__);
3399
3400 mcp->mb[0] = MBC_STOP_FIRMWARE;
3401 mcp->mb[1] = 0;
3402 mcp->out_mb = MBX_1|MBX_0;
3403 mcp->in_mb = MBX_0;
3404 mcp->tov = 5;
3405 mcp->flags = 0;
3406 rval = qla2x00_mailbox_command(vha, mcp);
3407
3408 if (rval != QLA_SUCCESS) {
3409 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
3410 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3411 rval = QLA_INVALID_COMMAND;
3412 } else {
3413 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3414 "Done %s.\n", __func__);
3415 }
3416
3417 return rval;
3418 }
3419
3420 int
3421 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
3422 uint16_t buffers)
3423 {
3424 int rval;
3425 mbx_cmd_t mc;
3426 mbx_cmd_t *mcp = &mc;
3427
3428 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3429 "Entered %s.\n", __func__);
3430
3431 if (!IS_FWI2_CAPABLE(vha->hw))
3432 return QLA_FUNCTION_FAILED;
3433
3434 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3435 return QLA_FUNCTION_FAILED;
3436
3437 mcp->mb[0] = MBC_TRACE_CONTROL;
3438 mcp->mb[1] = TC_EFT_ENABLE;
3439 mcp->mb[2] = LSW(eft_dma);
3440 mcp->mb[3] = MSW(eft_dma);
3441 mcp->mb[4] = LSW(MSD(eft_dma));
3442 mcp->mb[5] = MSW(MSD(eft_dma));
3443 mcp->mb[6] = buffers;
3444 mcp->mb[7] = TC_AEN_DISABLE;
3445 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3446 mcp->in_mb = MBX_1|MBX_0;
3447 mcp->tov = MBX_TOV_SECONDS;
3448 mcp->flags = 0;
3449 rval = qla2x00_mailbox_command(vha, mcp);
3450 if (rval != QLA_SUCCESS) {
3451 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3452 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3453 rval, mcp->mb[0], mcp->mb[1]);
3454 } else {
3455 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3456 "Done %s.\n", __func__);
3457 }
3458
3459 return rval;
3460 }
3461
3462 int
3463 qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
3464 {
3465 int rval;
3466 mbx_cmd_t mc;
3467 mbx_cmd_t *mcp = &mc;
3468
3469 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3470 "Entered %s.\n", __func__);
3471
3472 if (!IS_FWI2_CAPABLE(vha->hw))
3473 return QLA_FUNCTION_FAILED;
3474
3475 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3476 return QLA_FUNCTION_FAILED;
3477
3478 mcp->mb[0] = MBC_TRACE_CONTROL;
3479 mcp->mb[1] = TC_EFT_DISABLE;
3480 mcp->out_mb = MBX_1|MBX_0;
3481 mcp->in_mb = MBX_1|MBX_0;
3482 mcp->tov = MBX_TOV_SECONDS;
3483 mcp->flags = 0;
3484 rval = qla2x00_mailbox_command(vha, mcp);
3485 if (rval != QLA_SUCCESS) {
3486 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3487 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3488 rval, mcp->mb[0], mcp->mb[1]);
3489 } else {
3490 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3491 "Done %s.\n", __func__);
3492 }
3493
3494 return rval;
3495 }
3496
3497 int
3498 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
3499 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3500 {
3501 int rval;
3502 mbx_cmd_t mc;
3503 mbx_cmd_t *mcp = &mc;
3504
3505 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3506 "Entered %s.\n", __func__);
3507
3508 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
3509 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
3510 return QLA_FUNCTION_FAILED;
3511
3512 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3513 return QLA_FUNCTION_FAILED;
3514
3515 mcp->mb[0] = MBC_TRACE_CONTROL;
3516 mcp->mb[1] = TC_FCE_ENABLE;
3517 mcp->mb[2] = LSW(fce_dma);
3518 mcp->mb[3] = MSW(fce_dma);
3519 mcp->mb[4] = LSW(MSD(fce_dma));
3520 mcp->mb[5] = MSW(MSD(fce_dma));
3521 mcp->mb[6] = buffers;
3522 mcp->mb[7] = TC_AEN_DISABLE;
3523 mcp->mb[8] = 0;
3524 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3525 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3526 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3527 MBX_1|MBX_0;
3528 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3529 mcp->tov = MBX_TOV_SECONDS;
3530 mcp->flags = 0;
3531 rval = qla2x00_mailbox_command(vha, mcp);
3532 if (rval != QLA_SUCCESS) {
3533 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3534 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3535 rval, mcp->mb[0], mcp->mb[1]);
3536 } else {
3537 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3538 "Done %s.\n", __func__);
3539
3540 if (mb)
3541 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3542 if (dwords)
3543 *dwords = buffers;
3544 }
3545
3546 return rval;
3547 }
3548
3549 int
3550 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
3551 {
3552 int rval;
3553 mbx_cmd_t mc;
3554 mbx_cmd_t *mcp = &mc;
3555
3556 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3557 "Entered %s.\n", __func__);
3558
3559 if (!IS_FWI2_CAPABLE(vha->hw))
3560 return QLA_FUNCTION_FAILED;
3561
3562 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3563 return QLA_FUNCTION_FAILED;
3564
3565 mcp->mb[0] = MBC_TRACE_CONTROL;
3566 mcp->mb[1] = TC_FCE_DISABLE;
3567 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3568 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3569 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3570 MBX_1|MBX_0;
3571 mcp->tov = MBX_TOV_SECONDS;
3572 mcp->flags = 0;
3573 rval = qla2x00_mailbox_command(vha, mcp);
3574 if (rval != QLA_SUCCESS) {
3575 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3576 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3577 rval, mcp->mb[0], mcp->mb[1]);
3578 } else {
3579 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3580 "Done %s.\n", __func__);
3581
3582 if (wr)
3583 *wr = (uint64_t) mcp->mb[5] << 48 |
3584 (uint64_t) mcp->mb[4] << 32 |
3585 (uint64_t) mcp->mb[3] << 16 |
3586 (uint64_t) mcp->mb[2];
3587 if (rd)
3588 *rd = (uint64_t) mcp->mb[9] << 48 |
3589 (uint64_t) mcp->mb[8] << 32 |
3590 (uint64_t) mcp->mb[7] << 16 |
3591 (uint64_t) mcp->mb[6];
3592 }
3593
3594 return rval;
3595 }
3596
3597 int
3598 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3599 uint16_t *port_speed, uint16_t *mb)
3600 {
3601 int rval;
3602 mbx_cmd_t mc;
3603 mbx_cmd_t *mcp = &mc;
3604
3605 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3606 "Entered %s.\n", __func__);
3607
3608 if (!IS_IIDMA_CAPABLE(vha->hw))
3609 return QLA_FUNCTION_FAILED;
3610
3611 mcp->mb[0] = MBC_PORT_PARAMS;
3612 mcp->mb[1] = loop_id;
3613 mcp->mb[2] = mcp->mb[3] = 0;
3614 mcp->mb[9] = vha->vp_idx;
3615 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3616 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3617 mcp->tov = MBX_TOV_SECONDS;
3618 mcp->flags = 0;
3619 rval = qla2x00_mailbox_command(vha, mcp);
3620
3621 /* Return mailbox statuses. */
3622 if (mb != NULL) {
3623 mb[0] = mcp->mb[0];
3624 mb[1] = mcp->mb[1];
3625 mb[3] = mcp->mb[3];
3626 }
3627
3628 if (rval != QLA_SUCCESS) {
3629 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
3630 } else {
3631 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3632 "Done %s.\n", __func__);
3633 if (port_speed)
3634 *port_speed = mcp->mb[3];
3635 }
3636
3637 return rval;
3638 }
3639
3640 int
3641 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3642 uint16_t port_speed, uint16_t *mb)
3643 {
3644 int rval;
3645 mbx_cmd_t mc;
3646 mbx_cmd_t *mcp = &mc;
3647
3648 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3649 "Entered %s.\n", __func__);
3650
3651 if (!IS_IIDMA_CAPABLE(vha->hw))
3652 return QLA_FUNCTION_FAILED;
3653
3654 mcp->mb[0] = MBC_PORT_PARAMS;
3655 mcp->mb[1] = loop_id;
3656 mcp->mb[2] = BIT_0;
3657 if (IS_CNA_CAPABLE(vha->hw))
3658 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3659 else
3660 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3661 mcp->mb[9] = vha->vp_idx;
3662 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3663 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3664 mcp->tov = MBX_TOV_SECONDS;
3665 mcp->flags = 0;
3666 rval = qla2x00_mailbox_command(vha, mcp);
3667
3668 /* Return mailbox statuses. */
3669 if (mb != NULL) {
3670 mb[0] = mcp->mb[0];
3671 mb[1] = mcp->mb[1];
3672 mb[3] = mcp->mb[3];
3673 }
3674
3675 if (rval != QLA_SUCCESS) {
3676 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3677 "Failed=%x.\n", rval);
3678 } else {
3679 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3680 "Done %s.\n", __func__);
3681 }
3682
3683 return rval;
3684 }
3685
3686 void
3687 qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
3688 struct vp_rpt_id_entry_24xx *rptid_entry)
3689 {
3690 uint8_t vp_idx;
3691 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
3692 struct qla_hw_data *ha = vha->hw;
3693 scsi_qla_host_t *vp;
3694 unsigned long flags;
3695 int found;
3696
3697 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3698 "Entered %s.\n", __func__);
3699
3700 if (rptid_entry->entry_status != 0)
3701 return;
3702
3703 if (rptid_entry->format == 0) {
3704 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
3705 "Format 0 : Number of VPs setup %d, number of "
3706 "VPs acquired %d.\n",
3707 MSB(le16_to_cpu(rptid_entry->vp_count)),
3708 LSB(le16_to_cpu(rptid_entry->vp_count)));
3709 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
3710 "Primary port id %02x%02x%02x.\n",
3711 rptid_entry->port_id[2], rptid_entry->port_id[1],
3712 rptid_entry->port_id[0]);
3713 } else if (rptid_entry->format == 1) {
3714 vp_idx = LSB(stat);
3715 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
3716 "Format 1: VP[%d] enabled - status %d - with "
3717 "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
3718 rptid_entry->port_id[2], rptid_entry->port_id[1],
3719 rptid_entry->port_id[0]);
3720
3721 /* buffer to buffer credit flag */
3722 vha->flags.bbcr_enable = (rptid_entry->bbcr & 0xf) != 0;
3723
3724 /* FA-WWN is only for physical port */
3725 if (!vp_idx) {
3726 void *wwpn = ha->init_cb->port_name;
3727
3728 if (!MSB(stat)) {
3729 if (rptid_entry->vp_idx_map[1] & BIT_6)
3730 wwpn = rptid_entry->reserved_4 + 8;
3731 }
3732 memcpy(vha->port_name, wwpn, WWN_SIZE);
3733 fc_host_port_name(vha->host) =
3734 wwn_to_u64(vha->port_name);
3735 ql_dbg(ql_dbg_mbx, vha, 0x1018,
3736 "FA-WWN portname %016llx (%x)\n",
3737 fc_host_port_name(vha->host), MSB(stat));
3738 }
3739
3740 vp = vha;
3741 if (vp_idx == 0)
3742 goto reg_needed;
3743
3744 if (MSB(stat) != 0 && MSB(stat) != 2) {
3745 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3746 "Could not acquire ID for VP[%d].\n", vp_idx);
3747 return;
3748 }
3749
3750 found = 0;
3751 spin_lock_irqsave(&ha->vport_slock, flags);
3752 list_for_each_entry(vp, &ha->vp_list, list) {
3753 if (vp_idx == vp->vp_idx) {
3754 found = 1;
3755 break;
3756 }
3757 }
3758 spin_unlock_irqrestore(&ha->vport_slock, flags);
3759
3760 if (!found)
3761 return;
3762
3763 vp->d_id.b.domain = rptid_entry->port_id[2];
3764 vp->d_id.b.area = rptid_entry->port_id[1];
3765 vp->d_id.b.al_pa = rptid_entry->port_id[0];
3766
3767 /*
3768 * Cannot configure here as we are still sitting on the
3769 * response queue. Handle it in dpc context.
3770 */
3771 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3772
3773 reg_needed:
3774 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3775 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3776 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
3777 qla2xxx_wake_dpc(vha);
3778 }
3779 }
3780
3781 /*
3782 * qla24xx_modify_vp_config
3783 * Change VP configuration for vha
3784 *
3785 * Input:
3786 * vha = adapter block pointer.
3787 *
3788 * Returns:
3789 * qla2xxx local function return status code.
3790 *
3791 * Context:
3792 * Kernel context.
3793 */
3794 int
3795 qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3796 {
3797 int rval;
3798 struct vp_config_entry_24xx *vpmod;
3799 dma_addr_t vpmod_dma;
3800 struct qla_hw_data *ha = vha->hw;
3801 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3802
3803 /* This can be called by the parent */
3804
3805 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3806 "Entered %s.\n", __func__);
3807
3808 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
3809 if (!vpmod) {
3810 ql_log(ql_log_warn, vha, 0x10bc,
3811 "Failed to allocate modify VP IOCB.\n");
3812 return QLA_MEMORY_ALLOC_FAILED;
3813 }
3814
3815 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3816 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3817 vpmod->entry_count = 1;
3818 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3819 vpmod->vp_count = 1;
3820 vpmod->vp_index1 = vha->vp_idx;
3821 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
3822
3823 qlt_modify_vp_config(vha, vpmod);
3824
3825 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3826 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3827 vpmod->entry_count = 1;
3828
3829 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
3830 if (rval != QLA_SUCCESS) {
3831 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3832 "Failed to issue VP config IOCB (%x).\n", rval);
3833 } else if (vpmod->comp_status != 0) {
3834 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3835 "Failed to complete IOCB -- error status (%x).\n",
3836 vpmod->comp_status);
3837 rval = QLA_FUNCTION_FAILED;
3838 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
3839 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3840 "Failed to complete IOCB -- completion status (%x).\n",
3841 le16_to_cpu(vpmod->comp_status));
3842 rval = QLA_FUNCTION_FAILED;
3843 } else {
3844 /* EMPTY */
3845 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3846 "Done %s.\n", __func__);
3847 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3848 }
3849 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
3850
3851 return rval;
3852 }
3853
3854 /*
3855 * qla24xx_control_vp
3856 * Enable a virtual port for given host
3857 *
3858 * Input:
3859 * ha = adapter block pointer.
3860 * vhba = virtual adapter (unused)
3861 * index = index number for enabled VP
3862 *
3863 * Returns:
3864 * qla2xxx local function return status code.
3865 *
3866 * Context:
3867 * Kernel context.
3868 */
3869 int
3870 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3871 {
3872 int rval;
3873 int map, pos;
3874 struct vp_ctrl_entry_24xx *vce;
3875 dma_addr_t vce_dma;
3876 struct qla_hw_data *ha = vha->hw;
3877 int vp_index = vha->vp_idx;
3878 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3879
3880 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
3881 "Entered %s enabling index %d.\n", __func__, vp_index);
3882
3883 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
3884 return QLA_PARAMETER_ERROR;
3885
3886 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3887 if (!vce) {
3888 ql_log(ql_log_warn, vha, 0x10c2,
3889 "Failed to allocate VP control IOCB.\n");
3890 return QLA_MEMORY_ALLOC_FAILED;
3891 }
3892 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3893
3894 vce->entry_type = VP_CTRL_IOCB_TYPE;
3895 vce->entry_count = 1;
3896 vce->command = cpu_to_le16(cmd);
3897 vce->vp_count = cpu_to_le16(1);
3898
3899 /* index map in firmware starts with 1; decrement index
3900 * this is ok as we never use index 0
3901 */
3902 map = (vp_index - 1) / 8;
3903 pos = (vp_index - 1) & 7;
3904 mutex_lock(&ha->vport_lock);
3905 vce->vp_idx_map[map] |= 1 << pos;
3906 mutex_unlock(&ha->vport_lock);
3907
3908 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
3909 if (rval != QLA_SUCCESS) {
3910 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3911 "Failed to issue VP control IOCB (%x).\n", rval);
3912 } else if (vce->entry_status != 0) {
3913 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3914 "Failed to complete IOCB -- error status (%x).\n",
3915 vce->entry_status);
3916 rval = QLA_FUNCTION_FAILED;
3917 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) {
3918 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3919 "Failed to complet IOCB -- completion status (%x).\n",
3920 le16_to_cpu(vce->comp_status));
3921 rval = QLA_FUNCTION_FAILED;
3922 } else {
3923 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3924 "Done %s.\n", __func__);
3925 }
3926
3927 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3928
3929 return rval;
3930 }
3931
3932 /*
3933 * qla2x00_send_change_request
3934 * Receive or disable RSCN request from fabric controller
3935 *
3936 * Input:
3937 * ha = adapter block pointer
3938 * format = registration format:
3939 * 0 - Reserved
3940 * 1 - Fabric detected registration
3941 * 2 - N_port detected registration
3942 * 3 - Full registration
3943 * FF - clear registration
3944 * vp_idx = Virtual port index
3945 *
3946 * Returns:
3947 * qla2x00 local function return status code.
3948 *
3949 * Context:
3950 * Kernel Context
3951 */
3952
3953 int
3954 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
3955 uint16_t vp_idx)
3956 {
3957 int rval;
3958 mbx_cmd_t mc;
3959 mbx_cmd_t *mcp = &mc;
3960
3961 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3962 "Entered %s.\n", __func__);
3963
3964 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3965 mcp->mb[1] = format;
3966 mcp->mb[9] = vp_idx;
3967 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3968 mcp->in_mb = MBX_0|MBX_1;
3969 mcp->tov = MBX_TOV_SECONDS;
3970 mcp->flags = 0;
3971 rval = qla2x00_mailbox_command(vha, mcp);
3972
3973 if (rval == QLA_SUCCESS) {
3974 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3975 rval = BIT_1;
3976 }
3977 } else
3978 rval = BIT_1;
3979
3980 return rval;
3981 }
3982
3983 int
3984 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
3985 uint32_t size)
3986 {
3987 int rval;
3988 mbx_cmd_t mc;
3989 mbx_cmd_t *mcp = &mc;
3990
3991 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3992 "Entered %s.\n", __func__);
3993
3994 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
3995 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3996 mcp->mb[8] = MSW(addr);
3997 mcp->out_mb = MBX_8|MBX_0;
3998 } else {
3999 mcp->mb[0] = MBC_DUMP_RISC_RAM;
4000 mcp->out_mb = MBX_0;
4001 }
4002 mcp->mb[1] = LSW(addr);
4003 mcp->mb[2] = MSW(req_dma);
4004 mcp->mb[3] = LSW(req_dma);
4005 mcp->mb[6] = MSW(MSD(req_dma));
4006 mcp->mb[7] = LSW(MSD(req_dma));
4007 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
4008 if (IS_FWI2_CAPABLE(vha->hw)) {
4009 mcp->mb[4] = MSW(size);
4010 mcp->mb[5] = LSW(size);
4011 mcp->out_mb |= MBX_5|MBX_4;
4012 } else {
4013 mcp->mb[4] = LSW(size);
4014 mcp->out_mb |= MBX_4;
4015 }
4016
4017 mcp->in_mb = MBX_0;
4018 mcp->tov = MBX_TOV_SECONDS;
4019 mcp->flags = 0;
4020 rval = qla2x00_mailbox_command(vha, mcp);
4021
4022 if (rval != QLA_SUCCESS) {
4023 ql_dbg(ql_dbg_mbx, vha, 0x1008,
4024 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4025 } else {
4026 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
4027 "Done %s.\n", __func__);
4028 }
4029
4030 return rval;
4031 }
4032 /* 84XX Support **************************************************************/
4033
4034 struct cs84xx_mgmt_cmd {
4035 union {
4036 struct verify_chip_entry_84xx req;
4037 struct verify_chip_rsp_84xx rsp;
4038 } p;
4039 };
4040
4041 int
4042 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4043 {
4044 int rval, retry;
4045 struct cs84xx_mgmt_cmd *mn;
4046 dma_addr_t mn_dma;
4047 uint16_t options;
4048 unsigned long flags;
4049 struct qla_hw_data *ha = vha->hw;
4050
4051 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4052 "Entered %s.\n", __func__);
4053
4054 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4055 if (mn == NULL) {
4056 return QLA_MEMORY_ALLOC_FAILED;
4057 }
4058
4059 /* Force Update? */
4060 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4061 /* Diagnostic firmware? */
4062 /* options |= MENLO_DIAG_FW; */
4063 /* We update the firmware with only one data sequence. */
4064 options |= VCO_END_OF_DATA;
4065
4066 do {
4067 retry = 0;
4068 memset(mn, 0, sizeof(*mn));
4069 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4070 mn->p.req.entry_count = 1;
4071 mn->p.req.options = cpu_to_le16(options);
4072
4073 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4074 "Dump of Verify Request.\n");
4075 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4076 (uint8_t *)mn, sizeof(*mn));
4077
4078 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4079 if (rval != QLA_SUCCESS) {
4080 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4081 "Failed to issue verify IOCB (%x).\n", rval);
4082 goto verify_done;
4083 }
4084
4085 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4086 "Dump of Verify Response.\n");
4087 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4088 (uint8_t *)mn, sizeof(*mn));
4089
4090 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4091 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4092 le16_to_cpu(mn->p.rsp.failure_code) : 0;
4093 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
4094 "cs=%x fc=%x.\n", status[0], status[1]);
4095
4096 if (status[0] != CS_COMPLETE) {
4097 rval = QLA_FUNCTION_FAILED;
4098 if (!(options & VCO_DONT_UPDATE_FW)) {
4099 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4100 "Firmware update failed. Retrying "
4101 "without update firmware.\n");
4102 options |= VCO_DONT_UPDATE_FW;
4103 options &= ~VCO_FORCE_UPDATE;
4104 retry = 1;
4105 }
4106 } else {
4107 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
4108 "Firmware updated to %x.\n",
4109 le32_to_cpu(mn->p.rsp.fw_ver));
4110
4111 /* NOTE: we only update OP firmware. */
4112 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4113 ha->cs84xx->op_fw_version =
4114 le32_to_cpu(mn->p.rsp.fw_ver);
4115 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4116 flags);
4117 }
4118 } while (retry);
4119
4120 verify_done:
4121 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4122
4123 if (rval != QLA_SUCCESS) {
4124 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4125 "Failed=%x.\n", rval);
4126 } else {
4127 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4128 "Done %s.\n", __func__);
4129 }
4130
4131 return rval;
4132 }
4133
4134 int
4135 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
4136 {
4137 int rval;
4138 unsigned long flags;
4139 mbx_cmd_t mc;
4140 mbx_cmd_t *mcp = &mc;
4141 struct qla_hw_data *ha = vha->hw;
4142
4143 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4144 "Entered %s.\n", __func__);
4145
4146 if (IS_SHADOW_REG_CAPABLE(ha))
4147 req->options |= BIT_13;
4148
4149 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
4150 mcp->mb[1] = req->options;
4151 mcp->mb[2] = MSW(LSD(req->dma));
4152 mcp->mb[3] = LSW(LSD(req->dma));
4153 mcp->mb[6] = MSW(MSD(req->dma));
4154 mcp->mb[7] = LSW(MSD(req->dma));
4155 mcp->mb[5] = req->length;
4156 if (req->rsp)
4157 mcp->mb[10] = req->rsp->id;
4158 mcp->mb[12] = req->qos;
4159 mcp->mb[11] = req->vp_idx;
4160 mcp->mb[13] = req->rid;
4161 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4162 mcp->mb[15] = 0;
4163
4164 mcp->mb[4] = req->id;
4165 /* que in ptr index */
4166 mcp->mb[8] = 0;
4167 /* que out ptr index */
4168 mcp->mb[9] = *req->out_ptr = 0;
4169 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4170 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4171 mcp->in_mb = MBX_0;
4172 mcp->flags = MBX_DMA_OUT;
4173 mcp->tov = MBX_TOV_SECONDS * 2;
4174
4175 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
4176 mcp->in_mb |= MBX_1;
4177 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
4178 mcp->out_mb |= MBX_15;
4179 /* debug q create issue in SR-IOV */
4180 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4181 }
4182
4183 spin_lock_irqsave(&ha->hardware_lock, flags);
4184 if (!(req->options & BIT_0)) {
4185 WRT_REG_DWORD(req->req_q_in, 0);
4186 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
4187 WRT_REG_DWORD(req->req_q_out, 0);
4188 }
4189 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4190
4191 rval = qla2x00_mailbox_command(vha, mcp);
4192 if (rval != QLA_SUCCESS) {
4193 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4194 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4195 } else {
4196 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4197 "Done %s.\n", __func__);
4198 }
4199
4200 return rval;
4201 }
4202
4203 int
4204 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
4205 {
4206 int rval;
4207 unsigned long flags;
4208 mbx_cmd_t mc;
4209 mbx_cmd_t *mcp = &mc;
4210 struct qla_hw_data *ha = vha->hw;
4211
4212 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4213 "Entered %s.\n", __func__);
4214
4215 if (IS_SHADOW_REG_CAPABLE(ha))
4216 rsp->options |= BIT_13;
4217
4218 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
4219 mcp->mb[1] = rsp->options;
4220 mcp->mb[2] = MSW(LSD(rsp->dma));
4221 mcp->mb[3] = LSW(LSD(rsp->dma));
4222 mcp->mb[6] = MSW(MSD(rsp->dma));
4223 mcp->mb[7] = LSW(MSD(rsp->dma));
4224 mcp->mb[5] = rsp->length;
4225 mcp->mb[14] = rsp->msix->entry;
4226 mcp->mb[13] = rsp->rid;
4227 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4228 mcp->mb[15] = 0;
4229
4230 mcp->mb[4] = rsp->id;
4231 /* que in ptr index */
4232 mcp->mb[8] = *rsp->in_ptr = 0;
4233 /* que out ptr index */
4234 mcp->mb[9] = 0;
4235 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
4236 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4237 mcp->in_mb = MBX_0;
4238 mcp->flags = MBX_DMA_OUT;
4239 mcp->tov = MBX_TOV_SECONDS * 2;
4240
4241 if (IS_QLA81XX(ha)) {
4242 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4243 mcp->in_mb |= MBX_1;
4244 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
4245 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4246 mcp->in_mb |= MBX_1;
4247 /* debug q create issue in SR-IOV */
4248 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4249 }
4250
4251 spin_lock_irqsave(&ha->hardware_lock, flags);
4252 if (!(rsp->options & BIT_0)) {
4253 WRT_REG_DWORD(rsp->rsp_q_out, 0);
4254 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
4255 WRT_REG_DWORD(rsp->rsp_q_in, 0);
4256 }
4257
4258 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4259
4260 rval = qla2x00_mailbox_command(vha, mcp);
4261 if (rval != QLA_SUCCESS) {
4262 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4263 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4264 } else {
4265 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4266 "Done %s.\n", __func__);
4267 }
4268
4269 return rval;
4270 }
4271
4272 int
4273 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4274 {
4275 int rval;
4276 mbx_cmd_t mc;
4277 mbx_cmd_t *mcp = &mc;
4278
4279 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4280 "Entered %s.\n", __func__);
4281
4282 mcp->mb[0] = MBC_IDC_ACK;
4283 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4284 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4285 mcp->in_mb = MBX_0;
4286 mcp->tov = MBX_TOV_SECONDS;
4287 mcp->flags = 0;
4288 rval = qla2x00_mailbox_command(vha, mcp);
4289
4290 if (rval != QLA_SUCCESS) {
4291 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4292 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4293 } else {
4294 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4295 "Done %s.\n", __func__);
4296 }
4297
4298 return rval;
4299 }
4300
4301 int
4302 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4303 {
4304 int rval;
4305 mbx_cmd_t mc;
4306 mbx_cmd_t *mcp = &mc;
4307
4308 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4309 "Entered %s.\n", __func__);
4310
4311 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4312 !IS_QLA27XX(vha->hw))
4313 return QLA_FUNCTION_FAILED;
4314
4315 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4316 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4317 mcp->out_mb = MBX_1|MBX_0;
4318 mcp->in_mb = MBX_1|MBX_0;
4319 mcp->tov = MBX_TOV_SECONDS;
4320 mcp->flags = 0;
4321 rval = qla2x00_mailbox_command(vha, mcp);
4322
4323 if (rval != QLA_SUCCESS) {
4324 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4325 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4326 rval, mcp->mb[0], mcp->mb[1]);
4327 } else {
4328 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4329 "Done %s.\n", __func__);
4330 *sector_size = mcp->mb[1];
4331 }
4332
4333 return rval;
4334 }
4335
4336 int
4337 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4338 {
4339 int rval;
4340 mbx_cmd_t mc;
4341 mbx_cmd_t *mcp = &mc;
4342
4343 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4344 !IS_QLA27XX(vha->hw))
4345 return QLA_FUNCTION_FAILED;
4346
4347 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4348 "Entered %s.\n", __func__);
4349
4350 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4351 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4352 FAC_OPT_CMD_WRITE_PROTECT;
4353 mcp->out_mb = MBX_1|MBX_0;
4354 mcp->in_mb = MBX_1|MBX_0;
4355 mcp->tov = MBX_TOV_SECONDS;
4356 mcp->flags = 0;
4357 rval = qla2x00_mailbox_command(vha, mcp);
4358
4359 if (rval != QLA_SUCCESS) {
4360 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4361 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4362 rval, mcp->mb[0], mcp->mb[1]);
4363 } else {
4364 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4365 "Done %s.\n", __func__);
4366 }
4367
4368 return rval;
4369 }
4370
4371 int
4372 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4373 {
4374 int rval;
4375 mbx_cmd_t mc;
4376 mbx_cmd_t *mcp = &mc;
4377
4378 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4379 !IS_QLA27XX(vha->hw))
4380 return QLA_FUNCTION_FAILED;
4381
4382 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4383 "Entered %s.\n", __func__);
4384
4385 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4386 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4387 mcp->mb[2] = LSW(start);
4388 mcp->mb[3] = MSW(start);
4389 mcp->mb[4] = LSW(finish);
4390 mcp->mb[5] = MSW(finish);
4391 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4392 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4393 mcp->tov = MBX_TOV_SECONDS;
4394 mcp->flags = 0;
4395 rval = qla2x00_mailbox_command(vha, mcp);
4396
4397 if (rval != QLA_SUCCESS) {
4398 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4399 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4400 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4401 } else {
4402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4403 "Done %s.\n", __func__);
4404 }
4405
4406 return rval;
4407 }
4408
4409 int
4410 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4411 {
4412 int rval = 0;
4413 mbx_cmd_t mc;
4414 mbx_cmd_t *mcp = &mc;
4415
4416 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4417 "Entered %s.\n", __func__);
4418
4419 mcp->mb[0] = MBC_RESTART_MPI_FW;
4420 mcp->out_mb = MBX_0;
4421 mcp->in_mb = MBX_0|MBX_1;
4422 mcp->tov = MBX_TOV_SECONDS;
4423 mcp->flags = 0;
4424 rval = qla2x00_mailbox_command(vha, mcp);
4425
4426 if (rval != QLA_SUCCESS) {
4427 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4428 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4429 rval, mcp->mb[0], mcp->mb[1]);
4430 } else {
4431 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4432 "Done %s.\n", __func__);
4433 }
4434
4435 return rval;
4436 }
4437
4438 int
4439 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4440 {
4441 int rval;
4442 mbx_cmd_t mc;
4443 mbx_cmd_t *mcp = &mc;
4444 int i;
4445 int len;
4446 uint16_t *str;
4447 struct qla_hw_data *ha = vha->hw;
4448
4449 if (!IS_P3P_TYPE(ha))
4450 return QLA_FUNCTION_FAILED;
4451
4452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4453 "Entered %s.\n", __func__);
4454
4455 str = (void *)version;
4456 len = strlen(version);
4457
4458 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4459 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4460 mcp->out_mb = MBX_1|MBX_0;
4461 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4462 mcp->mb[i] = cpu_to_le16p(str);
4463 mcp->out_mb |= 1<<i;
4464 }
4465 for (; i < 16; i++) {
4466 mcp->mb[i] = 0;
4467 mcp->out_mb |= 1<<i;
4468 }
4469 mcp->in_mb = MBX_1|MBX_0;
4470 mcp->tov = MBX_TOV_SECONDS;
4471 mcp->flags = 0;
4472 rval = qla2x00_mailbox_command(vha, mcp);
4473
4474 if (rval != QLA_SUCCESS) {
4475 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4476 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4477 } else {
4478 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4479 "Done %s.\n", __func__);
4480 }
4481
4482 return rval;
4483 }
4484
4485 int
4486 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4487 {
4488 int rval;
4489 mbx_cmd_t mc;
4490 mbx_cmd_t *mcp = &mc;
4491 int len;
4492 uint16_t dwlen;
4493 uint8_t *str;
4494 dma_addr_t str_dma;
4495 struct qla_hw_data *ha = vha->hw;
4496
4497 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4498 IS_P3P_TYPE(ha))
4499 return QLA_FUNCTION_FAILED;
4500
4501 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4502 "Entered %s.\n", __func__);
4503
4504 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4505 if (!str) {
4506 ql_log(ql_log_warn, vha, 0x117f,
4507 "Failed to allocate driver version param.\n");
4508 return QLA_MEMORY_ALLOC_FAILED;
4509 }
4510
4511 memcpy(str, "\x7\x3\x11\x0", 4);
4512 dwlen = str[0];
4513 len = dwlen * 4 - 4;
4514 memset(str + 4, 0, len);
4515 if (len > strlen(version))
4516 len = strlen(version);
4517 memcpy(str + 4, version, len);
4518
4519 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4520 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4521 mcp->mb[2] = MSW(LSD(str_dma));
4522 mcp->mb[3] = LSW(LSD(str_dma));
4523 mcp->mb[6] = MSW(MSD(str_dma));
4524 mcp->mb[7] = LSW(MSD(str_dma));
4525 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4526 mcp->in_mb = MBX_1|MBX_0;
4527 mcp->tov = MBX_TOV_SECONDS;
4528 mcp->flags = 0;
4529 rval = qla2x00_mailbox_command(vha, mcp);
4530
4531 if (rval != QLA_SUCCESS) {
4532 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4533 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4534 } else {
4535 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4536 "Done %s.\n", __func__);
4537 }
4538
4539 dma_pool_free(ha->s_dma_pool, str, str_dma);
4540
4541 return rval;
4542 }
4543
4544 static int
4545 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4546 {
4547 int rval;
4548 mbx_cmd_t mc;
4549 mbx_cmd_t *mcp = &mc;
4550
4551 if (!IS_FWI2_CAPABLE(vha->hw))
4552 return QLA_FUNCTION_FAILED;
4553
4554 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4555 "Entered %s.\n", __func__);
4556
4557 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4558 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4559 mcp->out_mb = MBX_1|MBX_0;
4560 mcp->in_mb = MBX_1|MBX_0;
4561 mcp->tov = MBX_TOV_SECONDS;
4562 mcp->flags = 0;
4563 rval = qla2x00_mailbox_command(vha, mcp);
4564 *temp = mcp->mb[1];
4565
4566 if (rval != QLA_SUCCESS) {
4567 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4568 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4569 } else {
4570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4571 "Done %s.\n", __func__);
4572 }
4573
4574 return rval;
4575 }
4576
4577 int
4578 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4579 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
4580 {
4581 int rval;
4582 mbx_cmd_t mc;
4583 mbx_cmd_t *mcp = &mc;
4584 struct qla_hw_data *ha = vha->hw;
4585
4586 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4587 "Entered %s.\n", __func__);
4588
4589 if (!IS_FWI2_CAPABLE(ha))
4590 return QLA_FUNCTION_FAILED;
4591
4592 if (len == 1)
4593 opt |= BIT_0;
4594
4595 mcp->mb[0] = MBC_READ_SFP;
4596 mcp->mb[1] = dev;
4597 mcp->mb[2] = MSW(sfp_dma);
4598 mcp->mb[3] = LSW(sfp_dma);
4599 mcp->mb[6] = MSW(MSD(sfp_dma));
4600 mcp->mb[7] = LSW(MSD(sfp_dma));
4601 mcp->mb[8] = len;
4602 mcp->mb[9] = off;
4603 mcp->mb[10] = opt;
4604 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4605 mcp->in_mb = MBX_1|MBX_0;
4606 mcp->tov = MBX_TOV_SECONDS;
4607 mcp->flags = 0;
4608 rval = qla2x00_mailbox_command(vha, mcp);
4609
4610 if (opt & BIT_0)
4611 *sfp = mcp->mb[1];
4612
4613 if (rval != QLA_SUCCESS) {
4614 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4615 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4616 } else {
4617 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4618 "Done %s.\n", __func__);
4619 }
4620
4621 return rval;
4622 }
4623
4624 int
4625 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4626 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
4627 {
4628 int rval;
4629 mbx_cmd_t mc;
4630 mbx_cmd_t *mcp = &mc;
4631 struct qla_hw_data *ha = vha->hw;
4632
4633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4634 "Entered %s.\n", __func__);
4635
4636 if (!IS_FWI2_CAPABLE(ha))
4637 return QLA_FUNCTION_FAILED;
4638
4639 if (len == 1)
4640 opt |= BIT_0;
4641
4642 if (opt & BIT_0)
4643 len = *sfp;
4644
4645 mcp->mb[0] = MBC_WRITE_SFP;
4646 mcp->mb[1] = dev;
4647 mcp->mb[2] = MSW(sfp_dma);
4648 mcp->mb[3] = LSW(sfp_dma);
4649 mcp->mb[6] = MSW(MSD(sfp_dma));
4650 mcp->mb[7] = LSW(MSD(sfp_dma));
4651 mcp->mb[8] = len;
4652 mcp->mb[9] = off;
4653 mcp->mb[10] = opt;
4654 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4655 mcp->in_mb = MBX_1|MBX_0;
4656 mcp->tov = MBX_TOV_SECONDS;
4657 mcp->flags = 0;
4658 rval = qla2x00_mailbox_command(vha, mcp);
4659
4660 if (rval != QLA_SUCCESS) {
4661 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4662 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4663 } else {
4664 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4665 "Done %s.\n", __func__);
4666 }
4667
4668 return rval;
4669 }
4670
4671 int
4672 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4673 uint16_t size_in_bytes, uint16_t *actual_size)
4674 {
4675 int rval;
4676 mbx_cmd_t mc;
4677 mbx_cmd_t *mcp = &mc;
4678
4679 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4680 "Entered %s.\n", __func__);
4681
4682 if (!IS_CNA_CAPABLE(vha->hw))
4683 return QLA_FUNCTION_FAILED;
4684
4685 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4686 mcp->mb[2] = MSW(stats_dma);
4687 mcp->mb[3] = LSW(stats_dma);
4688 mcp->mb[6] = MSW(MSD(stats_dma));
4689 mcp->mb[7] = LSW(MSD(stats_dma));
4690 mcp->mb[8] = size_in_bytes >> 2;
4691 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4692 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4693 mcp->tov = MBX_TOV_SECONDS;
4694 mcp->flags = 0;
4695 rval = qla2x00_mailbox_command(vha, mcp);
4696
4697 if (rval != QLA_SUCCESS) {
4698 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4699 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4700 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4701 } else {
4702 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4703 "Done %s.\n", __func__);
4704
4705
4706 *actual_size = mcp->mb[2] << 2;
4707 }
4708
4709 return rval;
4710 }
4711
4712 int
4713 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4714 uint16_t size)
4715 {
4716 int rval;
4717 mbx_cmd_t mc;
4718 mbx_cmd_t *mcp = &mc;
4719
4720 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4721 "Entered %s.\n", __func__);
4722
4723 if (!IS_CNA_CAPABLE(vha->hw))
4724 return QLA_FUNCTION_FAILED;
4725
4726 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4727 mcp->mb[1] = 0;
4728 mcp->mb[2] = MSW(tlv_dma);
4729 mcp->mb[3] = LSW(tlv_dma);
4730 mcp->mb[6] = MSW(MSD(tlv_dma));
4731 mcp->mb[7] = LSW(MSD(tlv_dma));
4732 mcp->mb[8] = size;
4733 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4734 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4735 mcp->tov = MBX_TOV_SECONDS;
4736 mcp->flags = 0;
4737 rval = qla2x00_mailbox_command(vha, mcp);
4738
4739 if (rval != QLA_SUCCESS) {
4740 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4741 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4742 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4743 } else {
4744 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4745 "Done %s.\n", __func__);
4746 }
4747
4748 return rval;
4749 }
4750
4751 int
4752 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4753 {
4754 int rval;
4755 mbx_cmd_t mc;
4756 mbx_cmd_t *mcp = &mc;
4757
4758 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4759 "Entered %s.\n", __func__);
4760
4761 if (!IS_FWI2_CAPABLE(vha->hw))
4762 return QLA_FUNCTION_FAILED;
4763
4764 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4765 mcp->mb[1] = LSW(risc_addr);
4766 mcp->mb[8] = MSW(risc_addr);
4767 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4768 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4769 mcp->tov = 30;
4770 mcp->flags = 0;
4771 rval = qla2x00_mailbox_command(vha, mcp);
4772 if (rval != QLA_SUCCESS) {
4773 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4774 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4775 } else {
4776 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4777 "Done %s.\n", __func__);
4778 *data = mcp->mb[3] << 16 | mcp->mb[2];
4779 }
4780
4781 return rval;
4782 }
4783
4784 int
4785 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4786 uint16_t *mresp)
4787 {
4788 int rval;
4789 mbx_cmd_t mc;
4790 mbx_cmd_t *mcp = &mc;
4791
4792 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4793 "Entered %s.\n", __func__);
4794
4795 memset(mcp->mb, 0 , sizeof(mcp->mb));
4796 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4797 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4798
4799 /* transfer count */
4800 mcp->mb[10] = LSW(mreq->transfer_size);
4801 mcp->mb[11] = MSW(mreq->transfer_size);
4802
4803 /* send data address */
4804 mcp->mb[14] = LSW(mreq->send_dma);
4805 mcp->mb[15] = MSW(mreq->send_dma);
4806 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4807 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4808
4809 /* receive data address */
4810 mcp->mb[16] = LSW(mreq->rcv_dma);
4811 mcp->mb[17] = MSW(mreq->rcv_dma);
4812 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4813 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4814
4815 /* Iteration count */
4816 mcp->mb[18] = LSW(mreq->iteration_count);
4817 mcp->mb[19] = MSW(mreq->iteration_count);
4818
4819 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4820 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
4821 if (IS_CNA_CAPABLE(vha->hw))
4822 mcp->out_mb |= MBX_2;
4823 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4824
4825 mcp->buf_size = mreq->transfer_size;
4826 mcp->tov = MBX_TOV_SECONDS;
4827 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4828
4829 rval = qla2x00_mailbox_command(vha, mcp);
4830
4831 if (rval != QLA_SUCCESS) {
4832 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4833 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4834 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4835 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
4836 } else {
4837 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4838 "Done %s.\n", __func__);
4839 }
4840
4841 /* Copy mailbox information */
4842 memcpy( mresp, mcp->mb, 64);
4843 return rval;
4844 }
4845
4846 int
4847 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4848 uint16_t *mresp)
4849 {
4850 int rval;
4851 mbx_cmd_t mc;
4852 mbx_cmd_t *mcp = &mc;
4853 struct qla_hw_data *ha = vha->hw;
4854
4855 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4856 "Entered %s.\n", __func__);
4857
4858 memset(mcp->mb, 0 , sizeof(mcp->mb));
4859 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
4860 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
4861 if (IS_CNA_CAPABLE(ha)) {
4862 mcp->mb[1] |= BIT_15;
4863 mcp->mb[2] = vha->fcoe_fcf_idx;
4864 }
4865 mcp->mb[16] = LSW(mreq->rcv_dma);
4866 mcp->mb[17] = MSW(mreq->rcv_dma);
4867 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4868 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4869
4870 mcp->mb[10] = LSW(mreq->transfer_size);
4871
4872 mcp->mb[14] = LSW(mreq->send_dma);
4873 mcp->mb[15] = MSW(mreq->send_dma);
4874 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4875 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4876
4877 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4878 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
4879 if (IS_CNA_CAPABLE(ha))
4880 mcp->out_mb |= MBX_2;
4881
4882 mcp->in_mb = MBX_0;
4883 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4884 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
4885 mcp->in_mb |= MBX_1;
4886 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
4887 mcp->in_mb |= MBX_3;
4888
4889 mcp->tov = MBX_TOV_SECONDS;
4890 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4891 mcp->buf_size = mreq->transfer_size;
4892
4893 rval = qla2x00_mailbox_command(vha, mcp);
4894
4895 if (rval != QLA_SUCCESS) {
4896 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4897 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4898 rval, mcp->mb[0], mcp->mb[1]);
4899 } else {
4900 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4901 "Done %s.\n", __func__);
4902 }
4903
4904 /* Copy mailbox information */
4905 memcpy(mresp, mcp->mb, 64);
4906 return rval;
4907 }
4908
4909 int
4910 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
4911 {
4912 int rval;
4913 mbx_cmd_t mc;
4914 mbx_cmd_t *mcp = &mc;
4915
4916 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
4917 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
4918
4919 mcp->mb[0] = MBC_ISP84XX_RESET;
4920 mcp->mb[1] = enable_diagnostic;
4921 mcp->out_mb = MBX_1|MBX_0;
4922 mcp->in_mb = MBX_1|MBX_0;
4923 mcp->tov = MBX_TOV_SECONDS;
4924 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4925 rval = qla2x00_mailbox_command(vha, mcp);
4926
4927 if (rval != QLA_SUCCESS)
4928 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
4929 else
4930 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4931 "Done %s.\n", __func__);
4932
4933 return rval;
4934 }
4935
4936 int
4937 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4938 {
4939 int rval;
4940 mbx_cmd_t mc;
4941 mbx_cmd_t *mcp = &mc;
4942
4943 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4944 "Entered %s.\n", __func__);
4945
4946 if (!IS_FWI2_CAPABLE(vha->hw))
4947 return QLA_FUNCTION_FAILED;
4948
4949 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4950 mcp->mb[1] = LSW(risc_addr);
4951 mcp->mb[2] = LSW(data);
4952 mcp->mb[3] = MSW(data);
4953 mcp->mb[8] = MSW(risc_addr);
4954 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4955 mcp->in_mb = MBX_0;
4956 mcp->tov = 30;
4957 mcp->flags = 0;
4958 rval = qla2x00_mailbox_command(vha, mcp);
4959 if (rval != QLA_SUCCESS) {
4960 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4961 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4962 } else {
4963 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4964 "Done %s.\n", __func__);
4965 }
4966
4967 return rval;
4968 }
4969
4970 int
4971 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4972 {
4973 int rval;
4974 uint32_t stat, timer;
4975 uint16_t mb0 = 0;
4976 struct qla_hw_data *ha = vha->hw;
4977 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4978
4979 rval = QLA_SUCCESS;
4980
4981 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4982 "Entered %s.\n", __func__);
4983
4984 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4985
4986 /* Write the MBC data to the registers */
4987 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4988 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4989 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4990 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4991 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4992
4993 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4994
4995 /* Poll for MBC interrupt */
4996 for (timer = 6000000; timer; timer--) {
4997 /* Check for pending interrupts. */
4998 stat = RD_REG_DWORD(&reg->host_status);
4999 if (stat & HSRX_RISC_INT) {
5000 stat &= 0xff;
5001
5002 if (stat == 0x1 || stat == 0x2 ||
5003 stat == 0x10 || stat == 0x11) {
5004 set_bit(MBX_INTERRUPT,
5005 &ha->mbx_cmd_flags);
5006 mb0 = RD_REG_WORD(&reg->mailbox0);
5007 WRT_REG_DWORD(&reg->hccr,
5008 HCCRX_CLR_RISC_INT);
5009 RD_REG_DWORD(&reg->hccr);
5010 break;
5011 }
5012 }
5013 udelay(5);
5014 }
5015
5016 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
5017 rval = mb0 & MBS_MASK;
5018 else
5019 rval = QLA_FUNCTION_FAILED;
5020
5021 if (rval != QLA_SUCCESS) {
5022 ql_dbg(ql_dbg_mbx, vha, 0x1104,
5023 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
5024 } else {
5025 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
5026 "Done %s.\n", __func__);
5027 }
5028
5029 return rval;
5030 }
5031
5032 int
5033 qla2x00_get_data_rate(scsi_qla_host_t *vha)
5034 {
5035 int rval;
5036 mbx_cmd_t mc;
5037 mbx_cmd_t *mcp = &mc;
5038 struct qla_hw_data *ha = vha->hw;
5039
5040 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5041 "Entered %s.\n", __func__);
5042
5043 if (!IS_FWI2_CAPABLE(ha))
5044 return QLA_FUNCTION_FAILED;
5045
5046 mcp->mb[0] = MBC_DATA_RATE;
5047 mcp->mb[1] = 0;
5048 mcp->out_mb = MBX_1|MBX_0;
5049 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5050 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
5051 mcp->in_mb |= MBX_3;
5052 mcp->tov = MBX_TOV_SECONDS;
5053 mcp->flags = 0;
5054 rval = qla2x00_mailbox_command(vha, mcp);
5055 if (rval != QLA_SUCCESS) {
5056 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5057 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5058 } else {
5059 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5060 "Done %s.\n", __func__);
5061 if (mcp->mb[1] != 0x7)
5062 ha->link_data_rate = mcp->mb[1];
5063 }
5064
5065 return rval;
5066 }
5067
5068 int
5069 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5070 {
5071 int rval;
5072 mbx_cmd_t mc;
5073 mbx_cmd_t *mcp = &mc;
5074 struct qla_hw_data *ha = vha->hw;
5075
5076 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5077 "Entered %s.\n", __func__);
5078
5079 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5080 !IS_QLA27XX(ha))
5081 return QLA_FUNCTION_FAILED;
5082 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5083 mcp->out_mb = MBX_0;
5084 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5085 mcp->tov = MBX_TOV_SECONDS;
5086 mcp->flags = 0;
5087
5088 rval = qla2x00_mailbox_command(vha, mcp);
5089
5090 if (rval != QLA_SUCCESS) {
5091 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5092 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5093 } else {
5094 /* Copy all bits to preserve original value */
5095 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5096
5097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5098 "Done %s.\n", __func__);
5099 }
5100 return rval;
5101 }
5102
5103 int
5104 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5105 {
5106 int rval;
5107 mbx_cmd_t mc;
5108 mbx_cmd_t *mcp = &mc;
5109
5110 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5111 "Entered %s.\n", __func__);
5112
5113 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5114 /* Copy all bits to preserve original setting */
5115 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5116 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5117 mcp->in_mb = MBX_0;
5118 mcp->tov = MBX_TOV_SECONDS;
5119 mcp->flags = 0;
5120 rval = qla2x00_mailbox_command(vha, mcp);
5121
5122 if (rval != QLA_SUCCESS) {
5123 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5124 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5125 } else
5126 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5127 "Done %s.\n", __func__);
5128
5129 return rval;
5130 }
5131
5132
5133 int
5134 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5135 uint16_t *mb)
5136 {
5137 int rval;
5138 mbx_cmd_t mc;
5139 mbx_cmd_t *mcp = &mc;
5140 struct qla_hw_data *ha = vha->hw;
5141
5142 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5143 "Entered %s.\n", __func__);
5144
5145 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5146 return QLA_FUNCTION_FAILED;
5147
5148 mcp->mb[0] = MBC_PORT_PARAMS;
5149 mcp->mb[1] = loop_id;
5150 if (ha->flags.fcp_prio_enabled)
5151 mcp->mb[2] = BIT_1;
5152 else
5153 mcp->mb[2] = BIT_2;
5154 mcp->mb[4] = priority & 0xf;
5155 mcp->mb[9] = vha->vp_idx;
5156 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5157 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5158 mcp->tov = 30;
5159 mcp->flags = 0;
5160 rval = qla2x00_mailbox_command(vha, mcp);
5161 if (mb != NULL) {
5162 mb[0] = mcp->mb[0];
5163 mb[1] = mcp->mb[1];
5164 mb[3] = mcp->mb[3];
5165 mb[4] = mcp->mb[4];
5166 }
5167
5168 if (rval != QLA_SUCCESS) {
5169 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
5170 } else {
5171 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5172 "Done %s.\n", __func__);
5173 }
5174
5175 return rval;
5176 }
5177
5178 int
5179 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
5180 {
5181 int rval = QLA_FUNCTION_FAILED;
5182 struct qla_hw_data *ha = vha->hw;
5183 uint8_t byte;
5184
5185 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5186 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5187 "Thermal not supported by this card.\n");
5188 return rval;
5189 }
5190
5191 if (IS_QLA25XX(ha)) {
5192 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5193 ha->pdev->subsystem_device == 0x0175) {
5194 rval = qla2x00_read_sfp(vha, 0, &byte,
5195 0x98, 0x1, 1, BIT_13|BIT_0);
5196 *temp = byte;
5197 return rval;
5198 }
5199 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5200 ha->pdev->subsystem_device == 0x338e) {
5201 rval = qla2x00_read_sfp(vha, 0, &byte,
5202 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5203 *temp = byte;
5204 return rval;
5205 }
5206 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5207 "Thermal not supported by this card.\n");
5208 return rval;
5209 }
5210
5211 if (IS_QLA82XX(ha)) {
5212 *temp = qla82xx_read_temperature(vha);
5213 rval = QLA_SUCCESS;
5214 return rval;
5215 } else if (IS_QLA8044(ha)) {
5216 *temp = qla8044_read_temperature(vha);
5217 rval = QLA_SUCCESS;
5218 return rval;
5219 }
5220
5221 rval = qla2x00_read_asic_temperature(vha, temp);
5222 return rval;
5223 }
5224
5225 int
5226 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5227 {
5228 int rval;
5229 struct qla_hw_data *ha = vha->hw;
5230 mbx_cmd_t mc;
5231 mbx_cmd_t *mcp = &mc;
5232
5233 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5234 "Entered %s.\n", __func__);
5235
5236 if (!IS_FWI2_CAPABLE(ha))
5237 return QLA_FUNCTION_FAILED;
5238
5239 memset(mcp, 0, sizeof(mbx_cmd_t));
5240 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
5241 mcp->mb[1] = 1;
5242
5243 mcp->out_mb = MBX_1|MBX_0;
5244 mcp->in_mb = MBX_0;
5245 mcp->tov = 30;
5246 mcp->flags = 0;
5247
5248 rval = qla2x00_mailbox_command(vha, mcp);
5249 if (rval != QLA_SUCCESS) {
5250 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5251 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5252 } else {
5253 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5254 "Done %s.\n", __func__);
5255 }
5256
5257 return rval;
5258 }
5259
5260 int
5261 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5262 {
5263 int rval;
5264 struct qla_hw_data *ha = vha->hw;
5265 mbx_cmd_t mc;
5266 mbx_cmd_t *mcp = &mc;
5267
5268 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5269 "Entered %s.\n", __func__);
5270
5271 if (!IS_P3P_TYPE(ha))
5272 return QLA_FUNCTION_FAILED;
5273
5274 memset(mcp, 0, sizeof(mbx_cmd_t));
5275 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
5276 mcp->mb[1] = 0;
5277
5278 mcp->out_mb = MBX_1|MBX_0;
5279 mcp->in_mb = MBX_0;
5280 mcp->tov = 30;
5281 mcp->flags = 0;
5282
5283 rval = qla2x00_mailbox_command(vha, mcp);
5284 if (rval != QLA_SUCCESS) {
5285 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5286 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5287 } else {
5288 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5289 "Done %s.\n", __func__);
5290 }
5291
5292 return rval;
5293 }
5294
5295 int
5296 qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5297 {
5298 struct qla_hw_data *ha = vha->hw;
5299 mbx_cmd_t mc;
5300 mbx_cmd_t *mcp = &mc;
5301 int rval = QLA_FUNCTION_FAILED;
5302
5303 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5304 "Entered %s.\n", __func__);
5305
5306 memset(mcp->mb, 0 , sizeof(mcp->mb));
5307 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5308 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5309 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5310 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5311
5312 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5313 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5314 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5315
5316 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5317 mcp->tov = MBX_TOV_SECONDS;
5318 rval = qla2x00_mailbox_command(vha, mcp);
5319
5320 /* Always copy back return mailbox values. */
5321 if (rval != QLA_SUCCESS) {
5322 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5323 "mailbox command FAILED=0x%x, subcode=%x.\n",
5324 (mcp->mb[1] << 16) | mcp->mb[0],
5325 (mcp->mb[3] << 16) | mcp->mb[2]);
5326 } else {
5327 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5328 "Done %s.\n", __func__);
5329 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5330 if (!ha->md_template_size) {
5331 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5332 "Null template size obtained.\n");
5333 rval = QLA_FUNCTION_FAILED;
5334 }
5335 }
5336 return rval;
5337 }
5338
5339 int
5340 qla82xx_md_get_template(scsi_qla_host_t *vha)
5341 {
5342 struct qla_hw_data *ha = vha->hw;
5343 mbx_cmd_t mc;
5344 mbx_cmd_t *mcp = &mc;
5345 int rval = QLA_FUNCTION_FAILED;
5346
5347 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5348 "Entered %s.\n", __func__);
5349
5350 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5351 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5352 if (!ha->md_tmplt_hdr) {
5353 ql_log(ql_log_warn, vha, 0x1124,
5354 "Unable to allocate memory for Minidump template.\n");
5355 return rval;
5356 }
5357
5358 memset(mcp->mb, 0 , sizeof(mcp->mb));
5359 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5360 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5361 mcp->mb[2] = LSW(RQST_TMPLT);
5362 mcp->mb[3] = MSW(RQST_TMPLT);
5363 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5364 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5365 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5366 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5367 mcp->mb[8] = LSW(ha->md_template_size);
5368 mcp->mb[9] = MSW(ha->md_template_size);
5369
5370 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5371 mcp->tov = MBX_TOV_SECONDS;
5372 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5373 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5374 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5375 rval = qla2x00_mailbox_command(vha, mcp);
5376
5377 if (rval != QLA_SUCCESS) {
5378 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5379 "mailbox command FAILED=0x%x, subcode=%x.\n",
5380 ((mcp->mb[1] << 16) | mcp->mb[0]),
5381 ((mcp->mb[3] << 16) | mcp->mb[2]));
5382 } else
5383 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5384 "Done %s.\n", __func__);
5385 return rval;
5386 }
5387
5388 int
5389 qla8044_md_get_template(scsi_qla_host_t *vha)
5390 {
5391 struct qla_hw_data *ha = vha->hw;
5392 mbx_cmd_t mc;
5393 mbx_cmd_t *mcp = &mc;
5394 int rval = QLA_FUNCTION_FAILED;
5395 int offset = 0, size = MINIDUMP_SIZE_36K;
5396 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5397 "Entered %s.\n", __func__);
5398
5399 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5400 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5401 if (!ha->md_tmplt_hdr) {
5402 ql_log(ql_log_warn, vha, 0xb11b,
5403 "Unable to allocate memory for Minidump template.\n");
5404 return rval;
5405 }
5406
5407 memset(mcp->mb, 0 , sizeof(mcp->mb));
5408 while (offset < ha->md_template_size) {
5409 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5410 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5411 mcp->mb[2] = LSW(RQST_TMPLT);
5412 mcp->mb[3] = MSW(RQST_TMPLT);
5413 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5414 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5415 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5416 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5417 mcp->mb[8] = LSW(size);
5418 mcp->mb[9] = MSW(size);
5419 mcp->mb[10] = offset & 0x0000FFFF;
5420 mcp->mb[11] = offset & 0xFFFF0000;
5421 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5422 mcp->tov = MBX_TOV_SECONDS;
5423 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5424 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5425 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5426 rval = qla2x00_mailbox_command(vha, mcp);
5427
5428 if (rval != QLA_SUCCESS) {
5429 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5430 "mailbox command FAILED=0x%x, subcode=%x.\n",
5431 ((mcp->mb[1] << 16) | mcp->mb[0]),
5432 ((mcp->mb[3] << 16) | mcp->mb[2]));
5433 return rval;
5434 } else
5435 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5436 "Done %s.\n", __func__);
5437 offset = offset + size;
5438 }
5439 return rval;
5440 }
5441
5442 int
5443 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5444 {
5445 int rval;
5446 struct qla_hw_data *ha = vha->hw;
5447 mbx_cmd_t mc;
5448 mbx_cmd_t *mcp = &mc;
5449
5450 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5451 return QLA_FUNCTION_FAILED;
5452
5453 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5454 "Entered %s.\n", __func__);
5455
5456 memset(mcp, 0, sizeof(mbx_cmd_t));
5457 mcp->mb[0] = MBC_SET_LED_CONFIG;
5458 mcp->mb[1] = led_cfg[0];
5459 mcp->mb[2] = led_cfg[1];
5460 if (IS_QLA8031(ha)) {
5461 mcp->mb[3] = led_cfg[2];
5462 mcp->mb[4] = led_cfg[3];
5463 mcp->mb[5] = led_cfg[4];
5464 mcp->mb[6] = led_cfg[5];
5465 }
5466
5467 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5468 if (IS_QLA8031(ha))
5469 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5470 mcp->in_mb = MBX_0;
5471 mcp->tov = 30;
5472 mcp->flags = 0;
5473
5474 rval = qla2x00_mailbox_command(vha, mcp);
5475 if (rval != QLA_SUCCESS) {
5476 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5477 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5478 } else {
5479 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5480 "Done %s.\n", __func__);
5481 }
5482
5483 return rval;
5484 }
5485
5486 int
5487 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5488 {
5489 int rval;
5490 struct qla_hw_data *ha = vha->hw;
5491 mbx_cmd_t mc;
5492 mbx_cmd_t *mcp = &mc;
5493
5494 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5495 return QLA_FUNCTION_FAILED;
5496
5497 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5498 "Entered %s.\n", __func__);
5499
5500 memset(mcp, 0, sizeof(mbx_cmd_t));
5501 mcp->mb[0] = MBC_GET_LED_CONFIG;
5502
5503 mcp->out_mb = MBX_0;
5504 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5505 if (IS_QLA8031(ha))
5506 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5507 mcp->tov = 30;
5508 mcp->flags = 0;
5509
5510 rval = qla2x00_mailbox_command(vha, mcp);
5511 if (rval != QLA_SUCCESS) {
5512 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5513 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5514 } else {
5515 led_cfg[0] = mcp->mb[1];
5516 led_cfg[1] = mcp->mb[2];
5517 if (IS_QLA8031(ha)) {
5518 led_cfg[2] = mcp->mb[3];
5519 led_cfg[3] = mcp->mb[4];
5520 led_cfg[4] = mcp->mb[5];
5521 led_cfg[5] = mcp->mb[6];
5522 }
5523 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5524 "Done %s.\n", __func__);
5525 }
5526
5527 return rval;
5528 }
5529
5530 int
5531 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5532 {
5533 int rval;
5534 struct qla_hw_data *ha = vha->hw;
5535 mbx_cmd_t mc;
5536 mbx_cmd_t *mcp = &mc;
5537
5538 if (!IS_P3P_TYPE(ha))
5539 return QLA_FUNCTION_FAILED;
5540
5541 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
5542 "Entered %s.\n", __func__);
5543
5544 memset(mcp, 0, sizeof(mbx_cmd_t));
5545 mcp->mb[0] = MBC_SET_LED_CONFIG;
5546 if (enable)
5547 mcp->mb[7] = 0xE;
5548 else
5549 mcp->mb[7] = 0xD;
5550
5551 mcp->out_mb = MBX_7|MBX_0;
5552 mcp->in_mb = MBX_0;
5553 mcp->tov = MBX_TOV_SECONDS;
5554 mcp->flags = 0;
5555
5556 rval = qla2x00_mailbox_command(vha, mcp);
5557 if (rval != QLA_SUCCESS) {
5558 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5559 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5560 } else {
5561 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
5562 "Done %s.\n", __func__);
5563 }
5564
5565 return rval;
5566 }
5567
5568 int
5569 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
5570 {
5571 int rval;
5572 struct qla_hw_data *ha = vha->hw;
5573 mbx_cmd_t mc;
5574 mbx_cmd_t *mcp = &mc;
5575
5576 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
5577 return QLA_FUNCTION_FAILED;
5578
5579 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5580 "Entered %s.\n", __func__);
5581
5582 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5583 mcp->mb[1] = LSW(reg);
5584 mcp->mb[2] = MSW(reg);
5585 mcp->mb[3] = LSW(data);
5586 mcp->mb[4] = MSW(data);
5587 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5588
5589 mcp->in_mb = MBX_1|MBX_0;
5590 mcp->tov = MBX_TOV_SECONDS;
5591 mcp->flags = 0;
5592 rval = qla2x00_mailbox_command(vha, mcp);
5593
5594 if (rval != QLA_SUCCESS) {
5595 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5596 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5597 } else {
5598 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
5599 "Done %s.\n", __func__);
5600 }
5601
5602 return rval;
5603 }
5604
5605 int
5606 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5607 {
5608 int rval;
5609 struct qla_hw_data *ha = vha->hw;
5610 mbx_cmd_t mc;
5611 mbx_cmd_t *mcp = &mc;
5612
5613 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5614 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
5615 "Implicit LOGO Unsupported.\n");
5616 return QLA_FUNCTION_FAILED;
5617 }
5618
5619
5620 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5621 "Entering %s.\n", __func__);
5622
5623 /* Perform Implicit LOGO. */
5624 mcp->mb[0] = MBC_PORT_LOGOUT;
5625 mcp->mb[1] = fcport->loop_id;
5626 mcp->mb[10] = BIT_15;
5627 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5628 mcp->in_mb = MBX_0;
5629 mcp->tov = MBX_TOV_SECONDS;
5630 mcp->flags = 0;
5631 rval = qla2x00_mailbox_command(vha, mcp);
5632 if (rval != QLA_SUCCESS)
5633 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5634 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5635 else
5636 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5637 "Done %s.\n", __func__);
5638
5639 return rval;
5640 }
5641
5642 int
5643 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5644 {
5645 int rval;
5646 mbx_cmd_t mc;
5647 mbx_cmd_t *mcp = &mc;
5648 struct qla_hw_data *ha = vha->hw;
5649 unsigned long retry_max_time = jiffies + (2 * HZ);
5650
5651 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
5652 return QLA_FUNCTION_FAILED;
5653
5654 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5655
5656 retry_rd_reg:
5657 mcp->mb[0] = MBC_READ_REMOTE_REG;
5658 mcp->mb[1] = LSW(reg);
5659 mcp->mb[2] = MSW(reg);
5660 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5661 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5662 mcp->tov = MBX_TOV_SECONDS;
5663 mcp->flags = 0;
5664 rval = qla2x00_mailbox_command(vha, mcp);
5665
5666 if (rval != QLA_SUCCESS) {
5667 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5668 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5669 rval, mcp->mb[0], mcp->mb[1]);
5670 } else {
5671 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5672 if (*data == QLA8XXX_BAD_VALUE) {
5673 /*
5674 * During soft-reset CAMRAM register reads might
5675 * return 0xbad0bad0. So retry for MAX of 2 sec
5676 * while reading camram registers.
5677 */
5678 if (time_after(jiffies, retry_max_time)) {
5679 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5680 "Failure to read CAMRAM register. "
5681 "data=0x%x.\n", *data);
5682 return QLA_FUNCTION_FAILED;
5683 }
5684 msleep(100);
5685 goto retry_rd_reg;
5686 }
5687 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5688 }
5689
5690 return rval;
5691 }
5692
5693 int
5694 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5695 {
5696 int rval;
5697 mbx_cmd_t mc;
5698 mbx_cmd_t *mcp = &mc;
5699 struct qla_hw_data *ha = vha->hw;
5700
5701 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
5702 return QLA_FUNCTION_FAILED;
5703
5704 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5705
5706 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5707 mcp->out_mb = MBX_0;
5708 mcp->in_mb = MBX_1|MBX_0;
5709 mcp->tov = MBX_TOV_SECONDS;
5710 mcp->flags = 0;
5711 rval = qla2x00_mailbox_command(vha, mcp);
5712
5713 if (rval != QLA_SUCCESS) {
5714 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5715 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5716 rval, mcp->mb[0], mcp->mb[1]);
5717 ha->isp_ops->fw_dump(vha, 0);
5718 } else {
5719 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5720 }
5721
5722 return rval;
5723 }
5724
5725 int
5726 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5727 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5728 {
5729 int rval;
5730 mbx_cmd_t mc;
5731 mbx_cmd_t *mcp = &mc;
5732 uint8_t subcode = (uint8_t)options;
5733 struct qla_hw_data *ha = vha->hw;
5734
5735 if (!IS_QLA8031(ha))
5736 return QLA_FUNCTION_FAILED;
5737
5738 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5739
5740 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5741 mcp->mb[1] = options;
5742 mcp->out_mb = MBX_1|MBX_0;
5743 if (subcode & BIT_2) {
5744 mcp->mb[2] = LSW(start_addr);
5745 mcp->mb[3] = MSW(start_addr);
5746 mcp->mb[4] = LSW(end_addr);
5747 mcp->mb[5] = MSW(end_addr);
5748 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5749 }
5750 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5751 if (!(subcode & (BIT_2 | BIT_5)))
5752 mcp->in_mb |= MBX_4|MBX_3;
5753 mcp->tov = MBX_TOV_SECONDS;
5754 mcp->flags = 0;
5755 rval = qla2x00_mailbox_command(vha, mcp);
5756
5757 if (rval != QLA_SUCCESS) {
5758 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5759 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5760 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5761 mcp->mb[4]);
5762 ha->isp_ops->fw_dump(vha, 0);
5763 } else {
5764 if (subcode & BIT_5)
5765 *sector_size = mcp->mb[1];
5766 else if (subcode & (BIT_6 | BIT_7)) {
5767 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5768 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5769 } else if (subcode & (BIT_3 | BIT_4)) {
5770 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5771 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5772 }
5773 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5774 }
5775
5776 return rval;
5777 }
5778
5779 int
5780 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5781 uint32_t size)
5782 {
5783 int rval;
5784 mbx_cmd_t mc;
5785 mbx_cmd_t *mcp = &mc;
5786
5787 if (!IS_MCTP_CAPABLE(vha->hw))
5788 return QLA_FUNCTION_FAILED;
5789
5790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5791 "Entered %s.\n", __func__);
5792
5793 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5794 mcp->mb[1] = LSW(addr);
5795 mcp->mb[2] = MSW(req_dma);
5796 mcp->mb[3] = LSW(req_dma);
5797 mcp->mb[4] = MSW(size);
5798 mcp->mb[5] = LSW(size);
5799 mcp->mb[6] = MSW(MSD(req_dma));
5800 mcp->mb[7] = LSW(MSD(req_dma));
5801 mcp->mb[8] = MSW(addr);
5802 /* Setting RAM ID to valid */
5803 mcp->mb[10] |= BIT_7;
5804 /* For MCTP RAM ID is 0x40 */
5805 mcp->mb[10] |= 0x40;
5806
5807 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5808 MBX_0;
5809
5810 mcp->in_mb = MBX_0;
5811 mcp->tov = MBX_TOV_SECONDS;
5812 mcp->flags = 0;
5813 rval = qla2x00_mailbox_command(vha, mcp);
5814
5815 if (rval != QLA_SUCCESS) {
5816 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5817 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5818 } else {
5819 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5820 "Done %s.\n", __func__);
5821 }
5822
5823 return rval;
5824 }
5825
5826 int
5827 qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
5828 void *dd_buf, uint size, uint options)
5829 {
5830 int rval;
5831 mbx_cmd_t mc;
5832 mbx_cmd_t *mcp = &mc;
5833 dma_addr_t dd_dma;
5834
5835 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
5836 return QLA_FUNCTION_FAILED;
5837
5838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
5839 "Entered %s.\n", __func__);
5840
5841 dd_dma = dma_map_single(&vha->hw->pdev->dev,
5842 dd_buf, size, DMA_FROM_DEVICE);
5843 if (!dd_dma) {
5844 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
5845 return QLA_MEMORY_ALLOC_FAILED;
5846 }
5847
5848 memset(dd_buf, 0, size);
5849
5850 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
5851 mcp->mb[1] = options;
5852 mcp->mb[2] = MSW(LSD(dd_dma));
5853 mcp->mb[3] = LSW(LSD(dd_dma));
5854 mcp->mb[6] = MSW(MSD(dd_dma));
5855 mcp->mb[7] = LSW(MSD(dd_dma));
5856 mcp->mb[8] = size;
5857 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5858 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5859 mcp->buf_size = size;
5860 mcp->flags = MBX_DMA_IN;
5861 mcp->tov = MBX_TOV_SECONDS * 4;
5862 rval = qla2x00_mailbox_command(vha, mcp);
5863
5864 if (rval != QLA_SUCCESS) {
5865 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
5866 } else {
5867 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
5868 "Done %s.\n", __func__);
5869 }
5870
5871 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
5872 size, DMA_FROM_DEVICE);
5873
5874 return rval;
5875 }
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