]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/scsi/qla2xxx/qla_mbx.c
[SCSI] qla2xxx: Add support for ISP2071.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_mbx.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include "qla_target.h"
9
10 #include <linux/delay.h>
11 #include <linux/gfp.h>
12
13
14 /*
15 * qla2x00_mailbox_command
16 * Issue mailbox command and waits for completion.
17 *
18 * Input:
19 * ha = adapter block pointer.
20 * mcp = driver internal mbx struct pointer.
21 *
22 * Output:
23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
24 *
25 * Returns:
26 * 0 : QLA_SUCCESS = cmd performed success
27 * 1 : QLA_FUNCTION_FAILED (error encountered)
28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
29 *
30 * Context:
31 * Kernel context.
32 */
33 static int
34 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
35 {
36 int rval;
37 unsigned long flags = 0;
38 device_reg_t *reg;
39 uint8_t abort_active;
40 uint8_t io_lock_on;
41 uint16_t command = 0;
42 uint16_t *iptr;
43 uint16_t __iomem *optr;
44 uint32_t cnt;
45 uint32_t mboxes;
46 unsigned long wait_time;
47 struct qla_hw_data *ha = vha->hw;
48 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
49
50 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
51
52 if (ha->pdev->error_state > pci_channel_io_frozen) {
53 ql_log(ql_log_warn, vha, 0x1001,
54 "error_state is greater than pci_channel_io_frozen, "
55 "exiting.\n");
56 return QLA_FUNCTION_TIMEOUT;
57 }
58
59 if (vha->device_flags & DFLG_DEV_FAILED) {
60 ql_log(ql_log_warn, vha, 0x1002,
61 "Device in failed state, exiting.\n");
62 return QLA_FUNCTION_TIMEOUT;
63 }
64
65 reg = ha->iobase;
66 io_lock_on = base_vha->flags.init_done;
67
68 rval = QLA_SUCCESS;
69 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
70
71
72 if (ha->flags.pci_channel_io_perm_failure) {
73 ql_log(ql_log_warn, vha, 0x1003,
74 "Perm failure on EEH timeout MBX, exiting.\n");
75 return QLA_FUNCTION_TIMEOUT;
76 }
77
78 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
79 /* Setting Link-Down error */
80 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
81 ql_log(ql_log_warn, vha, 0x1004,
82 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
83 return QLA_FUNCTION_TIMEOUT;
84 }
85
86 /*
87 * Wait for active mailbox commands to finish by waiting at most tov
88 * seconds. This is to serialize actual issuing of mailbox cmds during
89 * non ISP abort time.
90 */
91 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
92 /* Timeout occurred. Return error. */
93 ql_log(ql_log_warn, vha, 0x1005,
94 "Cmd access timeout, cmd=0x%x, Exiting.\n",
95 mcp->mb[0]);
96 return QLA_FUNCTION_TIMEOUT;
97 }
98
99 ha->flags.mbox_busy = 1;
100 /* Save mailbox command for debug */
101 ha->mcp = mcp;
102
103 ql_dbg(ql_dbg_mbx, vha, 0x1006,
104 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
105
106 spin_lock_irqsave(&ha->hardware_lock, flags);
107
108 /* Load mailbox registers. */
109 if (IS_P3P_TYPE(ha))
110 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
111 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
112 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
113 else
114 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
115
116 iptr = mcp->mb;
117 command = mcp->mb[0];
118 mboxes = mcp->out_mb;
119
120 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
121 "Mailbox registers (OUT):\n");
122 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
123 if (IS_QLA2200(ha) && cnt == 8)
124 optr =
125 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
126 if (mboxes & BIT_0) {
127 ql_dbg(ql_dbg_mbx, vha, 0x1112,
128 "mbox[%d]<-0x%04x\n", cnt, *iptr);
129 WRT_REG_WORD(optr, *iptr);
130 }
131
132 mboxes >>= 1;
133 optr++;
134 iptr++;
135 }
136
137 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
138 "I/O Address = %p.\n", optr);
139
140 /* Issue set host interrupt command to send cmd out. */
141 ha->flags.mbox_int = 0;
142 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
143
144 /* Unlock mbx registers and wait for interrupt */
145 ql_dbg(ql_dbg_mbx, vha, 0x100f,
146 "Going to unlock irq & waiting for interrupts. "
147 "jiffies=%lx.\n", jiffies);
148
149 /* Wait for mbx cmd completion until timeout */
150
151 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
152 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
153
154 if (IS_P3P_TYPE(ha)) {
155 if (RD_REG_DWORD(&reg->isp82.hint) &
156 HINT_MBX_INT_PENDING) {
157 spin_unlock_irqrestore(&ha->hardware_lock,
158 flags);
159 ha->flags.mbox_busy = 0;
160 ql_dbg(ql_dbg_mbx, vha, 0x1010,
161 "Pending mailbox timeout, exiting.\n");
162 rval = QLA_FUNCTION_TIMEOUT;
163 goto premature_exit;
164 }
165 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
166 } else if (IS_FWI2_CAPABLE(ha))
167 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
168 else
169 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
170 spin_unlock_irqrestore(&ha->hardware_lock, flags);
171
172 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
173 mcp->tov * HZ)) {
174 ql_dbg(ql_dbg_mbx, vha, 0x117a,
175 "cmd=%x Timeout.\n", command);
176 spin_lock_irqsave(&ha->hardware_lock, flags);
177 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
178 spin_unlock_irqrestore(&ha->hardware_lock, flags);
179 }
180 } else {
181 ql_dbg(ql_dbg_mbx, vha, 0x1011,
182 "Cmd=%x Polling Mode.\n", command);
183
184 if (IS_P3P_TYPE(ha)) {
185 if (RD_REG_DWORD(&reg->isp82.hint) &
186 HINT_MBX_INT_PENDING) {
187 spin_unlock_irqrestore(&ha->hardware_lock,
188 flags);
189 ha->flags.mbox_busy = 0;
190 ql_dbg(ql_dbg_mbx, vha, 0x1012,
191 "Pending mailbox timeout, exiting.\n");
192 rval = QLA_FUNCTION_TIMEOUT;
193 goto premature_exit;
194 }
195 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
196 } else if (IS_FWI2_CAPABLE(ha))
197 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
198 else
199 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
200 spin_unlock_irqrestore(&ha->hardware_lock, flags);
201
202 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
203 while (!ha->flags.mbox_int) {
204 if (time_after(jiffies, wait_time))
205 break;
206
207 /* Check for pending interrupts. */
208 qla2x00_poll(ha->rsp_q_map[0]);
209
210 if (!ha->flags.mbox_int &&
211 !(IS_QLA2200(ha) &&
212 command == MBC_LOAD_RISC_RAM_EXTENDED))
213 msleep(10);
214 } /* while */
215 ql_dbg(ql_dbg_mbx, vha, 0x1013,
216 "Waited %d sec.\n",
217 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
218 }
219
220 /* Check whether we timed out */
221 if (ha->flags.mbox_int) {
222 uint16_t *iptr2;
223
224 ql_dbg(ql_dbg_mbx, vha, 0x1014,
225 "Cmd=%x completed.\n", command);
226
227 /* Got interrupt. Clear the flag. */
228 ha->flags.mbox_int = 0;
229 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
230
231 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
232 ha->flags.mbox_busy = 0;
233 /* Setting Link-Down error */
234 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
235 ha->mcp = NULL;
236 rval = QLA_FUNCTION_FAILED;
237 ql_log(ql_log_warn, vha, 0x1015,
238 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
239 goto premature_exit;
240 }
241
242 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
243 rval = QLA_FUNCTION_FAILED;
244
245 /* Load return mailbox registers. */
246 iptr2 = mcp->mb;
247 iptr = (uint16_t *)&ha->mailbox_out[0];
248 mboxes = mcp->in_mb;
249
250 ql_dbg(ql_dbg_mbx, vha, 0x1113,
251 "Mailbox registers (IN):\n");
252 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
253 if (mboxes & BIT_0) {
254 *iptr2 = *iptr;
255 ql_dbg(ql_dbg_mbx, vha, 0x1114,
256 "mbox[%d]->0x%04x\n", cnt, *iptr2);
257 }
258
259 mboxes >>= 1;
260 iptr2++;
261 iptr++;
262 }
263 } else {
264
265 uint16_t mb0;
266 uint32_t ictrl;
267
268 if (IS_FWI2_CAPABLE(ha)) {
269 mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
270 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
271 } else {
272 mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
273 ictrl = RD_REG_WORD(&reg->isp.ictrl);
274 }
275 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
276 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
277 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
278 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
279
280 /*
281 * Attempt to capture a firmware dump for further analysis
282 * of the current firmware state. We do not need to do this
283 * if we are intentionally generating a dump.
284 */
285 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
286 ha->isp_ops->fw_dump(vha, 0);
287
288 rval = QLA_FUNCTION_TIMEOUT;
289 }
290
291 ha->flags.mbox_busy = 0;
292
293 /* Clean up */
294 ha->mcp = NULL;
295
296 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
297 ql_dbg(ql_dbg_mbx, vha, 0x101a,
298 "Checking for additional resp interrupt.\n");
299
300 /* polling mode for non isp_abort commands. */
301 qla2x00_poll(ha->rsp_q_map[0]);
302 }
303
304 if (rval == QLA_FUNCTION_TIMEOUT &&
305 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
306 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
307 ha->flags.eeh_busy) {
308 /* not in dpc. schedule it for dpc to take over. */
309 ql_dbg(ql_dbg_mbx, vha, 0x101b,
310 "Timeout, schedule isp_abort_needed.\n");
311
312 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
313 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
314 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
315 if (IS_QLA82XX(ha)) {
316 ql_dbg(ql_dbg_mbx, vha, 0x112a,
317 "disabling pause transmit on port "
318 "0 & 1.\n");
319 qla82xx_wr_32(ha,
320 QLA82XX_CRB_NIU + 0x98,
321 CRB_NIU_XG_PAUSE_CTL_P0|
322 CRB_NIU_XG_PAUSE_CTL_P1);
323 }
324 ql_log(ql_log_info, base_vha, 0x101c,
325 "Mailbox cmd timeout occurred, cmd=0x%x, "
326 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
327 "abort.\n", command, mcp->mb[0],
328 ha->flags.eeh_busy);
329 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
330 qla2xxx_wake_dpc(vha);
331 }
332 } else if (!abort_active) {
333 /* call abort directly since we are in the DPC thread */
334 ql_dbg(ql_dbg_mbx, vha, 0x101d,
335 "Timeout, calling abort_isp.\n");
336
337 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
338 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
339 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
340 if (IS_QLA82XX(ha)) {
341 ql_dbg(ql_dbg_mbx, vha, 0x112b,
342 "disabling pause transmit on port "
343 "0 & 1.\n");
344 qla82xx_wr_32(ha,
345 QLA82XX_CRB_NIU + 0x98,
346 CRB_NIU_XG_PAUSE_CTL_P0|
347 CRB_NIU_XG_PAUSE_CTL_P1);
348 }
349 ql_log(ql_log_info, base_vha, 0x101e,
350 "Mailbox cmd timeout occurred, cmd=0x%x, "
351 "mb[0]=0x%x. Scheduling ISP abort ",
352 command, mcp->mb[0]);
353 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
354 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
355 /* Allow next mbx cmd to come in. */
356 complete(&ha->mbx_cmd_comp);
357 if (ha->isp_ops->abort_isp(vha)) {
358 /* Failed. retry later. */
359 set_bit(ISP_ABORT_NEEDED,
360 &vha->dpc_flags);
361 }
362 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
363 ql_dbg(ql_dbg_mbx, vha, 0x101f,
364 "Finished abort_isp.\n");
365 goto mbx_done;
366 }
367 }
368 }
369
370 premature_exit:
371 /* Allow next mbx cmd to come in. */
372 complete(&ha->mbx_cmd_comp);
373
374 mbx_done:
375 if (rval) {
376 ql_log(ql_log_warn, base_vha, 0x1020,
377 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
378 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
379 } else {
380 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
381 }
382
383 return rval;
384 }
385
386 int
387 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
388 uint32_t risc_code_size)
389 {
390 int rval;
391 struct qla_hw_data *ha = vha->hw;
392 mbx_cmd_t mc;
393 mbx_cmd_t *mcp = &mc;
394
395 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
396 "Entered %s.\n", __func__);
397
398 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
399 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
400 mcp->mb[8] = MSW(risc_addr);
401 mcp->out_mb = MBX_8|MBX_0;
402 } else {
403 mcp->mb[0] = MBC_LOAD_RISC_RAM;
404 mcp->out_mb = MBX_0;
405 }
406 mcp->mb[1] = LSW(risc_addr);
407 mcp->mb[2] = MSW(req_dma);
408 mcp->mb[3] = LSW(req_dma);
409 mcp->mb[6] = MSW(MSD(req_dma));
410 mcp->mb[7] = LSW(MSD(req_dma));
411 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
412 if (IS_FWI2_CAPABLE(ha)) {
413 mcp->mb[4] = MSW(risc_code_size);
414 mcp->mb[5] = LSW(risc_code_size);
415 mcp->out_mb |= MBX_5|MBX_4;
416 } else {
417 mcp->mb[4] = LSW(risc_code_size);
418 mcp->out_mb |= MBX_4;
419 }
420
421 mcp->in_mb = MBX_0;
422 mcp->tov = MBX_TOV_SECONDS;
423 mcp->flags = 0;
424 rval = qla2x00_mailbox_command(vha, mcp);
425
426 if (rval != QLA_SUCCESS) {
427 ql_dbg(ql_dbg_mbx, vha, 0x1023,
428 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
429 } else {
430 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
431 "Done %s.\n", __func__);
432 }
433
434 return rval;
435 }
436
437 #define EXTENDED_BB_CREDITS BIT_0
438 /*
439 * qla2x00_execute_fw
440 * Start adapter firmware.
441 *
442 * Input:
443 * ha = adapter block pointer.
444 * TARGET_QUEUE_LOCK must be released.
445 * ADAPTER_STATE_LOCK must be released.
446 *
447 * Returns:
448 * qla2x00 local function return status code.
449 *
450 * Context:
451 * Kernel context.
452 */
453 int
454 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
455 {
456 int rval;
457 struct qla_hw_data *ha = vha->hw;
458 mbx_cmd_t mc;
459 mbx_cmd_t *mcp = &mc;
460
461 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
462 "Entered %s.\n", __func__);
463
464 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
465 mcp->out_mb = MBX_0;
466 mcp->in_mb = MBX_0;
467 if (IS_FWI2_CAPABLE(ha)) {
468 mcp->mb[1] = MSW(risc_addr);
469 mcp->mb[2] = LSW(risc_addr);
470 mcp->mb[3] = 0;
471 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
472 IS_QLA27XX(ha)) {
473 struct nvram_81xx *nv = ha->nvram;
474 mcp->mb[4] = (nv->enhanced_features &
475 EXTENDED_BB_CREDITS);
476 } else
477 mcp->mb[4] = 0;
478 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
479 mcp->in_mb |= MBX_1;
480 } else {
481 mcp->mb[1] = LSW(risc_addr);
482 mcp->out_mb |= MBX_1;
483 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
484 mcp->mb[2] = 0;
485 mcp->out_mb |= MBX_2;
486 }
487 }
488
489 mcp->tov = MBX_TOV_SECONDS;
490 mcp->flags = 0;
491 rval = qla2x00_mailbox_command(vha, mcp);
492
493 if (rval != QLA_SUCCESS) {
494 ql_dbg(ql_dbg_mbx, vha, 0x1026,
495 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
496 } else {
497 if (IS_FWI2_CAPABLE(ha)) {
498 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
499 "Done exchanges=%x.\n", mcp->mb[1]);
500 } else {
501 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
502 "Done %s.\n", __func__);
503 }
504 }
505
506 return rval;
507 }
508
509 /*
510 * qla2x00_get_fw_version
511 * Get firmware version.
512 *
513 * Input:
514 * ha: adapter state pointer.
515 * major: pointer for major number.
516 * minor: pointer for minor number.
517 * subminor: pointer for subminor number.
518 *
519 * Returns:
520 * qla2x00 local function return status code.
521 *
522 * Context:
523 * Kernel context.
524 */
525 int
526 qla2x00_get_fw_version(scsi_qla_host_t *vha)
527 {
528 int rval;
529 mbx_cmd_t mc;
530 mbx_cmd_t *mcp = &mc;
531 struct qla_hw_data *ha = vha->hw;
532
533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
534 "Entered %s.\n", __func__);
535
536 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
537 mcp->out_mb = MBX_0;
538 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
539 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
540 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
541 if (IS_FWI2_CAPABLE(ha))
542 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
543 if (IS_QLA27XX(ha))
544 mcp->in_mb |= MBX_21|MBX_20|MBX_19|MBX_18;
545 mcp->flags = 0;
546 mcp->tov = MBX_TOV_SECONDS;
547 rval = qla2x00_mailbox_command(vha, mcp);
548 if (rval != QLA_SUCCESS)
549 goto failed;
550
551 /* Return mailbox data. */
552 ha->fw_major_version = mcp->mb[1];
553 ha->fw_minor_version = mcp->mb[2];
554 ha->fw_subminor_version = mcp->mb[3];
555 ha->fw_attributes = mcp->mb[6];
556 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
557 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
558 else
559 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
560 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
561 ha->mpi_version[0] = mcp->mb[10] & 0xff;
562 ha->mpi_version[1] = mcp->mb[11] >> 8;
563 ha->mpi_version[2] = mcp->mb[11] & 0xff;
564 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
565 ha->phy_version[0] = mcp->mb[8] & 0xff;
566 ha->phy_version[1] = mcp->mb[9] >> 8;
567 ha->phy_version[2] = mcp->mb[9] & 0xff;
568 }
569 if (IS_FWI2_CAPABLE(ha)) {
570 ha->fw_attributes_h = mcp->mb[15];
571 ha->fw_attributes_ext[0] = mcp->mb[16];
572 ha->fw_attributes_ext[1] = mcp->mb[17];
573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
574 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
575 __func__, mcp->mb[15], mcp->mb[6]);
576 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
577 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
578 __func__, mcp->mb[17], mcp->mb[16]);
579 }
580 if (IS_QLA27XX(ha)) {
581 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
582 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
583 }
584
585 failed:
586 if (rval != QLA_SUCCESS) {
587 /*EMPTY*/
588 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
589 } else {
590 /*EMPTY*/
591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
592 "Done %s.\n", __func__);
593 }
594 return rval;
595 }
596
597 /*
598 * qla2x00_get_fw_options
599 * Set firmware options.
600 *
601 * Input:
602 * ha = adapter block pointer.
603 * fwopt = pointer for firmware options.
604 *
605 * Returns:
606 * qla2x00 local function return status code.
607 *
608 * Context:
609 * Kernel context.
610 */
611 int
612 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
613 {
614 int rval;
615 mbx_cmd_t mc;
616 mbx_cmd_t *mcp = &mc;
617
618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
619 "Entered %s.\n", __func__);
620
621 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
622 mcp->out_mb = MBX_0;
623 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
624 mcp->tov = MBX_TOV_SECONDS;
625 mcp->flags = 0;
626 rval = qla2x00_mailbox_command(vha, mcp);
627
628 if (rval != QLA_SUCCESS) {
629 /*EMPTY*/
630 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
631 } else {
632 fwopts[0] = mcp->mb[0];
633 fwopts[1] = mcp->mb[1];
634 fwopts[2] = mcp->mb[2];
635 fwopts[3] = mcp->mb[3];
636
637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
638 "Done %s.\n", __func__);
639 }
640
641 return rval;
642 }
643
644
645 /*
646 * qla2x00_set_fw_options
647 * Set firmware options.
648 *
649 * Input:
650 * ha = adapter block pointer.
651 * fwopt = pointer for firmware options.
652 *
653 * Returns:
654 * qla2x00 local function return status code.
655 *
656 * Context:
657 * Kernel context.
658 */
659 int
660 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
661 {
662 int rval;
663 mbx_cmd_t mc;
664 mbx_cmd_t *mcp = &mc;
665
666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
667 "Entered %s.\n", __func__);
668
669 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
670 mcp->mb[1] = fwopts[1];
671 mcp->mb[2] = fwopts[2];
672 mcp->mb[3] = fwopts[3];
673 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
674 mcp->in_mb = MBX_0;
675 if (IS_FWI2_CAPABLE(vha->hw)) {
676 mcp->in_mb |= MBX_1;
677 } else {
678 mcp->mb[10] = fwopts[10];
679 mcp->mb[11] = fwopts[11];
680 mcp->mb[12] = 0; /* Undocumented, but used */
681 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
682 }
683 mcp->tov = MBX_TOV_SECONDS;
684 mcp->flags = 0;
685 rval = qla2x00_mailbox_command(vha, mcp);
686
687 fwopts[0] = mcp->mb[0];
688
689 if (rval != QLA_SUCCESS) {
690 /*EMPTY*/
691 ql_dbg(ql_dbg_mbx, vha, 0x1030,
692 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
693 } else {
694 /*EMPTY*/
695 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
696 "Done %s.\n", __func__);
697 }
698
699 return rval;
700 }
701
702 /*
703 * qla2x00_mbx_reg_test
704 * Mailbox register wrap test.
705 *
706 * Input:
707 * ha = adapter block pointer.
708 * TARGET_QUEUE_LOCK must be released.
709 * ADAPTER_STATE_LOCK must be released.
710 *
711 * Returns:
712 * qla2x00 local function return status code.
713 *
714 * Context:
715 * Kernel context.
716 */
717 int
718 qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
719 {
720 int rval;
721 mbx_cmd_t mc;
722 mbx_cmd_t *mcp = &mc;
723
724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
725 "Entered %s.\n", __func__);
726
727 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
728 mcp->mb[1] = 0xAAAA;
729 mcp->mb[2] = 0x5555;
730 mcp->mb[3] = 0xAA55;
731 mcp->mb[4] = 0x55AA;
732 mcp->mb[5] = 0xA5A5;
733 mcp->mb[6] = 0x5A5A;
734 mcp->mb[7] = 0x2525;
735 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
736 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
737 mcp->tov = MBX_TOV_SECONDS;
738 mcp->flags = 0;
739 rval = qla2x00_mailbox_command(vha, mcp);
740
741 if (rval == QLA_SUCCESS) {
742 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
743 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
744 rval = QLA_FUNCTION_FAILED;
745 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
746 mcp->mb[7] != 0x2525)
747 rval = QLA_FUNCTION_FAILED;
748 }
749
750 if (rval != QLA_SUCCESS) {
751 /*EMPTY*/
752 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
753 } else {
754 /*EMPTY*/
755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
756 "Done %s.\n", __func__);
757 }
758
759 return rval;
760 }
761
762 /*
763 * qla2x00_verify_checksum
764 * Verify firmware checksum.
765 *
766 * Input:
767 * ha = adapter block pointer.
768 * TARGET_QUEUE_LOCK must be released.
769 * ADAPTER_STATE_LOCK must be released.
770 *
771 * Returns:
772 * qla2x00 local function return status code.
773 *
774 * Context:
775 * Kernel context.
776 */
777 int
778 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
779 {
780 int rval;
781 mbx_cmd_t mc;
782 mbx_cmd_t *mcp = &mc;
783
784 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
785 "Entered %s.\n", __func__);
786
787 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
788 mcp->out_mb = MBX_0;
789 mcp->in_mb = MBX_0;
790 if (IS_FWI2_CAPABLE(vha->hw)) {
791 mcp->mb[1] = MSW(risc_addr);
792 mcp->mb[2] = LSW(risc_addr);
793 mcp->out_mb |= MBX_2|MBX_1;
794 mcp->in_mb |= MBX_2|MBX_1;
795 } else {
796 mcp->mb[1] = LSW(risc_addr);
797 mcp->out_mb |= MBX_1;
798 mcp->in_mb |= MBX_1;
799 }
800
801 mcp->tov = MBX_TOV_SECONDS;
802 mcp->flags = 0;
803 rval = qla2x00_mailbox_command(vha, mcp);
804
805 if (rval != QLA_SUCCESS) {
806 ql_dbg(ql_dbg_mbx, vha, 0x1036,
807 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
808 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
809 } else {
810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
811 "Done %s.\n", __func__);
812 }
813
814 return rval;
815 }
816
817 /*
818 * qla2x00_issue_iocb
819 * Issue IOCB using mailbox command
820 *
821 * Input:
822 * ha = adapter state pointer.
823 * buffer = buffer pointer.
824 * phys_addr = physical address of buffer.
825 * size = size of buffer.
826 * TARGET_QUEUE_LOCK must be released.
827 * ADAPTER_STATE_LOCK must be released.
828 *
829 * Returns:
830 * qla2x00 local function return status code.
831 *
832 * Context:
833 * Kernel context.
834 */
835 int
836 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
837 dma_addr_t phys_addr, size_t size, uint32_t tov)
838 {
839 int rval;
840 mbx_cmd_t mc;
841 mbx_cmd_t *mcp = &mc;
842
843 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
844 "Entered %s.\n", __func__);
845
846 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
847 mcp->mb[1] = 0;
848 mcp->mb[2] = MSW(phys_addr);
849 mcp->mb[3] = LSW(phys_addr);
850 mcp->mb[6] = MSW(MSD(phys_addr));
851 mcp->mb[7] = LSW(MSD(phys_addr));
852 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
853 mcp->in_mb = MBX_2|MBX_0;
854 mcp->tov = tov;
855 mcp->flags = 0;
856 rval = qla2x00_mailbox_command(vha, mcp);
857
858 if (rval != QLA_SUCCESS) {
859 /*EMPTY*/
860 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
861 } else {
862 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
863
864 /* Mask reserved bits. */
865 sts_entry->entry_status &=
866 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
867 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
868 "Done %s.\n", __func__);
869 }
870
871 return rval;
872 }
873
874 int
875 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
876 size_t size)
877 {
878 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
879 MBX_TOV_SECONDS);
880 }
881
882 /*
883 * qla2x00_abort_command
884 * Abort command aborts a specified IOCB.
885 *
886 * Input:
887 * ha = adapter block pointer.
888 * sp = SB structure pointer.
889 *
890 * Returns:
891 * qla2x00 local function return status code.
892 *
893 * Context:
894 * Kernel context.
895 */
896 int
897 qla2x00_abort_command(srb_t *sp)
898 {
899 unsigned long flags = 0;
900 int rval;
901 uint32_t handle = 0;
902 mbx_cmd_t mc;
903 mbx_cmd_t *mcp = &mc;
904 fc_port_t *fcport = sp->fcport;
905 scsi_qla_host_t *vha = fcport->vha;
906 struct qla_hw_data *ha = vha->hw;
907 struct req_que *req = vha->req;
908 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
909
910 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
911 "Entered %s.\n", __func__);
912
913 spin_lock_irqsave(&ha->hardware_lock, flags);
914 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
915 if (req->outstanding_cmds[handle] == sp)
916 break;
917 }
918 spin_unlock_irqrestore(&ha->hardware_lock, flags);
919
920 if (handle == req->num_outstanding_cmds) {
921 /* command not found */
922 return QLA_FUNCTION_FAILED;
923 }
924
925 mcp->mb[0] = MBC_ABORT_COMMAND;
926 if (HAS_EXTENDED_IDS(ha))
927 mcp->mb[1] = fcport->loop_id;
928 else
929 mcp->mb[1] = fcport->loop_id << 8;
930 mcp->mb[2] = (uint16_t)handle;
931 mcp->mb[3] = (uint16_t)(handle >> 16);
932 mcp->mb[6] = (uint16_t)cmd->device->lun;
933 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
934 mcp->in_mb = MBX_0;
935 mcp->tov = MBX_TOV_SECONDS;
936 mcp->flags = 0;
937 rval = qla2x00_mailbox_command(vha, mcp);
938
939 if (rval != QLA_SUCCESS) {
940 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
941 } else {
942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
943 "Done %s.\n", __func__);
944 }
945
946 return rval;
947 }
948
949 int
950 qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
951 {
952 int rval, rval2;
953 mbx_cmd_t mc;
954 mbx_cmd_t *mcp = &mc;
955 scsi_qla_host_t *vha;
956 struct req_que *req;
957 struct rsp_que *rsp;
958
959 l = l;
960 vha = fcport->vha;
961
962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
963 "Entered %s.\n", __func__);
964
965 req = vha->hw->req_q_map[0];
966 rsp = req->rsp;
967 mcp->mb[0] = MBC_ABORT_TARGET;
968 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
969 if (HAS_EXTENDED_IDS(vha->hw)) {
970 mcp->mb[1] = fcport->loop_id;
971 mcp->mb[10] = 0;
972 mcp->out_mb |= MBX_10;
973 } else {
974 mcp->mb[1] = fcport->loop_id << 8;
975 }
976 mcp->mb[2] = vha->hw->loop_reset_delay;
977 mcp->mb[9] = vha->vp_idx;
978
979 mcp->in_mb = MBX_0;
980 mcp->tov = MBX_TOV_SECONDS;
981 mcp->flags = 0;
982 rval = qla2x00_mailbox_command(vha, mcp);
983 if (rval != QLA_SUCCESS) {
984 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
985 "Failed=%x.\n", rval);
986 }
987
988 /* Issue marker IOCB. */
989 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
990 MK_SYNC_ID);
991 if (rval2 != QLA_SUCCESS) {
992 ql_dbg(ql_dbg_mbx, vha, 0x1040,
993 "Failed to issue marker IOCB (%x).\n", rval2);
994 } else {
995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
996 "Done %s.\n", __func__);
997 }
998
999 return rval;
1000 }
1001
1002 int
1003 qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
1004 {
1005 int rval, rval2;
1006 mbx_cmd_t mc;
1007 mbx_cmd_t *mcp = &mc;
1008 scsi_qla_host_t *vha;
1009 struct req_que *req;
1010 struct rsp_que *rsp;
1011
1012 vha = fcport->vha;
1013
1014 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1015 "Entered %s.\n", __func__);
1016
1017 req = vha->hw->req_q_map[0];
1018 rsp = req->rsp;
1019 mcp->mb[0] = MBC_LUN_RESET;
1020 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
1021 if (HAS_EXTENDED_IDS(vha->hw))
1022 mcp->mb[1] = fcport->loop_id;
1023 else
1024 mcp->mb[1] = fcport->loop_id << 8;
1025 mcp->mb[2] = l;
1026 mcp->mb[3] = 0;
1027 mcp->mb[9] = vha->vp_idx;
1028
1029 mcp->in_mb = MBX_0;
1030 mcp->tov = MBX_TOV_SECONDS;
1031 mcp->flags = 0;
1032 rval = qla2x00_mailbox_command(vha, mcp);
1033 if (rval != QLA_SUCCESS) {
1034 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
1035 }
1036
1037 /* Issue marker IOCB. */
1038 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1039 MK_SYNC_ID_LUN);
1040 if (rval2 != QLA_SUCCESS) {
1041 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1042 "Failed to issue marker IOCB (%x).\n", rval2);
1043 } else {
1044 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1045 "Done %s.\n", __func__);
1046 }
1047
1048 return rval;
1049 }
1050
1051 /*
1052 * qla2x00_get_adapter_id
1053 * Get adapter ID and topology.
1054 *
1055 * Input:
1056 * ha = adapter block pointer.
1057 * id = pointer for loop ID.
1058 * al_pa = pointer for AL_PA.
1059 * area = pointer for area.
1060 * domain = pointer for domain.
1061 * top = pointer for topology.
1062 * TARGET_QUEUE_LOCK must be released.
1063 * ADAPTER_STATE_LOCK must be released.
1064 *
1065 * Returns:
1066 * qla2x00 local function return status code.
1067 *
1068 * Context:
1069 * Kernel context.
1070 */
1071 int
1072 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1073 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1074 {
1075 int rval;
1076 mbx_cmd_t mc;
1077 mbx_cmd_t *mcp = &mc;
1078
1079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1080 "Entered %s.\n", __func__);
1081
1082 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
1083 mcp->mb[9] = vha->vp_idx;
1084 mcp->out_mb = MBX_9|MBX_0;
1085 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1086 if (IS_CNA_CAPABLE(vha->hw))
1087 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
1088 mcp->tov = MBX_TOV_SECONDS;
1089 mcp->flags = 0;
1090 rval = qla2x00_mailbox_command(vha, mcp);
1091 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1092 rval = QLA_COMMAND_ERROR;
1093 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1094 rval = QLA_INVALID_COMMAND;
1095
1096 /* Return data. */
1097 *id = mcp->mb[1];
1098 *al_pa = LSB(mcp->mb[2]);
1099 *area = MSB(mcp->mb[2]);
1100 *domain = LSB(mcp->mb[3]);
1101 *top = mcp->mb[6];
1102 *sw_cap = mcp->mb[7];
1103
1104 if (rval != QLA_SUCCESS) {
1105 /*EMPTY*/
1106 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1107 } else {
1108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1109 "Done %s.\n", __func__);
1110
1111 if (IS_CNA_CAPABLE(vha->hw)) {
1112 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1113 vha->fcoe_fcf_idx = mcp->mb[10];
1114 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1115 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1116 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1117 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1118 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1119 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1120 }
1121 }
1122
1123 return rval;
1124 }
1125
1126 /*
1127 * qla2x00_get_retry_cnt
1128 * Get current firmware login retry count and delay.
1129 *
1130 * Input:
1131 * ha = adapter block pointer.
1132 * retry_cnt = pointer to login retry count.
1133 * tov = pointer to login timeout value.
1134 *
1135 * Returns:
1136 * qla2x00 local function return status code.
1137 *
1138 * Context:
1139 * Kernel context.
1140 */
1141 int
1142 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1143 uint16_t *r_a_tov)
1144 {
1145 int rval;
1146 uint16_t ratov;
1147 mbx_cmd_t mc;
1148 mbx_cmd_t *mcp = &mc;
1149
1150 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1151 "Entered %s.\n", __func__);
1152
1153 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1154 mcp->out_mb = MBX_0;
1155 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1156 mcp->tov = MBX_TOV_SECONDS;
1157 mcp->flags = 0;
1158 rval = qla2x00_mailbox_command(vha, mcp);
1159
1160 if (rval != QLA_SUCCESS) {
1161 /*EMPTY*/
1162 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1163 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1164 } else {
1165 /* Convert returned data and check our values. */
1166 *r_a_tov = mcp->mb[3] / 2;
1167 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1168 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1169 /* Update to the larger values */
1170 *retry_cnt = (uint8_t)mcp->mb[1];
1171 *tov = ratov;
1172 }
1173
1174 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
1175 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1176 }
1177
1178 return rval;
1179 }
1180
1181 /*
1182 * qla2x00_init_firmware
1183 * Initialize adapter firmware.
1184 *
1185 * Input:
1186 * ha = adapter block pointer.
1187 * dptr = Initialization control block pointer.
1188 * size = size of initialization control block.
1189 * TARGET_QUEUE_LOCK must be released.
1190 * ADAPTER_STATE_LOCK must be released.
1191 *
1192 * Returns:
1193 * qla2x00 local function return status code.
1194 *
1195 * Context:
1196 * Kernel context.
1197 */
1198 int
1199 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1200 {
1201 int rval;
1202 mbx_cmd_t mc;
1203 mbx_cmd_t *mcp = &mc;
1204 struct qla_hw_data *ha = vha->hw;
1205
1206 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1207 "Entered %s.\n", __func__);
1208
1209 if (IS_P3P_TYPE(ha) && ql2xdbwr)
1210 qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
1211 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1212
1213 if (ha->flags.npiv_supported)
1214 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1215 else
1216 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1217
1218 mcp->mb[1] = 0;
1219 mcp->mb[2] = MSW(ha->init_cb_dma);
1220 mcp->mb[3] = LSW(ha->init_cb_dma);
1221 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1222 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
1223 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1224 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1225 mcp->mb[1] = BIT_0;
1226 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1227 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1228 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1229 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1230 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1231 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1232 }
1233 /* 1 and 2 should normally be captured. */
1234 mcp->in_mb = MBX_2|MBX_1|MBX_0;
1235 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
1236 /* mb3 is additional info about the installed SFP. */
1237 mcp->in_mb |= MBX_3;
1238 mcp->buf_size = size;
1239 mcp->flags = MBX_DMA_OUT;
1240 mcp->tov = MBX_TOV_SECONDS;
1241 rval = qla2x00_mailbox_command(vha, mcp);
1242
1243 if (rval != QLA_SUCCESS) {
1244 /*EMPTY*/
1245 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1246 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1247 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1248 } else {
1249 /*EMPTY*/
1250 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1251 "Done %s.\n", __func__);
1252 }
1253
1254 return rval;
1255 }
1256
1257 /*
1258 * qla2x00_get_node_name_list
1259 * Issue get node name list mailbox command, kmalloc()
1260 * and return the resulting list. Caller must kfree() it!
1261 *
1262 * Input:
1263 * ha = adapter state pointer.
1264 * out_data = resulting list
1265 * out_len = length of the resulting list
1266 *
1267 * Returns:
1268 * qla2x00 local function return status code.
1269 *
1270 * Context:
1271 * Kernel context.
1272 */
1273 int
1274 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
1275 {
1276 struct qla_hw_data *ha = vha->hw;
1277 struct qla_port_24xx_data *list = NULL;
1278 void *pmap;
1279 mbx_cmd_t mc;
1280 dma_addr_t pmap_dma;
1281 ulong dma_size;
1282 int rval, left;
1283
1284 left = 1;
1285 while (left > 0) {
1286 dma_size = left * sizeof(*list);
1287 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
1288 &pmap_dma, GFP_KERNEL);
1289 if (!pmap) {
1290 ql_log(ql_log_warn, vha, 0x113f,
1291 "%s(%ld): DMA Alloc failed of %ld\n",
1292 __func__, vha->host_no, dma_size);
1293 rval = QLA_MEMORY_ALLOC_FAILED;
1294 goto out;
1295 }
1296
1297 mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
1298 mc.mb[1] = BIT_1 | BIT_3;
1299 mc.mb[2] = MSW(pmap_dma);
1300 mc.mb[3] = LSW(pmap_dma);
1301 mc.mb[6] = MSW(MSD(pmap_dma));
1302 mc.mb[7] = LSW(MSD(pmap_dma));
1303 mc.mb[8] = dma_size;
1304 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
1305 mc.in_mb = MBX_0|MBX_1;
1306 mc.tov = 30;
1307 mc.flags = MBX_DMA_IN;
1308
1309 rval = qla2x00_mailbox_command(vha, &mc);
1310 if (rval != QLA_SUCCESS) {
1311 if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
1312 (mc.mb[1] == 0xA)) {
1313 left += le16_to_cpu(mc.mb[2]) /
1314 sizeof(struct qla_port_24xx_data);
1315 goto restart;
1316 }
1317 goto out_free;
1318 }
1319
1320 left = 0;
1321
1322 list = kzalloc(dma_size, GFP_KERNEL);
1323 if (!list) {
1324 ql_log(ql_log_warn, vha, 0x1140,
1325 "%s(%ld): failed to allocate node names list "
1326 "structure.\n", __func__, vha->host_no);
1327 rval = QLA_MEMORY_ALLOC_FAILED;
1328 goto out_free;
1329 }
1330
1331 memcpy(list, pmap, dma_size);
1332 restart:
1333 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1334 }
1335
1336 *out_data = list;
1337 *out_len = dma_size;
1338
1339 out:
1340 return rval;
1341
1342 out_free:
1343 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1344 return rval;
1345 }
1346
1347 /*
1348 * qla2x00_get_port_database
1349 * Issue normal/enhanced get port database mailbox command
1350 * and copy device name as necessary.
1351 *
1352 * Input:
1353 * ha = adapter state pointer.
1354 * dev = structure pointer.
1355 * opt = enhanced cmd option byte.
1356 *
1357 * Returns:
1358 * qla2x00 local function return status code.
1359 *
1360 * Context:
1361 * Kernel context.
1362 */
1363 int
1364 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1365 {
1366 int rval;
1367 mbx_cmd_t mc;
1368 mbx_cmd_t *mcp = &mc;
1369 port_database_t *pd;
1370 struct port_database_24xx *pd24;
1371 dma_addr_t pd_dma;
1372 struct qla_hw_data *ha = vha->hw;
1373
1374 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1375 "Entered %s.\n", __func__);
1376
1377 pd24 = NULL;
1378 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1379 if (pd == NULL) {
1380 ql_log(ql_log_warn, vha, 0x1050,
1381 "Failed to allocate port database structure.\n");
1382 return QLA_MEMORY_ALLOC_FAILED;
1383 }
1384 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1385
1386 mcp->mb[0] = MBC_GET_PORT_DATABASE;
1387 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1388 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1389 mcp->mb[2] = MSW(pd_dma);
1390 mcp->mb[3] = LSW(pd_dma);
1391 mcp->mb[6] = MSW(MSD(pd_dma));
1392 mcp->mb[7] = LSW(MSD(pd_dma));
1393 mcp->mb[9] = vha->vp_idx;
1394 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1395 mcp->in_mb = MBX_0;
1396 if (IS_FWI2_CAPABLE(ha)) {
1397 mcp->mb[1] = fcport->loop_id;
1398 mcp->mb[10] = opt;
1399 mcp->out_mb |= MBX_10|MBX_1;
1400 mcp->in_mb |= MBX_1;
1401 } else if (HAS_EXTENDED_IDS(ha)) {
1402 mcp->mb[1] = fcport->loop_id;
1403 mcp->mb[10] = opt;
1404 mcp->out_mb |= MBX_10|MBX_1;
1405 } else {
1406 mcp->mb[1] = fcport->loop_id << 8 | opt;
1407 mcp->out_mb |= MBX_1;
1408 }
1409 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1410 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1411 mcp->flags = MBX_DMA_IN;
1412 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1413 rval = qla2x00_mailbox_command(vha, mcp);
1414 if (rval != QLA_SUCCESS)
1415 goto gpd_error_out;
1416
1417 if (IS_FWI2_CAPABLE(ha)) {
1418 uint64_t zero = 0;
1419 pd24 = (struct port_database_24xx *) pd;
1420
1421 /* Check for logged in state. */
1422 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1423 pd24->last_login_state != PDS_PRLI_COMPLETE) {
1424 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1425 "Unable to verify login-state (%x/%x) for "
1426 "loop_id %x.\n", pd24->current_login_state,
1427 pd24->last_login_state, fcport->loop_id);
1428 rval = QLA_FUNCTION_FAILED;
1429 goto gpd_error_out;
1430 }
1431
1432 if (fcport->loop_id == FC_NO_LOOP_ID ||
1433 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1434 memcmp(fcport->port_name, pd24->port_name, 8))) {
1435 /* We lost the device mid way. */
1436 rval = QLA_NOT_LOGGED_IN;
1437 goto gpd_error_out;
1438 }
1439
1440 /* Names are little-endian. */
1441 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1442 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1443
1444 /* Get port_id of device. */
1445 fcport->d_id.b.domain = pd24->port_id[0];
1446 fcport->d_id.b.area = pd24->port_id[1];
1447 fcport->d_id.b.al_pa = pd24->port_id[2];
1448 fcport->d_id.b.rsvd_1 = 0;
1449
1450 /* If not target must be initiator or unknown type. */
1451 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1452 fcport->port_type = FCT_INITIATOR;
1453 else
1454 fcport->port_type = FCT_TARGET;
1455
1456 /* Passback COS information. */
1457 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1458 FC_COS_CLASS2 : FC_COS_CLASS3;
1459
1460 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1461 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1462 } else {
1463 uint64_t zero = 0;
1464
1465 /* Check for logged in state. */
1466 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1467 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
1468 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1469 "Unable to verify login-state (%x/%x) - "
1470 "portid=%02x%02x%02x.\n", pd->master_state,
1471 pd->slave_state, fcport->d_id.b.domain,
1472 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1473 rval = QLA_FUNCTION_FAILED;
1474 goto gpd_error_out;
1475 }
1476
1477 if (fcport->loop_id == FC_NO_LOOP_ID ||
1478 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1479 memcmp(fcport->port_name, pd->port_name, 8))) {
1480 /* We lost the device mid way. */
1481 rval = QLA_NOT_LOGGED_IN;
1482 goto gpd_error_out;
1483 }
1484
1485 /* Names are little-endian. */
1486 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1487 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1488
1489 /* Get port_id of device. */
1490 fcport->d_id.b.domain = pd->port_id[0];
1491 fcport->d_id.b.area = pd->port_id[3];
1492 fcport->d_id.b.al_pa = pd->port_id[2];
1493 fcport->d_id.b.rsvd_1 = 0;
1494
1495 /* If not target must be initiator or unknown type. */
1496 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1497 fcport->port_type = FCT_INITIATOR;
1498 else
1499 fcport->port_type = FCT_TARGET;
1500
1501 /* Passback COS information. */
1502 fcport->supported_classes = (pd->options & BIT_4) ?
1503 FC_COS_CLASS2: FC_COS_CLASS3;
1504 }
1505
1506 gpd_error_out:
1507 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1508
1509 if (rval != QLA_SUCCESS) {
1510 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1511 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1512 mcp->mb[0], mcp->mb[1]);
1513 } else {
1514 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1515 "Done %s.\n", __func__);
1516 }
1517
1518 return rval;
1519 }
1520
1521 /*
1522 * qla2x00_get_firmware_state
1523 * Get adapter firmware state.
1524 *
1525 * Input:
1526 * ha = adapter block pointer.
1527 * dptr = pointer for firmware state.
1528 * TARGET_QUEUE_LOCK must be released.
1529 * ADAPTER_STATE_LOCK must be released.
1530 *
1531 * Returns:
1532 * qla2x00 local function return status code.
1533 *
1534 * Context:
1535 * Kernel context.
1536 */
1537 int
1538 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1539 {
1540 int rval;
1541 mbx_cmd_t mc;
1542 mbx_cmd_t *mcp = &mc;
1543
1544 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1545 "Entered %s.\n", __func__);
1546
1547 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1548 mcp->out_mb = MBX_0;
1549 if (IS_FWI2_CAPABLE(vha->hw))
1550 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1551 else
1552 mcp->in_mb = MBX_1|MBX_0;
1553 mcp->tov = MBX_TOV_SECONDS;
1554 mcp->flags = 0;
1555 rval = qla2x00_mailbox_command(vha, mcp);
1556
1557 /* Return firmware states. */
1558 states[0] = mcp->mb[1];
1559 if (IS_FWI2_CAPABLE(vha->hw)) {
1560 states[1] = mcp->mb[2];
1561 states[2] = mcp->mb[3];
1562 states[3] = mcp->mb[4];
1563 states[4] = mcp->mb[5];
1564 }
1565
1566 if (rval != QLA_SUCCESS) {
1567 /*EMPTY*/
1568 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1569 } else {
1570 /*EMPTY*/
1571 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1572 "Done %s.\n", __func__);
1573 }
1574
1575 return rval;
1576 }
1577
1578 /*
1579 * qla2x00_get_port_name
1580 * Issue get port name mailbox command.
1581 * Returned name is in big endian format.
1582 *
1583 * Input:
1584 * ha = adapter block pointer.
1585 * loop_id = loop ID of device.
1586 * name = pointer for name.
1587 * TARGET_QUEUE_LOCK must be released.
1588 * ADAPTER_STATE_LOCK must be released.
1589 *
1590 * Returns:
1591 * qla2x00 local function return status code.
1592 *
1593 * Context:
1594 * Kernel context.
1595 */
1596 int
1597 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1598 uint8_t opt)
1599 {
1600 int rval;
1601 mbx_cmd_t mc;
1602 mbx_cmd_t *mcp = &mc;
1603
1604 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1605 "Entered %s.\n", __func__);
1606
1607 mcp->mb[0] = MBC_GET_PORT_NAME;
1608 mcp->mb[9] = vha->vp_idx;
1609 mcp->out_mb = MBX_9|MBX_1|MBX_0;
1610 if (HAS_EXTENDED_IDS(vha->hw)) {
1611 mcp->mb[1] = loop_id;
1612 mcp->mb[10] = opt;
1613 mcp->out_mb |= MBX_10;
1614 } else {
1615 mcp->mb[1] = loop_id << 8 | opt;
1616 }
1617
1618 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1619 mcp->tov = MBX_TOV_SECONDS;
1620 mcp->flags = 0;
1621 rval = qla2x00_mailbox_command(vha, mcp);
1622
1623 if (rval != QLA_SUCCESS) {
1624 /*EMPTY*/
1625 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1626 } else {
1627 if (name != NULL) {
1628 /* This function returns name in big endian. */
1629 name[0] = MSB(mcp->mb[2]);
1630 name[1] = LSB(mcp->mb[2]);
1631 name[2] = MSB(mcp->mb[3]);
1632 name[3] = LSB(mcp->mb[3]);
1633 name[4] = MSB(mcp->mb[6]);
1634 name[5] = LSB(mcp->mb[6]);
1635 name[6] = MSB(mcp->mb[7]);
1636 name[7] = LSB(mcp->mb[7]);
1637 }
1638
1639 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
1640 "Done %s.\n", __func__);
1641 }
1642
1643 return rval;
1644 }
1645
1646 /*
1647 * qla24xx_link_initialization
1648 * Issue link initialization mailbox command.
1649 *
1650 * Input:
1651 * ha = adapter block pointer.
1652 * TARGET_QUEUE_LOCK must be released.
1653 * ADAPTER_STATE_LOCK must be released.
1654 *
1655 * Returns:
1656 * qla2x00 local function return status code.
1657 *
1658 * Context:
1659 * Kernel context.
1660 */
1661 int
1662 qla24xx_link_initialize(scsi_qla_host_t *vha)
1663 {
1664 int rval;
1665 mbx_cmd_t mc;
1666 mbx_cmd_t *mcp = &mc;
1667
1668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
1669 "Entered %s.\n", __func__);
1670
1671 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
1672 return QLA_FUNCTION_FAILED;
1673
1674 mcp->mb[0] = MBC_LINK_INITIALIZATION;
1675 mcp->mb[1] = BIT_4;
1676 if (vha->hw->operating_mode == LOOP)
1677 mcp->mb[1] |= BIT_6;
1678 else
1679 mcp->mb[1] |= BIT_5;
1680 mcp->mb[2] = 0;
1681 mcp->mb[3] = 0;
1682 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1683 mcp->in_mb = MBX_0;
1684 mcp->tov = MBX_TOV_SECONDS;
1685 mcp->flags = 0;
1686 rval = qla2x00_mailbox_command(vha, mcp);
1687
1688 if (rval != QLA_SUCCESS) {
1689 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
1690 } else {
1691 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
1692 "Done %s.\n", __func__);
1693 }
1694
1695 return rval;
1696 }
1697
1698 /*
1699 * qla2x00_lip_reset
1700 * Issue LIP reset mailbox command.
1701 *
1702 * Input:
1703 * ha = adapter block pointer.
1704 * TARGET_QUEUE_LOCK must be released.
1705 * ADAPTER_STATE_LOCK must be released.
1706 *
1707 * Returns:
1708 * qla2x00 local function return status code.
1709 *
1710 * Context:
1711 * Kernel context.
1712 */
1713 int
1714 qla2x00_lip_reset(scsi_qla_host_t *vha)
1715 {
1716 int rval;
1717 mbx_cmd_t mc;
1718 mbx_cmd_t *mcp = &mc;
1719
1720 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
1721 "Entered %s.\n", __func__);
1722
1723 if (IS_CNA_CAPABLE(vha->hw)) {
1724 /* Logout across all FCFs. */
1725 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1726 mcp->mb[1] = BIT_1;
1727 mcp->mb[2] = 0;
1728 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1729 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1730 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1731 mcp->mb[1] = BIT_6;
1732 mcp->mb[2] = 0;
1733 mcp->mb[3] = vha->hw->loop_reset_delay;
1734 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1735 } else {
1736 mcp->mb[0] = MBC_LIP_RESET;
1737 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1738 if (HAS_EXTENDED_IDS(vha->hw)) {
1739 mcp->mb[1] = 0x00ff;
1740 mcp->mb[10] = 0;
1741 mcp->out_mb |= MBX_10;
1742 } else {
1743 mcp->mb[1] = 0xff00;
1744 }
1745 mcp->mb[2] = vha->hw->loop_reset_delay;
1746 mcp->mb[3] = 0;
1747 }
1748 mcp->in_mb = MBX_0;
1749 mcp->tov = MBX_TOV_SECONDS;
1750 mcp->flags = 0;
1751 rval = qla2x00_mailbox_command(vha, mcp);
1752
1753 if (rval != QLA_SUCCESS) {
1754 /*EMPTY*/
1755 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1756 } else {
1757 /*EMPTY*/
1758 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
1759 "Done %s.\n", __func__);
1760 }
1761
1762 return rval;
1763 }
1764
1765 /*
1766 * qla2x00_send_sns
1767 * Send SNS command.
1768 *
1769 * Input:
1770 * ha = adapter block pointer.
1771 * sns = pointer for command.
1772 * cmd_size = command size.
1773 * buf_size = response/command size.
1774 * TARGET_QUEUE_LOCK must be released.
1775 * ADAPTER_STATE_LOCK must be released.
1776 *
1777 * Returns:
1778 * qla2x00 local function return status code.
1779 *
1780 * Context:
1781 * Kernel context.
1782 */
1783 int
1784 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1785 uint16_t cmd_size, size_t buf_size)
1786 {
1787 int rval;
1788 mbx_cmd_t mc;
1789 mbx_cmd_t *mcp = &mc;
1790
1791 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
1792 "Entered %s.\n", __func__);
1793
1794 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
1795 "Retry cnt=%d ratov=%d total tov=%d.\n",
1796 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1797
1798 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
1799 mcp->mb[1] = cmd_size;
1800 mcp->mb[2] = MSW(sns_phys_address);
1801 mcp->mb[3] = LSW(sns_phys_address);
1802 mcp->mb[6] = MSW(MSD(sns_phys_address));
1803 mcp->mb[7] = LSW(MSD(sns_phys_address));
1804 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1805 mcp->in_mb = MBX_0|MBX_1;
1806 mcp->buf_size = buf_size;
1807 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
1808 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
1809 rval = qla2x00_mailbox_command(vha, mcp);
1810
1811 if (rval != QLA_SUCCESS) {
1812 /*EMPTY*/
1813 ql_dbg(ql_dbg_mbx, vha, 0x105f,
1814 "Failed=%x mb[0]=%x mb[1]=%x.\n",
1815 rval, mcp->mb[0], mcp->mb[1]);
1816 } else {
1817 /*EMPTY*/
1818 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
1819 "Done %s.\n", __func__);
1820 }
1821
1822 return rval;
1823 }
1824
1825 int
1826 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1827 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1828 {
1829 int rval;
1830
1831 struct logio_entry_24xx *lg;
1832 dma_addr_t lg_dma;
1833 uint32_t iop[2];
1834 struct qla_hw_data *ha = vha->hw;
1835 struct req_que *req;
1836 struct rsp_que *rsp;
1837
1838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
1839 "Entered %s.\n", __func__);
1840
1841 if (ha->flags.cpu_affinity_enabled)
1842 req = ha->req_q_map[0];
1843 else
1844 req = vha->req;
1845 rsp = req->rsp;
1846
1847 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1848 if (lg == NULL) {
1849 ql_log(ql_log_warn, vha, 0x1062,
1850 "Failed to allocate login IOCB.\n");
1851 return QLA_MEMORY_ALLOC_FAILED;
1852 }
1853 memset(lg, 0, sizeof(struct logio_entry_24xx));
1854
1855 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1856 lg->entry_count = 1;
1857 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1858 lg->nport_handle = cpu_to_le16(loop_id);
1859 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
1860 if (opt & BIT_0)
1861 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
1862 if (opt & BIT_1)
1863 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
1864 lg->port_id[0] = al_pa;
1865 lg->port_id[1] = area;
1866 lg->port_id[2] = domain;
1867 lg->vp_index = vha->vp_idx;
1868 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
1869 (ha->r_a_tov / 10 * 2) + 2);
1870 if (rval != QLA_SUCCESS) {
1871 ql_dbg(ql_dbg_mbx, vha, 0x1063,
1872 "Failed to issue login IOCB (%x).\n", rval);
1873 } else if (lg->entry_status != 0) {
1874 ql_dbg(ql_dbg_mbx, vha, 0x1064,
1875 "Failed to complete IOCB -- error status (%x).\n",
1876 lg->entry_status);
1877 rval = QLA_FUNCTION_FAILED;
1878 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
1879 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1880 iop[1] = le32_to_cpu(lg->io_parameter[1]);
1881
1882 ql_dbg(ql_dbg_mbx, vha, 0x1065,
1883 "Failed to complete IOCB -- completion status (%x) "
1884 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1885 iop[0], iop[1]);
1886
1887 switch (iop[0]) {
1888 case LSC_SCODE_PORTID_USED:
1889 mb[0] = MBS_PORT_ID_USED;
1890 mb[1] = LSW(iop[1]);
1891 break;
1892 case LSC_SCODE_NPORT_USED:
1893 mb[0] = MBS_LOOP_ID_USED;
1894 break;
1895 case LSC_SCODE_NOLINK:
1896 case LSC_SCODE_NOIOCB:
1897 case LSC_SCODE_NOXCB:
1898 case LSC_SCODE_CMD_FAILED:
1899 case LSC_SCODE_NOFABRIC:
1900 case LSC_SCODE_FW_NOT_READY:
1901 case LSC_SCODE_NOT_LOGGED_IN:
1902 case LSC_SCODE_NOPCB:
1903 case LSC_SCODE_ELS_REJECT:
1904 case LSC_SCODE_CMD_PARAM_ERR:
1905 case LSC_SCODE_NONPORT:
1906 case LSC_SCODE_LOGGED_IN:
1907 case LSC_SCODE_NOFLOGI_ACC:
1908 default:
1909 mb[0] = MBS_COMMAND_ERROR;
1910 break;
1911 }
1912 } else {
1913 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
1914 "Done %s.\n", __func__);
1915
1916 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1917
1918 mb[0] = MBS_COMMAND_COMPLETE;
1919 mb[1] = 0;
1920 if (iop[0] & BIT_4) {
1921 if (iop[0] & BIT_8)
1922 mb[1] |= BIT_1;
1923 } else
1924 mb[1] = BIT_0;
1925
1926 /* Passback COS information. */
1927 mb[10] = 0;
1928 if (lg->io_parameter[7] || lg->io_parameter[8])
1929 mb[10] |= BIT_0; /* Class 2. */
1930 if (lg->io_parameter[9] || lg->io_parameter[10])
1931 mb[10] |= BIT_1; /* Class 3. */
1932 if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
1933 mb[10] |= BIT_7; /* Confirmed Completion
1934 * Allowed
1935 */
1936 }
1937
1938 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1939
1940 return rval;
1941 }
1942
1943 /*
1944 * qla2x00_login_fabric
1945 * Issue login fabric port mailbox command.
1946 *
1947 * Input:
1948 * ha = adapter block pointer.
1949 * loop_id = device loop ID.
1950 * domain = device domain.
1951 * area = device area.
1952 * al_pa = device AL_PA.
1953 * status = pointer for return status.
1954 * opt = command options.
1955 * TARGET_QUEUE_LOCK must be released.
1956 * ADAPTER_STATE_LOCK must be released.
1957 *
1958 * Returns:
1959 * qla2x00 local function return status code.
1960 *
1961 * Context:
1962 * Kernel context.
1963 */
1964 int
1965 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1966 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1967 {
1968 int rval;
1969 mbx_cmd_t mc;
1970 mbx_cmd_t *mcp = &mc;
1971 struct qla_hw_data *ha = vha->hw;
1972
1973 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
1974 "Entered %s.\n", __func__);
1975
1976 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
1977 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1978 if (HAS_EXTENDED_IDS(ha)) {
1979 mcp->mb[1] = loop_id;
1980 mcp->mb[10] = opt;
1981 mcp->out_mb |= MBX_10;
1982 } else {
1983 mcp->mb[1] = (loop_id << 8) | opt;
1984 }
1985 mcp->mb[2] = domain;
1986 mcp->mb[3] = area << 8 | al_pa;
1987
1988 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
1989 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1990 mcp->flags = 0;
1991 rval = qla2x00_mailbox_command(vha, mcp);
1992
1993 /* Return mailbox statuses. */
1994 if (mb != NULL) {
1995 mb[0] = mcp->mb[0];
1996 mb[1] = mcp->mb[1];
1997 mb[2] = mcp->mb[2];
1998 mb[6] = mcp->mb[6];
1999 mb[7] = mcp->mb[7];
2000 /* COS retrieved from Get-Port-Database mailbox command. */
2001 mb[10] = 0;
2002 }
2003
2004 if (rval != QLA_SUCCESS) {
2005 /* RLU tmp code: need to change main mailbox_command function to
2006 * return ok even when the mailbox completion value is not
2007 * SUCCESS. The caller needs to be responsible to interpret
2008 * the return values of this mailbox command if we're not
2009 * to change too much of the existing code.
2010 */
2011 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2012 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2013 mcp->mb[0] == 0x4006)
2014 rval = QLA_SUCCESS;
2015
2016 /*EMPTY*/
2017 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2018 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2019 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
2020 } else {
2021 /*EMPTY*/
2022 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2023 "Done %s.\n", __func__);
2024 }
2025
2026 return rval;
2027 }
2028
2029 /*
2030 * qla2x00_login_local_device
2031 * Issue login loop port mailbox command.
2032 *
2033 * Input:
2034 * ha = adapter block pointer.
2035 * loop_id = device loop ID.
2036 * opt = command options.
2037 *
2038 * Returns:
2039 * Return status code.
2040 *
2041 * Context:
2042 * Kernel context.
2043 *
2044 */
2045 int
2046 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
2047 uint16_t *mb_ret, uint8_t opt)
2048 {
2049 int rval;
2050 mbx_cmd_t mc;
2051 mbx_cmd_t *mcp = &mc;
2052 struct qla_hw_data *ha = vha->hw;
2053
2054 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2055 "Entered %s.\n", __func__);
2056
2057 if (IS_FWI2_CAPABLE(ha))
2058 return qla24xx_login_fabric(vha, fcport->loop_id,
2059 fcport->d_id.b.domain, fcport->d_id.b.area,
2060 fcport->d_id.b.al_pa, mb_ret, opt);
2061
2062 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2063 if (HAS_EXTENDED_IDS(ha))
2064 mcp->mb[1] = fcport->loop_id;
2065 else
2066 mcp->mb[1] = fcport->loop_id << 8;
2067 mcp->mb[2] = opt;
2068 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2069 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2070 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2071 mcp->flags = 0;
2072 rval = qla2x00_mailbox_command(vha, mcp);
2073
2074 /* Return mailbox statuses. */
2075 if (mb_ret != NULL) {
2076 mb_ret[0] = mcp->mb[0];
2077 mb_ret[1] = mcp->mb[1];
2078 mb_ret[6] = mcp->mb[6];
2079 mb_ret[7] = mcp->mb[7];
2080 }
2081
2082 if (rval != QLA_SUCCESS) {
2083 /* AV tmp code: need to change main mailbox_command function to
2084 * return ok even when the mailbox completion value is not
2085 * SUCCESS. The caller needs to be responsible to interpret
2086 * the return values of this mailbox command if we're not
2087 * to change too much of the existing code.
2088 */
2089 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2090 rval = QLA_SUCCESS;
2091
2092 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2093 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2094 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
2095 } else {
2096 /*EMPTY*/
2097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2098 "Done %s.\n", __func__);
2099 }
2100
2101 return (rval);
2102 }
2103
2104 int
2105 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2106 uint8_t area, uint8_t al_pa)
2107 {
2108 int rval;
2109 struct logio_entry_24xx *lg;
2110 dma_addr_t lg_dma;
2111 struct qla_hw_data *ha = vha->hw;
2112 struct req_que *req;
2113 struct rsp_que *rsp;
2114
2115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2116 "Entered %s.\n", __func__);
2117
2118 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2119 if (lg == NULL) {
2120 ql_log(ql_log_warn, vha, 0x106e,
2121 "Failed to allocate logout IOCB.\n");
2122 return QLA_MEMORY_ALLOC_FAILED;
2123 }
2124 memset(lg, 0, sizeof(struct logio_entry_24xx));
2125
2126 if (ql2xmaxqueues > 1)
2127 req = ha->req_q_map[0];
2128 else
2129 req = vha->req;
2130 rsp = req->rsp;
2131 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2132 lg->entry_count = 1;
2133 lg->handle = MAKE_HANDLE(req->id, lg->handle);
2134 lg->nport_handle = cpu_to_le16(loop_id);
2135 lg->control_flags =
2136 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
2137 LCF_FREE_NPORT);
2138 lg->port_id[0] = al_pa;
2139 lg->port_id[1] = area;
2140 lg->port_id[2] = domain;
2141 lg->vp_index = vha->vp_idx;
2142 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2143 (ha->r_a_tov / 10 * 2) + 2);
2144 if (rval != QLA_SUCCESS) {
2145 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2146 "Failed to issue logout IOCB (%x).\n", rval);
2147 } else if (lg->entry_status != 0) {
2148 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2149 "Failed to complete IOCB -- error status (%x).\n",
2150 lg->entry_status);
2151 rval = QLA_FUNCTION_FAILED;
2152 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
2153 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2154 "Failed to complete IOCB -- completion status (%x) "
2155 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2156 le32_to_cpu(lg->io_parameter[0]),
2157 le32_to_cpu(lg->io_parameter[1]));
2158 } else {
2159 /*EMPTY*/
2160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2161 "Done %s.\n", __func__);
2162 }
2163
2164 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2165
2166 return rval;
2167 }
2168
2169 /*
2170 * qla2x00_fabric_logout
2171 * Issue logout fabric port mailbox command.
2172 *
2173 * Input:
2174 * ha = adapter block pointer.
2175 * loop_id = device loop ID.
2176 * TARGET_QUEUE_LOCK must be released.
2177 * ADAPTER_STATE_LOCK must be released.
2178 *
2179 * Returns:
2180 * qla2x00 local function return status code.
2181 *
2182 * Context:
2183 * Kernel context.
2184 */
2185 int
2186 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2187 uint8_t area, uint8_t al_pa)
2188 {
2189 int rval;
2190 mbx_cmd_t mc;
2191 mbx_cmd_t *mcp = &mc;
2192
2193 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2194 "Entered %s.\n", __func__);
2195
2196 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2197 mcp->out_mb = MBX_1|MBX_0;
2198 if (HAS_EXTENDED_IDS(vha->hw)) {
2199 mcp->mb[1] = loop_id;
2200 mcp->mb[10] = 0;
2201 mcp->out_mb |= MBX_10;
2202 } else {
2203 mcp->mb[1] = loop_id << 8;
2204 }
2205
2206 mcp->in_mb = MBX_1|MBX_0;
2207 mcp->tov = MBX_TOV_SECONDS;
2208 mcp->flags = 0;
2209 rval = qla2x00_mailbox_command(vha, mcp);
2210
2211 if (rval != QLA_SUCCESS) {
2212 /*EMPTY*/
2213 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2214 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
2215 } else {
2216 /*EMPTY*/
2217 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2218 "Done %s.\n", __func__);
2219 }
2220
2221 return rval;
2222 }
2223
2224 /*
2225 * qla2x00_full_login_lip
2226 * Issue full login LIP mailbox command.
2227 *
2228 * Input:
2229 * ha = adapter block pointer.
2230 * TARGET_QUEUE_LOCK must be released.
2231 * ADAPTER_STATE_LOCK must be released.
2232 *
2233 * Returns:
2234 * qla2x00 local function return status code.
2235 *
2236 * Context:
2237 * Kernel context.
2238 */
2239 int
2240 qla2x00_full_login_lip(scsi_qla_host_t *vha)
2241 {
2242 int rval;
2243 mbx_cmd_t mc;
2244 mbx_cmd_t *mcp = &mc;
2245
2246 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2247 "Entered %s.\n", __func__);
2248
2249 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2250 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
2251 mcp->mb[2] = 0;
2252 mcp->mb[3] = 0;
2253 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2254 mcp->in_mb = MBX_0;
2255 mcp->tov = MBX_TOV_SECONDS;
2256 mcp->flags = 0;
2257 rval = qla2x00_mailbox_command(vha, mcp);
2258
2259 if (rval != QLA_SUCCESS) {
2260 /*EMPTY*/
2261 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
2262 } else {
2263 /*EMPTY*/
2264 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2265 "Done %s.\n", __func__);
2266 }
2267
2268 return rval;
2269 }
2270
2271 /*
2272 * qla2x00_get_id_list
2273 *
2274 * Input:
2275 * ha = adapter block pointer.
2276 *
2277 * Returns:
2278 * qla2x00 local function return status code.
2279 *
2280 * Context:
2281 * Kernel context.
2282 */
2283 int
2284 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
2285 uint16_t *entries)
2286 {
2287 int rval;
2288 mbx_cmd_t mc;
2289 mbx_cmd_t *mcp = &mc;
2290
2291 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2292 "Entered %s.\n", __func__);
2293
2294 if (id_list == NULL)
2295 return QLA_FUNCTION_FAILED;
2296
2297 mcp->mb[0] = MBC_GET_ID_LIST;
2298 mcp->out_mb = MBX_0;
2299 if (IS_FWI2_CAPABLE(vha->hw)) {
2300 mcp->mb[2] = MSW(id_list_dma);
2301 mcp->mb[3] = LSW(id_list_dma);
2302 mcp->mb[6] = MSW(MSD(id_list_dma));
2303 mcp->mb[7] = LSW(MSD(id_list_dma));
2304 mcp->mb[8] = 0;
2305 mcp->mb[9] = vha->vp_idx;
2306 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
2307 } else {
2308 mcp->mb[1] = MSW(id_list_dma);
2309 mcp->mb[2] = LSW(id_list_dma);
2310 mcp->mb[3] = MSW(MSD(id_list_dma));
2311 mcp->mb[6] = LSW(MSD(id_list_dma));
2312 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2313 }
2314 mcp->in_mb = MBX_1|MBX_0;
2315 mcp->tov = MBX_TOV_SECONDS;
2316 mcp->flags = 0;
2317 rval = qla2x00_mailbox_command(vha, mcp);
2318
2319 if (rval != QLA_SUCCESS) {
2320 /*EMPTY*/
2321 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
2322 } else {
2323 *entries = mcp->mb[1];
2324 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2325 "Done %s.\n", __func__);
2326 }
2327
2328 return rval;
2329 }
2330
2331 /*
2332 * qla2x00_get_resource_cnts
2333 * Get current firmware resource counts.
2334 *
2335 * Input:
2336 * ha = adapter block pointer.
2337 *
2338 * Returns:
2339 * qla2x00 local function return status code.
2340 *
2341 * Context:
2342 * Kernel context.
2343 */
2344 int
2345 qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
2346 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
2347 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
2348 {
2349 int rval;
2350 mbx_cmd_t mc;
2351 mbx_cmd_t *mcp = &mc;
2352
2353 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2354 "Entered %s.\n", __func__);
2355
2356 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2357 mcp->out_mb = MBX_0;
2358 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2359 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
2360 mcp->in_mb |= MBX_12;
2361 mcp->tov = MBX_TOV_SECONDS;
2362 mcp->flags = 0;
2363 rval = qla2x00_mailbox_command(vha, mcp);
2364
2365 if (rval != QLA_SUCCESS) {
2366 /*EMPTY*/
2367 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2368 "Failed mb[0]=%x.\n", mcp->mb[0]);
2369 } else {
2370 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
2371 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2372 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2373 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2374 mcp->mb[11], mcp->mb[12]);
2375
2376 if (cur_xchg_cnt)
2377 *cur_xchg_cnt = mcp->mb[3];
2378 if (orig_xchg_cnt)
2379 *orig_xchg_cnt = mcp->mb[6];
2380 if (cur_iocb_cnt)
2381 *cur_iocb_cnt = mcp->mb[7];
2382 if (orig_iocb_cnt)
2383 *orig_iocb_cnt = mcp->mb[10];
2384 if (vha->hw->flags.npiv_supported && max_npiv_vports)
2385 *max_npiv_vports = mcp->mb[11];
2386 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
2387 *max_fcfs = mcp->mb[12];
2388 }
2389
2390 return (rval);
2391 }
2392
2393 /*
2394 * qla2x00_get_fcal_position_map
2395 * Get FCAL (LILP) position map using mailbox command
2396 *
2397 * Input:
2398 * ha = adapter state pointer.
2399 * pos_map = buffer pointer (can be NULL).
2400 *
2401 * Returns:
2402 * qla2x00 local function return status code.
2403 *
2404 * Context:
2405 * Kernel context.
2406 */
2407 int
2408 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
2409 {
2410 int rval;
2411 mbx_cmd_t mc;
2412 mbx_cmd_t *mcp = &mc;
2413 char *pmap;
2414 dma_addr_t pmap_dma;
2415 struct qla_hw_data *ha = vha->hw;
2416
2417 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2418 "Entered %s.\n", __func__);
2419
2420 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
2421 if (pmap == NULL) {
2422 ql_log(ql_log_warn, vha, 0x1080,
2423 "Memory alloc failed.\n");
2424 return QLA_MEMORY_ALLOC_FAILED;
2425 }
2426 memset(pmap, 0, FCAL_MAP_SIZE);
2427
2428 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2429 mcp->mb[2] = MSW(pmap_dma);
2430 mcp->mb[3] = LSW(pmap_dma);
2431 mcp->mb[6] = MSW(MSD(pmap_dma));
2432 mcp->mb[7] = LSW(MSD(pmap_dma));
2433 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2434 mcp->in_mb = MBX_1|MBX_0;
2435 mcp->buf_size = FCAL_MAP_SIZE;
2436 mcp->flags = MBX_DMA_IN;
2437 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2438 rval = qla2x00_mailbox_command(vha, mcp);
2439
2440 if (rval == QLA_SUCCESS) {
2441 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
2442 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2443 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2444 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2445 pmap, pmap[0] + 1);
2446
2447 if (pos_map)
2448 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2449 }
2450 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2451
2452 if (rval != QLA_SUCCESS) {
2453 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
2454 } else {
2455 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2456 "Done %s.\n", __func__);
2457 }
2458
2459 return rval;
2460 }
2461
2462 /*
2463 * qla2x00_get_link_status
2464 *
2465 * Input:
2466 * ha = adapter block pointer.
2467 * loop_id = device loop ID.
2468 * ret_buf = pointer to link status return buffer.
2469 *
2470 * Returns:
2471 * 0 = success.
2472 * BIT_0 = mem alloc error.
2473 * BIT_1 = mailbox error.
2474 */
2475 int
2476 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
2477 struct link_statistics *stats, dma_addr_t stats_dma)
2478 {
2479 int rval;
2480 mbx_cmd_t mc;
2481 mbx_cmd_t *mcp = &mc;
2482 uint32_t *siter, *diter, dwords;
2483 struct qla_hw_data *ha = vha->hw;
2484
2485 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2486 "Entered %s.\n", __func__);
2487
2488 mcp->mb[0] = MBC_GET_LINK_STATUS;
2489 mcp->mb[2] = MSW(stats_dma);
2490 mcp->mb[3] = LSW(stats_dma);
2491 mcp->mb[6] = MSW(MSD(stats_dma));
2492 mcp->mb[7] = LSW(MSD(stats_dma));
2493 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2494 mcp->in_mb = MBX_0;
2495 if (IS_FWI2_CAPABLE(ha)) {
2496 mcp->mb[1] = loop_id;
2497 mcp->mb[4] = 0;
2498 mcp->mb[10] = 0;
2499 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2500 mcp->in_mb |= MBX_1;
2501 } else if (HAS_EXTENDED_IDS(ha)) {
2502 mcp->mb[1] = loop_id;
2503 mcp->mb[10] = 0;
2504 mcp->out_mb |= MBX_10|MBX_1;
2505 } else {
2506 mcp->mb[1] = loop_id << 8;
2507 mcp->out_mb |= MBX_1;
2508 }
2509 mcp->tov = MBX_TOV_SECONDS;
2510 mcp->flags = IOCTL_CMD;
2511 rval = qla2x00_mailbox_command(vha, mcp);
2512
2513 if (rval == QLA_SUCCESS) {
2514 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2515 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2516 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2517 rval = QLA_FUNCTION_FAILED;
2518 } else {
2519 /* Copy over data -- firmware data is LE. */
2520 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2521 "Done %s.\n", __func__);
2522 dwords = offsetof(struct link_statistics, unused1) / 4;
2523 siter = diter = &stats->link_fail_cnt;
2524 while (dwords--)
2525 *diter++ = le32_to_cpu(*siter++);
2526 }
2527 } else {
2528 /* Failed. */
2529 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
2530 }
2531
2532 return rval;
2533 }
2534
2535 int
2536 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
2537 dma_addr_t stats_dma)
2538 {
2539 int rval;
2540 mbx_cmd_t mc;
2541 mbx_cmd_t *mcp = &mc;
2542 uint32_t *siter, *diter, dwords;
2543
2544 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2545 "Entered %s.\n", __func__);
2546
2547 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
2548 mcp->mb[2] = MSW(stats_dma);
2549 mcp->mb[3] = LSW(stats_dma);
2550 mcp->mb[6] = MSW(MSD(stats_dma));
2551 mcp->mb[7] = LSW(MSD(stats_dma));
2552 mcp->mb[8] = sizeof(struct link_statistics) / 4;
2553 mcp->mb[9] = vha->vp_idx;
2554 mcp->mb[10] = 0;
2555 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2556 mcp->in_mb = MBX_2|MBX_1|MBX_0;
2557 mcp->tov = MBX_TOV_SECONDS;
2558 mcp->flags = IOCTL_CMD;
2559 rval = qla2x00_mailbox_command(vha, mcp);
2560
2561 if (rval == QLA_SUCCESS) {
2562 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2563 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2564 "Failed mb[0]=%x.\n", mcp->mb[0]);
2565 rval = QLA_FUNCTION_FAILED;
2566 } else {
2567 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2568 "Done %s.\n", __func__);
2569 /* Copy over data -- firmware data is LE. */
2570 dwords = sizeof(struct link_statistics) / 4;
2571 siter = diter = &stats->link_fail_cnt;
2572 while (dwords--)
2573 *diter++ = le32_to_cpu(*siter++);
2574 }
2575 } else {
2576 /* Failed. */
2577 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
2578 }
2579
2580 return rval;
2581 }
2582
2583 int
2584 qla24xx_abort_command(srb_t *sp)
2585 {
2586 int rval;
2587 unsigned long flags = 0;
2588
2589 struct abort_entry_24xx *abt;
2590 dma_addr_t abt_dma;
2591 uint32_t handle;
2592 fc_port_t *fcport = sp->fcport;
2593 struct scsi_qla_host *vha = fcport->vha;
2594 struct qla_hw_data *ha = vha->hw;
2595 struct req_que *req = vha->req;
2596
2597 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2598 "Entered %s.\n", __func__);
2599
2600 spin_lock_irqsave(&ha->hardware_lock, flags);
2601 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
2602 if (req->outstanding_cmds[handle] == sp)
2603 break;
2604 }
2605 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2606 if (handle == req->num_outstanding_cmds) {
2607 /* Command not found. */
2608 return QLA_FUNCTION_FAILED;
2609 }
2610
2611 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2612 if (abt == NULL) {
2613 ql_log(ql_log_warn, vha, 0x108d,
2614 "Failed to allocate abort IOCB.\n");
2615 return QLA_MEMORY_ALLOC_FAILED;
2616 }
2617 memset(abt, 0, sizeof(struct abort_entry_24xx));
2618
2619 abt->entry_type = ABORT_IOCB_TYPE;
2620 abt->entry_count = 1;
2621 abt->handle = MAKE_HANDLE(req->id, abt->handle);
2622 abt->nport_handle = cpu_to_le16(fcport->loop_id);
2623 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
2624 abt->port_id[0] = fcport->d_id.b.al_pa;
2625 abt->port_id[1] = fcport->d_id.b.area;
2626 abt->port_id[2] = fcport->d_id.b.domain;
2627 abt->vp_index = fcport->vha->vp_idx;
2628
2629 abt->req_que_no = cpu_to_le16(req->id);
2630
2631 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
2632 if (rval != QLA_SUCCESS) {
2633 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2634 "Failed to issue IOCB (%x).\n", rval);
2635 } else if (abt->entry_status != 0) {
2636 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2637 "Failed to complete IOCB -- error status (%x).\n",
2638 abt->entry_status);
2639 rval = QLA_FUNCTION_FAILED;
2640 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
2641 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2642 "Failed to complete IOCB -- completion status (%x).\n",
2643 le16_to_cpu(abt->nport_handle));
2644 rval = QLA_FUNCTION_FAILED;
2645 } else {
2646 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
2647 "Done %s.\n", __func__);
2648 }
2649
2650 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2651
2652 return rval;
2653 }
2654
2655 struct tsk_mgmt_cmd {
2656 union {
2657 struct tsk_mgmt_entry tsk;
2658 struct sts_entry_24xx sts;
2659 } p;
2660 };
2661
2662 static int
2663 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
2664 unsigned int l, int tag)
2665 {
2666 int rval, rval2;
2667 struct tsk_mgmt_cmd *tsk;
2668 struct sts_entry_24xx *sts;
2669 dma_addr_t tsk_dma;
2670 scsi_qla_host_t *vha;
2671 struct qla_hw_data *ha;
2672 struct req_que *req;
2673 struct rsp_que *rsp;
2674
2675 vha = fcport->vha;
2676 ha = vha->hw;
2677 req = vha->req;
2678
2679 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
2680 "Entered %s.\n", __func__);
2681
2682 if (ha->flags.cpu_affinity_enabled)
2683 rsp = ha->rsp_q_map[tag + 1];
2684 else
2685 rsp = req->rsp;
2686 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
2687 if (tsk == NULL) {
2688 ql_log(ql_log_warn, vha, 0x1093,
2689 "Failed to allocate task management IOCB.\n");
2690 return QLA_MEMORY_ALLOC_FAILED;
2691 }
2692 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
2693
2694 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
2695 tsk->p.tsk.entry_count = 1;
2696 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
2697 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
2698 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
2699 tsk->p.tsk.control_flags = cpu_to_le32(type);
2700 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
2701 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
2702 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
2703 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
2704 if (type == TCF_LUN_RESET) {
2705 int_to_scsilun(l, &tsk->p.tsk.lun);
2706 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
2707 sizeof(tsk->p.tsk.lun));
2708 }
2709
2710 sts = &tsk->p.sts;
2711 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
2712 if (rval != QLA_SUCCESS) {
2713 ql_dbg(ql_dbg_mbx, vha, 0x1094,
2714 "Failed to issue %s reset IOCB (%x).\n", name, rval);
2715 } else if (sts->entry_status != 0) {
2716 ql_dbg(ql_dbg_mbx, vha, 0x1095,
2717 "Failed to complete IOCB -- error status (%x).\n",
2718 sts->entry_status);
2719 rval = QLA_FUNCTION_FAILED;
2720 } else if (sts->comp_status !=
2721 __constant_cpu_to_le16(CS_COMPLETE)) {
2722 ql_dbg(ql_dbg_mbx, vha, 0x1096,
2723 "Failed to complete IOCB -- completion status (%x).\n",
2724 le16_to_cpu(sts->comp_status));
2725 rval = QLA_FUNCTION_FAILED;
2726 } else if (le16_to_cpu(sts->scsi_status) &
2727 SS_RESPONSE_INFO_LEN_VALID) {
2728 if (le32_to_cpu(sts->rsp_data_len) < 4) {
2729 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
2730 "Ignoring inconsistent data length -- not enough "
2731 "response info (%d).\n",
2732 le32_to_cpu(sts->rsp_data_len));
2733 } else if (sts->data[3]) {
2734 ql_dbg(ql_dbg_mbx, vha, 0x1098,
2735 "Failed to complete IOCB -- response (%x).\n",
2736 sts->data[3]);
2737 rval = QLA_FUNCTION_FAILED;
2738 }
2739 }
2740
2741 /* Issue marker IOCB. */
2742 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
2743 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
2744 if (rval2 != QLA_SUCCESS) {
2745 ql_dbg(ql_dbg_mbx, vha, 0x1099,
2746 "Failed to issue marker IOCB (%x).\n", rval2);
2747 } else {
2748 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
2749 "Done %s.\n", __func__);
2750 }
2751
2752 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
2753
2754 return rval;
2755 }
2756
2757 int
2758 qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
2759 {
2760 struct qla_hw_data *ha = fcport->vha->hw;
2761
2762 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2763 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
2764
2765 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
2766 }
2767
2768 int
2769 qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
2770 {
2771 struct qla_hw_data *ha = fcport->vha->hw;
2772
2773 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2774 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
2775
2776 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
2777 }
2778
2779 int
2780 qla2x00_system_error(scsi_qla_host_t *vha)
2781 {
2782 int rval;
2783 mbx_cmd_t mc;
2784 mbx_cmd_t *mcp = &mc;
2785 struct qla_hw_data *ha = vha->hw;
2786
2787 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
2788 return QLA_FUNCTION_FAILED;
2789
2790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
2791 "Entered %s.\n", __func__);
2792
2793 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
2794 mcp->out_mb = MBX_0;
2795 mcp->in_mb = MBX_0;
2796 mcp->tov = 5;
2797 mcp->flags = 0;
2798 rval = qla2x00_mailbox_command(vha, mcp);
2799
2800 if (rval != QLA_SUCCESS) {
2801 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
2802 } else {
2803 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
2804 "Done %s.\n", __func__);
2805 }
2806
2807 return rval;
2808 }
2809
2810 int
2811 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
2812 {
2813 int rval;
2814 mbx_cmd_t mc;
2815 mbx_cmd_t *mcp = &mc;
2816
2817 if (!IS_QLA2031(vha->hw))
2818 return QLA_FUNCTION_FAILED;
2819
2820 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
2821 "Entered %s.\n", __func__);
2822
2823 mcp->mb[0] = MBC_WRITE_SERDES;
2824 mcp->mb[1] = addr;
2825 mcp->mb[2] = data & 0xff;
2826 mcp->mb[3] = 0;
2827 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2828 mcp->in_mb = MBX_0;
2829 mcp->tov = MBX_TOV_SECONDS;
2830 mcp->flags = 0;
2831 rval = qla2x00_mailbox_command(vha, mcp);
2832
2833 if (rval != QLA_SUCCESS) {
2834 ql_dbg(ql_dbg_mbx, vha, 0x1183,
2835 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2836 } else {
2837 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
2838 "Done %s.\n", __func__);
2839 }
2840
2841 return rval;
2842 }
2843
2844 int
2845 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
2846 {
2847 int rval;
2848 mbx_cmd_t mc;
2849 mbx_cmd_t *mcp = &mc;
2850
2851 if (!IS_QLA2031(vha->hw))
2852 return QLA_FUNCTION_FAILED;
2853
2854 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
2855 "Entered %s.\n", __func__);
2856
2857 mcp->mb[0] = MBC_READ_SERDES;
2858 mcp->mb[1] = addr;
2859 mcp->mb[3] = 0;
2860 mcp->out_mb = MBX_3|MBX_1|MBX_0;
2861 mcp->in_mb = MBX_1|MBX_0;
2862 mcp->tov = MBX_TOV_SECONDS;
2863 mcp->flags = 0;
2864 rval = qla2x00_mailbox_command(vha, mcp);
2865
2866 *data = mcp->mb[1] & 0xff;
2867
2868 if (rval != QLA_SUCCESS) {
2869 ql_dbg(ql_dbg_mbx, vha, 0x1186,
2870 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2871 } else {
2872 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
2873 "Done %s.\n", __func__);
2874 }
2875
2876 return rval;
2877 }
2878
2879 /**
2880 * qla2x00_set_serdes_params() -
2881 * @ha: HA context
2882 *
2883 * Returns
2884 */
2885 int
2886 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
2887 uint16_t sw_em_2g, uint16_t sw_em_4g)
2888 {
2889 int rval;
2890 mbx_cmd_t mc;
2891 mbx_cmd_t *mcp = &mc;
2892
2893 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
2894 "Entered %s.\n", __func__);
2895
2896 mcp->mb[0] = MBC_SERDES_PARAMS;
2897 mcp->mb[1] = BIT_0;
2898 mcp->mb[2] = sw_em_1g | BIT_15;
2899 mcp->mb[3] = sw_em_2g | BIT_15;
2900 mcp->mb[4] = sw_em_4g | BIT_15;
2901 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2902 mcp->in_mb = MBX_0;
2903 mcp->tov = MBX_TOV_SECONDS;
2904 mcp->flags = 0;
2905 rval = qla2x00_mailbox_command(vha, mcp);
2906
2907 if (rval != QLA_SUCCESS) {
2908 /*EMPTY*/
2909 ql_dbg(ql_dbg_mbx, vha, 0x109f,
2910 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2911 } else {
2912 /*EMPTY*/
2913 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
2914 "Done %s.\n", __func__);
2915 }
2916
2917 return rval;
2918 }
2919
2920 int
2921 qla2x00_stop_firmware(scsi_qla_host_t *vha)
2922 {
2923 int rval;
2924 mbx_cmd_t mc;
2925 mbx_cmd_t *mcp = &mc;
2926
2927 if (!IS_FWI2_CAPABLE(vha->hw))
2928 return QLA_FUNCTION_FAILED;
2929
2930 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
2931 "Entered %s.\n", __func__);
2932
2933 mcp->mb[0] = MBC_STOP_FIRMWARE;
2934 mcp->mb[1] = 0;
2935 mcp->out_mb = MBX_1|MBX_0;
2936 mcp->in_mb = MBX_0;
2937 mcp->tov = 5;
2938 mcp->flags = 0;
2939 rval = qla2x00_mailbox_command(vha, mcp);
2940
2941 if (rval != QLA_SUCCESS) {
2942 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
2943 if (mcp->mb[0] == MBS_INVALID_COMMAND)
2944 rval = QLA_INVALID_COMMAND;
2945 } else {
2946 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
2947 "Done %s.\n", __func__);
2948 }
2949
2950 return rval;
2951 }
2952
2953 int
2954 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
2955 uint16_t buffers)
2956 {
2957 int rval;
2958 mbx_cmd_t mc;
2959 mbx_cmd_t *mcp = &mc;
2960
2961 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
2962 "Entered %s.\n", __func__);
2963
2964 if (!IS_FWI2_CAPABLE(vha->hw))
2965 return QLA_FUNCTION_FAILED;
2966
2967 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2968 return QLA_FUNCTION_FAILED;
2969
2970 mcp->mb[0] = MBC_TRACE_CONTROL;
2971 mcp->mb[1] = TC_EFT_ENABLE;
2972 mcp->mb[2] = LSW(eft_dma);
2973 mcp->mb[3] = MSW(eft_dma);
2974 mcp->mb[4] = LSW(MSD(eft_dma));
2975 mcp->mb[5] = MSW(MSD(eft_dma));
2976 mcp->mb[6] = buffers;
2977 mcp->mb[7] = TC_AEN_DISABLE;
2978 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2979 mcp->in_mb = MBX_1|MBX_0;
2980 mcp->tov = MBX_TOV_SECONDS;
2981 mcp->flags = 0;
2982 rval = qla2x00_mailbox_command(vha, mcp);
2983 if (rval != QLA_SUCCESS) {
2984 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
2985 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2986 rval, mcp->mb[0], mcp->mb[1]);
2987 } else {
2988 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
2989 "Done %s.\n", __func__);
2990 }
2991
2992 return rval;
2993 }
2994
2995 int
2996 qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
2997 {
2998 int rval;
2999 mbx_cmd_t mc;
3000 mbx_cmd_t *mcp = &mc;
3001
3002 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3003 "Entered %s.\n", __func__);
3004
3005 if (!IS_FWI2_CAPABLE(vha->hw))
3006 return QLA_FUNCTION_FAILED;
3007
3008 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3009 return QLA_FUNCTION_FAILED;
3010
3011 mcp->mb[0] = MBC_TRACE_CONTROL;
3012 mcp->mb[1] = TC_EFT_DISABLE;
3013 mcp->out_mb = MBX_1|MBX_0;
3014 mcp->in_mb = MBX_1|MBX_0;
3015 mcp->tov = MBX_TOV_SECONDS;
3016 mcp->flags = 0;
3017 rval = qla2x00_mailbox_command(vha, mcp);
3018 if (rval != QLA_SUCCESS) {
3019 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3020 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3021 rval, mcp->mb[0], mcp->mb[1]);
3022 } else {
3023 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3024 "Done %s.\n", __func__);
3025 }
3026
3027 return rval;
3028 }
3029
3030 int
3031 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
3032 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3033 {
3034 int rval;
3035 mbx_cmd_t mc;
3036 mbx_cmd_t *mcp = &mc;
3037
3038 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3039 "Entered %s.\n", __func__);
3040
3041 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
3042 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
3043 return QLA_FUNCTION_FAILED;
3044
3045 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3046 return QLA_FUNCTION_FAILED;
3047
3048 mcp->mb[0] = MBC_TRACE_CONTROL;
3049 mcp->mb[1] = TC_FCE_ENABLE;
3050 mcp->mb[2] = LSW(fce_dma);
3051 mcp->mb[3] = MSW(fce_dma);
3052 mcp->mb[4] = LSW(MSD(fce_dma));
3053 mcp->mb[5] = MSW(MSD(fce_dma));
3054 mcp->mb[6] = buffers;
3055 mcp->mb[7] = TC_AEN_DISABLE;
3056 mcp->mb[8] = 0;
3057 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3058 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3059 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3060 MBX_1|MBX_0;
3061 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3062 mcp->tov = MBX_TOV_SECONDS;
3063 mcp->flags = 0;
3064 rval = qla2x00_mailbox_command(vha, mcp);
3065 if (rval != QLA_SUCCESS) {
3066 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3067 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3068 rval, mcp->mb[0], mcp->mb[1]);
3069 } else {
3070 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3071 "Done %s.\n", __func__);
3072
3073 if (mb)
3074 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3075 if (dwords)
3076 *dwords = buffers;
3077 }
3078
3079 return rval;
3080 }
3081
3082 int
3083 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
3084 {
3085 int rval;
3086 mbx_cmd_t mc;
3087 mbx_cmd_t *mcp = &mc;
3088
3089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3090 "Entered %s.\n", __func__);
3091
3092 if (!IS_FWI2_CAPABLE(vha->hw))
3093 return QLA_FUNCTION_FAILED;
3094
3095 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3096 return QLA_FUNCTION_FAILED;
3097
3098 mcp->mb[0] = MBC_TRACE_CONTROL;
3099 mcp->mb[1] = TC_FCE_DISABLE;
3100 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3101 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3102 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3103 MBX_1|MBX_0;
3104 mcp->tov = MBX_TOV_SECONDS;
3105 mcp->flags = 0;
3106 rval = qla2x00_mailbox_command(vha, mcp);
3107 if (rval != QLA_SUCCESS) {
3108 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3109 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3110 rval, mcp->mb[0], mcp->mb[1]);
3111 } else {
3112 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3113 "Done %s.\n", __func__);
3114
3115 if (wr)
3116 *wr = (uint64_t) mcp->mb[5] << 48 |
3117 (uint64_t) mcp->mb[4] << 32 |
3118 (uint64_t) mcp->mb[3] << 16 |
3119 (uint64_t) mcp->mb[2];
3120 if (rd)
3121 *rd = (uint64_t) mcp->mb[9] << 48 |
3122 (uint64_t) mcp->mb[8] << 32 |
3123 (uint64_t) mcp->mb[7] << 16 |
3124 (uint64_t) mcp->mb[6];
3125 }
3126
3127 return rval;
3128 }
3129
3130 int
3131 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3132 uint16_t *port_speed, uint16_t *mb)
3133 {
3134 int rval;
3135 mbx_cmd_t mc;
3136 mbx_cmd_t *mcp = &mc;
3137
3138 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3139 "Entered %s.\n", __func__);
3140
3141 if (!IS_IIDMA_CAPABLE(vha->hw))
3142 return QLA_FUNCTION_FAILED;
3143
3144 mcp->mb[0] = MBC_PORT_PARAMS;
3145 mcp->mb[1] = loop_id;
3146 mcp->mb[2] = mcp->mb[3] = 0;
3147 mcp->mb[9] = vha->vp_idx;
3148 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3149 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3150 mcp->tov = MBX_TOV_SECONDS;
3151 mcp->flags = 0;
3152 rval = qla2x00_mailbox_command(vha, mcp);
3153
3154 /* Return mailbox statuses. */
3155 if (mb != NULL) {
3156 mb[0] = mcp->mb[0];
3157 mb[1] = mcp->mb[1];
3158 mb[3] = mcp->mb[3];
3159 }
3160
3161 if (rval != QLA_SUCCESS) {
3162 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
3163 } else {
3164 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3165 "Done %s.\n", __func__);
3166 if (port_speed)
3167 *port_speed = mcp->mb[3];
3168 }
3169
3170 return rval;
3171 }
3172
3173 int
3174 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3175 uint16_t port_speed, uint16_t *mb)
3176 {
3177 int rval;
3178 mbx_cmd_t mc;
3179 mbx_cmd_t *mcp = &mc;
3180
3181 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3182 "Entered %s.\n", __func__);
3183
3184 if (!IS_IIDMA_CAPABLE(vha->hw))
3185 return QLA_FUNCTION_FAILED;
3186
3187 mcp->mb[0] = MBC_PORT_PARAMS;
3188 mcp->mb[1] = loop_id;
3189 mcp->mb[2] = BIT_0;
3190 if (IS_CNA_CAPABLE(vha->hw))
3191 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3192 else
3193 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3194 mcp->mb[9] = vha->vp_idx;
3195 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3196 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3197 mcp->tov = MBX_TOV_SECONDS;
3198 mcp->flags = 0;
3199 rval = qla2x00_mailbox_command(vha, mcp);
3200
3201 /* Return mailbox statuses. */
3202 if (mb != NULL) {
3203 mb[0] = mcp->mb[0];
3204 mb[1] = mcp->mb[1];
3205 mb[3] = mcp->mb[3];
3206 }
3207
3208 if (rval != QLA_SUCCESS) {
3209 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3210 "Failed=%x.\n", rval);
3211 } else {
3212 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3213 "Done %s.\n", __func__);
3214 }
3215
3216 return rval;
3217 }
3218
3219 void
3220 qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
3221 struct vp_rpt_id_entry_24xx *rptid_entry)
3222 {
3223 uint8_t vp_idx;
3224 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
3225 struct qla_hw_data *ha = vha->hw;
3226 scsi_qla_host_t *vp;
3227 unsigned long flags;
3228 int found;
3229
3230 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3231 "Entered %s.\n", __func__);
3232
3233 if (rptid_entry->entry_status != 0)
3234 return;
3235
3236 if (rptid_entry->format == 0) {
3237 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
3238 "Format 0 : Number of VPs setup %d, number of "
3239 "VPs acquired %d.\n",
3240 MSB(le16_to_cpu(rptid_entry->vp_count)),
3241 LSB(le16_to_cpu(rptid_entry->vp_count)));
3242 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
3243 "Primary port id %02x%02x%02x.\n",
3244 rptid_entry->port_id[2], rptid_entry->port_id[1],
3245 rptid_entry->port_id[0]);
3246 } else if (rptid_entry->format == 1) {
3247 vp_idx = LSB(stat);
3248 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
3249 "Format 1: VP[%d] enabled - status %d - with "
3250 "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
3251 rptid_entry->port_id[2], rptid_entry->port_id[1],
3252 rptid_entry->port_id[0]);
3253
3254 vp = vha;
3255 if (vp_idx == 0 && (MSB(stat) != 1))
3256 goto reg_needed;
3257
3258 if (MSB(stat) != 0 && MSB(stat) != 2) {
3259 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3260 "Could not acquire ID for VP[%d].\n", vp_idx);
3261 return;
3262 }
3263
3264 found = 0;
3265 spin_lock_irqsave(&ha->vport_slock, flags);
3266 list_for_each_entry(vp, &ha->vp_list, list) {
3267 if (vp_idx == vp->vp_idx) {
3268 found = 1;
3269 break;
3270 }
3271 }
3272 spin_unlock_irqrestore(&ha->vport_slock, flags);
3273
3274 if (!found)
3275 return;
3276
3277 vp->d_id.b.domain = rptid_entry->port_id[2];
3278 vp->d_id.b.area = rptid_entry->port_id[1];
3279 vp->d_id.b.al_pa = rptid_entry->port_id[0];
3280
3281 /*
3282 * Cannot configure here as we are still sitting on the
3283 * response queue. Handle it in dpc context.
3284 */
3285 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3286
3287 reg_needed:
3288 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3289 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3290 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
3291 qla2xxx_wake_dpc(vha);
3292 }
3293 }
3294
3295 /*
3296 * qla24xx_modify_vp_config
3297 * Change VP configuration for vha
3298 *
3299 * Input:
3300 * vha = adapter block pointer.
3301 *
3302 * Returns:
3303 * qla2xxx local function return status code.
3304 *
3305 * Context:
3306 * Kernel context.
3307 */
3308 int
3309 qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3310 {
3311 int rval;
3312 struct vp_config_entry_24xx *vpmod;
3313 dma_addr_t vpmod_dma;
3314 struct qla_hw_data *ha = vha->hw;
3315 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3316
3317 /* This can be called by the parent */
3318
3319 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3320 "Entered %s.\n", __func__);
3321
3322 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
3323 if (!vpmod) {
3324 ql_log(ql_log_warn, vha, 0x10bc,
3325 "Failed to allocate modify VP IOCB.\n");
3326 return QLA_MEMORY_ALLOC_FAILED;
3327 }
3328
3329 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3330 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3331 vpmod->entry_count = 1;
3332 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3333 vpmod->vp_count = 1;
3334 vpmod->vp_index1 = vha->vp_idx;
3335 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
3336
3337 qlt_modify_vp_config(vha, vpmod);
3338
3339 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3340 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3341 vpmod->entry_count = 1;
3342
3343 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
3344 if (rval != QLA_SUCCESS) {
3345 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3346 "Failed to issue VP config IOCB (%x).\n", rval);
3347 } else if (vpmod->comp_status != 0) {
3348 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3349 "Failed to complete IOCB -- error status (%x).\n",
3350 vpmod->comp_status);
3351 rval = QLA_FUNCTION_FAILED;
3352 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
3353 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3354 "Failed to complete IOCB -- completion status (%x).\n",
3355 le16_to_cpu(vpmod->comp_status));
3356 rval = QLA_FUNCTION_FAILED;
3357 } else {
3358 /* EMPTY */
3359 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3360 "Done %s.\n", __func__);
3361 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3362 }
3363 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
3364
3365 return rval;
3366 }
3367
3368 /*
3369 * qla24xx_control_vp
3370 * Enable a virtual port for given host
3371 *
3372 * Input:
3373 * ha = adapter block pointer.
3374 * vhba = virtual adapter (unused)
3375 * index = index number for enabled VP
3376 *
3377 * Returns:
3378 * qla2xxx local function return status code.
3379 *
3380 * Context:
3381 * Kernel context.
3382 */
3383 int
3384 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3385 {
3386 int rval;
3387 int map, pos;
3388 struct vp_ctrl_entry_24xx *vce;
3389 dma_addr_t vce_dma;
3390 struct qla_hw_data *ha = vha->hw;
3391 int vp_index = vha->vp_idx;
3392 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3393
3394 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
3395 "Entered %s enabling index %d.\n", __func__, vp_index);
3396
3397 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
3398 return QLA_PARAMETER_ERROR;
3399
3400 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3401 if (!vce) {
3402 ql_log(ql_log_warn, vha, 0x10c2,
3403 "Failed to allocate VP control IOCB.\n");
3404 return QLA_MEMORY_ALLOC_FAILED;
3405 }
3406 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3407
3408 vce->entry_type = VP_CTRL_IOCB_TYPE;
3409 vce->entry_count = 1;
3410 vce->command = cpu_to_le16(cmd);
3411 vce->vp_count = __constant_cpu_to_le16(1);
3412
3413 /* index map in firmware starts with 1; decrement index
3414 * this is ok as we never use index 0
3415 */
3416 map = (vp_index - 1) / 8;
3417 pos = (vp_index - 1) & 7;
3418 mutex_lock(&ha->vport_lock);
3419 vce->vp_idx_map[map] |= 1 << pos;
3420 mutex_unlock(&ha->vport_lock);
3421
3422 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
3423 if (rval != QLA_SUCCESS) {
3424 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3425 "Failed to issue VP control IOCB (%x).\n", rval);
3426 } else if (vce->entry_status != 0) {
3427 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3428 "Failed to complete IOCB -- error status (%x).\n",
3429 vce->entry_status);
3430 rval = QLA_FUNCTION_FAILED;
3431 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
3432 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3433 "Failed to complet IOCB -- completion status (%x).\n",
3434 le16_to_cpu(vce->comp_status));
3435 rval = QLA_FUNCTION_FAILED;
3436 } else {
3437 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3438 "Done %s.\n", __func__);
3439 }
3440
3441 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3442
3443 return rval;
3444 }
3445
3446 /*
3447 * qla2x00_send_change_request
3448 * Receive or disable RSCN request from fabric controller
3449 *
3450 * Input:
3451 * ha = adapter block pointer
3452 * format = registration format:
3453 * 0 - Reserved
3454 * 1 - Fabric detected registration
3455 * 2 - N_port detected registration
3456 * 3 - Full registration
3457 * FF - clear registration
3458 * vp_idx = Virtual port index
3459 *
3460 * Returns:
3461 * qla2x00 local function return status code.
3462 *
3463 * Context:
3464 * Kernel Context
3465 */
3466
3467 int
3468 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
3469 uint16_t vp_idx)
3470 {
3471 int rval;
3472 mbx_cmd_t mc;
3473 mbx_cmd_t *mcp = &mc;
3474
3475 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3476 "Entered %s.\n", __func__);
3477
3478 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3479 mcp->mb[1] = format;
3480 mcp->mb[9] = vp_idx;
3481 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3482 mcp->in_mb = MBX_0|MBX_1;
3483 mcp->tov = MBX_TOV_SECONDS;
3484 mcp->flags = 0;
3485 rval = qla2x00_mailbox_command(vha, mcp);
3486
3487 if (rval == QLA_SUCCESS) {
3488 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3489 rval = BIT_1;
3490 }
3491 } else
3492 rval = BIT_1;
3493
3494 return rval;
3495 }
3496
3497 int
3498 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
3499 uint32_t size)
3500 {
3501 int rval;
3502 mbx_cmd_t mc;
3503 mbx_cmd_t *mcp = &mc;
3504
3505 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3506 "Entered %s.\n", __func__);
3507
3508 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
3509 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3510 mcp->mb[8] = MSW(addr);
3511 mcp->out_mb = MBX_8|MBX_0;
3512 } else {
3513 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3514 mcp->out_mb = MBX_0;
3515 }
3516 mcp->mb[1] = LSW(addr);
3517 mcp->mb[2] = MSW(req_dma);
3518 mcp->mb[3] = LSW(req_dma);
3519 mcp->mb[6] = MSW(MSD(req_dma));
3520 mcp->mb[7] = LSW(MSD(req_dma));
3521 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
3522 if (IS_FWI2_CAPABLE(vha->hw)) {
3523 mcp->mb[4] = MSW(size);
3524 mcp->mb[5] = LSW(size);
3525 mcp->out_mb |= MBX_5|MBX_4;
3526 } else {
3527 mcp->mb[4] = LSW(size);
3528 mcp->out_mb |= MBX_4;
3529 }
3530
3531 mcp->in_mb = MBX_0;
3532 mcp->tov = MBX_TOV_SECONDS;
3533 mcp->flags = 0;
3534 rval = qla2x00_mailbox_command(vha, mcp);
3535
3536 if (rval != QLA_SUCCESS) {
3537 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3538 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3539 } else {
3540 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
3541 "Done %s.\n", __func__);
3542 }
3543
3544 return rval;
3545 }
3546 /* 84XX Support **************************************************************/
3547
3548 struct cs84xx_mgmt_cmd {
3549 union {
3550 struct verify_chip_entry_84xx req;
3551 struct verify_chip_rsp_84xx rsp;
3552 } p;
3553 };
3554
3555 int
3556 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
3557 {
3558 int rval, retry;
3559 struct cs84xx_mgmt_cmd *mn;
3560 dma_addr_t mn_dma;
3561 uint16_t options;
3562 unsigned long flags;
3563 struct qla_hw_data *ha = vha->hw;
3564
3565 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
3566 "Entered %s.\n", __func__);
3567
3568 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
3569 if (mn == NULL) {
3570 return QLA_MEMORY_ALLOC_FAILED;
3571 }
3572
3573 /* Force Update? */
3574 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
3575 /* Diagnostic firmware? */
3576 /* options |= MENLO_DIAG_FW; */
3577 /* We update the firmware with only one data sequence. */
3578 options |= VCO_END_OF_DATA;
3579
3580 do {
3581 retry = 0;
3582 memset(mn, 0, sizeof(*mn));
3583 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
3584 mn->p.req.entry_count = 1;
3585 mn->p.req.options = cpu_to_le16(options);
3586
3587 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
3588 "Dump of Verify Request.\n");
3589 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
3590 (uint8_t *)mn, sizeof(*mn));
3591
3592 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
3593 if (rval != QLA_SUCCESS) {
3594 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
3595 "Failed to issue verify IOCB (%x).\n", rval);
3596 goto verify_done;
3597 }
3598
3599 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
3600 "Dump of Verify Response.\n");
3601 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
3602 (uint8_t *)mn, sizeof(*mn));
3603
3604 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
3605 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
3606 le16_to_cpu(mn->p.rsp.failure_code) : 0;
3607 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
3608 "cs=%x fc=%x.\n", status[0], status[1]);
3609
3610 if (status[0] != CS_COMPLETE) {
3611 rval = QLA_FUNCTION_FAILED;
3612 if (!(options & VCO_DONT_UPDATE_FW)) {
3613 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
3614 "Firmware update failed. Retrying "
3615 "without update firmware.\n");
3616 options |= VCO_DONT_UPDATE_FW;
3617 options &= ~VCO_FORCE_UPDATE;
3618 retry = 1;
3619 }
3620 } else {
3621 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
3622 "Firmware updated to %x.\n",
3623 le32_to_cpu(mn->p.rsp.fw_ver));
3624
3625 /* NOTE: we only update OP firmware. */
3626 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
3627 ha->cs84xx->op_fw_version =
3628 le32_to_cpu(mn->p.rsp.fw_ver);
3629 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
3630 flags);
3631 }
3632 } while (retry);
3633
3634 verify_done:
3635 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
3636
3637 if (rval != QLA_SUCCESS) {
3638 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
3639 "Failed=%x.\n", rval);
3640 } else {
3641 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
3642 "Done %s.\n", __func__);
3643 }
3644
3645 return rval;
3646 }
3647
3648 int
3649 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
3650 {
3651 int rval;
3652 unsigned long flags;
3653 mbx_cmd_t mc;
3654 mbx_cmd_t *mcp = &mc;
3655 struct qla_hw_data *ha = vha->hw;
3656
3657 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
3658 "Entered %s.\n", __func__);
3659
3660 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
3661 mcp->mb[1] = req->options;
3662 mcp->mb[2] = MSW(LSD(req->dma));
3663 mcp->mb[3] = LSW(LSD(req->dma));
3664 mcp->mb[6] = MSW(MSD(req->dma));
3665 mcp->mb[7] = LSW(MSD(req->dma));
3666 mcp->mb[5] = req->length;
3667 if (req->rsp)
3668 mcp->mb[10] = req->rsp->id;
3669 mcp->mb[12] = req->qos;
3670 mcp->mb[11] = req->vp_idx;
3671 mcp->mb[13] = req->rid;
3672 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3673 mcp->mb[15] = 0;
3674
3675 mcp->mb[4] = req->id;
3676 /* que in ptr index */
3677 mcp->mb[8] = 0;
3678 /* que out ptr index */
3679 mcp->mb[9] = 0;
3680 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
3681 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3682 mcp->in_mb = MBX_0;
3683 mcp->flags = MBX_DMA_OUT;
3684 mcp->tov = MBX_TOV_SECONDS * 2;
3685
3686 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3687 mcp->in_mb |= MBX_1;
3688 if (IS_QLA83XX(ha) || !IS_QLA27XX(ha)) {
3689 mcp->out_mb |= MBX_15;
3690 /* debug q create issue in SR-IOV */
3691 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3692 }
3693
3694 spin_lock_irqsave(&ha->hardware_lock, flags);
3695 if (!(req->options & BIT_0)) {
3696 WRT_REG_DWORD(req->req_q_in, 0);
3697 if (!IS_QLA83XX(ha) || !IS_QLA27XX(ha))
3698 WRT_REG_DWORD(req->req_q_out, 0);
3699 }
3700 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3701
3702 rval = qla2x00_mailbox_command(vha, mcp);
3703 if (rval != QLA_SUCCESS) {
3704 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
3705 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3706 } else {
3707 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
3708 "Done %s.\n", __func__);
3709 }
3710
3711 return rval;
3712 }
3713
3714 int
3715 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
3716 {
3717 int rval;
3718 unsigned long flags;
3719 mbx_cmd_t mc;
3720 mbx_cmd_t *mcp = &mc;
3721 struct qla_hw_data *ha = vha->hw;
3722
3723 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
3724 "Entered %s.\n", __func__);
3725
3726 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
3727 mcp->mb[1] = rsp->options;
3728 mcp->mb[2] = MSW(LSD(rsp->dma));
3729 mcp->mb[3] = LSW(LSD(rsp->dma));
3730 mcp->mb[6] = MSW(MSD(rsp->dma));
3731 mcp->mb[7] = LSW(MSD(rsp->dma));
3732 mcp->mb[5] = rsp->length;
3733 mcp->mb[14] = rsp->msix->entry;
3734 mcp->mb[13] = rsp->rid;
3735 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3736 mcp->mb[15] = 0;
3737
3738 mcp->mb[4] = rsp->id;
3739 /* que in ptr index */
3740 mcp->mb[8] = 0;
3741 /* que out ptr index */
3742 mcp->mb[9] = 0;
3743 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
3744 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3745 mcp->in_mb = MBX_0;
3746 mcp->flags = MBX_DMA_OUT;
3747 mcp->tov = MBX_TOV_SECONDS * 2;
3748
3749 if (IS_QLA81XX(ha)) {
3750 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
3751 mcp->in_mb |= MBX_1;
3752 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3753 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
3754 mcp->in_mb |= MBX_1;
3755 /* debug q create issue in SR-IOV */
3756 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3757 }
3758
3759 spin_lock_irqsave(&ha->hardware_lock, flags);
3760 if (!(rsp->options & BIT_0)) {
3761 WRT_REG_DWORD(rsp->rsp_q_out, 0);
3762 if (!IS_QLA83XX(ha))
3763 WRT_REG_DWORD(rsp->rsp_q_in, 0);
3764 }
3765
3766 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3767
3768 rval = qla2x00_mailbox_command(vha, mcp);
3769 if (rval != QLA_SUCCESS) {
3770 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
3771 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3772 } else {
3773 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
3774 "Done %s.\n", __func__);
3775 }
3776
3777 return rval;
3778 }
3779
3780 int
3781 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
3782 {
3783 int rval;
3784 mbx_cmd_t mc;
3785 mbx_cmd_t *mcp = &mc;
3786
3787 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
3788 "Entered %s.\n", __func__);
3789
3790 mcp->mb[0] = MBC_IDC_ACK;
3791 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3792 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3793 mcp->in_mb = MBX_0;
3794 mcp->tov = MBX_TOV_SECONDS;
3795 mcp->flags = 0;
3796 rval = qla2x00_mailbox_command(vha, mcp);
3797
3798 if (rval != QLA_SUCCESS) {
3799 ql_dbg(ql_dbg_mbx, vha, 0x10da,
3800 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3801 } else {
3802 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
3803 "Done %s.\n", __func__);
3804 }
3805
3806 return rval;
3807 }
3808
3809 int
3810 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
3811 {
3812 int rval;
3813 mbx_cmd_t mc;
3814 mbx_cmd_t *mcp = &mc;
3815
3816 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
3817 "Entered %s.\n", __func__);
3818
3819 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
3820 !IS_QLA27XX(vha->hw))
3821 return QLA_FUNCTION_FAILED;
3822
3823 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3824 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
3825 mcp->out_mb = MBX_1|MBX_0;
3826 mcp->in_mb = MBX_1|MBX_0;
3827 mcp->tov = MBX_TOV_SECONDS;
3828 mcp->flags = 0;
3829 rval = qla2x00_mailbox_command(vha, mcp);
3830
3831 if (rval != QLA_SUCCESS) {
3832 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
3833 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3834 rval, mcp->mb[0], mcp->mb[1]);
3835 } else {
3836 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
3837 "Done %s.\n", __func__);
3838 *sector_size = mcp->mb[1];
3839 }
3840
3841 return rval;
3842 }
3843
3844 int
3845 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
3846 {
3847 int rval;
3848 mbx_cmd_t mc;
3849 mbx_cmd_t *mcp = &mc;
3850
3851 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
3852 !IS_QLA27XX(vha->hw))
3853 return QLA_FUNCTION_FAILED;
3854
3855 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
3856 "Entered %s.\n", __func__);
3857
3858 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3859 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
3860 FAC_OPT_CMD_WRITE_PROTECT;
3861 mcp->out_mb = MBX_1|MBX_0;
3862 mcp->in_mb = MBX_1|MBX_0;
3863 mcp->tov = MBX_TOV_SECONDS;
3864 mcp->flags = 0;
3865 rval = qla2x00_mailbox_command(vha, mcp);
3866
3867 if (rval != QLA_SUCCESS) {
3868 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
3869 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3870 rval, mcp->mb[0], mcp->mb[1]);
3871 } else {
3872 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
3873 "Done %s.\n", __func__);
3874 }
3875
3876 return rval;
3877 }
3878
3879 int
3880 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
3881 {
3882 int rval;
3883 mbx_cmd_t mc;
3884 mbx_cmd_t *mcp = &mc;
3885
3886 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
3887 !IS_QLA27XX(vha->hw))
3888 return QLA_FUNCTION_FAILED;
3889
3890 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
3891 "Entered %s.\n", __func__);
3892
3893 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3894 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
3895 mcp->mb[2] = LSW(start);
3896 mcp->mb[3] = MSW(start);
3897 mcp->mb[4] = LSW(finish);
3898 mcp->mb[5] = MSW(finish);
3899 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3900 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3901 mcp->tov = MBX_TOV_SECONDS;
3902 mcp->flags = 0;
3903 rval = qla2x00_mailbox_command(vha, mcp);
3904
3905 if (rval != QLA_SUCCESS) {
3906 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
3907 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3908 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
3909 } else {
3910 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
3911 "Done %s.\n", __func__);
3912 }
3913
3914 return rval;
3915 }
3916
3917 int
3918 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
3919 {
3920 int rval = 0;
3921 mbx_cmd_t mc;
3922 mbx_cmd_t *mcp = &mc;
3923
3924 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
3925 "Entered %s.\n", __func__);
3926
3927 mcp->mb[0] = MBC_RESTART_MPI_FW;
3928 mcp->out_mb = MBX_0;
3929 mcp->in_mb = MBX_0|MBX_1;
3930 mcp->tov = MBX_TOV_SECONDS;
3931 mcp->flags = 0;
3932 rval = qla2x00_mailbox_command(vha, mcp);
3933
3934 if (rval != QLA_SUCCESS) {
3935 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
3936 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3937 rval, mcp->mb[0], mcp->mb[1]);
3938 } else {
3939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
3940 "Done %s.\n", __func__);
3941 }
3942
3943 return rval;
3944 }
3945
3946 int
3947 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
3948 {
3949 int rval;
3950 mbx_cmd_t mc;
3951 mbx_cmd_t *mcp = &mc;
3952 int i;
3953 int len;
3954 uint16_t *str;
3955 struct qla_hw_data *ha = vha->hw;
3956
3957 if (!IS_P3P_TYPE(ha))
3958 return QLA_FUNCTION_FAILED;
3959
3960 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
3961 "Entered %s.\n", __func__);
3962
3963 str = (void *)version;
3964 len = strlen(version);
3965
3966 mcp->mb[0] = MBC_SET_RNID_PARAMS;
3967 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
3968 mcp->out_mb = MBX_1|MBX_0;
3969 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
3970 mcp->mb[i] = cpu_to_le16p(str);
3971 mcp->out_mb |= 1<<i;
3972 }
3973 for (; i < 16; i++) {
3974 mcp->mb[i] = 0;
3975 mcp->out_mb |= 1<<i;
3976 }
3977 mcp->in_mb = MBX_1|MBX_0;
3978 mcp->tov = MBX_TOV_SECONDS;
3979 mcp->flags = 0;
3980 rval = qla2x00_mailbox_command(vha, mcp);
3981
3982 if (rval != QLA_SUCCESS) {
3983 ql_dbg(ql_dbg_mbx, vha, 0x117c,
3984 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
3985 } else {
3986 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
3987 "Done %s.\n", __func__);
3988 }
3989
3990 return rval;
3991 }
3992
3993 int
3994 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
3995 {
3996 int rval;
3997 mbx_cmd_t mc;
3998 mbx_cmd_t *mcp = &mc;
3999 int len;
4000 uint16_t dwlen;
4001 uint8_t *str;
4002 dma_addr_t str_dma;
4003 struct qla_hw_data *ha = vha->hw;
4004
4005 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4006 IS_P3P_TYPE(ha))
4007 return QLA_FUNCTION_FAILED;
4008
4009 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4010 "Entered %s.\n", __func__);
4011
4012 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4013 if (!str) {
4014 ql_log(ql_log_warn, vha, 0x117f,
4015 "Failed to allocate driver version param.\n");
4016 return QLA_MEMORY_ALLOC_FAILED;
4017 }
4018
4019 memcpy(str, "\x7\x3\x11\x0", 4);
4020 dwlen = str[0];
4021 len = dwlen * 4 - 4;
4022 memset(str + 4, 0, len);
4023 if (len > strlen(version))
4024 len = strlen(version);
4025 memcpy(str + 4, version, len);
4026
4027 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4028 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4029 mcp->mb[2] = MSW(LSD(str_dma));
4030 mcp->mb[3] = LSW(LSD(str_dma));
4031 mcp->mb[6] = MSW(MSD(str_dma));
4032 mcp->mb[7] = LSW(MSD(str_dma));
4033 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4034 mcp->in_mb = MBX_1|MBX_0;
4035 mcp->tov = MBX_TOV_SECONDS;
4036 mcp->flags = 0;
4037 rval = qla2x00_mailbox_command(vha, mcp);
4038
4039 if (rval != QLA_SUCCESS) {
4040 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4041 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4042 } else {
4043 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4044 "Done %s.\n", __func__);
4045 }
4046
4047 dma_pool_free(ha->s_dma_pool, str, str_dma);
4048
4049 return rval;
4050 }
4051
4052 static int
4053 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4054 {
4055 int rval;
4056 mbx_cmd_t mc;
4057 mbx_cmd_t *mcp = &mc;
4058
4059 if (!IS_FWI2_CAPABLE(vha->hw))
4060 return QLA_FUNCTION_FAILED;
4061
4062 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4063 "Entered %s.\n", __func__);
4064
4065 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4066 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4067 mcp->out_mb = MBX_1|MBX_0;
4068 mcp->in_mb = MBX_1|MBX_0;
4069 mcp->tov = MBX_TOV_SECONDS;
4070 mcp->flags = 0;
4071 rval = qla2x00_mailbox_command(vha, mcp);
4072 *temp = mcp->mb[1];
4073
4074 if (rval != QLA_SUCCESS) {
4075 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4076 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4077 } else {
4078 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4079 "Done %s.\n", __func__);
4080 }
4081
4082 return rval;
4083 }
4084
4085 int
4086 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4087 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
4088 {
4089 int rval;
4090 mbx_cmd_t mc;
4091 mbx_cmd_t *mcp = &mc;
4092 struct qla_hw_data *ha = vha->hw;
4093
4094 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4095 "Entered %s.\n", __func__);
4096
4097 if (!IS_FWI2_CAPABLE(ha))
4098 return QLA_FUNCTION_FAILED;
4099
4100 if (len == 1)
4101 opt |= BIT_0;
4102
4103 mcp->mb[0] = MBC_READ_SFP;
4104 mcp->mb[1] = dev;
4105 mcp->mb[2] = MSW(sfp_dma);
4106 mcp->mb[3] = LSW(sfp_dma);
4107 mcp->mb[6] = MSW(MSD(sfp_dma));
4108 mcp->mb[7] = LSW(MSD(sfp_dma));
4109 mcp->mb[8] = len;
4110 mcp->mb[9] = off;
4111 mcp->mb[10] = opt;
4112 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4113 mcp->in_mb = MBX_1|MBX_0;
4114 mcp->tov = MBX_TOV_SECONDS;
4115 mcp->flags = 0;
4116 rval = qla2x00_mailbox_command(vha, mcp);
4117
4118 if (opt & BIT_0)
4119 *sfp = mcp->mb[1];
4120
4121 if (rval != QLA_SUCCESS) {
4122 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4123 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4124 } else {
4125 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4126 "Done %s.\n", __func__);
4127 }
4128
4129 return rval;
4130 }
4131
4132 int
4133 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4134 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
4135 {
4136 int rval;
4137 mbx_cmd_t mc;
4138 mbx_cmd_t *mcp = &mc;
4139 struct qla_hw_data *ha = vha->hw;
4140
4141 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4142 "Entered %s.\n", __func__);
4143
4144 if (!IS_FWI2_CAPABLE(ha))
4145 return QLA_FUNCTION_FAILED;
4146
4147 if (len == 1)
4148 opt |= BIT_0;
4149
4150 if (opt & BIT_0)
4151 len = *sfp;
4152
4153 mcp->mb[0] = MBC_WRITE_SFP;
4154 mcp->mb[1] = dev;
4155 mcp->mb[2] = MSW(sfp_dma);
4156 mcp->mb[3] = LSW(sfp_dma);
4157 mcp->mb[6] = MSW(MSD(sfp_dma));
4158 mcp->mb[7] = LSW(MSD(sfp_dma));
4159 mcp->mb[8] = len;
4160 mcp->mb[9] = off;
4161 mcp->mb[10] = opt;
4162 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4163 mcp->in_mb = MBX_1|MBX_0;
4164 mcp->tov = MBX_TOV_SECONDS;
4165 mcp->flags = 0;
4166 rval = qla2x00_mailbox_command(vha, mcp);
4167
4168 if (rval != QLA_SUCCESS) {
4169 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4170 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4171 } else {
4172 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4173 "Done %s.\n", __func__);
4174 }
4175
4176 return rval;
4177 }
4178
4179 int
4180 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4181 uint16_t size_in_bytes, uint16_t *actual_size)
4182 {
4183 int rval;
4184 mbx_cmd_t mc;
4185 mbx_cmd_t *mcp = &mc;
4186
4187 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4188 "Entered %s.\n", __func__);
4189
4190 if (!IS_CNA_CAPABLE(vha->hw))
4191 return QLA_FUNCTION_FAILED;
4192
4193 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4194 mcp->mb[2] = MSW(stats_dma);
4195 mcp->mb[3] = LSW(stats_dma);
4196 mcp->mb[6] = MSW(MSD(stats_dma));
4197 mcp->mb[7] = LSW(MSD(stats_dma));
4198 mcp->mb[8] = size_in_bytes >> 2;
4199 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4200 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4201 mcp->tov = MBX_TOV_SECONDS;
4202 mcp->flags = 0;
4203 rval = qla2x00_mailbox_command(vha, mcp);
4204
4205 if (rval != QLA_SUCCESS) {
4206 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4207 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4208 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4209 } else {
4210 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4211 "Done %s.\n", __func__);
4212
4213
4214 *actual_size = mcp->mb[2] << 2;
4215 }
4216
4217 return rval;
4218 }
4219
4220 int
4221 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4222 uint16_t size)
4223 {
4224 int rval;
4225 mbx_cmd_t mc;
4226 mbx_cmd_t *mcp = &mc;
4227
4228 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4229 "Entered %s.\n", __func__);
4230
4231 if (!IS_CNA_CAPABLE(vha->hw))
4232 return QLA_FUNCTION_FAILED;
4233
4234 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4235 mcp->mb[1] = 0;
4236 mcp->mb[2] = MSW(tlv_dma);
4237 mcp->mb[3] = LSW(tlv_dma);
4238 mcp->mb[6] = MSW(MSD(tlv_dma));
4239 mcp->mb[7] = LSW(MSD(tlv_dma));
4240 mcp->mb[8] = size;
4241 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4242 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4243 mcp->tov = MBX_TOV_SECONDS;
4244 mcp->flags = 0;
4245 rval = qla2x00_mailbox_command(vha, mcp);
4246
4247 if (rval != QLA_SUCCESS) {
4248 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4249 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4250 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4251 } else {
4252 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4253 "Done %s.\n", __func__);
4254 }
4255
4256 return rval;
4257 }
4258
4259 int
4260 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4261 {
4262 int rval;
4263 mbx_cmd_t mc;
4264 mbx_cmd_t *mcp = &mc;
4265
4266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4267 "Entered %s.\n", __func__);
4268
4269 if (!IS_FWI2_CAPABLE(vha->hw))
4270 return QLA_FUNCTION_FAILED;
4271
4272 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4273 mcp->mb[1] = LSW(risc_addr);
4274 mcp->mb[8] = MSW(risc_addr);
4275 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4276 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4277 mcp->tov = 30;
4278 mcp->flags = 0;
4279 rval = qla2x00_mailbox_command(vha, mcp);
4280 if (rval != QLA_SUCCESS) {
4281 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4282 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4283 } else {
4284 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4285 "Done %s.\n", __func__);
4286 *data = mcp->mb[3] << 16 | mcp->mb[2];
4287 }
4288
4289 return rval;
4290 }
4291
4292 int
4293 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4294 uint16_t *mresp)
4295 {
4296 int rval;
4297 mbx_cmd_t mc;
4298 mbx_cmd_t *mcp = &mc;
4299
4300 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4301 "Entered %s.\n", __func__);
4302
4303 memset(mcp->mb, 0 , sizeof(mcp->mb));
4304 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4305 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4306
4307 /* transfer count */
4308 mcp->mb[10] = LSW(mreq->transfer_size);
4309 mcp->mb[11] = MSW(mreq->transfer_size);
4310
4311 /* send data address */
4312 mcp->mb[14] = LSW(mreq->send_dma);
4313 mcp->mb[15] = MSW(mreq->send_dma);
4314 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4315 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4316
4317 /* receive data address */
4318 mcp->mb[16] = LSW(mreq->rcv_dma);
4319 mcp->mb[17] = MSW(mreq->rcv_dma);
4320 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4321 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4322
4323 /* Iteration count */
4324 mcp->mb[18] = LSW(mreq->iteration_count);
4325 mcp->mb[19] = MSW(mreq->iteration_count);
4326
4327 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4328 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
4329 if (IS_CNA_CAPABLE(vha->hw))
4330 mcp->out_mb |= MBX_2;
4331 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4332
4333 mcp->buf_size = mreq->transfer_size;
4334 mcp->tov = MBX_TOV_SECONDS;
4335 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4336
4337 rval = qla2x00_mailbox_command(vha, mcp);
4338
4339 if (rval != QLA_SUCCESS) {
4340 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4341 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4342 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4343 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
4344 } else {
4345 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4346 "Done %s.\n", __func__);
4347 }
4348
4349 /* Copy mailbox information */
4350 memcpy( mresp, mcp->mb, 64);
4351 return rval;
4352 }
4353
4354 int
4355 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4356 uint16_t *mresp)
4357 {
4358 int rval;
4359 mbx_cmd_t mc;
4360 mbx_cmd_t *mcp = &mc;
4361 struct qla_hw_data *ha = vha->hw;
4362
4363 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4364 "Entered %s.\n", __func__);
4365
4366 memset(mcp->mb, 0 , sizeof(mcp->mb));
4367 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
4368 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
4369 if (IS_CNA_CAPABLE(ha)) {
4370 mcp->mb[1] |= BIT_15;
4371 mcp->mb[2] = vha->fcoe_fcf_idx;
4372 }
4373 mcp->mb[16] = LSW(mreq->rcv_dma);
4374 mcp->mb[17] = MSW(mreq->rcv_dma);
4375 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4376 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4377
4378 mcp->mb[10] = LSW(mreq->transfer_size);
4379
4380 mcp->mb[14] = LSW(mreq->send_dma);
4381 mcp->mb[15] = MSW(mreq->send_dma);
4382 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4383 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4384
4385 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4386 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
4387 if (IS_CNA_CAPABLE(ha))
4388 mcp->out_mb |= MBX_2;
4389
4390 mcp->in_mb = MBX_0;
4391 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4392 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
4393 mcp->in_mb |= MBX_1;
4394 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
4395 mcp->in_mb |= MBX_3;
4396
4397 mcp->tov = MBX_TOV_SECONDS;
4398 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4399 mcp->buf_size = mreq->transfer_size;
4400
4401 rval = qla2x00_mailbox_command(vha, mcp);
4402
4403 if (rval != QLA_SUCCESS) {
4404 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4405 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4406 rval, mcp->mb[0], mcp->mb[1]);
4407 } else {
4408 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4409 "Done %s.\n", __func__);
4410 }
4411
4412 /* Copy mailbox information */
4413 memcpy(mresp, mcp->mb, 64);
4414 return rval;
4415 }
4416
4417 int
4418 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
4419 {
4420 int rval;
4421 mbx_cmd_t mc;
4422 mbx_cmd_t *mcp = &mc;
4423
4424 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
4425 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
4426
4427 mcp->mb[0] = MBC_ISP84XX_RESET;
4428 mcp->mb[1] = enable_diagnostic;
4429 mcp->out_mb = MBX_1|MBX_0;
4430 mcp->in_mb = MBX_1|MBX_0;
4431 mcp->tov = MBX_TOV_SECONDS;
4432 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4433 rval = qla2x00_mailbox_command(vha, mcp);
4434
4435 if (rval != QLA_SUCCESS)
4436 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
4437 else
4438 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4439 "Done %s.\n", __func__);
4440
4441 return rval;
4442 }
4443
4444 int
4445 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4446 {
4447 int rval;
4448 mbx_cmd_t mc;
4449 mbx_cmd_t *mcp = &mc;
4450
4451 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4452 "Entered %s.\n", __func__);
4453
4454 if (!IS_FWI2_CAPABLE(vha->hw))
4455 return QLA_FUNCTION_FAILED;
4456
4457 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4458 mcp->mb[1] = LSW(risc_addr);
4459 mcp->mb[2] = LSW(data);
4460 mcp->mb[3] = MSW(data);
4461 mcp->mb[8] = MSW(risc_addr);
4462 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4463 mcp->in_mb = MBX_0;
4464 mcp->tov = 30;
4465 mcp->flags = 0;
4466 rval = qla2x00_mailbox_command(vha, mcp);
4467 if (rval != QLA_SUCCESS) {
4468 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4469 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4470 } else {
4471 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4472 "Done %s.\n", __func__);
4473 }
4474
4475 return rval;
4476 }
4477
4478 int
4479 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4480 {
4481 int rval;
4482 uint32_t stat, timer;
4483 uint16_t mb0 = 0;
4484 struct qla_hw_data *ha = vha->hw;
4485 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4486
4487 rval = QLA_SUCCESS;
4488
4489 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4490 "Entered %s.\n", __func__);
4491
4492 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4493
4494 /* Write the MBC data to the registers */
4495 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4496 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4497 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4498 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4499 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4500
4501 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4502
4503 /* Poll for MBC interrupt */
4504 for (timer = 6000000; timer; timer--) {
4505 /* Check for pending interrupts. */
4506 stat = RD_REG_DWORD(&reg->host_status);
4507 if (stat & HSRX_RISC_INT) {
4508 stat &= 0xff;
4509
4510 if (stat == 0x1 || stat == 0x2 ||
4511 stat == 0x10 || stat == 0x11) {
4512 set_bit(MBX_INTERRUPT,
4513 &ha->mbx_cmd_flags);
4514 mb0 = RD_REG_WORD(&reg->mailbox0);
4515 WRT_REG_DWORD(&reg->hccr,
4516 HCCRX_CLR_RISC_INT);
4517 RD_REG_DWORD(&reg->hccr);
4518 break;
4519 }
4520 }
4521 udelay(5);
4522 }
4523
4524 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
4525 rval = mb0 & MBS_MASK;
4526 else
4527 rval = QLA_FUNCTION_FAILED;
4528
4529 if (rval != QLA_SUCCESS) {
4530 ql_dbg(ql_dbg_mbx, vha, 0x1104,
4531 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
4532 } else {
4533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
4534 "Done %s.\n", __func__);
4535 }
4536
4537 return rval;
4538 }
4539
4540 int
4541 qla2x00_get_data_rate(scsi_qla_host_t *vha)
4542 {
4543 int rval;
4544 mbx_cmd_t mc;
4545 mbx_cmd_t *mcp = &mc;
4546 struct qla_hw_data *ha = vha->hw;
4547
4548 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
4549 "Entered %s.\n", __func__);
4550
4551 if (!IS_FWI2_CAPABLE(ha))
4552 return QLA_FUNCTION_FAILED;
4553
4554 mcp->mb[0] = MBC_DATA_RATE;
4555 mcp->mb[1] = 0;
4556 mcp->out_mb = MBX_1|MBX_0;
4557 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4558 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4559 mcp->in_mb |= MBX_3;
4560 mcp->tov = MBX_TOV_SECONDS;
4561 mcp->flags = 0;
4562 rval = qla2x00_mailbox_command(vha, mcp);
4563 if (rval != QLA_SUCCESS) {
4564 ql_dbg(ql_dbg_mbx, vha, 0x1107,
4565 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4566 } else {
4567 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
4568 "Done %s.\n", __func__);
4569 if (mcp->mb[1] != 0x7)
4570 ha->link_data_rate = mcp->mb[1];
4571 }
4572
4573 return rval;
4574 }
4575
4576 int
4577 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4578 {
4579 int rval;
4580 mbx_cmd_t mc;
4581 mbx_cmd_t *mcp = &mc;
4582 struct qla_hw_data *ha = vha->hw;
4583
4584 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
4585 "Entered %s.\n", __func__);
4586
4587 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
4588 !IS_QLA27XX(ha))
4589 return QLA_FUNCTION_FAILED;
4590 mcp->mb[0] = MBC_GET_PORT_CONFIG;
4591 mcp->out_mb = MBX_0;
4592 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4593 mcp->tov = MBX_TOV_SECONDS;
4594 mcp->flags = 0;
4595
4596 rval = qla2x00_mailbox_command(vha, mcp);
4597
4598 if (rval != QLA_SUCCESS) {
4599 ql_dbg(ql_dbg_mbx, vha, 0x110a,
4600 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4601 } else {
4602 /* Copy all bits to preserve original value */
4603 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
4604
4605 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
4606 "Done %s.\n", __func__);
4607 }
4608 return rval;
4609 }
4610
4611 int
4612 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4613 {
4614 int rval;
4615 mbx_cmd_t mc;
4616 mbx_cmd_t *mcp = &mc;
4617
4618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
4619 "Entered %s.\n", __func__);
4620
4621 mcp->mb[0] = MBC_SET_PORT_CONFIG;
4622 /* Copy all bits to preserve original setting */
4623 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
4624 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4625 mcp->in_mb = MBX_0;
4626 mcp->tov = MBX_TOV_SECONDS;
4627 mcp->flags = 0;
4628 rval = qla2x00_mailbox_command(vha, mcp);
4629
4630 if (rval != QLA_SUCCESS) {
4631 ql_dbg(ql_dbg_mbx, vha, 0x110d,
4632 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4633 } else
4634 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
4635 "Done %s.\n", __func__);
4636
4637 return rval;
4638 }
4639
4640
4641 int
4642 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
4643 uint16_t *mb)
4644 {
4645 int rval;
4646 mbx_cmd_t mc;
4647 mbx_cmd_t *mcp = &mc;
4648 struct qla_hw_data *ha = vha->hw;
4649
4650 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
4651 "Entered %s.\n", __func__);
4652
4653 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
4654 return QLA_FUNCTION_FAILED;
4655
4656 mcp->mb[0] = MBC_PORT_PARAMS;
4657 mcp->mb[1] = loop_id;
4658 if (ha->flags.fcp_prio_enabled)
4659 mcp->mb[2] = BIT_1;
4660 else
4661 mcp->mb[2] = BIT_2;
4662 mcp->mb[4] = priority & 0xf;
4663 mcp->mb[9] = vha->vp_idx;
4664 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4665 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
4666 mcp->tov = 30;
4667 mcp->flags = 0;
4668 rval = qla2x00_mailbox_command(vha, mcp);
4669 if (mb != NULL) {
4670 mb[0] = mcp->mb[0];
4671 mb[1] = mcp->mb[1];
4672 mb[3] = mcp->mb[3];
4673 mb[4] = mcp->mb[4];
4674 }
4675
4676 if (rval != QLA_SUCCESS) {
4677 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
4678 } else {
4679 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
4680 "Done %s.\n", __func__);
4681 }
4682
4683 return rval;
4684 }
4685
4686 int
4687 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
4688 {
4689 int rval = QLA_FUNCTION_FAILED;
4690 struct qla_hw_data *ha = vha->hw;
4691 uint8_t byte;
4692
4693 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
4694 ql_dbg(ql_dbg_mbx, vha, 0x1150,
4695 "Thermal not supported by this card.\n");
4696 return rval;
4697 }
4698
4699 if (IS_QLA25XX(ha)) {
4700 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
4701 ha->pdev->subsystem_device == 0x0175) {
4702 rval = qla2x00_read_sfp(vha, 0, &byte,
4703 0x98, 0x1, 1, BIT_13|BIT_0);
4704 *temp = byte;
4705 return rval;
4706 }
4707 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
4708 ha->pdev->subsystem_device == 0x338e) {
4709 rval = qla2x00_read_sfp(vha, 0, &byte,
4710 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
4711 *temp = byte;
4712 return rval;
4713 }
4714 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
4715 "Thermal not supported by this card.\n");
4716 return rval;
4717 }
4718
4719 if (IS_QLA82XX(ha)) {
4720 *temp = qla82xx_read_temperature(vha);
4721 rval = QLA_SUCCESS;
4722 return rval;
4723 } else if (IS_QLA8044(ha)) {
4724 *temp = qla8044_read_temperature(vha);
4725 rval = QLA_SUCCESS;
4726 return rval;
4727 }
4728
4729 rval = qla2x00_read_asic_temperature(vha, temp);
4730 return rval;
4731 }
4732
4733 int
4734 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
4735 {
4736 int rval;
4737 struct qla_hw_data *ha = vha->hw;
4738 mbx_cmd_t mc;
4739 mbx_cmd_t *mcp = &mc;
4740
4741 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
4742 "Entered %s.\n", __func__);
4743
4744 if (!IS_FWI2_CAPABLE(ha))
4745 return QLA_FUNCTION_FAILED;
4746
4747 memset(mcp, 0, sizeof(mbx_cmd_t));
4748 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
4749 mcp->mb[1] = 1;
4750
4751 mcp->out_mb = MBX_1|MBX_0;
4752 mcp->in_mb = MBX_0;
4753 mcp->tov = 30;
4754 mcp->flags = 0;
4755
4756 rval = qla2x00_mailbox_command(vha, mcp);
4757 if (rval != QLA_SUCCESS) {
4758 ql_dbg(ql_dbg_mbx, vha, 0x1016,
4759 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4760 } else {
4761 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
4762 "Done %s.\n", __func__);
4763 }
4764
4765 return rval;
4766 }
4767
4768 int
4769 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
4770 {
4771 int rval;
4772 struct qla_hw_data *ha = vha->hw;
4773 mbx_cmd_t mc;
4774 mbx_cmd_t *mcp = &mc;
4775
4776 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
4777 "Entered %s.\n", __func__);
4778
4779 if (!IS_P3P_TYPE(ha))
4780 return QLA_FUNCTION_FAILED;
4781
4782 memset(mcp, 0, sizeof(mbx_cmd_t));
4783 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
4784 mcp->mb[1] = 0;
4785
4786 mcp->out_mb = MBX_1|MBX_0;
4787 mcp->in_mb = MBX_0;
4788 mcp->tov = 30;
4789 mcp->flags = 0;
4790
4791 rval = qla2x00_mailbox_command(vha, mcp);
4792 if (rval != QLA_SUCCESS) {
4793 ql_dbg(ql_dbg_mbx, vha, 0x100c,
4794 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4795 } else {
4796 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
4797 "Done %s.\n", __func__);
4798 }
4799
4800 return rval;
4801 }
4802
4803 int
4804 qla82xx_md_get_template_size(scsi_qla_host_t *vha)
4805 {
4806 struct qla_hw_data *ha = vha->hw;
4807 mbx_cmd_t mc;
4808 mbx_cmd_t *mcp = &mc;
4809 int rval = QLA_FUNCTION_FAILED;
4810
4811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
4812 "Entered %s.\n", __func__);
4813
4814 memset(mcp->mb, 0 , sizeof(mcp->mb));
4815 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4816 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4817 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
4818 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
4819
4820 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4821 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
4822 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4823
4824 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4825 mcp->tov = MBX_TOV_SECONDS;
4826 rval = qla2x00_mailbox_command(vha, mcp);
4827
4828 /* Always copy back return mailbox values. */
4829 if (rval != QLA_SUCCESS) {
4830 ql_dbg(ql_dbg_mbx, vha, 0x1120,
4831 "mailbox command FAILED=0x%x, subcode=%x.\n",
4832 (mcp->mb[1] << 16) | mcp->mb[0],
4833 (mcp->mb[3] << 16) | mcp->mb[2]);
4834 } else {
4835 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
4836 "Done %s.\n", __func__);
4837 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
4838 if (!ha->md_template_size) {
4839 ql_dbg(ql_dbg_mbx, vha, 0x1122,
4840 "Null template size obtained.\n");
4841 rval = QLA_FUNCTION_FAILED;
4842 }
4843 }
4844 return rval;
4845 }
4846
4847 int
4848 qla82xx_md_get_template(scsi_qla_host_t *vha)
4849 {
4850 struct qla_hw_data *ha = vha->hw;
4851 mbx_cmd_t mc;
4852 mbx_cmd_t *mcp = &mc;
4853 int rval = QLA_FUNCTION_FAILED;
4854
4855 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
4856 "Entered %s.\n", __func__);
4857
4858 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4859 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4860 if (!ha->md_tmplt_hdr) {
4861 ql_log(ql_log_warn, vha, 0x1124,
4862 "Unable to allocate memory for Minidump template.\n");
4863 return rval;
4864 }
4865
4866 memset(mcp->mb, 0 , sizeof(mcp->mb));
4867 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4868 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4869 mcp->mb[2] = LSW(RQST_TMPLT);
4870 mcp->mb[3] = MSW(RQST_TMPLT);
4871 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
4872 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
4873 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
4874 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
4875 mcp->mb[8] = LSW(ha->md_template_size);
4876 mcp->mb[9] = MSW(ha->md_template_size);
4877
4878 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4879 mcp->tov = MBX_TOV_SECONDS;
4880 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
4881 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4882 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4883 rval = qla2x00_mailbox_command(vha, mcp);
4884
4885 if (rval != QLA_SUCCESS) {
4886 ql_dbg(ql_dbg_mbx, vha, 0x1125,
4887 "mailbox command FAILED=0x%x, subcode=%x.\n",
4888 ((mcp->mb[1] << 16) | mcp->mb[0]),
4889 ((mcp->mb[3] << 16) | mcp->mb[2]));
4890 } else
4891 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
4892 "Done %s.\n", __func__);
4893 return rval;
4894 }
4895
4896 int
4897 qla8044_md_get_template(scsi_qla_host_t *vha)
4898 {
4899 struct qla_hw_data *ha = vha->hw;
4900 mbx_cmd_t mc;
4901 mbx_cmd_t *mcp = &mc;
4902 int rval = QLA_FUNCTION_FAILED;
4903 int offset = 0, size = MINIDUMP_SIZE_36K;
4904 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
4905 "Entered %s.\n", __func__);
4906
4907 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4908 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4909 if (!ha->md_tmplt_hdr) {
4910 ql_log(ql_log_warn, vha, 0xb11b,
4911 "Unable to allocate memory for Minidump template.\n");
4912 return rval;
4913 }
4914
4915 memset(mcp->mb, 0 , sizeof(mcp->mb));
4916 while (offset < ha->md_template_size) {
4917 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4918 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4919 mcp->mb[2] = LSW(RQST_TMPLT);
4920 mcp->mb[3] = MSW(RQST_TMPLT);
4921 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
4922 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
4923 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
4924 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
4925 mcp->mb[8] = LSW(size);
4926 mcp->mb[9] = MSW(size);
4927 mcp->mb[10] = offset & 0x0000FFFF;
4928 mcp->mb[11] = offset & 0xFFFF0000;
4929 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4930 mcp->tov = MBX_TOV_SECONDS;
4931 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
4932 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4933 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4934 rval = qla2x00_mailbox_command(vha, mcp);
4935
4936 if (rval != QLA_SUCCESS) {
4937 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
4938 "mailbox command FAILED=0x%x, subcode=%x.\n",
4939 ((mcp->mb[1] << 16) | mcp->mb[0]),
4940 ((mcp->mb[3] << 16) | mcp->mb[2]));
4941 return rval;
4942 } else
4943 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
4944 "Done %s.\n", __func__);
4945 offset = offset + size;
4946 }
4947 return rval;
4948 }
4949
4950 int
4951 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
4952 {
4953 int rval;
4954 struct qla_hw_data *ha = vha->hw;
4955 mbx_cmd_t mc;
4956 mbx_cmd_t *mcp = &mc;
4957
4958 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
4959 return QLA_FUNCTION_FAILED;
4960
4961 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
4962 "Entered %s.\n", __func__);
4963
4964 memset(mcp, 0, sizeof(mbx_cmd_t));
4965 mcp->mb[0] = MBC_SET_LED_CONFIG;
4966 mcp->mb[1] = led_cfg[0];
4967 mcp->mb[2] = led_cfg[1];
4968 if (IS_QLA8031(ha)) {
4969 mcp->mb[3] = led_cfg[2];
4970 mcp->mb[4] = led_cfg[3];
4971 mcp->mb[5] = led_cfg[4];
4972 mcp->mb[6] = led_cfg[5];
4973 }
4974
4975 mcp->out_mb = MBX_2|MBX_1|MBX_0;
4976 if (IS_QLA8031(ha))
4977 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
4978 mcp->in_mb = MBX_0;
4979 mcp->tov = 30;
4980 mcp->flags = 0;
4981
4982 rval = qla2x00_mailbox_command(vha, mcp);
4983 if (rval != QLA_SUCCESS) {
4984 ql_dbg(ql_dbg_mbx, vha, 0x1134,
4985 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4986 } else {
4987 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
4988 "Done %s.\n", __func__);
4989 }
4990
4991 return rval;
4992 }
4993
4994 int
4995 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
4996 {
4997 int rval;
4998 struct qla_hw_data *ha = vha->hw;
4999 mbx_cmd_t mc;
5000 mbx_cmd_t *mcp = &mc;
5001
5002 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5003 return QLA_FUNCTION_FAILED;
5004
5005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5006 "Entered %s.\n", __func__);
5007
5008 memset(mcp, 0, sizeof(mbx_cmd_t));
5009 mcp->mb[0] = MBC_GET_LED_CONFIG;
5010
5011 mcp->out_mb = MBX_0;
5012 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5013 if (IS_QLA8031(ha))
5014 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5015 mcp->tov = 30;
5016 mcp->flags = 0;
5017
5018 rval = qla2x00_mailbox_command(vha, mcp);
5019 if (rval != QLA_SUCCESS) {
5020 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5021 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5022 } else {
5023 led_cfg[0] = mcp->mb[1];
5024 led_cfg[1] = mcp->mb[2];
5025 if (IS_QLA8031(ha)) {
5026 led_cfg[2] = mcp->mb[3];
5027 led_cfg[3] = mcp->mb[4];
5028 led_cfg[4] = mcp->mb[5];
5029 led_cfg[5] = mcp->mb[6];
5030 }
5031 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5032 "Done %s.\n", __func__);
5033 }
5034
5035 return rval;
5036 }
5037
5038 int
5039 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5040 {
5041 int rval;
5042 struct qla_hw_data *ha = vha->hw;
5043 mbx_cmd_t mc;
5044 mbx_cmd_t *mcp = &mc;
5045
5046 if (!IS_P3P_TYPE(ha))
5047 return QLA_FUNCTION_FAILED;
5048
5049 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
5050 "Entered %s.\n", __func__);
5051
5052 memset(mcp, 0, sizeof(mbx_cmd_t));
5053 mcp->mb[0] = MBC_SET_LED_CONFIG;
5054 if (enable)
5055 mcp->mb[7] = 0xE;
5056 else
5057 mcp->mb[7] = 0xD;
5058
5059 mcp->out_mb = MBX_7|MBX_0;
5060 mcp->in_mb = MBX_0;
5061 mcp->tov = MBX_TOV_SECONDS;
5062 mcp->flags = 0;
5063
5064 rval = qla2x00_mailbox_command(vha, mcp);
5065 if (rval != QLA_SUCCESS) {
5066 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5067 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5068 } else {
5069 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
5070 "Done %s.\n", __func__);
5071 }
5072
5073 return rval;
5074 }
5075
5076 int
5077 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
5078 {
5079 int rval;
5080 struct qla_hw_data *ha = vha->hw;
5081 mbx_cmd_t mc;
5082 mbx_cmd_t *mcp = &mc;
5083
5084 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
5085 return QLA_FUNCTION_FAILED;
5086
5087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5088 "Entered %s.\n", __func__);
5089
5090 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5091 mcp->mb[1] = LSW(reg);
5092 mcp->mb[2] = MSW(reg);
5093 mcp->mb[3] = LSW(data);
5094 mcp->mb[4] = MSW(data);
5095 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5096
5097 mcp->in_mb = MBX_1|MBX_0;
5098 mcp->tov = MBX_TOV_SECONDS;
5099 mcp->flags = 0;
5100 rval = qla2x00_mailbox_command(vha, mcp);
5101
5102 if (rval != QLA_SUCCESS) {
5103 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5104 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5105 } else {
5106 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
5107 "Done %s.\n", __func__);
5108 }
5109
5110 return rval;
5111 }
5112
5113 int
5114 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5115 {
5116 int rval;
5117 struct qla_hw_data *ha = vha->hw;
5118 mbx_cmd_t mc;
5119 mbx_cmd_t *mcp = &mc;
5120
5121 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5122 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
5123 "Implicit LOGO Unsupported.\n");
5124 return QLA_FUNCTION_FAILED;
5125 }
5126
5127
5128 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5129 "Entering %s.\n", __func__);
5130
5131 /* Perform Implicit LOGO. */
5132 mcp->mb[0] = MBC_PORT_LOGOUT;
5133 mcp->mb[1] = fcport->loop_id;
5134 mcp->mb[10] = BIT_15;
5135 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5136 mcp->in_mb = MBX_0;
5137 mcp->tov = MBX_TOV_SECONDS;
5138 mcp->flags = 0;
5139 rval = qla2x00_mailbox_command(vha, mcp);
5140 if (rval != QLA_SUCCESS)
5141 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5142 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5143 else
5144 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5145 "Done %s.\n", __func__);
5146
5147 return rval;
5148 }
5149
5150 int
5151 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5152 {
5153 int rval;
5154 mbx_cmd_t mc;
5155 mbx_cmd_t *mcp = &mc;
5156 struct qla_hw_data *ha = vha->hw;
5157 unsigned long retry_max_time = jiffies + (2 * HZ);
5158
5159 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
5160 return QLA_FUNCTION_FAILED;
5161
5162 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5163
5164 retry_rd_reg:
5165 mcp->mb[0] = MBC_READ_REMOTE_REG;
5166 mcp->mb[1] = LSW(reg);
5167 mcp->mb[2] = MSW(reg);
5168 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5169 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5170 mcp->tov = MBX_TOV_SECONDS;
5171 mcp->flags = 0;
5172 rval = qla2x00_mailbox_command(vha, mcp);
5173
5174 if (rval != QLA_SUCCESS) {
5175 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5176 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5177 rval, mcp->mb[0], mcp->mb[1]);
5178 } else {
5179 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5180 if (*data == QLA8XXX_BAD_VALUE) {
5181 /*
5182 * During soft-reset CAMRAM register reads might
5183 * return 0xbad0bad0. So retry for MAX of 2 sec
5184 * while reading camram registers.
5185 */
5186 if (time_after(jiffies, retry_max_time)) {
5187 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5188 "Failure to read CAMRAM register. "
5189 "data=0x%x.\n", *data);
5190 return QLA_FUNCTION_FAILED;
5191 }
5192 msleep(100);
5193 goto retry_rd_reg;
5194 }
5195 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5196 }
5197
5198 return rval;
5199 }
5200
5201 int
5202 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5203 {
5204 int rval;
5205 mbx_cmd_t mc;
5206 mbx_cmd_t *mcp = &mc;
5207 struct qla_hw_data *ha = vha->hw;
5208
5209 if (!IS_QLA83XX(ha))
5210 return QLA_FUNCTION_FAILED;
5211
5212 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5213
5214 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5215 mcp->out_mb = MBX_0;
5216 mcp->in_mb = MBX_1|MBX_0;
5217 mcp->tov = MBX_TOV_SECONDS;
5218 mcp->flags = 0;
5219 rval = qla2x00_mailbox_command(vha, mcp);
5220
5221 if (rval != QLA_SUCCESS) {
5222 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5223 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5224 rval, mcp->mb[0], mcp->mb[1]);
5225 ha->isp_ops->fw_dump(vha, 0);
5226 } else {
5227 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5228 }
5229
5230 return rval;
5231 }
5232
5233 int
5234 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5235 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5236 {
5237 int rval;
5238 mbx_cmd_t mc;
5239 mbx_cmd_t *mcp = &mc;
5240 uint8_t subcode = (uint8_t)options;
5241 struct qla_hw_data *ha = vha->hw;
5242
5243 if (!IS_QLA8031(ha))
5244 return QLA_FUNCTION_FAILED;
5245
5246 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5247
5248 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5249 mcp->mb[1] = options;
5250 mcp->out_mb = MBX_1|MBX_0;
5251 if (subcode & BIT_2) {
5252 mcp->mb[2] = LSW(start_addr);
5253 mcp->mb[3] = MSW(start_addr);
5254 mcp->mb[4] = LSW(end_addr);
5255 mcp->mb[5] = MSW(end_addr);
5256 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5257 }
5258 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5259 if (!(subcode & (BIT_2 | BIT_5)))
5260 mcp->in_mb |= MBX_4|MBX_3;
5261 mcp->tov = MBX_TOV_SECONDS;
5262 mcp->flags = 0;
5263 rval = qla2x00_mailbox_command(vha, mcp);
5264
5265 if (rval != QLA_SUCCESS) {
5266 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5267 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5268 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5269 mcp->mb[4]);
5270 ha->isp_ops->fw_dump(vha, 0);
5271 } else {
5272 if (subcode & BIT_5)
5273 *sector_size = mcp->mb[1];
5274 else if (subcode & (BIT_6 | BIT_7)) {
5275 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5276 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5277 } else if (subcode & (BIT_3 | BIT_4)) {
5278 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5279 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5280 }
5281 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5282 }
5283
5284 return rval;
5285 }
5286
5287 int
5288 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5289 uint32_t size)
5290 {
5291 int rval;
5292 mbx_cmd_t mc;
5293 mbx_cmd_t *mcp = &mc;
5294
5295 if (!IS_MCTP_CAPABLE(vha->hw))
5296 return QLA_FUNCTION_FAILED;
5297
5298 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5299 "Entered %s.\n", __func__);
5300
5301 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5302 mcp->mb[1] = LSW(addr);
5303 mcp->mb[2] = MSW(req_dma);
5304 mcp->mb[3] = LSW(req_dma);
5305 mcp->mb[4] = MSW(size);
5306 mcp->mb[5] = LSW(size);
5307 mcp->mb[6] = MSW(MSD(req_dma));
5308 mcp->mb[7] = LSW(MSD(req_dma));
5309 mcp->mb[8] = MSW(addr);
5310 /* Setting RAM ID to valid */
5311 mcp->mb[10] |= BIT_7;
5312 /* For MCTP RAM ID is 0x40 */
5313 mcp->mb[10] |= 0x40;
5314
5315 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5316 MBX_0;
5317
5318 mcp->in_mb = MBX_0;
5319 mcp->tov = MBX_TOV_SECONDS;
5320 mcp->flags = 0;
5321 rval = qla2x00_mailbox_command(vha, mcp);
5322
5323 if (rval != QLA_SUCCESS) {
5324 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5325 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5326 } else {
5327 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5328 "Done %s.\n", __func__);
5329 }
5330
5331 return rval;
5332 }