]>
git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/scsi/qla2xxx/qla_sup.c
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <asm/uaccess.h>
12 static uint16_t qla2x00_nvram_request(scsi_qla_host_t
*, uint32_t);
13 static void qla2x00_nv_deselect(scsi_qla_host_t
*);
14 static void qla2x00_nv_write(scsi_qla_host_t
*, uint16_t);
17 * NVRAM support routines
21 * qla2x00_lock_nvram_access() -
25 qla2x00_lock_nvram_access(scsi_qla_host_t
*ha
)
28 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
30 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
31 data
= RD_REG_WORD(®
->nvram
);
32 while (data
& NVR_BUSY
) {
34 data
= RD_REG_WORD(®
->nvram
);
38 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
39 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
41 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
42 while ((data
& BIT_0
) == 0) {
45 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
46 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
48 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
54 * qla2x00_unlock_nvram_access() -
58 qla2x00_unlock_nvram_access(scsi_qla_host_t
*ha
)
60 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
62 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
63 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0);
64 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
69 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
70 * request routine to get the word from NVRAM.
72 * @addr: Address in NVRAM to read
74 * Returns the word read from nvram @addr.
77 qla2x00_get_nvram_word(scsi_qla_host_t
*ha
, uint32_t addr
)
84 data
= qla2x00_nvram_request(ha
, nv_cmd
);
90 * qla2x00_write_nvram_word() - Write NVRAM data.
92 * @addr: Address in NVRAM to write
93 * @data: word to program
96 qla2x00_write_nvram_word(scsi_qla_host_t
*ha
, uint32_t addr
, uint16_t data
)
101 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
103 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
104 qla2x00_nv_write(ha
, 0);
105 qla2x00_nv_write(ha
, 0);
107 for (word
= 0; word
< 8; word
++)
108 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
110 qla2x00_nv_deselect(ha
);
113 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
116 for (count
= 0; count
< 27; count
++) {
118 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
120 qla2x00_nv_write(ha
, 0);
125 qla2x00_nv_deselect(ha
);
127 /* Wait for NVRAM to become ready */
128 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
131 word
= RD_REG_WORD(®
->nvram
);
132 } while ((word
& NVR_DATA_IN
) == 0);
134 qla2x00_nv_deselect(ha
);
137 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
138 for (count
= 0; count
< 10; count
++)
139 qla2x00_nv_write(ha
, 0);
141 qla2x00_nv_deselect(ha
);
145 qla2x00_write_nvram_word_tmo(scsi_qla_host_t
*ha
, uint32_t addr
, uint16_t data
,
151 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
155 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
156 qla2x00_nv_write(ha
, 0);
157 qla2x00_nv_write(ha
, 0);
159 for (word
= 0; word
< 8; word
++)
160 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
162 qla2x00_nv_deselect(ha
);
165 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
168 for (count
= 0; count
< 27; count
++) {
170 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
172 qla2x00_nv_write(ha
, 0);
177 qla2x00_nv_deselect(ha
);
179 /* Wait for NVRAM to become ready */
180 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
183 word
= RD_REG_WORD(®
->nvram
);
185 ret
= QLA_FUNCTION_FAILED
;
188 } while ((word
& NVR_DATA_IN
) == 0);
190 qla2x00_nv_deselect(ha
);
193 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
194 for (count
= 0; count
< 10; count
++)
195 qla2x00_nv_write(ha
, 0);
197 qla2x00_nv_deselect(ha
);
203 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
206 * @nv_cmd: NVRAM command
208 * Bit definitions for NVRAM command:
211 * Bit 25, 24 = opcode
212 * Bit 23-16 = address
213 * Bit 15-0 = write data
215 * Returns the word read from nvram @addr.
218 qla2x00_nvram_request(scsi_qla_host_t
*ha
, uint32_t nv_cmd
)
221 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
225 /* Send command to NVRAM. */
227 for (cnt
= 0; cnt
< 11; cnt
++) {
229 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
231 qla2x00_nv_write(ha
, 0);
235 /* Read data from NVRAM. */
236 for (cnt
= 0; cnt
< 16; cnt
++) {
237 WRT_REG_WORD(®
->nvram
, NVR_SELECT
| NVR_CLOCK
);
240 reg_data
= RD_REG_WORD(®
->nvram
);
241 if (reg_data
& NVR_DATA_IN
)
243 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
244 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
249 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
250 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
257 * qla2x00_nv_write() - Clean NVRAM operations.
261 qla2x00_nv_deselect(scsi_qla_host_t
*ha
)
263 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
265 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
266 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
271 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
273 * @data: Serial interface selector
276 qla2x00_nv_write(scsi_qla_host_t
*ha
, uint16_t data
)
278 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
280 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
281 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
283 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_CLOCK
|
285 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
287 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
288 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
293 * qla2x00_clear_nvram_protection() -
297 qla2x00_clear_nvram_protection(scsi_qla_host_t
*ha
)
300 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
302 uint16_t wprot
, wprot_old
;
304 /* Clear NVRAM write protection. */
305 ret
= QLA_FUNCTION_FAILED
;
306 wprot_old
= cpu_to_le16(qla2x00_get_nvram_word(ha
, 0));
307 stat
= qla2x00_write_nvram_word_tmo(ha
, 0,
308 __constant_cpu_to_le16(0x1234), 100000);
309 wprot
= cpu_to_le16(qla2x00_get_nvram_word(ha
, 0));
310 if (stat
!= QLA_SUCCESS
|| wprot
!= __constant_cpu_to_le16(0x1234)) {
312 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
313 qla2x00_nv_write(ha
, 0);
314 qla2x00_nv_write(ha
, 0);
315 for (word
= 0; word
< 8; word
++)
316 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
318 qla2x00_nv_deselect(ha
);
320 /* Enable protection register. */
321 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
322 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
323 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
324 for (word
= 0; word
< 8; word
++)
325 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
327 qla2x00_nv_deselect(ha
);
329 /* Clear protection register (ffff is cleared). */
330 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
331 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
332 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
333 for (word
= 0; word
< 8; word
++)
334 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
336 qla2x00_nv_deselect(ha
);
338 /* Wait for NVRAM to become ready. */
339 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
342 word
= RD_REG_WORD(®
->nvram
);
343 } while ((word
& NVR_DATA_IN
) == 0);
347 qla2x00_write_nvram_word(ha
, 0, wprot_old
);
353 qla2x00_set_nvram_protection(scsi_qla_host_t
*ha
, int stat
)
355 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
358 if (stat
!= QLA_SUCCESS
)
361 /* Set NVRAM write protection. */
363 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
364 qla2x00_nv_write(ha
, 0);
365 qla2x00_nv_write(ha
, 0);
366 for (word
= 0; word
< 8; word
++)
367 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
369 qla2x00_nv_deselect(ha
);
371 /* Enable protection register. */
372 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
373 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
374 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
375 for (word
= 0; word
< 8; word
++)
376 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
378 qla2x00_nv_deselect(ha
);
380 /* Enable protection register. */
381 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
382 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
383 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
384 for (word
= 0; word
< 8; word
++)
385 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
387 qla2x00_nv_deselect(ha
);
389 /* Wait for NVRAM to become ready. */
390 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
393 word
= RD_REG_WORD(®
->nvram
);
394 } while ((word
& NVR_DATA_IN
) == 0);
398 /*****************************************************************************/
399 /* Flash Manipulation Routines */
400 /*****************************************************************************/
402 static inline uint32_t
403 flash_conf_to_access_addr(uint32_t faddr
)
405 return FARX_ACCESS_FLASH_CONF
| faddr
;
408 static inline uint32_t
409 flash_data_to_access_addr(uint32_t faddr
)
411 return FARX_ACCESS_FLASH_DATA
| faddr
;
414 static inline uint32_t
415 nvram_conf_to_access_addr(uint32_t naddr
)
417 return FARX_ACCESS_NVRAM_CONF
| naddr
;
420 static inline uint32_t
421 nvram_data_to_access_addr(uint32_t naddr
)
423 return FARX_ACCESS_NVRAM_DATA
| naddr
;
427 qla24xx_read_flash_dword(scsi_qla_host_t
*ha
, uint32_t addr
)
431 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
433 WRT_REG_DWORD(®
->flash_addr
, addr
& ~FARX_DATA_FLAG
);
434 /* Wait for READ cycle to complete. */
437 (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) == 0 &&
438 rval
== QLA_SUCCESS
; cnt
--) {
442 rval
= QLA_FUNCTION_TIMEOUT
;
445 /* TODO: What happens if we time out? */
447 if (rval
== QLA_SUCCESS
)
448 data
= RD_REG_DWORD(®
->flash_data
);
454 qla24xx_read_flash_data(scsi_qla_host_t
*ha
, uint32_t *dwptr
, uint32_t faddr
,
459 /* Dword reads to flash. */
460 for (i
= 0; i
< dwords
; i
++, faddr
++)
461 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
462 flash_data_to_access_addr(faddr
)));
468 qla24xx_write_flash_dword(scsi_qla_host_t
*ha
, uint32_t addr
, uint32_t data
)
472 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
474 WRT_REG_DWORD(®
->flash_data
, data
);
475 RD_REG_DWORD(®
->flash_data
); /* PCI Posting. */
476 WRT_REG_DWORD(®
->flash_addr
, addr
| FARX_DATA_FLAG
);
477 /* Wait for Write cycle to complete. */
479 for (cnt
= 500000; (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) &&
480 rval
== QLA_SUCCESS
; cnt
--) {
484 rval
= QLA_FUNCTION_TIMEOUT
;
490 qla24xx_get_flash_manufacturer(scsi_qla_host_t
*ha
, uint8_t *man_id
,
495 ids
= qla24xx_read_flash_dword(ha
, flash_data_to_access_addr(0xd03ab));
497 *flash_id
= MSB(ids
);
501 qla24xx_write_flash_data(scsi_qla_host_t
*ha
, uint32_t *dwptr
, uint32_t faddr
,
506 uint32_t sec_mask
, rest_addr
, conf_addr
;
508 uint8_t man_id
, flash_id
;
509 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
513 qla24xx_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
514 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__
,
515 ha
->host_no
, man_id
, flash_id
));
517 conf_addr
= flash_conf_to_access_addr(0x03d8);
519 case 0xbf: /* STT flash. */
522 if (flash_id
== 0x80)
523 conf_addr
= flash_conf_to_access_addr(0x0352);
525 case 0x13: /* ST M25P80. */
530 /* Default to 64 kb sector size. */
536 /* Enable flash write. */
537 WRT_REG_DWORD(®
->ctrl_status
,
538 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
539 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
541 /* Disable flash write-protection. */
542 qla24xx_write_flash_dword(ha
, flash_conf_to_access_addr(0x101), 0);
544 do { /* Loop once to provide quick error exit. */
545 for (liter
= 0; liter
< dwords
; liter
++, faddr
++, dwptr
++) {
546 /* Are we at the beginning of a sector? */
547 if ((faddr
& rest_addr
) == 0) {
548 fdata
= (faddr
& sec_mask
) << 2;
549 ret
= qla24xx_write_flash_dword(ha
, conf_addr
,
550 (fdata
& 0xff00) |((fdata
<< 16) &
551 0xff0000) | ((fdata
>> 16) & 0xff));
552 if (ret
!= QLA_SUCCESS
) {
553 DEBUG9(printk("%s(%ld) Unable to flash "
554 "sector: address=%x.\n", __func__
,
555 ha
->host_no
, faddr
));
559 ret
= qla24xx_write_flash_dword(ha
,
560 flash_data_to_access_addr(faddr
),
561 cpu_to_le32(*dwptr
));
562 if (ret
!= QLA_SUCCESS
) {
563 DEBUG9(printk("%s(%ld) Unable to program flash "
564 "address=%x data=%x.\n", __func__
,
565 ha
->host_no
, faddr
, *dwptr
));
571 /* Disable flash write. */
572 WRT_REG_DWORD(®
->ctrl_status
,
573 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
574 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
580 qla2x00_read_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
586 /* Word reads to NVRAM via registers. */
587 wptr
= (uint16_t *)buf
;
588 qla2x00_lock_nvram_access(ha
);
589 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++)
590 wptr
[i
] = cpu_to_le16(qla2x00_get_nvram_word(ha
,
592 qla2x00_unlock_nvram_access(ha
);
598 qla24xx_read_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
604 /* Dword reads to flash. */
605 dwptr
= (uint32_t *)buf
;
606 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
607 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
608 nvram_data_to_access_addr(naddr
)));
614 qla2x00_write_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
623 qla2x00_lock_nvram_access(ha
);
625 /* Disable NVRAM write-protection. */
626 stat
= qla2x00_clear_nvram_protection(ha
);
628 wptr
= (uint16_t *)buf
;
629 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++) {
630 qla2x00_write_nvram_word(ha
, naddr
,
635 /* Enable NVRAM write-protection. */
636 qla2x00_set_nvram_protection(ha
, stat
);
638 qla2x00_unlock_nvram_access(ha
);
644 qla24xx_write_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
650 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
654 /* Enable flash write. */
655 WRT_REG_DWORD(®
->ctrl_status
,
656 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
657 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
659 /* Disable NVRAM write-protection. */
660 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
662 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
665 /* Dword writes to flash. */
666 dwptr
= (uint32_t *)buf
;
667 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++, dwptr
++) {
668 ret
= qla24xx_write_flash_dword(ha
,
669 nvram_data_to_access_addr(naddr
),
670 cpu_to_le32(*dwptr
));
671 if (ret
!= QLA_SUCCESS
) {
672 DEBUG9(printk("%s(%ld) Unable to program "
673 "nvram address=%x data=%x.\n", __func__
,
674 ha
->host_no
, naddr
, *dwptr
));
679 /* Enable NVRAM write-protection. */
680 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
683 /* Disable flash write. */
684 WRT_REG_DWORD(®
->ctrl_status
,
685 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
686 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */