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Merge tag 'devprop-fix-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_tmpl.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include "qla_tmpl.h"
9
10 /* note default template is in big endian */
11 static const uint32_t ql27xx_fwdt_default_template[] = {
12 0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
13 0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
14 0x00000000, 0x00000000, 0x00000000, 0x00000000,
15 0x00000000, 0x00000000, 0x00000000, 0x00000000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000,
17 0x00000000, 0x00000000, 0x00000000, 0x00000000,
18 0x00000000, 0x00000000, 0x00000000, 0x00000000,
19 0x00000000, 0x00000000, 0x00000000, 0x00000000,
20 0x00000000, 0x00000000, 0x00000000, 0x00000000,
21 0x00000000, 0x00000000, 0x00000000, 0x00000000,
22 0x00000000, 0x04010000, 0x14000000, 0x00000000,
23 0x02000000, 0x44000000, 0x09010000, 0x10000000,
24 0x00000000, 0x02000000, 0x01010000, 0x1c000000,
25 0x00000000, 0x02000000, 0x00600000, 0x00000000,
26 0xc0000000, 0x01010000, 0x1c000000, 0x00000000,
27 0x02000000, 0x00600000, 0x00000000, 0xcc000000,
28 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
29 0x10600000, 0x00000000, 0xd4000000, 0x01010000,
30 0x1c000000, 0x00000000, 0x02000000, 0x700f0000,
31 0x00000060, 0xf0000000, 0x00010000, 0x18000000,
32 0x00000000, 0x02000000, 0x00700000, 0x041000c0,
33 0x00010000, 0x18000000, 0x00000000, 0x02000000,
34 0x10700000, 0x041000c0, 0x00010000, 0x18000000,
35 0x00000000, 0x02000000, 0x40700000, 0x041000c0,
36 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
37 0x007c0000, 0x01000000, 0xc0000000, 0x00010000,
38 0x18000000, 0x00000000, 0x02000000, 0x007c0000,
39 0x040300c4, 0x00010000, 0x18000000, 0x00000000,
40 0x02000000, 0x007c0000, 0x040100c0, 0x01010000,
41 0x1c000000, 0x00000000, 0x02000000, 0x007c0000,
42 0x00000000, 0xc0000000, 0x00010000, 0x18000000,
43 0x00000000, 0x02000000, 0x007c0000, 0x04200000,
44 0x0b010000, 0x18000000, 0x00000000, 0x02000000,
45 0x0c000000, 0x00000000, 0x02010000, 0x20000000,
46 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
47 0xf0000000, 0x000000b0, 0x02010000, 0x20000000,
48 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
49 0xf0000000, 0x000010b0, 0x02010000, 0x20000000,
50 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
51 0xf0000000, 0x000020b0, 0x02010000, 0x20000000,
52 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
53 0xf0000000, 0x000030b0, 0x02010000, 0x20000000,
54 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
55 0xf0000000, 0x000040b0, 0x02010000, 0x20000000,
56 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
57 0xf0000000, 0x000050b0, 0x02010000, 0x20000000,
58 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
59 0xf0000000, 0x000060b0, 0x02010000, 0x20000000,
60 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
61 0xf0000000, 0x000070b0, 0x02010000, 0x20000000,
62 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
63 0xf0000000, 0x000080b0, 0x02010000, 0x20000000,
64 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
65 0xf0000000, 0x000090b0, 0x02010000, 0x20000000,
66 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
67 0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000,
68 0x00000000, 0x02000000, 0x0a000000, 0x040100c0,
69 0x00010000, 0x18000000, 0x00000000, 0x02000000,
70 0x0a000000, 0x04200080, 0x00010000, 0x18000000,
71 0x00000000, 0x02000000, 0x00be0000, 0x041000c0,
72 0x00010000, 0x18000000, 0x00000000, 0x02000000,
73 0x10be0000, 0x041000c0, 0x00010000, 0x18000000,
74 0x00000000, 0x02000000, 0x20be0000, 0x041000c0,
75 0x00010000, 0x18000000, 0x00000000, 0x02000000,
76 0x30be0000, 0x041000c0, 0x00010000, 0x18000000,
77 0x00000000, 0x02000000, 0x00b00000, 0x041000c0,
78 0x00010000, 0x18000000, 0x00000000, 0x02000000,
79 0x10b00000, 0x041000c0, 0x00010000, 0x18000000,
80 0x00000000, 0x02000000, 0x20b00000, 0x041000c0,
81 0x00010000, 0x18000000, 0x00000000, 0x02000000,
82 0x30b00000, 0x041000c0, 0x00010000, 0x18000000,
83 0x00000000, 0x02000000, 0x00300000, 0x041000c0,
84 0x00010000, 0x18000000, 0x00000000, 0x02000000,
85 0x10300000, 0x041000c0, 0x00010000, 0x18000000,
86 0x00000000, 0x02000000, 0x20300000, 0x041000c0,
87 0x00010000, 0x18000000, 0x00000000, 0x02000000,
88 0x30300000, 0x041000c0, 0x0a010000, 0x10000000,
89 0x00000000, 0x02000000, 0x06010000, 0x1c000000,
90 0x00000000, 0x02000000, 0x01000000, 0x00000200,
91 0xff230200, 0x06010000, 0x1c000000, 0x00000000,
92 0x02000000, 0x02000000, 0x00001000, 0x00000000,
93 0x07010000, 0x18000000, 0x00000000, 0x02000000,
94 0x00000000, 0x01000000, 0x07010000, 0x18000000,
95 0x00000000, 0x02000000, 0x00000000, 0x02000000,
96 0x07010000, 0x18000000, 0x00000000, 0x02000000,
97 0x00000000, 0x03000000, 0x0d010000, 0x14000000,
98 0x00000000, 0x02000000, 0x00000000, 0xff000000,
99 0x10000000, 0x00000000, 0x00000080,
100 };
101
102 static inline void __iomem *
103 qla27xx_isp_reg(struct scsi_qla_host *vha)
104 {
105 return &vha->hw->iobase->isp24;
106 }
107
108 static inline void
109 qla27xx_insert16(uint16_t value, void *buf, ulong *len)
110 {
111 if (buf) {
112 buf += *len;
113 *(__le16 *)buf = cpu_to_le16(value);
114 }
115 *len += sizeof(value);
116 }
117
118 static inline void
119 qla27xx_insert32(uint32_t value, void *buf, ulong *len)
120 {
121 if (buf) {
122 buf += *len;
123 *(__le32 *)buf = cpu_to_le32(value);
124 }
125 *len += sizeof(value);
126 }
127
128 static inline void
129 qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
130 {
131
132 if (buf && mem && size) {
133 buf += *len;
134 memcpy(buf, mem, size);
135 }
136 *len += size;
137 }
138
139 static inline void
140 qla27xx_read8(void __iomem *window, void *buf, ulong *len)
141 {
142 uint8_t value = ~0;
143
144 if (buf) {
145 value = RD_REG_BYTE(window);
146 }
147 qla27xx_insert32(value, buf, len);
148 }
149
150 static inline void
151 qla27xx_read16(void __iomem *window, void *buf, ulong *len)
152 {
153 uint16_t value = ~0;
154
155 if (buf) {
156 value = RD_REG_WORD(window);
157 }
158 qla27xx_insert32(value, buf, len);
159 }
160
161 static inline void
162 qla27xx_read32(void __iomem *window, void *buf, ulong *len)
163 {
164 uint32_t value = ~0;
165
166 if (buf) {
167 value = RD_REG_DWORD(window);
168 }
169 qla27xx_insert32(value, buf, len);
170 }
171
172 static inline void (*qla27xx_read_vector(uint width))(void __iomem*, void *, ulong *)
173 {
174 return
175 (width == 1) ? qla27xx_read8 :
176 (width == 2) ? qla27xx_read16 :
177 qla27xx_read32;
178 }
179
180 static inline void
181 qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
182 uint offset, void *buf, ulong *len)
183 {
184 void __iomem *window = (void __iomem *)reg + offset;
185
186 qla27xx_read32(window, buf, len);
187 }
188
189 static inline void
190 qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
191 uint offset, uint32_t data, void *buf)
192 {
193 __iomem void *window = (void __iomem *)reg + offset;
194
195 if (buf) {
196 WRT_REG_DWORD(window, data);
197 }
198 }
199
200 static inline void
201 qla27xx_read_window(__iomem struct device_reg_24xx *reg,
202 uint32_t addr, uint offset, uint count, uint width, void *buf,
203 ulong *len)
204 {
205 void __iomem *window = (void __iomem *)reg + offset;
206 void (*readn)(void __iomem*, void *, ulong *) = qla27xx_read_vector(width);
207
208 qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
209 while (count--) {
210 qla27xx_insert32(addr, buf, len);
211 readn(window, buf, len);
212 window += width;
213 addr++;
214 }
215 }
216
217 static inline void
218 qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
219 {
220 if (buf)
221 ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY;
222 }
223
224 static int
225 qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
226 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
227 {
228 ql_dbg(ql_dbg_misc, vha, 0xd100,
229 "%s: nop [%lx]\n", __func__, *len);
230 qla27xx_skip_entry(ent, buf);
231
232 return false;
233 }
234
235 static int
236 qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
237 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
238 {
239 ql_dbg(ql_dbg_misc, vha, 0xd1ff,
240 "%s: end [%lx]\n", __func__, *len);
241 qla27xx_skip_entry(ent, buf);
242
243 /* terminate */
244 return true;
245 }
246
247 static int
248 qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
249 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
250 {
251 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
252
253 ql_dbg(ql_dbg_misc, vha, 0xd200,
254 "%s: rdio t1 [%lx]\n", __func__, *len);
255 qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
256 ent->t256.reg_count, ent->t256.reg_width, buf, len);
257
258 return false;
259 }
260
261 static int
262 qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
263 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
264 {
265 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
266
267 ql_dbg(ql_dbg_misc, vha, 0xd201,
268 "%s: wrio t1 [%lx]\n", __func__, *len);
269 qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
270 qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
271
272 return false;
273 }
274
275 static int
276 qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
277 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
278 {
279 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
280
281 ql_dbg(ql_dbg_misc, vha, 0xd202,
282 "%s: rdio t2 [%lx]\n", __func__, *len);
283 qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
284 qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
285 ent->t258.reg_count, ent->t258.reg_width, buf, len);
286
287 return false;
288 }
289
290 static int
291 qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
292 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
293 {
294 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
295
296 ql_dbg(ql_dbg_misc, vha, 0xd203,
297 "%s: wrio t2 [%lx]\n", __func__, *len);
298 qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
299 qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
300 qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
301
302 return false;
303 }
304
305 static int
306 qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
307 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
308 {
309 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
310
311 ql_dbg(ql_dbg_misc, vha, 0xd204,
312 "%s: rdpci [%lx]\n", __func__, *len);
313 qla27xx_insert32(ent->t260.pci_offset, buf, len);
314 qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
315
316 return false;
317 }
318
319 static int
320 qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
321 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
322 {
323 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
324
325 ql_dbg(ql_dbg_misc, vha, 0xd205,
326 "%s: wrpci [%lx]\n", __func__, *len);
327 qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
328
329 return false;
330 }
331
332 static int
333 qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
334 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
335 {
336 ulong dwords;
337 ulong start;
338 ulong end;
339
340 ql_dbg(ql_dbg_misc, vha, 0xd206,
341 "%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
342 start = ent->t262.start_addr;
343 end = ent->t262.end_addr;
344
345 if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
346 ;
347 } else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
348 end = vha->hw->fw_memory_size;
349 if (buf)
350 ent->t262.end_addr = end;
351 } else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
352 start = vha->hw->fw_shared_ram_start;
353 end = vha->hw->fw_shared_ram_end;
354 if (buf) {
355 ent->t262.start_addr = start;
356 ent->t262.end_addr = end;
357 }
358 } else if (ent->t262.ram_area == T262_RAM_AREA_DDR_RAM) {
359 start = vha->hw->fw_ddr_ram_start;
360 end = vha->hw->fw_ddr_ram_end;
361 if (buf) {
362 ent->t262.start_addr = start;
363 ent->t262.end_addr = end;
364 }
365 } else {
366 ql_dbg(ql_dbg_misc, vha, 0xd022,
367 "%s: unknown area %x\n", __func__, ent->t262.ram_area);
368 qla27xx_skip_entry(ent, buf);
369 goto done;
370 }
371
372 if (end < start || start == 0 || end == 0) {
373 ql_dbg(ql_dbg_misc, vha, 0xd023,
374 "%s: unusable range (start=%x end=%x)\n", __func__,
375 ent->t262.end_addr, ent->t262.start_addr);
376 qla27xx_skip_entry(ent, buf);
377 goto done;
378 }
379
380 dwords = end - start + 1;
381 if (buf) {
382 buf += *len;
383 qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
384 }
385 *len += dwords * sizeof(uint32_t);
386 done:
387 return false;
388 }
389
390 static int
391 qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
392 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
393 {
394 uint count = 0;
395 uint i;
396 uint length;
397
398 ql_dbg(ql_dbg_misc, vha, 0xd207,
399 "%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
400 if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
401 for (i = 0; i < vha->hw->max_req_queues; i++) {
402 struct req_que *req = vha->hw->req_q_map[i];
403
404 if (!test_bit(i, vha->hw->req_qid_map))
405 continue;
406
407 if (req || !buf) {
408 length = req ?
409 req->length : REQUEST_ENTRY_CNT_24XX;
410 qla27xx_insert16(i, buf, len);
411 qla27xx_insert16(length, buf, len);
412 qla27xx_insertbuf(req ? req->ring : NULL,
413 length * sizeof(*req->ring), buf, len);
414 count++;
415 }
416 }
417 } else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
418 for (i = 0; i < vha->hw->max_rsp_queues; i++) {
419 struct rsp_que *rsp = vha->hw->rsp_q_map[i];
420
421 if (!test_bit(i, vha->hw->rsp_qid_map))
422 continue;
423
424 if (rsp || !buf) {
425 length = rsp ?
426 rsp->length : RESPONSE_ENTRY_CNT_MQ;
427 qla27xx_insert16(i, buf, len);
428 qla27xx_insert16(length, buf, len);
429 qla27xx_insertbuf(rsp ? rsp->ring : NULL,
430 length * sizeof(*rsp->ring), buf, len);
431 count++;
432 }
433 }
434 } else if (QLA_TGT_MODE_ENABLED() &&
435 ent->t263.queue_type == T263_QUEUE_TYPE_ATIO) {
436 struct qla_hw_data *ha = vha->hw;
437 struct atio *atr = ha->tgt.atio_ring;
438
439 if (atr || !buf) {
440 length = ha->tgt.atio_q_length;
441 qla27xx_insert16(0, buf, len);
442 qla27xx_insert16(length, buf, len);
443 qla27xx_insertbuf(atr, length * sizeof(*atr), buf, len);
444 count++;
445 }
446 } else {
447 ql_dbg(ql_dbg_misc, vha, 0xd026,
448 "%s: unknown queue %x\n", __func__, ent->t263.queue_type);
449 qla27xx_skip_entry(ent, buf);
450 }
451
452 if (buf)
453 ent->t263.num_queues = count;
454
455 return false;
456 }
457
458 static int
459 qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
460 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
461 {
462 ql_dbg(ql_dbg_misc, vha, 0xd208,
463 "%s: getfce [%lx]\n", __func__, *len);
464 if (vha->hw->fce) {
465 if (buf) {
466 ent->t264.fce_trace_size = FCE_SIZE;
467 ent->t264.write_pointer = vha->hw->fce_wr;
468 ent->t264.base_pointer = vha->hw->fce_dma;
469 ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
470 ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
471 ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
472 ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
473 ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
474 ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
475 }
476 qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
477 } else {
478 ql_dbg(ql_dbg_misc, vha, 0xd027,
479 "%s: missing fce\n", __func__);
480 qla27xx_skip_entry(ent, buf);
481 }
482
483 return false;
484 }
485
486 static int
487 qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
488 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
489 {
490 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
491
492 ql_dbg(ql_dbg_misc, vha, 0xd209,
493 "%s: pause risc [%lx]\n", __func__, *len);
494 if (buf)
495 qla24xx_pause_risc(reg, vha->hw);
496
497 return false;
498 }
499
500 static int
501 qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
502 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
503 {
504 ql_dbg(ql_dbg_misc, vha, 0xd20a,
505 "%s: reset risc [%lx]\n", __func__, *len);
506 if (buf)
507 qla24xx_soft_reset(vha->hw);
508
509 return false;
510 }
511
512 static int
513 qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
514 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
515 {
516 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
517
518 ql_dbg(ql_dbg_misc, vha, 0xd20b,
519 "%s: dis intr [%lx]\n", __func__, *len);
520 qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
521
522 return false;
523 }
524
525 static int
526 qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
527 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
528 {
529 ql_dbg(ql_dbg_misc, vha, 0xd20c,
530 "%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len);
531 if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_TRACE) {
532 if (vha->hw->eft) {
533 if (buf) {
534 ent->t268.buf_size = EFT_SIZE;
535 ent->t268.start_addr = vha->hw->eft_dma;
536 }
537 qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
538 } else {
539 ql_dbg(ql_dbg_misc, vha, 0xd028,
540 "%s: missing eft\n", __func__);
541 qla27xx_skip_entry(ent, buf);
542 }
543 } else {
544 ql_dbg(ql_dbg_misc, vha, 0xd02b,
545 "%s: unknown buffer %x\n", __func__, ent->t268.buf_type);
546 qla27xx_skip_entry(ent, buf);
547 }
548
549 return false;
550 }
551
552 static int
553 qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
554 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
555 {
556 ql_dbg(ql_dbg_misc, vha, 0xd20d,
557 "%s: scratch [%lx]\n", __func__, *len);
558 qla27xx_insert32(0xaaaaaaaa, buf, len);
559 qla27xx_insert32(0xbbbbbbbb, buf, len);
560 qla27xx_insert32(0xcccccccc, buf, len);
561 qla27xx_insert32(0xdddddddd, buf, len);
562 qla27xx_insert32(*len + sizeof(uint32_t), buf, len);
563 if (buf)
564 ent->t269.scratch_size = 5 * sizeof(uint32_t);
565
566 return false;
567 }
568
569 static int
570 qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
571 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
572 {
573 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
574 ulong dwords = ent->t270.count;
575 ulong addr = ent->t270.addr;
576
577 ql_dbg(ql_dbg_misc, vha, 0xd20e,
578 "%s: rdremreg [%lx]\n", __func__, *len);
579 qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
580 while (dwords--) {
581 qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
582 qla27xx_insert32(addr, buf, len);
583 qla27xx_read_reg(reg, 0xc4, buf, len);
584 addr += sizeof(uint32_t);
585 }
586
587 return false;
588 }
589
590 static int
591 qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
592 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
593 {
594 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
595 ulong addr = ent->t271.addr;
596 ulong data = ent->t271.data;
597
598 ql_dbg(ql_dbg_misc, vha, 0xd20f,
599 "%s: wrremreg [%lx]\n", __func__, *len);
600 qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
601 qla27xx_write_reg(reg, 0xc4, data, buf);
602 qla27xx_write_reg(reg, 0xc0, addr, buf);
603
604 return false;
605 }
606
607 static int
608 qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
609 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
610 {
611 ulong dwords = ent->t272.count;
612 ulong start = ent->t272.addr;
613
614 ql_dbg(ql_dbg_misc, vha, 0xd210,
615 "%s: rdremram [%lx]\n", __func__, *len);
616 if (buf) {
617 ql_dbg(ql_dbg_misc, vha, 0xd02c,
618 "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
619 buf += *len;
620 qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
621 }
622 *len += dwords * sizeof(uint32_t);
623
624 return false;
625 }
626
627 static int
628 qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
629 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
630 {
631 ulong dwords = ent->t273.count;
632 ulong addr = ent->t273.addr;
633 uint32_t value;
634
635 ql_dbg(ql_dbg_misc, vha, 0xd211,
636 "%s: pcicfg [%lx]\n", __func__, *len);
637 while (dwords--) {
638 value = ~0;
639 if (pci_read_config_dword(vha->hw->pdev, addr, &value))
640 ql_dbg(ql_dbg_misc, vha, 0xd02d,
641 "%s: failed pcicfg read at %lx\n", __func__, addr);
642 qla27xx_insert32(addr, buf, len);
643 qla27xx_insert32(value, buf, len);
644 addr += sizeof(uint32_t);
645 }
646
647 return false;
648 }
649
650 static int
651 qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
652 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
653 {
654 uint count = 0;
655 uint i;
656
657 ql_dbg(ql_dbg_misc, vha, 0xd212,
658 "%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
659 if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
660 for (i = 0; i < vha->hw->max_req_queues; i++) {
661 struct req_que *req = vha->hw->req_q_map[i];
662
663 if (!test_bit(i, vha->hw->req_qid_map))
664 continue;
665
666 if (req || !buf) {
667 qla27xx_insert16(i, buf, len);
668 qla27xx_insert16(1, buf, len);
669 qla27xx_insert32(req && req->out_ptr ?
670 *req->out_ptr : 0, buf, len);
671 count++;
672 }
673 }
674 } else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
675 for (i = 0; i < vha->hw->max_rsp_queues; i++) {
676 struct rsp_que *rsp = vha->hw->rsp_q_map[i];
677
678 if (!test_bit(i, vha->hw->rsp_qid_map))
679 continue;
680
681 if (rsp || !buf) {
682 qla27xx_insert16(i, buf, len);
683 qla27xx_insert16(1, buf, len);
684 qla27xx_insert32(rsp && rsp->in_ptr ?
685 *rsp->in_ptr : 0, buf, len);
686 count++;
687 }
688 }
689 } else if (QLA_TGT_MODE_ENABLED() &&
690 ent->t274.queue_type == T274_QUEUE_TYPE_ATIO_SHAD) {
691 struct qla_hw_data *ha = vha->hw;
692 struct atio *atr = ha->tgt.atio_ring_ptr;
693
694 if (atr || !buf) {
695 qla27xx_insert16(0, buf, len);
696 qla27xx_insert16(1, buf, len);
697 qla27xx_insert32(ha->tgt.atio_q_in ?
698 readl(ha->tgt.atio_q_in) : 0, buf, len);
699 count++;
700 }
701 } else {
702 ql_dbg(ql_dbg_misc, vha, 0xd02f,
703 "%s: unknown queue %x\n", __func__, ent->t274.queue_type);
704 qla27xx_skip_entry(ent, buf);
705 }
706
707 if (buf)
708 ent->t274.num_queues = count;
709
710 if (!count)
711 qla27xx_skip_entry(ent, buf);
712
713 return false;
714 }
715
716 static int
717 qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
718 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
719 {
720 ulong offset = offsetof(typeof(*ent), t275.buffer);
721
722 ql_dbg(ql_dbg_misc, vha, 0xd213,
723 "%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
724 if (!ent->t275.length) {
725 ql_dbg(ql_dbg_misc, vha, 0xd020,
726 "%s: buffer zero length\n", __func__);
727 qla27xx_skip_entry(ent, buf);
728 goto done;
729 }
730 if (offset + ent->t275.length > ent->hdr.entry_size) {
731 ql_dbg(ql_dbg_misc, vha, 0xd030,
732 "%s: buffer overflow\n", __func__);
733 qla27xx_skip_entry(ent, buf);
734 goto done;
735 }
736
737 qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
738 done:
739 return false;
740 }
741
742 static int
743 qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
744 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
745 {
746 ql_dbg(ql_dbg_misc, vha, 0xd2ff,
747 "%s: type %x [%lx]\n", __func__, ent->hdr.entry_type, *len);
748 qla27xx_skip_entry(ent, buf);
749
750 return false;
751 }
752
753 struct qla27xx_fwdt_entry_call {
754 uint type;
755 int (*call)(
756 struct scsi_qla_host *,
757 struct qla27xx_fwdt_entry *,
758 void *,
759 ulong *);
760 };
761
762 static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = {
763 { ENTRY_TYPE_NOP , qla27xx_fwdt_entry_t0 } ,
764 { ENTRY_TYPE_TMP_END , qla27xx_fwdt_entry_t255 } ,
765 { ENTRY_TYPE_RD_IOB_T1 , qla27xx_fwdt_entry_t256 } ,
766 { ENTRY_TYPE_WR_IOB_T1 , qla27xx_fwdt_entry_t257 } ,
767 { ENTRY_TYPE_RD_IOB_T2 , qla27xx_fwdt_entry_t258 } ,
768 { ENTRY_TYPE_WR_IOB_T2 , qla27xx_fwdt_entry_t259 } ,
769 { ENTRY_TYPE_RD_PCI , qla27xx_fwdt_entry_t260 } ,
770 { ENTRY_TYPE_WR_PCI , qla27xx_fwdt_entry_t261 } ,
771 { ENTRY_TYPE_RD_RAM , qla27xx_fwdt_entry_t262 } ,
772 { ENTRY_TYPE_GET_QUEUE , qla27xx_fwdt_entry_t263 } ,
773 { ENTRY_TYPE_GET_FCE , qla27xx_fwdt_entry_t264 } ,
774 { ENTRY_TYPE_PSE_RISC , qla27xx_fwdt_entry_t265 } ,
775 { ENTRY_TYPE_RST_RISC , qla27xx_fwdt_entry_t266 } ,
776 { ENTRY_TYPE_DIS_INTR , qla27xx_fwdt_entry_t267 } ,
777 { ENTRY_TYPE_GET_HBUF , qla27xx_fwdt_entry_t268 } ,
778 { ENTRY_TYPE_SCRATCH , qla27xx_fwdt_entry_t269 } ,
779 { ENTRY_TYPE_RDREMREG , qla27xx_fwdt_entry_t270 } ,
780 { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } ,
781 { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } ,
782 { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } ,
783 { ENTRY_TYPE_GET_SHADOW , qla27xx_fwdt_entry_t274 } ,
784 { ENTRY_TYPE_WRITE_BUF , qla27xx_fwdt_entry_t275 } ,
785 { -1 , qla27xx_fwdt_entry_other }
786 };
787
788 static inline int (*qla27xx_find_entry(uint type))
789 (struct scsi_qla_host *, struct qla27xx_fwdt_entry *, void *, ulong *)
790 {
791 struct qla27xx_fwdt_entry_call *list = ql27xx_fwdt_entry_call_list;
792
793 while (list->type < type)
794 list++;
795
796 if (list->type == type)
797 return list->call;
798 return qla27xx_fwdt_entry_other;
799 }
800
801 static inline void *
802 qla27xx_next_entry(void *p)
803 {
804 struct qla27xx_fwdt_entry *ent = p;
805
806 return p + ent->hdr.entry_size;
807 }
808
809 static void
810 qla27xx_walk_template(struct scsi_qla_host *vha,
811 struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
812 {
813 struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
814 ulong count = tmp->entry_count;
815
816 ql_dbg(ql_dbg_misc, vha, 0xd01a,
817 "%s: entry count %lx\n", __func__, count);
818 while (count--) {
819 if (buf && *len >= vha->hw->fw_dump_len)
820 break;
821 if (qla27xx_find_entry(ent->hdr.entry_type)(vha, ent, buf, len))
822 break;
823 ent = qla27xx_next_entry(ent);
824 }
825
826 if (count)
827 ql_dbg(ql_dbg_misc, vha, 0xd018,
828 "%s: entry residual count (%lx)\n", __func__, count);
829
830 if (ent->hdr.entry_type != ENTRY_TYPE_TMP_END)
831 ql_dbg(ql_dbg_misc, vha, 0xd019,
832 "%s: missing end entry (%lx)\n", __func__, count);
833
834 if (buf && *len != vha->hw->fw_dump_len)
835 ql_dbg(ql_dbg_misc, vha, 0xd01b,
836 "%s: length=%#lx residual=%+ld\n",
837 __func__, *len, vha->hw->fw_dump_len - *len);
838
839 if (buf) {
840 ql_log(ql_log_warn, vha, 0xd015,
841 "Firmware dump saved to temp buffer (%lu/%p)\n",
842 vha->host_no, vha->hw->fw_dump);
843 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
844 }
845 }
846
847 static void
848 qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp)
849 {
850 tmp->capture_timestamp = jiffies;
851 }
852
853 static void
854 qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
855 {
856 uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
857
858 sscanf(qla2x00_version_str, "%hhu.%hhu.%hhu.%hhu.%hhu.%hhu",
859 v+0, v+1, v+2, v+3, v+4, v+5);
860
861 tmp->driver_info[0] = v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0];
862 tmp->driver_info[1] = v[5] << 8 | v[4];
863 tmp->driver_info[2] = 0x12345678;
864 }
865
866 static void
867 qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp,
868 struct scsi_qla_host *vha)
869 {
870 tmp->firmware_version[0] = vha->hw->fw_major_version;
871 tmp->firmware_version[1] = vha->hw->fw_minor_version;
872 tmp->firmware_version[2] = vha->hw->fw_subminor_version;
873 tmp->firmware_version[3] =
874 vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes;
875 tmp->firmware_version[4] =
876 vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0];
877 }
878
879 static void
880 ql27xx_edit_template(struct scsi_qla_host *vha,
881 struct qla27xx_fwdt_template *tmp)
882 {
883 qla27xx_time_stamp(tmp);
884 qla27xx_driver_info(tmp);
885 qla27xx_firmware_info(tmp, vha);
886 }
887
888 static inline uint32_t
889 qla27xx_template_checksum(void *p, ulong size)
890 {
891 uint32_t *buf = p;
892 uint64_t sum = 0;
893
894 size /= sizeof(*buf);
895
896 while (size--)
897 sum += *buf++;
898
899 sum = (sum & 0xffffffff) + (sum >> 32);
900
901 return ~sum;
902 }
903
904 static inline int
905 qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
906 {
907 return qla27xx_template_checksum(tmp, tmp->template_size) == 0;
908 }
909
910 static inline int
911 qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
912 {
913 return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
914 }
915
916 static void
917 qla27xx_execute_fwdt_template(struct scsi_qla_host *vha)
918 {
919 struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
920 ulong len;
921
922 if (qla27xx_fwdt_template_valid(tmp)) {
923 len = tmp->template_size;
924 tmp = memcpy(vha->hw->fw_dump, tmp, len);
925 ql27xx_edit_template(vha, tmp);
926 qla27xx_walk_template(vha, tmp, tmp, &len);
927 vha->hw->fw_dump_len = len;
928 vha->hw->fw_dumped = 1;
929 }
930 }
931
932 ulong
933 qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha)
934 {
935 struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
936 ulong len = 0;
937
938 if (qla27xx_fwdt_template_valid(tmp)) {
939 len = tmp->template_size;
940 qla27xx_walk_template(vha, tmp, NULL, &len);
941 }
942
943 return len;
944 }
945
946 ulong
947 qla27xx_fwdt_template_size(void *p)
948 {
949 struct qla27xx_fwdt_template *tmp = p;
950
951 return tmp->template_size;
952 }
953
954 ulong
955 qla27xx_fwdt_template_default_size(void)
956 {
957 return sizeof(ql27xx_fwdt_default_template);
958 }
959
960 const void *
961 qla27xx_fwdt_template_default(void)
962 {
963 return ql27xx_fwdt_default_template;
964 }
965
966 int
967 qla27xx_fwdt_template_valid(void *p)
968 {
969 struct qla27xx_fwdt_template *tmp = p;
970
971 if (!qla27xx_verify_template_header(tmp)) {
972 ql_log(ql_log_warn, NULL, 0xd01c,
973 "%s: template type %x\n", __func__, tmp->template_type);
974 return false;
975 }
976
977 if (!qla27xx_verify_template_checksum(tmp)) {
978 ql_log(ql_log_warn, NULL, 0xd01d,
979 "%s: failed template checksum\n", __func__);
980 return false;
981 }
982
983 return true;
984 }
985
986 void
987 qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked)
988 {
989 ulong flags = 0;
990
991 #ifndef __CHECKER__
992 if (!hardware_locked)
993 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
994 #endif
995
996 if (!vha->hw->fw_dump)
997 ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n");
998 else if (!vha->hw->fw_dump_template)
999 ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n");
1000 else if (vha->hw->fw_dumped)
1001 ql_log(ql_log_warn, vha, 0xd300,
1002 "Firmware has been previously dumped (%p),"
1003 " -- ignoring request\n", vha->hw->fw_dump);
1004 else
1005 qla27xx_execute_fwdt_template(vha);
1006
1007 #ifndef __CHECKER__
1008 if (!hardware_locked)
1009 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
1010 #endif
1011 }
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