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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[mirror_ubuntu-eoan-kernel.git] / drivers / scsi / qla4xxx / ql4_nx.c
1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7 #include <linux/delay.h>
8 #include <linux/io.h>
9 #include <linux/pci.h>
10 #include "ql4_def.h"
11 #include "ql4_glbl.h"
12
13 #include <asm-generic/io-64-nonatomic-lo-hi.h>
14
15 #define MASK(n) DMA_BIT_MASK(n)
16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
18 #define MS_WIN(addr) (addr & 0x0ffc0000)
19 #define QLA82XX_PCI_MN_2M (0)
20 #define QLA82XX_PCI_MS_2M (0x80000)
21 #define QLA82XX_PCI_OCM0_2M (0xc0000)
22 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
23 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
24
25 /* CRB window related */
26 #define CRB_BLK(off) ((off >> 20) & 0x3f)
27 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
28 #define CRB_WINDOW_2M (0x130060)
29 #define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \
30 ((off) & 0xf0000))
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
33 #define CRB_INDIRECT_2M (0x1e0000UL)
34
35 static inline void __iomem *
36 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
37 {
38 if ((off < ha->first_page_group_end) &&
39 (off >= ha->first_page_group_start))
40 return (void __iomem *)(ha->nx_pcibase + off);
41
42 return NULL;
43 }
44
45 #define MAX_CRB_XFORM 60
46 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
47 static int qla4_8xxx_crb_table_initialized;
48
49 #define qla4_8xxx_crb_addr_transform(name) \
50 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
51 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
52 static void
53 qla4_8xxx_crb_addr_transform_setup(void)
54 {
55 qla4_8xxx_crb_addr_transform(XDMA);
56 qla4_8xxx_crb_addr_transform(TIMR);
57 qla4_8xxx_crb_addr_transform(SRE);
58 qla4_8xxx_crb_addr_transform(SQN3);
59 qla4_8xxx_crb_addr_transform(SQN2);
60 qla4_8xxx_crb_addr_transform(SQN1);
61 qla4_8xxx_crb_addr_transform(SQN0);
62 qla4_8xxx_crb_addr_transform(SQS3);
63 qla4_8xxx_crb_addr_transform(SQS2);
64 qla4_8xxx_crb_addr_transform(SQS1);
65 qla4_8xxx_crb_addr_transform(SQS0);
66 qla4_8xxx_crb_addr_transform(RPMX7);
67 qla4_8xxx_crb_addr_transform(RPMX6);
68 qla4_8xxx_crb_addr_transform(RPMX5);
69 qla4_8xxx_crb_addr_transform(RPMX4);
70 qla4_8xxx_crb_addr_transform(RPMX3);
71 qla4_8xxx_crb_addr_transform(RPMX2);
72 qla4_8xxx_crb_addr_transform(RPMX1);
73 qla4_8xxx_crb_addr_transform(RPMX0);
74 qla4_8xxx_crb_addr_transform(ROMUSB);
75 qla4_8xxx_crb_addr_transform(SN);
76 qla4_8xxx_crb_addr_transform(QMN);
77 qla4_8xxx_crb_addr_transform(QMS);
78 qla4_8xxx_crb_addr_transform(PGNI);
79 qla4_8xxx_crb_addr_transform(PGND);
80 qla4_8xxx_crb_addr_transform(PGN3);
81 qla4_8xxx_crb_addr_transform(PGN2);
82 qla4_8xxx_crb_addr_transform(PGN1);
83 qla4_8xxx_crb_addr_transform(PGN0);
84 qla4_8xxx_crb_addr_transform(PGSI);
85 qla4_8xxx_crb_addr_transform(PGSD);
86 qla4_8xxx_crb_addr_transform(PGS3);
87 qla4_8xxx_crb_addr_transform(PGS2);
88 qla4_8xxx_crb_addr_transform(PGS1);
89 qla4_8xxx_crb_addr_transform(PGS0);
90 qla4_8xxx_crb_addr_transform(PS);
91 qla4_8xxx_crb_addr_transform(PH);
92 qla4_8xxx_crb_addr_transform(NIU);
93 qla4_8xxx_crb_addr_transform(I2Q);
94 qla4_8xxx_crb_addr_transform(EG);
95 qla4_8xxx_crb_addr_transform(MN);
96 qla4_8xxx_crb_addr_transform(MS);
97 qla4_8xxx_crb_addr_transform(CAS2);
98 qla4_8xxx_crb_addr_transform(CAS1);
99 qla4_8xxx_crb_addr_transform(CAS0);
100 qla4_8xxx_crb_addr_transform(CAM);
101 qla4_8xxx_crb_addr_transform(C2C1);
102 qla4_8xxx_crb_addr_transform(C2C0);
103 qla4_8xxx_crb_addr_transform(SMB);
104 qla4_8xxx_crb_addr_transform(OCM0);
105 qla4_8xxx_crb_addr_transform(I2C0);
106
107 qla4_8xxx_crb_table_initialized = 1;
108 }
109
110 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
111 {{{0, 0, 0, 0} } }, /* 0: PCI */
112 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
113 {1, 0x0110000, 0x0120000, 0x130000},
114 {1, 0x0120000, 0x0122000, 0x124000},
115 {1, 0x0130000, 0x0132000, 0x126000},
116 {1, 0x0140000, 0x0142000, 0x128000},
117 {1, 0x0150000, 0x0152000, 0x12a000},
118 {1, 0x0160000, 0x0170000, 0x110000},
119 {1, 0x0170000, 0x0172000, 0x12e000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x01e0000, 0x01e0800, 0x122000},
127 {0, 0x0000000, 0x0000000, 0x000000} } },
128 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
129 {{{0, 0, 0, 0} } }, /* 3: */
130 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
131 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
134 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {1, 0x08f0000, 0x08f2000, 0x172000} } },
150 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {1, 0x09f0000, 0x09f2000, 0x176000} } },
166 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
182 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
203 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
204 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
205 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
206 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
207 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
208 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
209 {{{0, 0, 0, 0} } }, /* 23: */
210 {{{0, 0, 0, 0} } }, /* 24: */
211 {{{0, 0, 0, 0} } }, /* 25: */
212 {{{0, 0, 0, 0} } }, /* 26: */
213 {{{0, 0, 0, 0} } }, /* 27: */
214 {{{0, 0, 0, 0} } }, /* 28: */
215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
218 {{{0} } }, /* 32: PCI */
219 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
220 {1, 0x2110000, 0x2120000, 0x130000},
221 {1, 0x2120000, 0x2122000, 0x124000},
222 {1, 0x2130000, 0x2132000, 0x126000},
223 {1, 0x2140000, 0x2142000, 0x128000},
224 {1, 0x2150000, 0x2152000, 0x12a000},
225 {1, 0x2160000, 0x2170000, 0x110000},
226 {1, 0x2170000, 0x2172000, 0x12e000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000} } },
235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
236 {{{0} } }, /* 35: */
237 {{{0} } }, /* 36: */
238 {{{0} } }, /* 37: */
239 {{{0} } }, /* 38: */
240 {{{0} } }, /* 39: */
241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
242 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
253 {{{0} } }, /* 52: */
254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
260 {{{0} } }, /* 59: I2C0 */
261 {{{0} } }, /* 60: I2C1 */
262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
265 };
266
267 /*
268 * top 12 bits of crb internal address (hub, agent)
269 */
270 static unsigned qla4_8xxx_crb_hub_agt[64] = {
271 0,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
275 0,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
298 0,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
301 0,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
303 0,
304 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
306 0,
307 0,
308 0,
309 0,
310 0,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
312 0,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
323 0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
328 0,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
330 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
332 0,
333 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
334 0,
335 };
336
337 /* Device states */
338 static char *qdev_state[] = {
339 "Unknown",
340 "Cold",
341 "Initializing",
342 "Ready",
343 "Need Reset",
344 "Need Quiescent",
345 "Failed",
346 "Quiescent",
347 };
348
349 /*
350 * In: 'off' is offset from CRB space in 128M pci map
351 * Out: 'off' is 2M pci map addr
352 * side effect: lock crb window
353 */
354 static void
355 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
356 {
357 u32 win_read;
358
359 ha->crb_win = CRB_HI(*off);
360 writel(ha->crb_win,
361 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
362
363 /* Read back value to make sure write has gone through before trying
364 * to use it. */
365 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
366 if (win_read != ha->crb_win) {
367 DEBUG2(ql4_printk(KERN_INFO, ha,
368 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
369 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
370 }
371 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
372 }
373
374 void
375 qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
376 {
377 unsigned long flags = 0;
378 int rv;
379
380 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
381
382 BUG_ON(rv == -1);
383
384 if (rv == 1) {
385 write_lock_irqsave(&ha->hw_lock, flags);
386 qla4_8xxx_crb_win_lock(ha);
387 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
388 }
389
390 writel(data, (void __iomem *)off);
391
392 if (rv == 1) {
393 qla4_8xxx_crb_win_unlock(ha);
394 write_unlock_irqrestore(&ha->hw_lock, flags);
395 }
396 }
397
398 int
399 qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off)
400 {
401 unsigned long flags = 0;
402 int rv;
403 u32 data;
404
405 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
406
407 BUG_ON(rv == -1);
408
409 if (rv == 1) {
410 write_lock_irqsave(&ha->hw_lock, flags);
411 qla4_8xxx_crb_win_lock(ha);
412 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
413 }
414 data = readl((void __iomem *)off);
415
416 if (rv == 1) {
417 qla4_8xxx_crb_win_unlock(ha);
418 write_unlock_irqrestore(&ha->hw_lock, flags);
419 }
420 return data;
421 }
422
423 #define CRB_WIN_LOCK_TIMEOUT 100000000
424
425 int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha)
426 {
427 int i;
428 int done = 0, timeout = 0;
429
430 while (!done) {
431 /* acquire semaphore3 from PCI HW block */
432 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
433 if (done == 1)
434 break;
435 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
436 return -1;
437
438 timeout++;
439
440 /* Yield CPU */
441 if (!in_interrupt())
442 schedule();
443 else {
444 for (i = 0; i < 20; i++)
445 cpu_relax(); /*This a nop instr on i386*/
446 }
447 }
448 qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
449 return 0;
450 }
451
452 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha)
453 {
454 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
455 }
456
457 #define IDC_LOCK_TIMEOUT 100000000
458
459 /**
460 * qla4_8xxx_idc_lock - hw_lock
461 * @ha: pointer to adapter structure
462 *
463 * General purpose lock used to synchronize access to
464 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
465 **/
466 int qla4_8xxx_idc_lock(struct scsi_qla_host *ha)
467 {
468 int i;
469 int done = 0, timeout = 0;
470
471 while (!done) {
472 /* acquire semaphore5 from PCI HW block */
473 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
474 if (done == 1)
475 break;
476 if (timeout >= IDC_LOCK_TIMEOUT)
477 return -1;
478
479 timeout++;
480
481 /* Yield CPU */
482 if (!in_interrupt())
483 schedule();
484 else {
485 for (i = 0; i < 20; i++)
486 cpu_relax(); /*This a nop instr on i386*/
487 }
488 }
489 return 0;
490 }
491
492 void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha)
493 {
494 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
495 }
496
497 int
498 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
499 {
500 struct crb_128M_2M_sub_block_map *m;
501
502 if (*off >= QLA82XX_CRB_MAX)
503 return -1;
504
505 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
506 *off = (*off - QLA82XX_PCI_CAMQM) +
507 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
508 return 0;
509 }
510
511 if (*off < QLA82XX_PCI_CRBSPACE)
512 return -1;
513
514 *off -= QLA82XX_PCI_CRBSPACE;
515 /*
516 * Try direct map
517 */
518
519 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
520
521 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
522 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
523 return 0;
524 }
525
526 /*
527 * Not in direct map, use crb window
528 */
529 return 1;
530 }
531
532 /* PCI Windowing for DDR regions. */
533 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
534 (((addr) <= (high)) && ((addr) >= (low)))
535
536 /*
537 * check memory access boundary.
538 * used by test agent. support ddr access only for now
539 */
540 static unsigned long
541 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha,
542 unsigned long long addr, int size)
543 {
544 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
545 QLA82XX_ADDR_DDR_NET_MAX) ||
546 !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
547 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
548 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
549 return 0;
550 }
551 return 1;
552 }
553
554 static int qla4_8xxx_pci_set_window_warning_count;
555
556 static unsigned long
557 qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
558 {
559 int window;
560 u32 win_read;
561
562 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
563 QLA82XX_ADDR_DDR_NET_MAX)) {
564 /* DDR network side */
565 window = MN_WIN(addr);
566 ha->ddr_mn_window = window;
567 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
568 QLA82XX_PCI_CRBSPACE, window);
569 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
570 QLA82XX_PCI_CRBSPACE);
571 if ((win_read << 17) != window) {
572 ql4_printk(KERN_WARNING, ha,
573 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
574 __func__, window, win_read);
575 }
576 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
577 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
578 QLA82XX_ADDR_OCM0_MAX)) {
579 unsigned int temp1;
580 /* if bits 19:18&17:11 are on */
581 if ((addr & 0x00ff800) == 0xff800) {
582 printk("%s: QM access not handled.\n", __func__);
583 addr = -1UL;
584 }
585
586 window = OCM_WIN(addr);
587 ha->ddr_mn_window = window;
588 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
589 QLA82XX_PCI_CRBSPACE, window);
590 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
591 QLA82XX_PCI_CRBSPACE);
592 temp1 = ((window & 0x1FF) << 7) |
593 ((window & 0x0FFFE0000) >> 17);
594 if (win_read != temp1) {
595 printk("%s: Written OCMwin (0x%x) != Read"
596 " OCMwin (0x%x)\n", __func__, temp1, win_read);
597 }
598 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
599
600 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
601 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
602 /* QDR network side */
603 window = MS_WIN(addr);
604 ha->qdr_sn_window = window;
605 qla4_8xxx_wr_32(ha, ha->ms_win_crb |
606 QLA82XX_PCI_CRBSPACE, window);
607 win_read = qla4_8xxx_rd_32(ha,
608 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
609 if (win_read != window) {
610 printk("%s: Written MSwin (0x%x) != Read "
611 "MSwin (0x%x)\n", __func__, window, win_read);
612 }
613 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
614
615 } else {
616 /*
617 * peg gdb frequently accesses memory that doesn't exist,
618 * this limits the chit chat so debugging isn't slowed down.
619 */
620 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) ||
621 (qla4_8xxx_pci_set_window_warning_count%64 == 0)) {
622 printk("%s: Warning:%s Unknown address range!\n",
623 __func__, DRIVER_NAME);
624 }
625 addr = -1UL;
626 }
627 return addr;
628 }
629
630 /* check if address is in the same windows as the previous access */
631 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
632 unsigned long long addr)
633 {
634 int window;
635 unsigned long long qdr_max;
636
637 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
638
639 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
640 QLA82XX_ADDR_DDR_NET_MAX)) {
641 /* DDR network side */
642 BUG(); /* MN access can not come here */
643 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
644 QLA82XX_ADDR_OCM0_MAX)) {
645 return 1;
646 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
647 QLA82XX_ADDR_OCM1_MAX)) {
648 return 1;
649 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
650 qdr_max)) {
651 /* QDR network side */
652 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
653 if (ha->qdr_sn_window == window)
654 return 1;
655 }
656
657 return 0;
658 }
659
660 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
661 u64 off, void *data, int size)
662 {
663 unsigned long flags;
664 void __iomem *addr;
665 int ret = 0;
666 u64 start;
667 void __iomem *mem_ptr = NULL;
668 unsigned long mem_base;
669 unsigned long mem_page;
670
671 write_lock_irqsave(&ha->hw_lock, flags);
672
673 /*
674 * If attempting to access unknown address or straddle hw windows,
675 * do not access.
676 */
677 start = qla4_8xxx_pci_set_window(ha, off);
678 if ((start == -1UL) ||
679 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
680 write_unlock_irqrestore(&ha->hw_lock, flags);
681 printk(KERN_ERR"%s out of bound pci memory access. "
682 "offset is 0x%llx\n", DRIVER_NAME, off);
683 return -1;
684 }
685
686 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
687 if (!addr) {
688 write_unlock_irqrestore(&ha->hw_lock, flags);
689 mem_base = pci_resource_start(ha->pdev, 0);
690 mem_page = start & PAGE_MASK;
691 /* Map two pages whenever user tries to access addresses in two
692 consecutive pages.
693 */
694 if (mem_page != ((start + size - 1) & PAGE_MASK))
695 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
696 else
697 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
698
699 if (mem_ptr == NULL) {
700 *(u8 *)data = 0;
701 return -1;
702 }
703 addr = mem_ptr;
704 addr += start & (PAGE_SIZE - 1);
705 write_lock_irqsave(&ha->hw_lock, flags);
706 }
707
708 switch (size) {
709 case 1:
710 *(u8 *)data = readb(addr);
711 break;
712 case 2:
713 *(u16 *)data = readw(addr);
714 break;
715 case 4:
716 *(u32 *)data = readl(addr);
717 break;
718 case 8:
719 *(u64 *)data = readq(addr);
720 break;
721 default:
722 ret = -1;
723 break;
724 }
725 write_unlock_irqrestore(&ha->hw_lock, flags);
726
727 if (mem_ptr)
728 iounmap(mem_ptr);
729 return ret;
730 }
731
732 static int
733 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
734 void *data, int size)
735 {
736 unsigned long flags;
737 void __iomem *addr;
738 int ret = 0;
739 u64 start;
740 void __iomem *mem_ptr = NULL;
741 unsigned long mem_base;
742 unsigned long mem_page;
743
744 write_lock_irqsave(&ha->hw_lock, flags);
745
746 /*
747 * If attempting to access unknown address or straddle hw windows,
748 * do not access.
749 */
750 start = qla4_8xxx_pci_set_window(ha, off);
751 if ((start == -1UL) ||
752 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
753 write_unlock_irqrestore(&ha->hw_lock, flags);
754 printk(KERN_ERR"%s out of bound pci memory access. "
755 "offset is 0x%llx\n", DRIVER_NAME, off);
756 return -1;
757 }
758
759 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
760 if (!addr) {
761 write_unlock_irqrestore(&ha->hw_lock, flags);
762 mem_base = pci_resource_start(ha->pdev, 0);
763 mem_page = start & PAGE_MASK;
764 /* Map two pages whenever user tries to access addresses in two
765 consecutive pages.
766 */
767 if (mem_page != ((start + size - 1) & PAGE_MASK))
768 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
769 else
770 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
771 if (mem_ptr == NULL)
772 return -1;
773
774 addr = mem_ptr;
775 addr += start & (PAGE_SIZE - 1);
776 write_lock_irqsave(&ha->hw_lock, flags);
777 }
778
779 switch (size) {
780 case 1:
781 writeb(*(u8 *)data, addr);
782 break;
783 case 2:
784 writew(*(u16 *)data, addr);
785 break;
786 case 4:
787 writel(*(u32 *)data, addr);
788 break;
789 case 8:
790 writeq(*(u64 *)data, addr);
791 break;
792 default:
793 ret = -1;
794 break;
795 }
796 write_unlock_irqrestore(&ha->hw_lock, flags);
797 if (mem_ptr)
798 iounmap(mem_ptr);
799 return ret;
800 }
801
802 #define MTU_FUDGE_FACTOR 100
803
804 static unsigned long
805 qla4_8xxx_decode_crb_addr(unsigned long addr)
806 {
807 int i;
808 unsigned long base_addr, offset, pci_base;
809
810 if (!qla4_8xxx_crb_table_initialized)
811 qla4_8xxx_crb_addr_transform_setup();
812
813 pci_base = ADDR_ERROR;
814 base_addr = addr & 0xfff00000;
815 offset = addr & 0x000fffff;
816
817 for (i = 0; i < MAX_CRB_XFORM; i++) {
818 if (crb_addr_xform[i] == base_addr) {
819 pci_base = i << 20;
820 break;
821 }
822 }
823 if (pci_base == ADDR_ERROR)
824 return pci_base;
825 else
826 return pci_base + offset;
827 }
828
829 static long rom_max_timeout = 100;
830 static long qla4_8xxx_rom_lock_timeout = 100;
831
832 static int
833 qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
834 {
835 int i;
836 int done = 0, timeout = 0;
837
838 while (!done) {
839 /* acquire semaphore2 from PCI HW block */
840
841 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
842 if (done == 1)
843 break;
844 if (timeout >= qla4_8xxx_rom_lock_timeout)
845 return -1;
846
847 timeout++;
848
849 /* Yield CPU */
850 if (!in_interrupt())
851 schedule();
852 else {
853 for (i = 0; i < 20; i++)
854 cpu_relax(); /*This a nop instr on i386*/
855 }
856 }
857 qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
858 return 0;
859 }
860
861 static void
862 qla4_8xxx_rom_unlock(struct scsi_qla_host *ha)
863 {
864 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
865 }
866
867 static int
868 qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha)
869 {
870 long timeout = 0;
871 long done = 0 ;
872
873 while (done == 0) {
874 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
875 done &= 2;
876 timeout++;
877 if (timeout >= rom_max_timeout) {
878 printk("%s: Timeout reached waiting for rom done",
879 DRIVER_NAME);
880 return -1;
881 }
882 }
883 return 0;
884 }
885
886 static int
887 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
888 {
889 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
890 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
891 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
892 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
893 if (qla4_8xxx_wait_rom_done(ha)) {
894 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
895 return -1;
896 }
897 /* reset abyte_cnt and dummy_byte_cnt */
898 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
899 udelay(10);
900 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
901
902 *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
903 return 0;
904 }
905
906 static int
907 qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
908 {
909 int ret, loops = 0;
910
911 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
912 udelay(100);
913 loops++;
914 }
915 if (loops >= 50000) {
916 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME);
917 return -1;
918 }
919 ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp);
920 qla4_8xxx_rom_unlock(ha);
921 return ret;
922 }
923
924 /**
925 * This routine does CRB initialize sequence
926 * to put the ISP into operational state
927 **/
928 static int
929 qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
930 {
931 int addr, val;
932 int i ;
933 struct crb_addr_pair *buf;
934 unsigned long off;
935 unsigned offset, n;
936
937 struct crb_addr_pair {
938 long addr;
939 long data;
940 };
941
942 /* Halt all the indiviual PEGs and other blocks of the ISP */
943 qla4_8xxx_rom_lock(ha);
944
945 /* disable all I2Q */
946 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
947 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
948 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
949 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
950 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
951 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
952
953 /* disable all niu interrupts */
954 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
955 /* disable xge rx/tx */
956 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
957 /* disable xg1 rx/tx */
958 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
959 /* disable sideband mac */
960 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
961 /* disable ap0 mac */
962 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
963 /* disable ap1 mac */
964 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
965
966 /* halt sre */
967 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
968 qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
969
970 /* halt epg */
971 qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
972
973 /* halt timers */
974 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
975 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
976 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
977 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
978 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
979 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
980
981 /* halt pegs */
982 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
983 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
984 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
985 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
986 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
987 msleep(5);
988
989 /* big hammer */
990 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
991 /* don't reset CAM block on reset */
992 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
993 else
994 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
995
996 qla4_8xxx_rom_unlock(ha);
997
998 /* Read the signature value from the flash.
999 * Offset 0: Contain signature (0xcafecafe)
1000 * Offset 4: Offset and number of addr/value pairs
1001 * that present in CRB initialize sequence
1002 */
1003 if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1004 qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) {
1005 ql4_printk(KERN_WARNING, ha,
1006 "[ERROR] Reading crb_init area: n: %08x\n", n);
1007 return -1;
1008 }
1009
1010 /* Offset in flash = lower 16 bits
1011 * Number of enteries = upper 16 bits
1012 */
1013 offset = n & 0xffffU;
1014 n = (n >> 16) & 0xffffU;
1015
1016 /* number of addr/value pair should not exceed 1024 enteries */
1017 if (n >= 1024) {
1018 ql4_printk(KERN_WARNING, ha,
1019 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1020 DRIVER_NAME, __func__, n);
1021 return -1;
1022 }
1023
1024 ql4_printk(KERN_INFO, ha,
1025 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1026
1027 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1028 if (buf == NULL) {
1029 ql4_printk(KERN_WARNING, ha,
1030 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1031 return -1;
1032 }
1033
1034 for (i = 0; i < n; i++) {
1035 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1036 qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1037 0) {
1038 kfree(buf);
1039 return -1;
1040 }
1041
1042 buf[i].addr = addr;
1043 buf[i].data = val;
1044 }
1045
1046 for (i = 0; i < n; i++) {
1047 /* Translate internal CRB initialization
1048 * address to PCI bus address
1049 */
1050 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) +
1051 QLA82XX_PCI_CRBSPACE;
1052 /* Not all CRB addr/value pair to be written,
1053 * some of them are skipped
1054 */
1055
1056 /* skip if LS bit is set*/
1057 if (off & 0x1) {
1058 DEBUG2(ql4_printk(KERN_WARNING, ha,
1059 "Skip CRB init replay for offset = 0x%lx\n", off));
1060 continue;
1061 }
1062
1063 /* skipping cold reboot MAGIC */
1064 if (off == QLA82XX_CAM_RAM(0x1fc))
1065 continue;
1066
1067 /* do not reset PCI */
1068 if (off == (ROMUSB_GLB + 0xbc))
1069 continue;
1070
1071 /* skip core clock, so that firmware can increase the clock */
1072 if (off == (ROMUSB_GLB + 0xc8))
1073 continue;
1074
1075 /* skip the function enable register */
1076 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1077 continue;
1078
1079 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1080 continue;
1081
1082 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1083 continue;
1084
1085 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1086 continue;
1087
1088 if (off == ADDR_ERROR) {
1089 ql4_printk(KERN_WARNING, ha,
1090 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1091 DRIVER_NAME, buf[i].addr);
1092 continue;
1093 }
1094
1095 qla4_8xxx_wr_32(ha, off, buf[i].data);
1096
1097 /* ISP requires much bigger delay to settle down,
1098 * else crb_window returns 0xffffffff
1099 */
1100 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1101 msleep(1000);
1102
1103 /* ISP requires millisec delay between
1104 * successive CRB register updation
1105 */
1106 msleep(1);
1107 }
1108
1109 kfree(buf);
1110
1111 /* Resetting the data and instruction cache */
1112 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1113 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1114 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1115
1116 /* Clear all protocol processing engines */
1117 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1118 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1119 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1120 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1121 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1122 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1123 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1124 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1125
1126 return 0;
1127 }
1128
1129 static int
1130 qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1131 {
1132 int i, rval = 0;
1133 long size = 0;
1134 long flashaddr, memaddr;
1135 u64 data;
1136 u32 high, low;
1137
1138 flashaddr = memaddr = ha->hw.flt_region_bootload;
1139 size = (image_start - flashaddr) / 8;
1140
1141 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1142 ha->host_no, __func__, flashaddr, image_start));
1143
1144 for (i = 0; i < size; i++) {
1145 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1146 (qla4_8xxx_rom_fast_read(ha, flashaddr + 4,
1147 (int *)&high))) {
1148 rval = -1;
1149 goto exit_load_from_flash;
1150 }
1151 data = ((u64)high << 32) | low ;
1152 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8);
1153 if (rval)
1154 goto exit_load_from_flash;
1155
1156 flashaddr += 8;
1157 memaddr += 8;
1158
1159 if (i % 0x1000 == 0)
1160 msleep(1);
1161
1162 }
1163
1164 udelay(100);
1165
1166 read_lock(&ha->hw_lock);
1167 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1168 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1169 read_unlock(&ha->hw_lock);
1170
1171 exit_load_from_flash:
1172 return rval;
1173 }
1174
1175 static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1176 {
1177 u32 rst;
1178
1179 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1180 if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1181 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1182 __func__);
1183 return QLA_ERROR;
1184 }
1185
1186 udelay(500);
1187
1188 /* at this point, QM is in reset. This could be a problem if there are
1189 * incoming d* transition queue messages. QM/PCIE could wedge.
1190 * To get around this, QM is brought out of reset.
1191 */
1192
1193 rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1194 /* unreset qm */
1195 rst &= ~(1 << 28);
1196 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1197
1198 if (qla4_8xxx_load_from_flash(ha, image_start)) {
1199 printk("%s: Error trying to load fw from flash!\n", __func__);
1200 return QLA_ERROR;
1201 }
1202
1203 return QLA_SUCCESS;
1204 }
1205
1206 int
1207 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1208 u64 off, void *data, int size)
1209 {
1210 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1211 int shift_amount;
1212 uint32_t temp;
1213 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1214
1215 /*
1216 * If not MN, go check for MS or invalid.
1217 */
1218
1219 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1220 mem_crb = QLA82XX_CRB_QDR_NET;
1221 else {
1222 mem_crb = QLA82XX_CRB_DDR_NET;
1223 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1224 return qla4_8xxx_pci_mem_read_direct(ha,
1225 off, data, size);
1226 }
1227
1228
1229 off8 = off & 0xfffffff0;
1230 off0[0] = off & 0xf;
1231 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1232 shift_amount = 4;
1233
1234 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1235 off0[1] = 0;
1236 sz[1] = size - sz[0];
1237
1238 for (i = 0; i < loop; i++) {
1239 temp = off8 + (i << shift_amount);
1240 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1241 temp = 0;
1242 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1243 temp = MIU_TA_CTL_ENABLE;
1244 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1245 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1246 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1247
1248 for (j = 0; j < MAX_CTL_CHECK; j++) {
1249 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1250 if ((temp & MIU_TA_CTL_BUSY) == 0)
1251 break;
1252 }
1253
1254 if (j >= MAX_CTL_CHECK) {
1255 if (printk_ratelimit())
1256 ql4_printk(KERN_ERR, ha,
1257 "failed to read through agent\n");
1258 break;
1259 }
1260
1261 start = off0[i] >> 2;
1262 end = (off0[i] + sz[i] - 1) >> 2;
1263 for (k = start; k <= end; k++) {
1264 temp = qla4_8xxx_rd_32(ha,
1265 mem_crb + MIU_TEST_AGT_RDDATA(k));
1266 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1267 }
1268 }
1269
1270 if (j >= MAX_CTL_CHECK)
1271 return -1;
1272
1273 if ((off0[0] & 7) == 0) {
1274 val = word[0];
1275 } else {
1276 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1277 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1278 }
1279
1280 switch (size) {
1281 case 1:
1282 *(uint8_t *)data = val;
1283 break;
1284 case 2:
1285 *(uint16_t *)data = val;
1286 break;
1287 case 4:
1288 *(uint32_t *)data = val;
1289 break;
1290 case 8:
1291 *(uint64_t *)data = val;
1292 break;
1293 }
1294 return 0;
1295 }
1296
1297 int
1298 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1299 u64 off, void *data, int size)
1300 {
1301 int i, j, ret = 0, loop, sz[2], off0;
1302 int scale, shift_amount, startword;
1303 uint32_t temp;
1304 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1305
1306 /*
1307 * If not MN, go check for MS or invalid.
1308 */
1309 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1310 mem_crb = QLA82XX_CRB_QDR_NET;
1311 else {
1312 mem_crb = QLA82XX_CRB_DDR_NET;
1313 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1314 return qla4_8xxx_pci_mem_write_direct(ha,
1315 off, data, size);
1316 }
1317
1318 off0 = off & 0x7;
1319 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1320 sz[1] = size - sz[0];
1321
1322 off8 = off & 0xfffffff0;
1323 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1324 shift_amount = 4;
1325 scale = 2;
1326 startword = (off & 0xf)/8;
1327
1328 for (i = 0; i < loop; i++) {
1329 if (qla4_8xxx_pci_mem_read_2M(ha, off8 +
1330 (i << shift_amount), &word[i * scale], 8))
1331 return -1;
1332 }
1333
1334 switch (size) {
1335 case 1:
1336 tmpw = *((uint8_t *)data);
1337 break;
1338 case 2:
1339 tmpw = *((uint16_t *)data);
1340 break;
1341 case 4:
1342 tmpw = *((uint32_t *)data);
1343 break;
1344 case 8:
1345 default:
1346 tmpw = *((uint64_t *)data);
1347 break;
1348 }
1349
1350 if (sz[0] == 8)
1351 word[startword] = tmpw;
1352 else {
1353 word[startword] &=
1354 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1355 word[startword] |= tmpw << (off0 * 8);
1356 }
1357
1358 if (sz[1] != 0) {
1359 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1360 word[startword+1] |= tmpw >> (sz[0] * 8);
1361 }
1362
1363 for (i = 0; i < loop; i++) {
1364 temp = off8 + (i << shift_amount);
1365 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1366 temp = 0;
1367 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1368 temp = word[i * scale] & 0xffffffff;
1369 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1370 temp = (word[i * scale] >> 32) & 0xffffffff;
1371 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1372 temp = word[i*scale + 1] & 0xffffffff;
1373 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1374 temp);
1375 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1376 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1377 temp);
1378
1379 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1380 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1381 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1382 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1383
1384 for (j = 0; j < MAX_CTL_CHECK; j++) {
1385 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1386 if ((temp & MIU_TA_CTL_BUSY) == 0)
1387 break;
1388 }
1389
1390 if (j >= MAX_CTL_CHECK) {
1391 if (printk_ratelimit())
1392 ql4_printk(KERN_ERR, ha,
1393 "failed to write through agent\n");
1394 ret = -1;
1395 break;
1396 }
1397 }
1398
1399 return ret;
1400 }
1401
1402 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1403 {
1404 u32 val = 0;
1405 int retries = 60;
1406
1407 if (!pegtune_val) {
1408 do {
1409 val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE);
1410 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1411 (val == PHAN_INITIALIZE_ACK))
1412 return 0;
1413 set_current_state(TASK_UNINTERRUPTIBLE);
1414 schedule_timeout(500);
1415
1416 } while (--retries);
1417
1418 if (!retries) {
1419 pegtune_val = qla4_8xxx_rd_32(ha,
1420 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1421 printk(KERN_WARNING "%s: init failed, "
1422 "pegtune_val = %x\n", __func__, pegtune_val);
1423 return -1;
1424 }
1425 }
1426 return 0;
1427 }
1428
1429 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha)
1430 {
1431 uint32_t state = 0;
1432 int loops = 0;
1433
1434 /* Window 1 call */
1435 read_lock(&ha->hw_lock);
1436 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1437 read_unlock(&ha->hw_lock);
1438
1439 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1440 udelay(100);
1441 /* Window 1 call */
1442 read_lock(&ha->hw_lock);
1443 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1444 read_unlock(&ha->hw_lock);
1445
1446 loops++;
1447 }
1448
1449 if (loops >= 30000) {
1450 DEBUG2(ql4_printk(KERN_INFO, ha,
1451 "Receive Peg initialization not complete: 0x%x.\n", state));
1452 return QLA_ERROR;
1453 }
1454
1455 return QLA_SUCCESS;
1456 }
1457
1458 void
1459 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1460 {
1461 uint32_t drv_active;
1462
1463 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1464 drv_active |= (1 << (ha->func_num * 4));
1465 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1466 }
1467
1468 void
1469 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1470 {
1471 uint32_t drv_active;
1472
1473 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1474 drv_active &= ~(1 << (ha->func_num * 4));
1475 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1476 }
1477
1478 static inline int
1479 qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1480 {
1481 uint32_t drv_state, drv_active;
1482 int rval;
1483
1484 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1485 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1486 rval = drv_state & (1 << (ha->func_num * 4));
1487 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1488 rval = 1;
1489
1490 return rval;
1491 }
1492
1493 static inline void
1494 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1495 {
1496 uint32_t drv_state;
1497
1498 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1499 drv_state |= (1 << (ha->func_num * 4));
1500 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1501 }
1502
1503 static inline void
1504 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1505 {
1506 uint32_t drv_state;
1507
1508 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1509 drv_state &= ~(1 << (ha->func_num * 4));
1510 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1511 }
1512
1513 static inline void
1514 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1515 {
1516 uint32_t qsnt_state;
1517
1518 qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1519 qsnt_state |= (2 << (ha->func_num * 4));
1520 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1521 }
1522
1523
1524 static int
1525 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1526 {
1527 int pcie_cap;
1528 uint16_t lnk;
1529
1530 /* scrub dma mask expansion register */
1531 qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1532
1533 /* Overwrite stale initialization register values */
1534 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1535 qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1536 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1537 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1538
1539 if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) {
1540 printk("%s: Error trying to start fw!\n", __func__);
1541 return QLA_ERROR;
1542 }
1543
1544 /* Handshake with the card before we register the devices. */
1545 if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1546 printk("%s: Error during card handshake!\n", __func__);
1547 return QLA_ERROR;
1548 }
1549
1550 /* Negotiated Link width */
1551 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
1552 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1553 ha->link_width = (lnk >> 4) & 0x3f;
1554
1555 /* Synchronize with Receive peg */
1556 return qla4_8xxx_rcvpeg_ready(ha);
1557 }
1558
1559 static int
1560 qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1561 {
1562 int rval = QLA_ERROR;
1563
1564 /*
1565 * FW Load priority:
1566 * 1) Operational firmware residing in flash.
1567 * 2) Fail
1568 */
1569
1570 ql4_printk(KERN_INFO, ha,
1571 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1572 rval = qla4_8xxx_get_flash_info(ha);
1573 if (rval != QLA_SUCCESS)
1574 return rval;
1575
1576 ql4_printk(KERN_INFO, ha,
1577 "FW: Attempting to load firmware from flash...\n");
1578 rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw);
1579
1580 if (rval != QLA_SUCCESS) {
1581 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1582 " FAILED...\n");
1583 return rval;
1584 }
1585
1586 return rval;
1587 }
1588
1589 static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha)
1590 {
1591 if (qla4_8xxx_rom_lock(ha)) {
1592 /* Someone else is holding the lock. */
1593 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1594 }
1595
1596 /*
1597 * Either we got the lock, or someone
1598 * else died while holding it.
1599 * In either case, unlock.
1600 */
1601 qla4_8xxx_rom_unlock(ha);
1602 }
1603
1604 /**
1605 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
1606 * @ha: pointer to adapter structure
1607 *
1608 * Note: IDC lock must be held upon entry
1609 **/
1610 static int
1611 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
1612 {
1613 int rval = QLA_ERROR;
1614 int i, timeout;
1615 uint32_t old_count, count;
1616 int need_reset = 0, peg_stuck = 1;
1617
1618 need_reset = qla4_8xxx_need_reset(ha);
1619
1620 old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1621
1622 for (i = 0; i < 10; i++) {
1623 timeout = msleep_interruptible(200);
1624 if (timeout) {
1625 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1626 QLA82XX_DEV_FAILED);
1627 return rval;
1628 }
1629
1630 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1631 if (count != old_count)
1632 peg_stuck = 0;
1633 }
1634
1635 if (need_reset) {
1636 /* We are trying to perform a recovery here. */
1637 if (peg_stuck)
1638 qla4_8xxx_rom_lock_recovery(ha);
1639 goto dev_initialize;
1640 } else {
1641 /* Start of day for this ha context. */
1642 if (peg_stuck) {
1643 /* Either we are the first or recovery in progress. */
1644 qla4_8xxx_rom_lock_recovery(ha);
1645 goto dev_initialize;
1646 } else {
1647 /* Firmware already running. */
1648 rval = QLA_SUCCESS;
1649 goto dev_ready;
1650 }
1651 }
1652
1653 dev_initialize:
1654 /* set to DEV_INITIALIZING */
1655 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
1656 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
1657
1658 /* Driver that sets device state to initializating sets IDC version */
1659 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
1660
1661 qla4_8xxx_idc_unlock(ha);
1662 rval = qla4_8xxx_try_start_fw(ha);
1663 qla4_8xxx_idc_lock(ha);
1664
1665 if (rval != QLA_SUCCESS) {
1666 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
1667 qla4_8xxx_clear_drv_active(ha);
1668 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
1669 return rval;
1670 }
1671
1672 dev_ready:
1673 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
1674 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
1675
1676 return rval;
1677 }
1678
1679 /**
1680 * qla4_8xxx_need_reset_handler - Code to start reset sequence
1681 * @ha: pointer to adapter structure
1682 *
1683 * Note: IDC lock must be held upon entry
1684 **/
1685 static void
1686 qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
1687 {
1688 uint32_t dev_state, drv_state, drv_active;
1689 unsigned long reset_timeout;
1690
1691 ql4_printk(KERN_INFO, ha,
1692 "Performing ISP error recovery\n");
1693
1694 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
1695 qla4_8xxx_idc_unlock(ha);
1696 ha->isp_ops->disable_intrs(ha);
1697 qla4_8xxx_idc_lock(ha);
1698 }
1699
1700 qla4_8xxx_set_rst_ready(ha);
1701
1702 /* wait for 10 seconds for reset ack from all functions */
1703 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
1704
1705 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1706 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1707
1708 ql4_printk(KERN_INFO, ha,
1709 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1710 __func__, ha->host_no, drv_state, drv_active);
1711
1712 while (drv_state != drv_active) {
1713 if (time_after_eq(jiffies, reset_timeout)) {
1714 printk("%s: RESET TIMEOUT!\n", DRIVER_NAME);
1715 break;
1716 }
1717
1718 qla4_8xxx_idc_unlock(ha);
1719 msleep(1000);
1720 qla4_8xxx_idc_lock(ha);
1721
1722 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1723 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1724 }
1725
1726 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1727 ql4_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state,
1728 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1729
1730 /* Force to DEV_COLD unless someone else is starting a reset */
1731 if (dev_state != QLA82XX_DEV_INITIALIZING) {
1732 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
1733 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
1734 }
1735 }
1736
1737 /**
1738 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
1739 * @ha: pointer to adapter structure
1740 **/
1741 void
1742 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
1743 {
1744 qla4_8xxx_idc_lock(ha);
1745 qla4_8xxx_set_qsnt_ready(ha);
1746 qla4_8xxx_idc_unlock(ha);
1747 }
1748
1749 /**
1750 * qla4_8xxx_device_state_handler - Adapter state machine
1751 * @ha: pointer to host adapter structure.
1752 *
1753 * Note: IDC lock must be UNLOCKED upon entry
1754 **/
1755 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
1756 {
1757 uint32_t dev_state;
1758 int rval = QLA_SUCCESS;
1759 unsigned long dev_init_timeout;
1760
1761 if (!test_bit(AF_INIT_DONE, &ha->flags)) {
1762 qla4_8xxx_idc_lock(ha);
1763 qla4_8xxx_set_drv_active(ha);
1764 qla4_8xxx_idc_unlock(ha);
1765 }
1766
1767 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1768 ql4_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state,
1769 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1770
1771 /* wait for 30 seconds for device to go ready */
1772 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
1773
1774 qla4_8xxx_idc_lock(ha);
1775 while (1) {
1776
1777 if (time_after_eq(jiffies, dev_init_timeout)) {
1778 ql4_printk(KERN_WARNING, ha, "Device init failed!\n");
1779 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1780 QLA82XX_DEV_FAILED);
1781 }
1782
1783 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1784 ql4_printk(KERN_INFO, ha,
1785 "2:Device state is 0x%x = %s\n", dev_state,
1786 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1787
1788 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1789 switch (dev_state) {
1790 case QLA82XX_DEV_READY:
1791 goto exit;
1792 case QLA82XX_DEV_COLD:
1793 rval = qla4_8xxx_device_bootstrap(ha);
1794 goto exit;
1795 case QLA82XX_DEV_INITIALIZING:
1796 qla4_8xxx_idc_unlock(ha);
1797 msleep(1000);
1798 qla4_8xxx_idc_lock(ha);
1799 break;
1800 case QLA82XX_DEV_NEED_RESET:
1801 if (!ql4xdontresethba) {
1802 qla4_8xxx_need_reset_handler(ha);
1803 /* Update timeout value after need
1804 * reset handler */
1805 dev_init_timeout = jiffies +
1806 (ha->nx_dev_init_timeout * HZ);
1807 } else {
1808 qla4_8xxx_idc_unlock(ha);
1809 msleep(1000);
1810 qla4_8xxx_idc_lock(ha);
1811 }
1812 break;
1813 case QLA82XX_DEV_NEED_QUIESCENT:
1814 /* idc locked/unlocked in handler */
1815 qla4_8xxx_need_qsnt_handler(ha);
1816 break;
1817 case QLA82XX_DEV_QUIESCENT:
1818 qla4_8xxx_idc_unlock(ha);
1819 msleep(1000);
1820 qla4_8xxx_idc_lock(ha);
1821 break;
1822 case QLA82XX_DEV_FAILED:
1823 qla4_8xxx_idc_unlock(ha);
1824 qla4xxx_dead_adapter_cleanup(ha);
1825 rval = QLA_ERROR;
1826 qla4_8xxx_idc_lock(ha);
1827 goto exit;
1828 default:
1829 qla4_8xxx_idc_unlock(ha);
1830 qla4xxx_dead_adapter_cleanup(ha);
1831 rval = QLA_ERROR;
1832 qla4_8xxx_idc_lock(ha);
1833 goto exit;
1834 }
1835 }
1836 exit:
1837 qla4_8xxx_idc_unlock(ha);
1838 return rval;
1839 }
1840
1841 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
1842 {
1843 int retval;
1844
1845 /* clear the interrupt */
1846 writel(0, &ha->qla4_8xxx_reg->host_int);
1847 readl(&ha->qla4_8xxx_reg->host_int);
1848
1849 retval = qla4_8xxx_device_state_handler(ha);
1850
1851 if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags))
1852 retval = qla4xxx_request_irqs(ha);
1853
1854 return retval;
1855 }
1856
1857 /*****************************************************************************/
1858 /* Flash Manipulation Routines */
1859 /*****************************************************************************/
1860
1861 #define OPTROM_BURST_SIZE 0x1000
1862 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
1863
1864 #define FARX_DATA_FLAG BIT_31
1865 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
1866 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
1867
1868 static inline uint32_t
1869 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1870 {
1871 return hw->flash_conf_off | faddr;
1872 }
1873
1874 static inline uint32_t
1875 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1876 {
1877 return hw->flash_data_off | faddr;
1878 }
1879
1880 static uint32_t *
1881 qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
1882 uint32_t faddr, uint32_t length)
1883 {
1884 uint32_t i;
1885 uint32_t val;
1886 int loops = 0;
1887 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
1888 udelay(100);
1889 cond_resched();
1890 loops++;
1891 }
1892 if (loops >= 50000) {
1893 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
1894 return dwptr;
1895 }
1896
1897 /* Dword reads to flash. */
1898 for (i = 0; i < length/4; i++, faddr += 4) {
1899 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) {
1900 ql4_printk(KERN_WARNING, ha,
1901 "Do ROM fast read failed\n");
1902 goto done_read;
1903 }
1904 dwptr[i] = __constant_cpu_to_le32(val);
1905 }
1906
1907 done_read:
1908 qla4_8xxx_rom_unlock(ha);
1909 return dwptr;
1910 }
1911
1912 /**
1913 * Address and length are byte address
1914 **/
1915 static uint8_t *
1916 qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1917 uint32_t offset, uint32_t length)
1918 {
1919 qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length);
1920 return buf;
1921 }
1922
1923 static int
1924 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
1925 {
1926 const char *loc, *locations[] = { "DEF", "PCI" };
1927
1928 /*
1929 * FLT-location structure resides after the last PCI region.
1930 */
1931
1932 /* Begin with sane defaults. */
1933 loc = locations[0];
1934 *start = FA_FLASH_LAYOUT_ADDR_82;
1935
1936 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
1937 return QLA_SUCCESS;
1938 }
1939
1940 static void
1941 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
1942 {
1943 const char *loc, *locations[] = { "DEF", "FLT" };
1944 uint16_t *wptr;
1945 uint16_t cnt, chksum;
1946 uint32_t start;
1947 struct qla_flt_header *flt;
1948 struct qla_flt_region *region;
1949 struct ql82xx_hw_data *hw = &ha->hw;
1950
1951 hw->flt_region_flt = flt_addr;
1952 wptr = (uint16_t *)ha->request_ring;
1953 flt = (struct qla_flt_header *)ha->request_ring;
1954 region = (struct qla_flt_region *)&flt[1];
1955 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
1956 flt_addr << 2, OPTROM_BURST_SIZE);
1957 if (*wptr == __constant_cpu_to_le16(0xffff))
1958 goto no_flash_data;
1959 if (flt->version != __constant_cpu_to_le16(1)) {
1960 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
1961 "version=0x%x length=0x%x checksum=0x%x.\n",
1962 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1963 le16_to_cpu(flt->checksum)));
1964 goto no_flash_data;
1965 }
1966
1967 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
1968 for (chksum = 0; cnt; cnt--)
1969 chksum += le16_to_cpu(*wptr++);
1970 if (chksum) {
1971 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
1972 "version=0x%x length=0x%x checksum=0x%x.\n",
1973 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1974 chksum));
1975 goto no_flash_data;
1976 }
1977
1978 loc = locations[1];
1979 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
1980 for ( ; cnt; cnt--, region++) {
1981 /* Store addresses as DWORD offsets. */
1982 start = le32_to_cpu(region->start) >> 2;
1983
1984 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
1985 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
1986 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
1987
1988 switch (le32_to_cpu(region->code) & 0xff) {
1989 case FLT_REG_FDT:
1990 hw->flt_region_fdt = start;
1991 break;
1992 case FLT_REG_BOOT_CODE_82:
1993 hw->flt_region_boot = start;
1994 break;
1995 case FLT_REG_FW_82:
1996 case FLT_REG_FW_82_1:
1997 hw->flt_region_fw = start;
1998 break;
1999 case FLT_REG_BOOTLOAD_82:
2000 hw->flt_region_bootload = start;
2001 break;
2002 case FLT_REG_ISCSI_PARAM:
2003 hw->flt_iscsi_param = start;
2004 break;
2005 case FLT_REG_ISCSI_CHAP:
2006 hw->flt_region_chap = start;
2007 hw->flt_chap_size = le32_to_cpu(region->size);
2008 break;
2009 }
2010 }
2011 goto done;
2012
2013 no_flash_data:
2014 /* Use hardcoded defaults. */
2015 loc = locations[0];
2016
2017 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
2018 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
2019 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
2020 hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
2021 hw->flt_region_chap = FA_FLASH_ISCSI_CHAP;
2022 hw->flt_chap_size = FA_FLASH_CHAP_SIZE;
2023
2024 done:
2025 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
2026 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
2027 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
2028 hw->flt_region_fw));
2029 }
2030
2031 static void
2032 qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha)
2033 {
2034 #define FLASH_BLK_SIZE_4K 0x1000
2035 #define FLASH_BLK_SIZE_32K 0x8000
2036 #define FLASH_BLK_SIZE_64K 0x10000
2037 const char *loc, *locations[] = { "MID", "FDT" };
2038 uint16_t cnt, chksum;
2039 uint16_t *wptr;
2040 struct qla_fdt_layout *fdt;
2041 uint16_t mid = 0;
2042 uint16_t fid = 0;
2043 struct ql82xx_hw_data *hw = &ha->hw;
2044
2045 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2046 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
2047
2048 wptr = (uint16_t *)ha->request_ring;
2049 fdt = (struct qla_fdt_layout *)ha->request_ring;
2050 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2051 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2052
2053 if (*wptr == __constant_cpu_to_le16(0xffff))
2054 goto no_flash_data;
2055
2056 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2057 fdt->sig[3] != 'D')
2058 goto no_flash_data;
2059
2060 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
2061 cnt++)
2062 chksum += le16_to_cpu(*wptr++);
2063
2064 if (chksum) {
2065 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
2066 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
2067 le16_to_cpu(fdt->version)));
2068 goto no_flash_data;
2069 }
2070
2071 loc = locations[1];
2072 mid = le16_to_cpu(fdt->man_id);
2073 fid = le16_to_cpu(fdt->id);
2074 hw->fdt_wrt_disable = fdt->wrt_disable_bits;
2075 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
2076 hw->fdt_block_size = le32_to_cpu(fdt->block_size);
2077
2078 if (fdt->unprotect_sec_cmd) {
2079 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
2080 fdt->unprotect_sec_cmd);
2081 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
2082 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
2083 flash_conf_addr(hw, 0x0336);
2084 }
2085 goto done;
2086
2087 no_flash_data:
2088 loc = locations[0];
2089 hw->fdt_block_size = FLASH_BLK_SIZE_64K;
2090 done:
2091 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2092 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2093 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2094 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2095 hw->fdt_block_size));
2096 }
2097
2098 static void
2099 qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2100 {
2101 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
2102 uint32_t *wptr;
2103
2104 if (!is_qla8022(ha))
2105 return;
2106 wptr = (uint32_t *)ha->request_ring;
2107 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2108 QLA82XX_IDC_PARAM_ADDR , 8);
2109
2110 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2111 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2112 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2113 } else {
2114 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2115 ha->nx_reset_timeout = le32_to_cpu(*wptr);
2116 }
2117
2118 DEBUG2(ql4_printk(KERN_DEBUG, ha,
2119 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
2120 DEBUG2(ql4_printk(KERN_DEBUG, ha,
2121 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
2122 return;
2123 }
2124
2125 int
2126 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2127 {
2128 int ret;
2129 uint32_t flt_addr;
2130
2131 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2132 if (ret != QLA_SUCCESS)
2133 return ret;
2134
2135 qla4_8xxx_get_flt_info(ha, flt_addr);
2136 qla4_8xxx_get_fdt_info(ha);
2137 qla4_8xxx_get_idc_param(ha);
2138
2139 return QLA_SUCCESS;
2140 }
2141
2142 /**
2143 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2144 * @ha: pointer to host adapter structure.
2145 *
2146 * Remarks:
2147 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2148 * not be available after successful return. Driver must cleanup potential
2149 * outstanding I/O's after calling this funcion.
2150 **/
2151 int
2152 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2153 {
2154 int status;
2155 uint32_t mbox_cmd[MBOX_REG_COUNT];
2156 uint32_t mbox_sts[MBOX_REG_COUNT];
2157
2158 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2159 memset(&mbox_sts, 0, sizeof(mbox_sts));
2160
2161 mbox_cmd[0] = MBOX_CMD_STOP_FW;
2162 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
2163 &mbox_cmd[0], &mbox_sts[0]);
2164
2165 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2166 __func__, status));
2167 return status;
2168 }
2169
2170 /**
2171 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands.
2172 * @ha: pointer to host adapter structure.
2173 **/
2174 int
2175 qla4_8xxx_isp_reset(struct scsi_qla_host *ha)
2176 {
2177 int rval;
2178 uint32_t dev_state;
2179
2180 qla4_8xxx_idc_lock(ha);
2181 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2182
2183 if (dev_state == QLA82XX_DEV_READY) {
2184 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2185 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2186 QLA82XX_DEV_NEED_RESET);
2187 } else
2188 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2189
2190 qla4_8xxx_idc_unlock(ha);
2191
2192 rval = qla4_8xxx_device_state_handler(ha);
2193
2194 qla4_8xxx_idc_lock(ha);
2195 qla4_8xxx_clear_rst_ready(ha);
2196 qla4_8xxx_idc_unlock(ha);
2197
2198 if (rval == QLA_SUCCESS)
2199 clear_bit(AF_FW_RECOVERY, &ha->flags);
2200
2201 return rval;
2202 }
2203
2204 /**
2205 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2206 * @ha: pointer to host adapter structure.
2207 *
2208 **/
2209 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
2210 {
2211 uint32_t mbox_cmd[MBOX_REG_COUNT];
2212 uint32_t mbox_sts[MBOX_REG_COUNT];
2213 struct mbx_sys_info *sys_info;
2214 dma_addr_t sys_info_dma;
2215 int status = QLA_ERROR;
2216
2217 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
2218 &sys_info_dma, GFP_KERNEL);
2219 if (sys_info == NULL) {
2220 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
2221 ha->host_no, __func__));
2222 return status;
2223 }
2224
2225 memset(sys_info, 0, sizeof(*sys_info));
2226 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2227 memset(&mbox_sts, 0, sizeof(mbox_sts));
2228
2229 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
2230 mbox_cmd[1] = LSDW(sys_info_dma);
2231 mbox_cmd[2] = MSDW(sys_info_dma);
2232 mbox_cmd[4] = sizeof(*sys_info);
2233
2234 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
2235 &mbox_sts[0]) != QLA_SUCCESS) {
2236 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
2237 ha->host_no, __func__));
2238 goto exit_validate_mac82;
2239 }
2240
2241 /* Make sure we receive the minimum required data to cache internally */
2242 if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) {
2243 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
2244 " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
2245 goto exit_validate_mac82;
2246
2247 }
2248
2249 /* Save M.A.C. address & serial_number */
2250 ha->port_num = sys_info->port_num;
2251 memcpy(ha->my_mac, &sys_info->mac_addr[0],
2252 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
2253 memcpy(ha->serial_number, &sys_info->serial_number,
2254 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
2255 memcpy(ha->model_name, &sys_info->board_id_str,
2256 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
2257 ha->phy_port_cnt = sys_info->phys_port_cnt;
2258 ha->phy_port_num = sys_info->port_num;
2259 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
2260
2261 DEBUG2(printk("scsi%ld: %s: "
2262 "mac %02x:%02x:%02x:%02x:%02x:%02x "
2263 "serial %s\n", ha->host_no, __func__,
2264 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
2265 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
2266 ha->serial_number));
2267
2268 status = QLA_SUCCESS;
2269
2270 exit_validate_mac82:
2271 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
2272 sys_info_dma);
2273 return status;
2274 }
2275
2276 /* Interrupt handling helpers. */
2277
2278 static int
2279 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2280 {
2281 uint32_t mbox_cmd[MBOX_REG_COUNT];
2282 uint32_t mbox_sts[MBOX_REG_COUNT];
2283
2284 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2285
2286 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2287 memset(&mbox_sts, 0, sizeof(mbox_sts));
2288 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2289 mbox_cmd[1] = INTR_ENABLE;
2290 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2291 &mbox_sts[0]) != QLA_SUCCESS) {
2292 DEBUG2(ql4_printk(KERN_INFO, ha,
2293 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2294 __func__, mbox_sts[0]));
2295 return QLA_ERROR;
2296 }
2297 return QLA_SUCCESS;
2298 }
2299
2300 static int
2301 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
2302 {
2303 uint32_t mbox_cmd[MBOX_REG_COUNT];
2304 uint32_t mbox_sts[MBOX_REG_COUNT];
2305
2306 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2307
2308 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2309 memset(&mbox_sts, 0, sizeof(mbox_sts));
2310 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2311 mbox_cmd[1] = INTR_DISABLE;
2312 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2313 &mbox_sts[0]) != QLA_SUCCESS) {
2314 DEBUG2(ql4_printk(KERN_INFO, ha,
2315 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2316 __func__, mbox_sts[0]));
2317 return QLA_ERROR;
2318 }
2319
2320 return QLA_SUCCESS;
2321 }
2322
2323 void
2324 qla4_8xxx_enable_intrs(struct scsi_qla_host *ha)
2325 {
2326 qla4_8xxx_mbx_intr_enable(ha);
2327
2328 spin_lock_irq(&ha->hardware_lock);
2329 /* BIT 10 - reset */
2330 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2331 spin_unlock_irq(&ha->hardware_lock);
2332 set_bit(AF_INTERRUPTS_ON, &ha->flags);
2333 }
2334
2335 void
2336 qla4_8xxx_disable_intrs(struct scsi_qla_host *ha)
2337 {
2338 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
2339 qla4_8xxx_mbx_intr_disable(ha);
2340
2341 spin_lock_irq(&ha->hardware_lock);
2342 /* BIT 10 - set */
2343 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2344 spin_unlock_irq(&ha->hardware_lock);
2345 }
2346
2347 struct ql4_init_msix_entry {
2348 uint16_t entry;
2349 uint16_t index;
2350 const char *name;
2351 irq_handler_t handler;
2352 };
2353
2354 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
2355 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
2356 "qla4xxx (default)",
2357 (irq_handler_t)qla4_8xxx_default_intr_handler },
2358 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
2359 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
2360 };
2361
2362 void
2363 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
2364 {
2365 int i;
2366 struct ql4_msix_entry *qentry;
2367
2368 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2369 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2370 if (qentry->have_irq) {
2371 free_irq(qentry->msix_vector, ha);
2372 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2373 __func__, qla4_8xxx_msix_entries[i].name));
2374 }
2375 }
2376 pci_disable_msix(ha->pdev);
2377 clear_bit(AF_MSIX_ENABLED, &ha->flags);
2378 }
2379
2380 int
2381 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
2382 {
2383 int i, ret;
2384 struct msix_entry entries[QLA_MSIX_ENTRIES];
2385 struct ql4_msix_entry *qentry;
2386
2387 for (i = 0; i < QLA_MSIX_ENTRIES; i++)
2388 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
2389
2390 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
2391 if (ret) {
2392 ql4_printk(KERN_WARNING, ha,
2393 "MSI-X: Failed to enable support -- %d/%d\n",
2394 QLA_MSIX_ENTRIES, ret);
2395 goto msix_out;
2396 }
2397 set_bit(AF_MSIX_ENABLED, &ha->flags);
2398
2399 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2400 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2401 qentry->msix_vector = entries[i].vector;
2402 qentry->msix_entry = entries[i].entry;
2403 qentry->have_irq = 0;
2404 ret = request_irq(qentry->msix_vector,
2405 qla4_8xxx_msix_entries[i].handler, 0,
2406 qla4_8xxx_msix_entries[i].name, ha);
2407 if (ret) {
2408 ql4_printk(KERN_WARNING, ha,
2409 "MSI-X: Unable to register handler -- %x/%d.\n",
2410 qla4_8xxx_msix_entries[i].index, ret);
2411 qla4_8xxx_disable_msix(ha);
2412 goto msix_out;
2413 }
2414 qentry->have_irq = 1;
2415 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2416 __func__, qla4_8xxx_msix_entries[i].name));
2417 }
2418 msix_out:
2419 return ret;
2420 }
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