drivers/scsi/sata_sil.c

   1 /*
   2  *  sata_sil.c - Silicon Image SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003 Red Hat, Inc.
   9  *  Copyright 2003 Benjamin Herrenschmidt
  10  *
  11  *  The contents of this file are subject to the Open
  12  *  Software License version 1.1 that can be found at
  13  *  http://www.opensource.org/licenses/osl-1.1.txt and is included herein
  14  *  by reference.
  15  *
  16  *  Alternatively, the contents of this file may be used under the terms
  17  *  of the GNU General Public License version 2 (the "GPL") as distributed
  18  *  in the kernel source COPYING file, in which case the provisions of
  19  *  the GPL are applicable instead of the above.  If you wish to allow
  20  *  the use of your version of this file only under the terms of the
  21  *  GPL and not to allow others to use your version of this file under
  22  *  the OSL, indicate your decision by deleting the provisions above and
  23  *  replace them with the notice and other provisions required by the GPL.
  24  *  If you do not delete the provisions above, a recipient may use your
  25  *  version of this file under either the OSL or the GPL.
  26  *
  27  *  Documentation for SiI 3112:
  28  *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  29  *
  30  *  Other errata and documentation available under NDA.
  31  *
  32  */
  33
  34 #include <linux/kernel.h>
  35 #include <linux/module.h>
  36 #include <linux/pci.h>
  37 #include <linux/init.h>
  38 #include <linux/blkdev.h>
  39 #include <linux/delay.h>
  40 #include <linux/interrupt.h>
  41 #include "scsi.h"
  42 #include <scsi/scsi_host.h>
  43 #include <linux/libata.h>
  44
  45 #define DRV_NAME        "sata_sil"
  46 #define DRV_VERSION     "0.9"
  47
  48 enum {
  49         SIL_FLAG_MOD15WRITE     = (1 << 30),
  50
  51         sil_3112                = 0,
  52         sil_3112_m15w           = 1,
  53         sil_3114                = 2,
  54
  55         SIL_FIFO_R0             = 0x40,
  56         SIL_FIFO_W0             = 0x41,
  57         SIL_FIFO_R1             = 0x44,
  58         SIL_FIFO_W1             = 0x45,
  59         SIL_FIFO_R2             = 0x240,
  60         SIL_FIFO_W2             = 0x241,
  61         SIL_FIFO_R3             = 0x244,
  62         SIL_FIFO_W3             = 0x245,
  63
  64         SIL_SYSCFG              = 0x48,
  65         SIL_MASK_IDE0_INT       = (1 << 22),
  66         SIL_MASK_IDE1_INT       = (1 << 23),
  67         SIL_MASK_IDE2_INT       = (1 << 24),
  68         SIL_MASK_IDE3_INT       = (1 << 25),
  69         SIL_MASK_2PORT          = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
  70         SIL_MASK_4PORT          = SIL_MASK_2PORT |
  71                                   SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
  72
  73         SIL_IDE2_BMDMA          = 0x200,
  74
  75         SIL_INTR_STEERING       = (1 << 1),
  76         SIL_QUIRK_MOD15WRITE    = (1 << 0),
  77         SIL_QUIRK_UDMA5MAX      = (1 << 1),
  78 };
  79
  80 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  81 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
  82 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
  83 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  84 static void sil_post_set_mode (struct ata_port *ap);
  85
  86 static struct pci_device_id sil_pci_tbl[] = {
  87         { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
  88         { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
  89         { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
  90         { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
  91         { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
  92         { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
  93         { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
  94         { }     /* terminate list */
  95 };
  96
  97
  98 /* TODO firmware versions should be added - eric */
  99 static const struct sil_drivelist {
 100         const char * product;
 101         unsigned int quirk;
 102 } sil_blacklist [] = {
 103         { "ST320012AS",         SIL_QUIRK_MOD15WRITE },
 104         { "ST330013AS",         SIL_QUIRK_MOD15WRITE },
 105         { "ST340017AS",         SIL_QUIRK_MOD15WRITE },
 106         { "ST360015AS",         SIL_QUIRK_MOD15WRITE },
 107         { "ST380013AS",         SIL_QUIRK_MOD15WRITE },
 108         { "ST380023AS",         SIL_QUIRK_MOD15WRITE },
 109         { "ST3120023AS",        SIL_QUIRK_MOD15WRITE },
 110         { "ST3160023AS",        SIL_QUIRK_MOD15WRITE },
 111         { "ST3120026AS",        SIL_QUIRK_MOD15WRITE },
 112         { "ST3200822AS",        SIL_QUIRK_MOD15WRITE },
 113         { "ST340014ASL",        SIL_QUIRK_MOD15WRITE },
 114         { "ST360014ASL",        SIL_QUIRK_MOD15WRITE },
 115         { "ST380011ASL",        SIL_QUIRK_MOD15WRITE },
 116         { "ST3120022ASL",       SIL_QUIRK_MOD15WRITE },
 117         { "ST3160021ASL",       SIL_QUIRK_MOD15WRITE },
 118         { "Maxtor 4D060H3",     SIL_QUIRK_UDMA5MAX },
 119         { }
 120 };
 121
 122 static struct pci_driver sil_pci_driver = {
 123         .name                   = DRV_NAME,
 124         .id_table               = sil_pci_tbl,
 125         .probe                  = sil_init_one,
 126         .remove                 = ata_pci_remove_one,
 127 };
 128
 129 static Scsi_Host_Template sil_sht = {
 130         .module                 = THIS_MODULE,
 131         .name                   = DRV_NAME,
 132         .ioctl                  = ata_scsi_ioctl,
 133         .queuecommand           = ata_scsi_queuecmd,
 134         .eh_strategy_handler    = ata_scsi_error,
 135         .can_queue              = ATA_DEF_QUEUE,
 136         .this_id                = ATA_SHT_THIS_ID,
 137         .sg_tablesize           = LIBATA_MAX_PRD,
 138         .max_sectors            = ATA_MAX_SECTORS,
 139         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 140         .emulated               = ATA_SHT_EMULATED,
 141         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 142         .proc_name              = DRV_NAME,
 143         .dma_boundary           = ATA_DMA_BOUNDARY,
 144         .slave_configure        = ata_scsi_slave_config,
 145         .bios_param             = ata_std_bios_param,
 146         .ordered_flush          = 1,
 147 };
 148
 149 static struct ata_port_operations sil_ops = {
 150         .port_disable           = ata_port_disable,
 151         .dev_config             = sil_dev_config,
 152         .tf_load                = ata_tf_load,
 153         .tf_read                = ata_tf_read,
 154         .check_status           = ata_check_status,
 155         .exec_command           = ata_exec_command,
 156         .dev_select             = ata_std_dev_select,
 157         .phy_reset              = sata_phy_reset,
 158         .post_set_mode          = sil_post_set_mode,
 159         .bmdma_setup            = ata_bmdma_setup,
 160         .bmdma_start            = ata_bmdma_start,
 161         .bmdma_stop             = ata_bmdma_stop,
 162         .bmdma_status           = ata_bmdma_status,
 163         .qc_prep                = ata_qc_prep,
 164         .qc_issue               = ata_qc_issue_prot,
 165         .eng_timeout            = ata_eng_timeout,
 166         .irq_handler            = ata_interrupt,
 167         .irq_clear              = ata_bmdma_irq_clear,
 168         .scr_read               = sil_scr_read,
 169         .scr_write              = sil_scr_write,
 170         .port_start             = ata_port_start,
 171         .port_stop              = ata_port_stop,
 172         .host_stop              = ata_host_stop,
 173 };
 174
 175 static struct ata_port_info sil_port_info[] = {
 176         /* sil_3112 */
 177         {
 178                 .sht            = &sil_sht,
 179                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 180                                   ATA_FLAG_SRST | ATA_FLAG_MMIO,
 181                 .pio_mask       = 0x1f,                 /* pio0-4 */
 182                 .mwdma_mask     = 0x07,                 /* mwdma0-2 */
 183                 .udma_mask      = 0x3f,                 /* udma0-5 */
 184                 .port_ops       = &sil_ops,
 185         }, /* sil_3112_15w - keep it sync'd w/ sil_3112 */
 186         {
 187                 .sht            = &sil_sht,
 188                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 189                                   ATA_FLAG_SRST | ATA_FLAG_MMIO |
 190                                   SIL_FLAG_MOD15WRITE,
 191                 .pio_mask       = 0x1f,                 /* pio0-4 */
 192                 .mwdma_mask     = 0x07,                 /* mwdma0-2 */
 193                 .udma_mask      = 0x3f,                 /* udma0-5 */
 194                 .port_ops       = &sil_ops,
 195         }, /* sil_3114 */
 196         {
 197                 .sht            = &sil_sht,
 198                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 199                                   ATA_FLAG_SRST | ATA_FLAG_MMIO,
 200                 .pio_mask       = 0x1f,                 /* pio0-4 */
 201                 .mwdma_mask     = 0x07,                 /* mwdma0-2 */
 202                 .udma_mask      = 0x3f,                 /* udma0-5 */
 203                 .port_ops       = &sil_ops,
 204         },
 205 };
 206
 207 /* per-port register offsets */
 208 /* TODO: we can probably calculate rather than use a table */
 209 static const struct {
 210         unsigned long tf;       /* ATA taskfile register block */
 211         unsigned long ctl;      /* ATA control/altstatus register block */
 212         unsigned long bmdma;    /* DMA register block */
 213         unsigned long scr;      /* SATA control register block */
 214         unsigned long sien;     /* SATA Interrupt Enable register */
 215         unsigned long xfer_mode;/* data transfer mode register */
 216 } sil_port[] = {
 217         /* port 0 ... */
 218         { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
 219         { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
 220         { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
 221         { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
 222         /* ... port 3 */
 223 };
 224
 225 MODULE_AUTHOR("Jeff Garzik");
 226 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
 227 MODULE_LICENSE("GPL");
 228 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
 229 MODULE_VERSION(DRV_VERSION);
 230
 231 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
 232 {
 233         u8 cache_line = 0;
 234         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
 235         return cache_line;
 236 }
 237
 238 static void sil_post_set_mode (struct ata_port *ap)
 239 {
 240         struct ata_host_set *host_set = ap->host_set;
 241         struct ata_device *dev;
 242         void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
 243         u32 tmp, dev_mode[2];
 244         unsigned int i;
 245
 246         for (i = 0; i < 2; i++) {
 247                 dev = &ap->device[i];
 248                 if (!ata_dev_present(dev))
 249                         dev_mode[i] = 0;        /* PIO0/1/2 */
 250                 else if (dev->flags & ATA_DFLAG_PIO)
 251                         dev_mode[i] = 1;        /* PIO3/4 */
 252                 else
 253                         dev_mode[i] = 3;        /* UDMA */
 254                 /* value 2 indicates MDMA */
 255         }
 256
 257         tmp = readl(addr);
 258         tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
 259         tmp |= dev_mode[0];
 260         tmp |= (dev_mode[1] << 4);
 261         writel(tmp, addr);
 262         readl(addr);    /* flush */
 263 }
 264
 265 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
 266 {
 267         unsigned long offset = ap->ioaddr.scr_addr;
 268
 269         switch (sc_reg) {
 270         case SCR_STATUS:
 271                 return offset + 4;
 272         case SCR_ERROR:
 273                 return offset + 8;
 274         case SCR_CONTROL:
 275                 return offset;
 276         default:
 277                 /* do nothing */
 278                 break;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
 285 {
 286         void *mmio = (void *) sil_scr_addr(ap, sc_reg);
 287         if (mmio)
 288                 return readl(mmio);
 289         return 0xffffffffU;
 290 }
 291
 292 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 293 {
 294         void *mmio = (void *) sil_scr_addr(ap, sc_reg);
 295         if (mmio)
 296                 writel(val, mmio);
 297 }
 298
 299 /**
 300  *      sil_dev_config - Apply device/host-specific errata fixups
 301  *      @ap: Port containing device to be examined
 302  *      @dev: Device to be examined
 303  *
 304  *      After the IDENTIFY [PACKET] DEVICE step is complete, and a
 305  *      device is known to be present, this function is called.
 306  *      We apply two errata fixups which are specific to Silicon Image,
 307  *      a Seagate and a Maxtor fixup.
 308  *
 309  *      For certain Seagate devices, we must limit the maximum sectors
 310  *      to under 8K.
 311  *
 312  *      For certain Maxtor devices, we must not program the drive
 313  *      beyond udma5.
 314  *
 315  *      Both fixups are unfairly pessimistic.  As soon as I get more
 316  *      information on these errata, I will create a more exhaustive
 317  *      list, and apply the fixups to only the specific
 318  *      devices/hosts/firmwares that need it.
 319  *
 320  *      20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
 321  *      The Maxtor quirk is in the blacklist, but I'm keeping the original
 322  *      pessimistic fix for the following reasons...
 323  *      - There seems to be less info on it, only one device gleaned off the
 324  *      Windows driver, maybe only one is affected.  More info would be greatly
 325  *      appreciated.
 326  *      - But then again UDMA5 is hardly anything to complain about
 327  */
 328 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
 329 {
 330         unsigned int n, quirks = 0;
 331         unsigned char model_num[40];
 332         const char *s;
 333         unsigned int len;
 334
 335         ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
 336                           sizeof(model_num));
 337         s = &model_num[0];
 338         len = strnlen(s, sizeof(model_num));
 339
 340         /* ATAPI specifies that empty space is blank-filled; remove blanks */
 341         while ((len > 0) && (s[len - 1] == ' '))
 342                 len--;
 343
 344         for (n = 0; sil_blacklist[n].product; n++)
 345                 if (!memcmp(sil_blacklist[n].product, s,
 346                             strlen(sil_blacklist[n].product))) {
 347                         quirks = sil_blacklist[n].quirk;
 348                         break;
 349                 }
 350
 351         /* limit requests to 15 sectors */
 352         if ((ap->flags & SIL_FLAG_MOD15WRITE) && (quirks & SIL_QUIRK_MOD15WRITE)) {
 353                 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
 354                        ap->id, dev->devno);
 355                 ap->host->max_sectors = 15;
 356                 ap->host->hostt->max_sectors = 15;
 357                 dev->flags |= ATA_DFLAG_LOCK_SECTORS;
 358                 return;
 359         }
 360
 361         /* limit to udma5 */
 362         if (quirks & SIL_QUIRK_UDMA5MAX) {
 363                 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
 364                        ap->id, dev->devno, s);
 365                 ap->udma_mask &= ATA_UDMA5;
 366                 return;
 367         }
 368 }
 369
 370 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 371 {
 372         static int printed_version;
 373         struct ata_probe_ent *probe_ent = NULL;
 374         unsigned long base;
 375         void *mmio_base;
 376         int rc;
 377         unsigned int i;
 378         int pci_dev_busy = 0;
 379         u32 tmp, irq_mask;
 380         u8 cls;
 381
 382         if (!printed_version++)
 383                 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
 384
 385         /*
 386          * If this driver happens to only be useful on Apple's K2, then
 387          * we should check that here as it has a normal Serverworks ID
 388          */
 389         rc = pci_enable_device(pdev);
 390         if (rc)
 391                 return rc;
 392
 393         rc = pci_request_regions(pdev, DRV_NAME);
 394         if (rc) {
 395                 pci_dev_busy = 1;
 396                 goto err_out;
 397         }
 398
 399         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 400         if (rc)
 401                 goto err_out_regions;
 402         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 403         if (rc)
 404                 goto err_out_regions;
 405
 406         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
 407         if (probe_ent == NULL) {
 408                 rc = -ENOMEM;
 409                 goto err_out_regions;
 410         }
 411
 412         memset(probe_ent, 0, sizeof(*probe_ent));
 413         INIT_LIST_HEAD(&probe_ent->node);
 414         probe_ent->dev = pci_dev_to_dev(pdev);
 415         probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
 416         probe_ent->sht = sil_port_info[ent->driver_data].sht;
 417         probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
 418         probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
 419         probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
 420         probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
 421         probe_ent->irq = pdev->irq;
 422         probe_ent->irq_flags = SA_SHIRQ;
 423         probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
 424
 425         mmio_base = ioremap(pci_resource_start(pdev, 5),
 426                             pci_resource_len(pdev, 5));
 427         if (mmio_base == NULL) {
 428                 rc = -ENOMEM;
 429                 goto err_out_free_ent;
 430         }
 431
 432         probe_ent->mmio_base = mmio_base;
 433
 434         base = (unsigned long) mmio_base;
 435
 436         for (i = 0; i < probe_ent->n_ports; i++) {
 437                 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
 438                 probe_ent->port[i].altstatus_addr =
 439                 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
 440                 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
 441                 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
 442                 ata_std_ports(&probe_ent->port[i]);
 443         }
 444
 445         /* Initialize FIFO PCI bus arbitration */
 446         cls = sil_get_device_cache_line(pdev);
 447         if (cls) {
 448                 cls >>= 3;
 449                 cls++;  /* cls = (line_size/8)+1 */
 450                 writeb(cls, mmio_base + SIL_FIFO_R0);
 451                 writeb(cls, mmio_base + SIL_FIFO_W0);
 452                 writeb(cls, mmio_base + SIL_FIFO_R1);
 453                 writeb(cls, mmio_base + SIL_FIFO_W1);
 454                 if (ent->driver_data == sil_3114) {
 455                         writeb(cls, mmio_base + SIL_FIFO_R2);
 456                         writeb(cls, mmio_base + SIL_FIFO_W2);
 457                         writeb(cls, mmio_base + SIL_FIFO_R3);
 458                         writeb(cls, mmio_base + SIL_FIFO_W3);
 459                 }
 460         } else
 461                 printk(KERN_WARNING DRV_NAME "(%s): cache line size not set.  Driver may not function\n",
 462                         pci_name(pdev));
 463
 464         if (ent->driver_data == sil_3114) {
 465                 irq_mask = SIL_MASK_4PORT;
 466
 467                 /* flip the magic "make 4 ports work" bit */
 468                 tmp = readl(mmio_base + SIL_IDE2_BMDMA);
 469                 if ((tmp & SIL_INTR_STEERING) == 0)
 470                         writel(tmp | SIL_INTR_STEERING,
 471                                mmio_base + SIL_IDE2_BMDMA);
 472
 473         } else {
 474                 irq_mask = SIL_MASK_2PORT;
 475         }
 476
 477         /* make sure IDE0/1/2/3 interrupts are not masked */
 478         tmp = readl(mmio_base + SIL_SYSCFG);
 479         if (tmp & irq_mask) {
 480                 tmp &= ~irq_mask;
 481                 writel(tmp, mmio_base + SIL_SYSCFG);
 482                 readl(mmio_base + SIL_SYSCFG);  /* flush */
 483         }
 484
 485         /* mask all SATA phy-related interrupts */
 486         /* TODO: unmask bit 6 (SError N bit) for hotplug */
 487         for (i = 0; i < probe_ent->n_ports; i++)
 488                 writel(0, mmio_base + sil_port[i].sien);
 489
 490         pci_set_master(pdev);
 491
 492         /* FIXME: check ata_device_add return value */
 493         ata_device_add(probe_ent);
 494         kfree(probe_ent);
 495
 496         return 0;
 497
 498 err_out_free_ent:
 499         kfree(probe_ent);
 500 err_out_regions:
 501         pci_release_regions(pdev);
 502 err_out:
 503         if (!pci_dev_busy)
 504                 pci_disable_device(pdev);
 505         return rc;
 506 }
 507
 508 static int __init sil_init(void)
 509 {
 510         return pci_module_init(&sil_pci_driver);
 511 }
 512
 513 static void __exit sil_exit(void)
 514 {
 515         pci_unregister_driver(&sil_pci_driver);
 516 }
 517
 518
 519 module_init(sil_init);
 520 module_exit(sil_exit);