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Merge branch 'irq-pio'
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / sata_sil24.c
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31 #include <asm/io.h>
32
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.24"
35
36 /*
37 * Port request block (PRB) 32 bytes
38 */
39 struct sil24_prb {
40 u16 ctrl;
41 u16 prot;
42 u32 rx_cnt;
43 u8 fis[6 * 4];
44 };
45
46 /*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49 struct sil24_sge {
50 u64 addr;
51 u32 cnt;
52 u32 flags;
53 };
54
55 /*
56 * Port multiplier
57 */
58 struct sil24_port_multiplier {
59 u32 diag;
60 u32 sactive;
61 };
62
63 enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
89 /* HOST_CTRL bits */
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
95
96 /*
97 * Port registers
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
99 */
100 PORT_REGS_SIZE = 0x2000,
101 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
102
103 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
104 /* 32 bit regs */
105 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
106 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
107 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
108 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
109 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
110 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
111 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
112 PORT_CMD_ERR = 0x1024, /* command error number */
113 PORT_FIS_CFG = 0x1028,
114 PORT_FIFO_THRES = 0x102c,
115 /* 16 bit regs */
116 PORT_DECODE_ERR_CNT = 0x1040,
117 PORT_DECODE_ERR_THRESH = 0x1042,
118 PORT_CRC_ERR_CNT = 0x1044,
119 PORT_CRC_ERR_THRESH = 0x1046,
120 PORT_HSHK_ERR_CNT = 0x1048,
121 PORT_HSHK_ERR_THRESH = 0x104a,
122 /* 32 bit regs */
123 PORT_PHY_CFG = 0x1050,
124 PORT_SLOT_STAT = 0x1800,
125 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
126 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
127 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
128 PORT_SCONTROL = 0x1f00,
129 PORT_SSTATUS = 0x1f04,
130 PORT_SERROR = 0x1f08,
131 PORT_SACTIVE = 0x1f0c,
132
133 /* PORT_CTRL_STAT bits */
134 PORT_CS_PORT_RST = (1 << 0), /* port reset */
135 PORT_CS_DEV_RST = (1 << 1), /* device reset */
136 PORT_CS_INIT = (1 << 2), /* port initialize */
137 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
138 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
139 PORT_CS_RESUME = (1 << 6), /* port resume */
140 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
141 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
142 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
143
144 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
145 /* bits[11:0] are masked */
146 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
147 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
148 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
149 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
150 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
151 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
152 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
153 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
154 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
155 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
156 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
157 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
158
159 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
160 PORT_IRQ_DEV_XCHG | PORT_IRQ_UNK_FIS,
161
162 /* bits[27:16] are unmasked (raw) */
163 PORT_IRQ_RAW_SHIFT = 16,
164 PORT_IRQ_MASKED_MASK = 0x7ff,
165 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
166
167 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
168 PORT_IRQ_STEER_SHIFT = 30,
169 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
170
171 /* PORT_CMD_ERR constants */
172 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
173 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
174 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
175 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
176 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
177 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
178 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
179 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
180 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
181 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
182 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
183 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
184 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
185 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
186 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
187 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
188 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
189 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
190 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
191 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
192 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
193 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
194
195 /* bits of PRB control field */
196 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
197 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
198 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
199 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
200 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
201
202 /* PRB protocol field */
203 PRB_PROT_PACKET = (1 << 0),
204 PRB_PROT_TCQ = (1 << 1),
205 PRB_PROT_NCQ = (1 << 2),
206 PRB_PROT_READ = (1 << 3),
207 PRB_PROT_WRITE = (1 << 4),
208 PRB_PROT_TRANSPARENT = (1 << 5),
209
210 /*
211 * Other constants
212 */
213 SGE_TRM = (1 << 31), /* Last SGE in chain */
214 SGE_LNK = (1 << 30), /* linked list
215 Points to SGT, not SGE */
216 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
217 data address ignored */
218
219 /* board id */
220 BID_SIL3124 = 0,
221 BID_SIL3132 = 1,
222 BID_SIL3131 = 2,
223
224 /* host flags */
225 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
226 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
227 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
228
229 IRQ_STAT_4PORTS = 0xf,
230 };
231
232 struct sil24_ata_block {
233 struct sil24_prb prb;
234 struct sil24_sge sge[LIBATA_MAX_PRD];
235 };
236
237 struct sil24_atapi_block {
238 struct sil24_prb prb;
239 u8 cdb[16];
240 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
241 };
242
243 union sil24_cmd_block {
244 struct sil24_ata_block ata;
245 struct sil24_atapi_block atapi;
246 };
247
248 static struct sil24_cerr_info {
249 unsigned int err_mask, action;
250 const char *desc;
251 } sil24_cerr_db[] = {
252 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
253 "device error" },
254 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
255 "device error via D2H FIS" },
256 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
257 "device error via SDB FIS" },
258 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
259 "error in data FIS" },
260 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
261 "failed to transmit command FIS" },
262 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
263 "protocol mismatch" },
264 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
265 "data directon mismatch" },
266 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
267 "ran out of SGEs while writing" },
268 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
269 "ran out of SGEs while reading" },
270 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
271 "invalid data directon for ATAPI CDB" },
272 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
273 "SGT no on qword boundary" },
274 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
275 "PCI target abort while fetching SGT" },
276 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
277 "PCI master abort while fetching SGT" },
278 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
279 "PCI parity error while fetching SGT" },
280 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
281 "PRB not on qword boundary" },
282 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
283 "PCI target abort while fetching PRB" },
284 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
285 "PCI master abort while fetching PRB" },
286 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
287 "PCI parity error while fetching PRB" },
288 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
289 "undefined error while transferring data" },
290 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI target abort while transferring data" },
292 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI master abort while transferring data" },
294 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
295 "PCI parity error while transferring data" },
296 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
297 "FIS received while sending service FIS" },
298 };
299
300 /*
301 * ap->private_data
302 *
303 * The preview driver always returned 0 for status. We emulate it
304 * here from the previous interrupt.
305 */
306 struct sil24_port_priv {
307 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
308 dma_addr_t cmd_block_dma; /* DMA base addr for them */
309 struct ata_taskfile tf; /* Cached taskfile registers */
310 };
311
312 /* ap->host_set->private_data */
313 struct sil24_host_priv {
314 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
315 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
316 };
317
318 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
319 static u8 sil24_check_status(struct ata_port *ap);
320 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
321 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
322 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
323 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
324 static void sil24_qc_prep(struct ata_queued_cmd *qc);
325 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
326 static void sil24_irq_clear(struct ata_port *ap);
327 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
328 static void sil24_freeze(struct ata_port *ap);
329 static void sil24_thaw(struct ata_port *ap);
330 static void sil24_error_handler(struct ata_port *ap);
331 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
332 static int sil24_port_start(struct ata_port *ap);
333 static void sil24_port_stop(struct ata_port *ap);
334 static void sil24_host_stop(struct ata_host_set *host_set);
335 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
336
337 static const struct pci_device_id sil24_pci_tbl[] = {
338 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
339 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
340 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
341 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
342 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
343 { } /* terminate list */
344 };
345
346 static struct pci_driver sil24_pci_driver = {
347 .name = DRV_NAME,
348 .id_table = sil24_pci_tbl,
349 .probe = sil24_init_one,
350 .remove = ata_pci_remove_one, /* safe? */
351 };
352
353 static struct scsi_host_template sil24_sht = {
354 .module = THIS_MODULE,
355 .name = DRV_NAME,
356 .ioctl = ata_scsi_ioctl,
357 .queuecommand = ata_scsi_queuecmd,
358 .can_queue = ATA_DEF_QUEUE,
359 .this_id = ATA_SHT_THIS_ID,
360 .sg_tablesize = LIBATA_MAX_PRD,
361 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
362 .emulated = ATA_SHT_EMULATED,
363 .use_clustering = ATA_SHT_USE_CLUSTERING,
364 .proc_name = DRV_NAME,
365 .dma_boundary = ATA_DMA_BOUNDARY,
366 .slave_configure = ata_scsi_slave_config,
367 .bios_param = ata_std_bios_param,
368 };
369
370 static const struct ata_port_operations sil24_ops = {
371 .port_disable = ata_port_disable,
372
373 .dev_config = sil24_dev_config,
374
375 .check_status = sil24_check_status,
376 .check_altstatus = sil24_check_status,
377 .dev_select = ata_noop_dev_select,
378
379 .tf_read = sil24_tf_read,
380
381 .probe_reset = sil24_probe_reset,
382
383 .qc_prep = sil24_qc_prep,
384 .qc_issue = sil24_qc_issue,
385
386 .irq_handler = sil24_interrupt,
387 .irq_clear = sil24_irq_clear,
388
389 .scr_read = sil24_scr_read,
390 .scr_write = sil24_scr_write,
391
392 .freeze = sil24_freeze,
393 .thaw = sil24_thaw,
394 .error_handler = sil24_error_handler,
395 .post_internal_cmd = sil24_post_internal_cmd,
396
397 .port_start = sil24_port_start,
398 .port_stop = sil24_port_stop,
399 .host_stop = sil24_host_stop,
400 };
401
402 /*
403 * Use bits 30-31 of host_flags to encode available port numbers.
404 * Current maxium is 4.
405 */
406 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
407 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
408
409 static struct ata_port_info sil24_port_info[] = {
410 /* sil_3124 */
411 {
412 .sht = &sil24_sht,
413 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
414 SIL24_FLAG_PCIX_IRQ_WOC,
415 .pio_mask = 0x1f, /* pio0-4 */
416 .mwdma_mask = 0x07, /* mwdma0-2 */
417 .udma_mask = 0x3f, /* udma0-5 */
418 .port_ops = &sil24_ops,
419 },
420 /* sil_3132 */
421 {
422 .sht = &sil24_sht,
423 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
424 .pio_mask = 0x1f, /* pio0-4 */
425 .mwdma_mask = 0x07, /* mwdma0-2 */
426 .udma_mask = 0x3f, /* udma0-5 */
427 .port_ops = &sil24_ops,
428 },
429 /* sil_3131/sil_3531 */
430 {
431 .sht = &sil24_sht,
432 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
433 .pio_mask = 0x1f, /* pio0-4 */
434 .mwdma_mask = 0x07, /* mwdma0-2 */
435 .udma_mask = 0x3f, /* udma0-5 */
436 .port_ops = &sil24_ops,
437 },
438 };
439
440 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
441 {
442 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
443
444 if (dev->cdb_len == 16)
445 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
446 else
447 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
448 }
449
450 static inline void sil24_update_tf(struct ata_port *ap)
451 {
452 struct sil24_port_priv *pp = ap->private_data;
453 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
454 struct sil24_prb __iomem *prb = port;
455 u8 fis[6 * 4];
456
457 memcpy_fromio(fis, prb->fis, 6 * 4);
458 ata_tf_from_fis(fis, &pp->tf);
459 }
460
461 static u8 sil24_check_status(struct ata_port *ap)
462 {
463 struct sil24_port_priv *pp = ap->private_data;
464 return pp->tf.command;
465 }
466
467 static int sil24_scr_map[] = {
468 [SCR_CONTROL] = 0,
469 [SCR_STATUS] = 1,
470 [SCR_ERROR] = 2,
471 [SCR_ACTIVE] = 3,
472 };
473
474 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
475 {
476 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
477 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
478 void __iomem *addr;
479 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
480 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
481 }
482 return 0xffffffffU;
483 }
484
485 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
486 {
487 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
488 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
489 void __iomem *addr;
490 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
491 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
492 }
493 }
494
495 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
496 {
497 struct sil24_port_priv *pp = ap->private_data;
498 *tf = pp->tf;
499 }
500
501 static int sil24_init_port(struct ata_port *ap)
502 {
503 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
504 u32 tmp;
505
506 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
507 ata_wait_register(port + PORT_CTRL_STAT,
508 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
509 tmp = ata_wait_register(port + PORT_CTRL_STAT,
510 PORT_CS_RDY, 0, 10, 100);
511
512 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
513 return -EIO;
514 return 0;
515 }
516
517 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
518 {
519 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
520 struct sil24_port_priv *pp = ap->private_data;
521 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
522 dma_addr_t paddr = pp->cmd_block_dma;
523 u32 mask, irq_stat;
524 const char *reason;
525
526 DPRINTK("ENTER\n");
527
528 if (ata_port_offline(ap)) {
529 DPRINTK("PHY reports no device\n");
530 *class = ATA_DEV_NONE;
531 goto out;
532 }
533
534 /* put the port into known state */
535 if (sil24_init_port(ap)) {
536 reason ="port not ready";
537 goto err;
538 }
539
540 /* do SRST */
541 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
542 prb->fis[1] = 0; /* no PM yet */
543
544 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
545 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
546
547 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
548 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
549 100, ATA_TMOUT_BOOT / HZ * 1000);
550
551 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
552 irq_stat >>= PORT_IRQ_RAW_SHIFT;
553
554 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
555 if (irq_stat & PORT_IRQ_ERROR)
556 reason = "SRST command error";
557 else
558 reason = "timeout";
559 goto err;
560 }
561
562 sil24_update_tf(ap);
563 *class = ata_dev_classify(&pp->tf);
564
565 if (*class == ATA_DEV_UNKNOWN)
566 *class = ATA_DEV_NONE;
567
568 out:
569 DPRINTK("EXIT, class=%u\n", *class);
570 return 0;
571
572 err:
573 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
574 return -EIO;
575 }
576
577 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
578 {
579 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
580 const char *reason;
581 int tout_msec;
582 u32 tmp;
583
584 /* sil24 does the right thing(tm) without any protection */
585 sata_set_spd(ap);
586
587 tout_msec = 100;
588 if (ata_port_online(ap))
589 tout_msec = 5000;
590
591 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
592 tmp = ata_wait_register(port + PORT_CTRL_STAT,
593 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
594
595 /* SStatus oscillates between zero and valid status for short
596 * duration after DEV_RST, give it time to settle.
597 */
598 msleep(100);
599
600 if (tmp & PORT_CS_DEV_RST) {
601 if (ata_port_offline(ap))
602 return 0;
603 reason = "link not ready";
604 goto err;
605 }
606
607 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
608 reason = "device not ready";
609 goto err;
610 }
611
612 /* sil24 doesn't report device class code after hardreset,
613 * leave *class alone.
614 */
615 return 0;
616
617 err:
618 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
619 return -EIO;
620 }
621
622 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes)
623 {
624 return ata_drive_probe_reset(ap, ata_std_probeinit,
625 sil24_softreset, sil24_hardreset,
626 ata_std_postreset, classes);
627 }
628
629 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
630 struct sil24_sge *sge)
631 {
632 struct scatterlist *sg;
633 unsigned int idx = 0;
634
635 ata_for_each_sg(sg, qc) {
636 sge->addr = cpu_to_le64(sg_dma_address(sg));
637 sge->cnt = cpu_to_le32(sg_dma_len(sg));
638 if (ata_sg_is_last(sg, qc))
639 sge->flags = cpu_to_le32(SGE_TRM);
640 else
641 sge->flags = 0;
642
643 sge++;
644 idx++;
645 }
646 }
647
648 static void sil24_qc_prep(struct ata_queued_cmd *qc)
649 {
650 struct ata_port *ap = qc->ap;
651 struct sil24_port_priv *pp = ap->private_data;
652 union sil24_cmd_block *cb = pp->cmd_block + qc->tag;
653 struct sil24_prb *prb;
654 struct sil24_sge *sge;
655 u16 ctrl = 0;
656
657 switch (qc->tf.protocol) {
658 case ATA_PROT_PIO:
659 case ATA_PROT_DMA:
660 case ATA_PROT_NODATA:
661 prb = &cb->ata.prb;
662 sge = cb->ata.sge;
663 break;
664
665 case ATA_PROT_ATAPI:
666 case ATA_PROT_ATAPI_DMA:
667 case ATA_PROT_ATAPI_NODATA:
668 prb = &cb->atapi.prb;
669 sge = cb->atapi.sge;
670 memset(cb->atapi.cdb, 0, 32);
671 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
672
673 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
674 if (qc->tf.flags & ATA_TFLAG_WRITE)
675 ctrl = PRB_CTRL_PACKET_WRITE;
676 else
677 ctrl = PRB_CTRL_PACKET_READ;
678 }
679 break;
680
681 default:
682 prb = NULL; /* shut up, gcc */
683 sge = NULL;
684 BUG();
685 }
686
687 prb->ctrl = cpu_to_le16(ctrl);
688 ata_tf_to_fis(&qc->tf, prb->fis, 0);
689
690 if (qc->flags & ATA_QCFLAG_DMAMAP)
691 sil24_fill_sg(qc, sge);
692 }
693
694 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
695 {
696 struct ata_port *ap = qc->ap;
697 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
698 struct sil24_port_priv *pp = ap->private_data;
699 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
700
701 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
702 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
703
704 return 0;
705 }
706
707 static void sil24_irq_clear(struct ata_port *ap)
708 {
709 /* unused */
710 }
711
712 static void sil24_freeze(struct ata_port *ap)
713 {
714 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
715
716 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
717 * PORT_IRQ_ENABLE instead.
718 */
719 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
720 }
721
722 static void sil24_thaw(struct ata_port *ap)
723 {
724 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
725 u32 tmp;
726
727 /* clear IRQ */
728 tmp = readl(port + PORT_IRQ_STAT);
729 writel(tmp, port + PORT_IRQ_STAT);
730
731 /* turn IRQ back on */
732 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
733 }
734
735 static void sil24_error_intr(struct ata_port *ap)
736 {
737 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
738 struct ata_eh_info *ehi = &ap->eh_info;
739 int freeze = 0;
740 u32 irq_stat;
741
742 /* on error, we need to clear IRQ explicitly */
743 irq_stat = readl(port + PORT_IRQ_STAT);
744 writel(irq_stat, port + PORT_IRQ_STAT);
745
746 /* first, analyze and record host port events */
747 ata_ehi_clear_desc(ehi);
748
749 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
750
751 if (irq_stat & PORT_IRQ_DEV_XCHG) {
752 ehi->err_mask |= AC_ERR_ATA_BUS;
753 /* sil24 doesn't recover very well from phy
754 * disconnection with a softreset. Force hardreset.
755 */
756 ehi->action |= ATA_EH_HARDRESET;
757 ata_ehi_push_desc(ehi, ", device_exchanged");
758 freeze = 1;
759 }
760
761 if (irq_stat & PORT_IRQ_UNK_FIS) {
762 ehi->err_mask |= AC_ERR_HSM;
763 ehi->action |= ATA_EH_SOFTRESET;
764 ata_ehi_push_desc(ehi , ", unknown FIS");
765 freeze = 1;
766 }
767
768 /* deal with command error */
769 if (irq_stat & PORT_IRQ_ERROR) {
770 struct sil24_cerr_info *ci = NULL;
771 unsigned int err_mask = 0, action = 0;
772 struct ata_queued_cmd *qc;
773 u32 cerr;
774
775 /* analyze CMD_ERR */
776 cerr = readl(port + PORT_CMD_ERR);
777 if (cerr < ARRAY_SIZE(sil24_cerr_db))
778 ci = &sil24_cerr_db[cerr];
779
780 if (ci && ci->desc) {
781 err_mask |= ci->err_mask;
782 action |= ci->action;
783 ata_ehi_push_desc(ehi, ", %s", ci->desc);
784 } else {
785 err_mask |= AC_ERR_OTHER;
786 action |= ATA_EH_SOFTRESET;
787 ata_ehi_push_desc(ehi, ", unknown command error %d",
788 cerr);
789 }
790
791 /* record error info */
792 qc = ata_qc_from_tag(ap, ap->active_tag);
793 if (qc) {
794 int tag = qc->tag;
795 if (unlikely(ata_tag_internal(tag)))
796 tag = 0;
797 sil24_update_tf(ap);
798 qc->err_mask |= err_mask;
799 } else
800 ehi->err_mask |= err_mask;
801
802 ehi->action |= action;
803 }
804
805 /* freeze or abort */
806 if (freeze)
807 ata_port_freeze(ap);
808 else
809 ata_port_abort(ap);
810 }
811
812 static inline void sil24_host_intr(struct ata_port *ap)
813 {
814 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
815 struct ata_queued_cmd *qc;
816 u32 slot_stat;
817
818 slot_stat = readl(port + PORT_SLOT_STAT);
819
820 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
821 sil24_error_intr(ap);
822 return;
823 }
824
825 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
826 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
827
828 qc = ata_qc_from_tag(ap, ap->active_tag);
829 if (qc) {
830 if (qc->flags & ATA_QCFLAG_RESULT_TF)
831 sil24_update_tf(ap);
832 ata_qc_complete(qc);
833 return;
834 }
835
836 if (ata_ratelimit())
837 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
838 "(slot_stat 0x%x active_tag %d)\n",
839 slot_stat, ap->active_tag);
840 }
841
842 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
843 {
844 struct ata_host_set *host_set = dev_instance;
845 struct sil24_host_priv *hpriv = host_set->private_data;
846 unsigned handled = 0;
847 u32 status;
848 int i;
849
850 status = readl(hpriv->host_base + HOST_IRQ_STAT);
851
852 if (status == 0xffffffff) {
853 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
854 "PCI fault or device removal?\n");
855 goto out;
856 }
857
858 if (!(status & IRQ_STAT_4PORTS))
859 goto out;
860
861 spin_lock(&host_set->lock);
862
863 for (i = 0; i < host_set->n_ports; i++)
864 if (status & (1 << i)) {
865 struct ata_port *ap = host_set->ports[i];
866 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
867 sil24_host_intr(host_set->ports[i]);
868 handled++;
869 } else
870 printk(KERN_ERR DRV_NAME
871 ": interrupt from disabled port %d\n", i);
872 }
873
874 spin_unlock(&host_set->lock);
875 out:
876 return IRQ_RETVAL(handled);
877 }
878
879 static void sil24_error_handler(struct ata_port *ap)
880 {
881 struct ata_eh_context *ehc = &ap->eh_context;
882
883 if (sil24_init_port(ap)) {
884 ata_eh_freeze_port(ap);
885 ehc->i.action |= ATA_EH_HARDRESET;
886 }
887
888 /* perform recovery */
889 ata_do_eh(ap, sil24_softreset, sil24_hardreset, ata_std_postreset);
890 }
891
892 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
893 {
894 struct ata_port *ap = qc->ap;
895
896 if (qc->flags & ATA_QCFLAG_FAILED)
897 qc->err_mask |= AC_ERR_OTHER;
898
899 /* make DMA engine forget about the failed command */
900 if (qc->err_mask)
901 sil24_init_port(ap);
902 }
903
904 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
905 {
906 const size_t cb_size = sizeof(*pp->cmd_block);
907
908 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
909 }
910
911 static int sil24_port_start(struct ata_port *ap)
912 {
913 struct device *dev = ap->host_set->dev;
914 struct sil24_port_priv *pp;
915 union sil24_cmd_block *cb;
916 size_t cb_size = sizeof(*cb);
917 dma_addr_t cb_dma;
918 int rc = -ENOMEM;
919
920 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
921 if (!pp)
922 goto err_out;
923
924 pp->tf.command = ATA_DRDY;
925
926 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
927 if (!cb)
928 goto err_out_pp;
929 memset(cb, 0, cb_size);
930
931 rc = ata_pad_alloc(ap, dev);
932 if (rc)
933 goto err_out_pad;
934
935 pp->cmd_block = cb;
936 pp->cmd_block_dma = cb_dma;
937
938 ap->private_data = pp;
939
940 return 0;
941
942 err_out_pad:
943 sil24_cblk_free(pp, dev);
944 err_out_pp:
945 kfree(pp);
946 err_out:
947 return rc;
948 }
949
950 static void sil24_port_stop(struct ata_port *ap)
951 {
952 struct device *dev = ap->host_set->dev;
953 struct sil24_port_priv *pp = ap->private_data;
954
955 sil24_cblk_free(pp, dev);
956 ata_pad_free(ap, dev);
957 kfree(pp);
958 }
959
960 static void sil24_host_stop(struct ata_host_set *host_set)
961 {
962 struct sil24_host_priv *hpriv = host_set->private_data;
963 struct pci_dev *pdev = to_pci_dev(host_set->dev);
964
965 pci_iounmap(pdev, hpriv->host_base);
966 pci_iounmap(pdev, hpriv->port_base);
967 kfree(hpriv);
968 }
969
970 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
971 {
972 static int printed_version = 0;
973 unsigned int board_id = (unsigned int)ent->driver_data;
974 struct ata_port_info *pinfo = &sil24_port_info[board_id];
975 struct ata_probe_ent *probe_ent = NULL;
976 struct sil24_host_priv *hpriv = NULL;
977 void __iomem *host_base = NULL;
978 void __iomem *port_base = NULL;
979 int i, rc;
980 u32 tmp;
981
982 if (!printed_version++)
983 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
984
985 rc = pci_enable_device(pdev);
986 if (rc)
987 return rc;
988
989 rc = pci_request_regions(pdev, DRV_NAME);
990 if (rc)
991 goto out_disable;
992
993 rc = -ENOMEM;
994 /* map mmio registers */
995 host_base = pci_iomap(pdev, 0, 0);
996 if (!host_base)
997 goto out_free;
998 port_base = pci_iomap(pdev, 2, 0);
999 if (!port_base)
1000 goto out_free;
1001
1002 /* allocate & init probe_ent and hpriv */
1003 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1004 if (!probe_ent)
1005 goto out_free;
1006
1007 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1008 if (!hpriv)
1009 goto out_free;
1010
1011 probe_ent->dev = pci_dev_to_dev(pdev);
1012 INIT_LIST_HEAD(&probe_ent->node);
1013
1014 probe_ent->sht = pinfo->sht;
1015 probe_ent->host_flags = pinfo->host_flags;
1016 probe_ent->pio_mask = pinfo->pio_mask;
1017 probe_ent->mwdma_mask = pinfo->mwdma_mask;
1018 probe_ent->udma_mask = pinfo->udma_mask;
1019 probe_ent->port_ops = pinfo->port_ops;
1020 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
1021
1022 probe_ent->irq = pdev->irq;
1023 probe_ent->irq_flags = SA_SHIRQ;
1024 probe_ent->mmio_base = port_base;
1025 probe_ent->private_data = hpriv;
1026
1027 hpriv->host_base = host_base;
1028 hpriv->port_base = port_base;
1029
1030 /*
1031 * Configure the device
1032 */
1033 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1034 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1035 if (rc) {
1036 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1037 if (rc) {
1038 dev_printk(KERN_ERR, &pdev->dev,
1039 "64-bit DMA enable failed\n");
1040 goto out_free;
1041 }
1042 }
1043 } else {
1044 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1045 if (rc) {
1046 dev_printk(KERN_ERR, &pdev->dev,
1047 "32-bit DMA enable failed\n");
1048 goto out_free;
1049 }
1050 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1051 if (rc) {
1052 dev_printk(KERN_ERR, &pdev->dev,
1053 "32-bit consistent DMA enable failed\n");
1054 goto out_free;
1055 }
1056 }
1057
1058 /* GPIO off */
1059 writel(0, host_base + HOST_FLASH_CMD);
1060
1061 /* Apply workaround for completion IRQ loss on PCI-X errata */
1062 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1063 tmp = readl(host_base + HOST_CTRL);
1064 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1065 dev_printk(KERN_INFO, &pdev->dev,
1066 "Applying completion IRQ loss on PCI-X "
1067 "errata fix\n");
1068 else
1069 probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1070 }
1071
1072 /* clear global reset & mask interrupts during initialization */
1073 writel(0, host_base + HOST_CTRL);
1074
1075 for (i = 0; i < probe_ent->n_ports; i++) {
1076 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1077 unsigned long portu = (unsigned long)port;
1078
1079 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
1080 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1081
1082 ata_std_ports(&probe_ent->port[i]);
1083
1084 /* Initial PHY setting */
1085 writel(0x20c, port + PORT_PHY_CFG);
1086
1087 /* Clear port RST */
1088 tmp = readl(port + PORT_CTRL_STAT);
1089 if (tmp & PORT_CS_PORT_RST) {
1090 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1091 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1092 PORT_CS_PORT_RST,
1093 PORT_CS_PORT_RST, 10, 100);
1094 if (tmp & PORT_CS_PORT_RST)
1095 dev_printk(KERN_ERR, &pdev->dev,
1096 "failed to clear port RST\n");
1097 }
1098
1099 /* Configure IRQ WoC */
1100 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1101 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1102 else
1103 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1104
1105 /* Zero error counters. */
1106 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1107 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1108 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1109 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1110 writel(0x0000, port + PORT_CRC_ERR_CNT);
1111 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1112
1113 /* Always use 64bit activation */
1114 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1115
1116 /* Clear port multiplier enable and resume bits */
1117 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
1118 }
1119
1120 /* Turn on interrupts */
1121 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1122
1123 pci_set_master(pdev);
1124
1125 /* FIXME: check ata_device_add return value */
1126 ata_device_add(probe_ent);
1127
1128 kfree(probe_ent);
1129 return 0;
1130
1131 out_free:
1132 if (host_base)
1133 pci_iounmap(pdev, host_base);
1134 if (port_base)
1135 pci_iounmap(pdev, port_base);
1136 kfree(probe_ent);
1137 kfree(hpriv);
1138 pci_release_regions(pdev);
1139 out_disable:
1140 pci_disable_device(pdev);
1141 return rc;
1142 }
1143
1144 static int __init sil24_init(void)
1145 {
1146 return pci_module_init(&sil24_pci_driver);
1147 }
1148
1149 static void __exit sil24_exit(void)
1150 {
1151 pci_unregister_driver(&sil24_pci_driver);
1152 }
1153
1154 MODULE_AUTHOR("Tejun Heo");
1155 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1156 MODULE_LICENSE("GPL");
1157 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1158
1159 module_init(sil24_init);
1160 module_exit(sil24_exit);
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