2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.23"
37 * Port request block (PRB) 32 bytes
47 * Scatter gather entry (SGE) 16 bytes
58 struct sil24_port_multiplier
{
65 * Global controller registers (128 bytes @ BAR0)
68 HOST_SLOT_STAT
= 0x00, /* 32 bit slot stat * 4 */
72 HOST_BIST_CTRL
= 0x50,
73 HOST_BIST_PTRN
= 0x54,
74 HOST_BIST_STAT
= 0x58,
75 HOST_MEM_BIST_STAT
= 0x5c,
76 HOST_FLASH_CMD
= 0x70,
78 HOST_FLASH_DATA
= 0x74,
79 HOST_TRANSITION_DETECT
= 0x75,
80 HOST_GPIO_CTRL
= 0x76,
81 HOST_I2C_ADDR
= 0x78, /* 32 bit */
83 HOST_I2C_XFER_CNT
= 0x7e,
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN
= (1 << 31),
91 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
93 PORT_REGS_SIZE
= 0x2000,
94 PORT_PRB
= 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
96 PORT_PM
= 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
98 PORT_CTRL_STAT
= 0x1000, /* write: ctrl-set, read: stat */
99 PORT_CTRL_CLR
= 0x1004, /* write: ctrl-clear */
100 PORT_IRQ_STAT
= 0x1008, /* high: status, low: interrupt */
101 PORT_IRQ_ENABLE_SET
= 0x1010, /* write: enable-set */
102 PORT_IRQ_ENABLE_CLR
= 0x1014, /* write: enable-clear */
103 PORT_ACTIVATE_UPPER_ADDR
= 0x101c,
104 PORT_EXEC_FIFO
= 0x1020, /* command execution fifo */
105 PORT_CMD_ERR
= 0x1024, /* command error number */
106 PORT_FIS_CFG
= 0x1028,
107 PORT_FIFO_THRES
= 0x102c,
109 PORT_DECODE_ERR_CNT
= 0x1040,
110 PORT_DECODE_ERR_THRESH
= 0x1042,
111 PORT_CRC_ERR_CNT
= 0x1044,
112 PORT_CRC_ERR_THRESH
= 0x1046,
113 PORT_HSHK_ERR_CNT
= 0x1048,
114 PORT_HSHK_ERR_THRESH
= 0x104a,
116 PORT_PHY_CFG
= 0x1050,
117 PORT_SLOT_STAT
= 0x1800,
118 PORT_CMD_ACTIVATE
= 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
119 PORT_EXEC_DIAG
= 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
120 PORT_PSD_DIAG
= 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
121 PORT_SCONTROL
= 0x1f00,
122 PORT_SSTATUS
= 0x1f04,
123 PORT_SERROR
= 0x1f08,
124 PORT_SACTIVE
= 0x1f0c,
126 /* PORT_CTRL_STAT bits */
127 PORT_CS_PORT_RST
= (1 << 0), /* port reset */
128 PORT_CS_DEV_RST
= (1 << 1), /* device reset */
129 PORT_CS_INIT
= (1 << 2), /* port initialize */
130 PORT_CS_IRQ_WOC
= (1 << 3), /* interrupt write one to clear */
131 PORT_CS_CDB16
= (1 << 5), /* 0=12b cdb, 1=16b cdb */
132 PORT_CS_RESUME
= (1 << 6), /* port resume */
133 PORT_CS_32BIT_ACTV
= (1 << 10), /* 32-bit activation */
134 PORT_CS_PM_EN
= (1 << 13), /* port multiplier enable */
135 PORT_CS_RDY
= (1 << 31), /* port ready to accept commands */
137 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
138 /* bits[11:0] are masked */
139 PORT_IRQ_COMPLETE
= (1 << 0), /* command(s) completed */
140 PORT_IRQ_ERROR
= (1 << 1), /* command execution error */
141 PORT_IRQ_PORTRDY_CHG
= (1 << 2), /* port ready change */
142 PORT_IRQ_PWR_CHG
= (1 << 3), /* power management change */
143 PORT_IRQ_PHYRDY_CHG
= (1 << 4), /* PHY ready change */
144 PORT_IRQ_COMWAKE
= (1 << 5), /* COMWAKE received */
145 PORT_IRQ_UNK_FIS
= (1 << 6), /* Unknown FIS received */
146 PORT_IRQ_SDB_FIS
= (1 << 11), /* SDB FIS received */
148 /* bits[27:16] are unmasked (raw) */
149 PORT_IRQ_RAW_SHIFT
= 16,
150 PORT_IRQ_MASKED_MASK
= 0x7ff,
151 PORT_IRQ_RAW_MASK
= (0x7ff << PORT_IRQ_RAW_SHIFT
),
153 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
154 PORT_IRQ_STEER_SHIFT
= 30,
155 PORT_IRQ_STEER_MASK
= (3 << PORT_IRQ_STEER_SHIFT
),
157 /* PORT_CMD_ERR constants */
158 PORT_CERR_DEV
= 1, /* Error bit in D2H Register FIS */
159 PORT_CERR_SDB
= 2, /* Error bit in SDB FIS */
160 PORT_CERR_DATA
= 3, /* Error in data FIS not detected by dev */
161 PORT_CERR_SEND
= 4, /* Initial cmd FIS transmission failure */
162 PORT_CERR_INCONSISTENT
= 5, /* Protocol mismatch */
163 PORT_CERR_DIRECTION
= 6, /* Data direction mismatch */
164 PORT_CERR_UNDERRUN
= 7, /* Ran out of SGEs while writing */
165 PORT_CERR_OVERRUN
= 8, /* Ran out of SGEs while reading */
166 PORT_CERR_PKT_PROT
= 11, /* DIR invalid in 1st PIO setup of ATAPI */
167 PORT_CERR_SGT_BOUNDARY
= 16, /* PLD ecode 00 - SGT not on qword boundary */
168 PORT_CERR_SGT_TGTABRT
= 17, /* PLD ecode 01 - target abort */
169 PORT_CERR_SGT_MSTABRT
= 18, /* PLD ecode 10 - master abort */
170 PORT_CERR_SGT_PCIPERR
= 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
171 PORT_CERR_CMD_BOUNDARY
= 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
172 PORT_CERR_CMD_TGTABRT
= 25, /* ctrl[15:13] 010 - target abort */
173 PORT_CERR_CMD_MSTABRT
= 26, /* ctrl[15:13] 100 - master abort */
174 PORT_CERR_CMD_PCIPERR
= 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
175 PORT_CERR_XFR_UNDEF
= 32, /* PSD ecode 00 - undefined */
176 PORT_CERR_XFR_TGTABRT
= 33, /* PSD ecode 01 - target abort */
177 PORT_CERR_XFR_MSGABRT
= 34, /* PSD ecode 10 - master abort */
178 PORT_CERR_XFR_PCIPERR
= 35, /* PSD ecode 11 - PCI prity err during transfer */
179 PORT_CERR_SENDSERVICE
= 36, /* FIS received while sending service */
181 /* bits of PRB control field */
182 PRB_CTRL_PROTOCOL
= (1 << 0), /* override def. ATA protocol */
183 PRB_CTRL_PACKET_READ
= (1 << 4), /* PACKET cmd read */
184 PRB_CTRL_PACKET_WRITE
= (1 << 5), /* PACKET cmd write */
185 PRB_CTRL_NIEN
= (1 << 6), /* Mask completion irq */
186 PRB_CTRL_SRST
= (1 << 7), /* Soft reset request (ign BSY?) */
188 /* PRB protocol field */
189 PRB_PROT_PACKET
= (1 << 0),
190 PRB_PROT_TCQ
= (1 << 1),
191 PRB_PROT_NCQ
= (1 << 2),
192 PRB_PROT_READ
= (1 << 3),
193 PRB_PROT_WRITE
= (1 << 4),
194 PRB_PROT_TRANSPARENT
= (1 << 5),
199 SGE_TRM
= (1 << 31), /* Last SGE in chain */
200 SGE_LNK
= (1 << 30), /* linked list
201 Points to SGT, not SGE */
202 SGE_DRD
= (1 << 29), /* discard data read (/dev/null)
203 data address ignored */
210 IRQ_STAT_4PORTS
= 0xf,
213 struct sil24_ata_block
{
214 struct sil24_prb prb
;
215 struct sil24_sge sge
[LIBATA_MAX_PRD
];
218 struct sil24_atapi_block
{
219 struct sil24_prb prb
;
221 struct sil24_sge sge
[LIBATA_MAX_PRD
- 1];
224 union sil24_cmd_block
{
225 struct sil24_ata_block ata
;
226 struct sil24_atapi_block atapi
;
232 * The preview driver always returned 0 for status. We emulate it
233 * here from the previous interrupt.
235 struct sil24_port_priv
{
236 union sil24_cmd_block
*cmd_block
; /* 32 cmd blocks */
237 dma_addr_t cmd_block_dma
; /* DMA base addr for them */
238 struct ata_taskfile tf
; /* Cached taskfile registers */
241 /* ap->host_set->private_data */
242 struct sil24_host_priv
{
243 void __iomem
*host_base
; /* global controller control (128 bytes @BAR0) */
244 void __iomem
*port_base
; /* port registers (4 * 8192 bytes @BAR2) */
247 static void sil24_dev_config(struct ata_port
*ap
, struct ata_device
*dev
);
248 static u8
sil24_check_status(struct ata_port
*ap
);
249 static u32
sil24_scr_read(struct ata_port
*ap
, unsigned sc_reg
);
250 static void sil24_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
);
251 static void sil24_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
252 static int sil24_probe_reset(struct ata_port
*ap
, unsigned int *classes
);
253 static void sil24_qc_prep(struct ata_queued_cmd
*qc
);
254 static unsigned int sil24_qc_issue(struct ata_queued_cmd
*qc
);
255 static void sil24_irq_clear(struct ata_port
*ap
);
256 static void sil24_eng_timeout(struct ata_port
*ap
);
257 static irqreturn_t
sil24_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
);
258 static int sil24_port_start(struct ata_port
*ap
);
259 static void sil24_port_stop(struct ata_port
*ap
);
260 static void sil24_host_stop(struct ata_host_set
*host_set
);
261 static int sil24_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
263 static const struct pci_device_id sil24_pci_tbl
[] = {
264 { 0x1095, 0x3124, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3124
},
265 { 0x8086, 0x3124, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3124
},
266 { 0x1095, 0x3132, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3132
},
267 { 0x1095, 0x3131, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3131
},
268 { 0x1095, 0x3531, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BID_SIL3131
},
269 { } /* terminate list */
272 static struct pci_driver sil24_pci_driver
= {
274 .id_table
= sil24_pci_tbl
,
275 .probe
= sil24_init_one
,
276 .remove
= ata_pci_remove_one
, /* safe? */
279 static struct scsi_host_template sil24_sht
= {
280 .module
= THIS_MODULE
,
282 .ioctl
= ata_scsi_ioctl
,
283 .queuecommand
= ata_scsi_queuecmd
,
284 .eh_timed_out
= ata_scsi_timed_out
,
285 .eh_strategy_handler
= ata_scsi_error
,
286 .can_queue
= ATA_DEF_QUEUE
,
287 .this_id
= ATA_SHT_THIS_ID
,
288 .sg_tablesize
= LIBATA_MAX_PRD
,
289 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
290 .emulated
= ATA_SHT_EMULATED
,
291 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
292 .proc_name
= DRV_NAME
,
293 .dma_boundary
= ATA_DMA_BOUNDARY
,
294 .slave_configure
= ata_scsi_slave_config
,
295 .bios_param
= ata_std_bios_param
,
298 static const struct ata_port_operations sil24_ops
= {
299 .port_disable
= ata_port_disable
,
301 .dev_config
= sil24_dev_config
,
303 .check_status
= sil24_check_status
,
304 .check_altstatus
= sil24_check_status
,
305 .dev_select
= ata_noop_dev_select
,
307 .tf_read
= sil24_tf_read
,
309 .probe_reset
= sil24_probe_reset
,
311 .qc_prep
= sil24_qc_prep
,
312 .qc_issue
= sil24_qc_issue
,
314 .eng_timeout
= sil24_eng_timeout
,
316 .irq_handler
= sil24_interrupt
,
317 .irq_clear
= sil24_irq_clear
,
319 .scr_read
= sil24_scr_read
,
320 .scr_write
= sil24_scr_write
,
322 .port_start
= sil24_port_start
,
323 .port_stop
= sil24_port_stop
,
324 .host_stop
= sil24_host_stop
,
328 * Use bits 30-31 of host_flags to encode available port numbers.
329 * Current maxium is 4.
331 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
332 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
334 static struct ata_port_info sil24_port_info
[] = {
338 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
339 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
340 SIL24_NPORTS2FLAG(4),
341 .pio_mask
= 0x1f, /* pio0-4 */
342 .mwdma_mask
= 0x07, /* mwdma0-2 */
343 .udma_mask
= 0x3f, /* udma0-5 */
344 .port_ops
= &sil24_ops
,
349 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
350 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
351 SIL24_NPORTS2FLAG(2),
352 .pio_mask
= 0x1f, /* pio0-4 */
353 .mwdma_mask
= 0x07, /* mwdma0-2 */
354 .udma_mask
= 0x3f, /* udma0-5 */
355 .port_ops
= &sil24_ops
,
357 /* sil_3131/sil_3531 */
360 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
361 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
362 SIL24_NPORTS2FLAG(1),
363 .pio_mask
= 0x1f, /* pio0-4 */
364 .mwdma_mask
= 0x07, /* mwdma0-2 */
365 .udma_mask
= 0x3f, /* udma0-5 */
366 .port_ops
= &sil24_ops
,
370 static void sil24_dev_config(struct ata_port
*ap
, struct ata_device
*dev
)
372 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
374 if (dev
->cdb_len
== 16)
375 writel(PORT_CS_CDB16
, port
+ PORT_CTRL_STAT
);
377 writel(PORT_CS_CDB16
, port
+ PORT_CTRL_CLR
);
380 static inline void sil24_update_tf(struct ata_port
*ap
)
382 struct sil24_port_priv
*pp
= ap
->private_data
;
383 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
384 struct sil24_prb __iomem
*prb
= port
;
387 memcpy_fromio(fis
, prb
->fis
, 6 * 4);
388 ata_tf_from_fis(fis
, &pp
->tf
);
391 static u8
sil24_check_status(struct ata_port
*ap
)
393 struct sil24_port_priv
*pp
= ap
->private_data
;
394 return pp
->tf
.command
;
397 static int sil24_scr_map
[] = {
404 static u32
sil24_scr_read(struct ata_port
*ap
, unsigned sc_reg
)
406 void __iomem
*scr_addr
= (void __iomem
*)ap
->ioaddr
.scr_addr
;
407 if (sc_reg
< ARRAY_SIZE(sil24_scr_map
)) {
409 addr
= scr_addr
+ sil24_scr_map
[sc_reg
] * 4;
410 return readl(scr_addr
+ sil24_scr_map
[sc_reg
] * 4);
415 static void sil24_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
)
417 void __iomem
*scr_addr
= (void __iomem
*)ap
->ioaddr
.scr_addr
;
418 if (sc_reg
< ARRAY_SIZE(sil24_scr_map
)) {
420 addr
= scr_addr
+ sil24_scr_map
[sc_reg
] * 4;
421 writel(val
, scr_addr
+ sil24_scr_map
[sc_reg
] * 4);
425 static void sil24_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
427 struct sil24_port_priv
*pp
= ap
->private_data
;
431 static int sil24_softreset(struct ata_port
*ap
, int verbose
,
434 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
435 struct sil24_port_priv
*pp
= ap
->private_data
;
436 struct sil24_prb
*prb
= &pp
->cmd_block
[0].ata
.prb
;
437 dma_addr_t paddr
= pp
->cmd_block_dma
;
438 unsigned long timeout
= jiffies
+ ATA_TMOUT_BOOT
* HZ
;
439 u32 irq_enable
, irq_stat
;
443 if (!sata_dev_present(ap
)) {
444 DPRINTK("PHY reports no device\n");
445 *class = ATA_DEV_NONE
;
449 /* temporarily turn off IRQs during SRST */
450 irq_enable
= readl(port
+ PORT_IRQ_ENABLE_SET
);
451 writel(irq_enable
, port
+ PORT_IRQ_ENABLE_CLR
);
454 * XXX: Not sure whether the following sleep is needed or not.
455 * The original driver had it. So....
459 prb
->ctrl
= PRB_CTRL_SRST
;
460 prb
->fis
[1] = 0; /* no PM yet */
462 writel((u32
)paddr
, port
+ PORT_CMD_ACTIVATE
);
465 irq_stat
= readl(port
+ PORT_IRQ_STAT
);
466 writel(irq_stat
, port
+ PORT_IRQ_STAT
); /* clear irq */
468 irq_stat
>>= PORT_IRQ_RAW_SHIFT
;
469 if (irq_stat
& (PORT_IRQ_COMPLETE
| PORT_IRQ_ERROR
))
473 } while (time_before(jiffies
, timeout
));
476 writel(irq_enable
, port
+ PORT_IRQ_ENABLE_SET
);
478 if (!(irq_stat
& PORT_IRQ_COMPLETE
)) {
479 DPRINTK("EXIT, srst failed\n");
484 *class = ata_dev_classify(&pp
->tf
);
486 if (*class == ATA_DEV_UNKNOWN
)
487 *class = ATA_DEV_NONE
;
490 DPRINTK("EXIT, class=%u\n", *class);
494 static int sil24_hardreset(struct ata_port
*ap
, int verbose
,
497 unsigned int dummy_class
;
499 /* sil24 doesn't report device signature after hard reset */
500 return sata_std_hardreset(ap
, verbose
, &dummy_class
);
503 static int sil24_probe_reset(struct ata_port
*ap
, unsigned int *classes
)
505 return ata_drive_probe_reset(ap
, ata_std_probeinit
,
506 sil24_softreset
, sil24_hardreset
,
507 ata_std_postreset
, classes
);
510 static inline void sil24_fill_sg(struct ata_queued_cmd
*qc
,
511 struct sil24_sge
*sge
)
513 struct scatterlist
*sg
;
514 unsigned int idx
= 0;
516 ata_for_each_sg(sg
, qc
) {
517 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
518 sge
->cnt
= cpu_to_le32(sg_dma_len(sg
));
519 if (ata_sg_is_last(sg
, qc
))
520 sge
->flags
= cpu_to_le32(SGE_TRM
);
529 static void sil24_qc_prep(struct ata_queued_cmd
*qc
)
531 struct ata_port
*ap
= qc
->ap
;
532 struct sil24_port_priv
*pp
= ap
->private_data
;
533 union sil24_cmd_block
*cb
= pp
->cmd_block
+ qc
->tag
;
534 struct sil24_prb
*prb
;
535 struct sil24_sge
*sge
;
537 switch (qc
->tf
.protocol
) {
540 case ATA_PROT_NODATA
:
547 case ATA_PROT_ATAPI_DMA
:
548 case ATA_PROT_ATAPI_NODATA
:
549 prb
= &cb
->atapi
.prb
;
551 memset(cb
->atapi
.cdb
, 0, 32);
552 memcpy(cb
->atapi
.cdb
, qc
->cdb
, qc
->dev
->cdb_len
);
554 if (qc
->tf
.protocol
!= ATA_PROT_ATAPI_NODATA
) {
555 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
556 prb
->ctrl
= PRB_CTRL_PACKET_WRITE
;
558 prb
->ctrl
= PRB_CTRL_PACKET_READ
;
565 prb
= NULL
; /* shut up, gcc */
570 ata_tf_to_fis(&qc
->tf
, prb
->fis
, 0);
572 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
573 sil24_fill_sg(qc
, sge
);
576 static unsigned int sil24_qc_issue(struct ata_queued_cmd
*qc
)
578 struct ata_port
*ap
= qc
->ap
;
579 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
580 struct sil24_port_priv
*pp
= ap
->private_data
;
581 dma_addr_t paddr
= pp
->cmd_block_dma
+ qc
->tag
* sizeof(*pp
->cmd_block
);
583 writel((u32
)paddr
, port
+ PORT_CMD_ACTIVATE
);
587 static void sil24_irq_clear(struct ata_port
*ap
)
592 static int __sil24_restart_controller(void __iomem
*port
)
597 writel(PORT_CS_INIT
, port
+ PORT_CTRL_STAT
);
600 for (cnt
= 0; cnt
< 10000; cnt
++) {
601 tmp
= readl(port
+ PORT_CTRL_STAT
);
602 if (tmp
& PORT_CS_RDY
)
610 static void sil24_restart_controller(struct ata_port
*ap
)
612 if (__sil24_restart_controller((void __iomem
*)ap
->ioaddr
.cmd_addr
))
613 printk(KERN_ERR DRV_NAME
614 " ata%u: failed to restart controller\n", ap
->id
);
617 static int __sil24_reset_controller(void __iomem
*port
)
622 /* Reset controller state. Is this correct? */
623 writel(PORT_CS_DEV_RST
, port
+ PORT_CTRL_STAT
);
624 readl(port
+ PORT_CTRL_STAT
); /* sync */
627 for (cnt
= 0; cnt
< 1000; cnt
++) {
629 tmp
= readl(port
+ PORT_CTRL_STAT
);
630 if (!(tmp
& PORT_CS_DEV_RST
))
634 if (tmp
& PORT_CS_DEV_RST
)
637 if (tmp
& PORT_CS_RDY
)
640 return __sil24_restart_controller(port
);
643 static void sil24_reset_controller(struct ata_port
*ap
)
645 printk(KERN_NOTICE DRV_NAME
646 " ata%u: resetting controller...\n", ap
->id
);
647 if (__sil24_reset_controller((void __iomem
*)ap
->ioaddr
.cmd_addr
))
648 printk(KERN_ERR DRV_NAME
649 " ata%u: failed to reset controller\n", ap
->id
);
652 static void sil24_eng_timeout(struct ata_port
*ap
)
654 struct ata_queued_cmd
*qc
;
656 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
658 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
659 qc
->err_mask
|= AC_ERR_TIMEOUT
;
660 ata_eh_qc_complete(qc
);
662 sil24_reset_controller(ap
);
665 static void sil24_error_intr(struct ata_port
*ap
, u32 slot_stat
)
667 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
668 struct sil24_port_priv
*pp
= ap
->private_data
;
669 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
670 u32 irq_stat
, cmd_err
, sstatus
, serror
;
671 unsigned int err_mask
;
673 irq_stat
= readl(port
+ PORT_IRQ_STAT
);
674 writel(irq_stat
, port
+ PORT_IRQ_STAT
); /* clear irq */
676 if (!(irq_stat
& PORT_IRQ_ERROR
)) {
677 /* ignore non-completion, non-error irqs for now */
678 printk(KERN_WARNING DRV_NAME
679 "ata%u: non-error exception irq (irq_stat %x)\n",
684 cmd_err
= readl(port
+ PORT_CMD_ERR
);
685 sstatus
= readl(port
+ PORT_SSTATUS
);
686 serror
= readl(port
+ PORT_SERROR
);
688 writel(serror
, port
+ PORT_SERROR
);
691 * Don't log ATAPI device errors. They're supposed to happen
692 * and any serious errors will be logged using sense data by
695 if (ap
->device
[0].class != ATA_DEV_ATAPI
|| cmd_err
> PORT_CERR_SDB
)
696 printk("ata%u: error interrupt on port%d\n"
697 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
698 ap
->id
, ap
->port_no
, slot_stat
, irq_stat
, cmd_err
, sstatus
, serror
);
700 if (cmd_err
== PORT_CERR_DEV
|| cmd_err
== PORT_CERR_SDB
) {
702 * Device is reporting error, tf registers are valid.
705 err_mask
= ac_err_mask(pp
->tf
.command
);
706 sil24_restart_controller(ap
);
709 * Other errors. libata currently doesn't have any
710 * mechanism to report these errors. Just turn on
713 err_mask
= AC_ERR_OTHER
;
714 sil24_reset_controller(ap
);
718 qc
->err_mask
|= err_mask
;
723 static inline void sil24_host_intr(struct ata_port
*ap
)
725 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
726 void __iomem
*port
= (void __iomem
*)ap
->ioaddr
.cmd_addr
;
729 slot_stat
= readl(port
+ PORT_SLOT_STAT
);
730 if (!(slot_stat
& HOST_SSTAT_ATTN
)) {
731 struct sil24_port_priv
*pp
= ap
->private_data
;
733 * !HOST_SSAT_ATTN guarantees successful completion,
734 * so reading back tf registers is unnecessary for
735 * most commands. TODO: read tf registers for
736 * commands which require these values on successful
737 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
738 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
743 qc
->err_mask
|= ac_err_mask(pp
->tf
.command
);
747 sil24_error_intr(ap
, slot_stat
);
750 static irqreturn_t
sil24_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
)
752 struct ata_host_set
*host_set
= dev_instance
;
753 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
754 unsigned handled
= 0;
758 status
= readl(hpriv
->host_base
+ HOST_IRQ_STAT
);
760 if (status
== 0xffffffff) {
761 printk(KERN_ERR DRV_NAME
": IRQ status == 0xffffffff, "
762 "PCI fault or device removal?\n");
766 if (!(status
& IRQ_STAT_4PORTS
))
769 spin_lock(&host_set
->lock
);
771 for (i
= 0; i
< host_set
->n_ports
; i
++)
772 if (status
& (1 << i
)) {
773 struct ata_port
*ap
= host_set
->ports
[i
];
774 if (ap
&& !(ap
->flags
& ATA_FLAG_PORT_DISABLED
)) {
775 sil24_host_intr(host_set
->ports
[i
]);
778 printk(KERN_ERR DRV_NAME
779 ": interrupt from disabled port %d\n", i
);
782 spin_unlock(&host_set
->lock
);
784 return IRQ_RETVAL(handled
);
787 static inline void sil24_cblk_free(struct sil24_port_priv
*pp
, struct device
*dev
)
789 const size_t cb_size
= sizeof(*pp
->cmd_block
);
791 dma_free_coherent(dev
, cb_size
, pp
->cmd_block
, pp
->cmd_block_dma
);
794 static int sil24_port_start(struct ata_port
*ap
)
796 struct device
*dev
= ap
->host_set
->dev
;
797 struct sil24_port_priv
*pp
;
798 union sil24_cmd_block
*cb
;
799 size_t cb_size
= sizeof(*cb
);
803 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
807 pp
->tf
.command
= ATA_DRDY
;
809 cb
= dma_alloc_coherent(dev
, cb_size
, &cb_dma
, GFP_KERNEL
);
812 memset(cb
, 0, cb_size
);
814 rc
= ata_pad_alloc(ap
, dev
);
819 pp
->cmd_block_dma
= cb_dma
;
821 ap
->private_data
= pp
;
826 sil24_cblk_free(pp
, dev
);
833 static void sil24_port_stop(struct ata_port
*ap
)
835 struct device
*dev
= ap
->host_set
->dev
;
836 struct sil24_port_priv
*pp
= ap
->private_data
;
838 sil24_cblk_free(pp
, dev
);
839 ata_pad_free(ap
, dev
);
843 static void sil24_host_stop(struct ata_host_set
*host_set
)
845 struct sil24_host_priv
*hpriv
= host_set
->private_data
;
847 iounmap(hpriv
->host_base
);
848 iounmap(hpriv
->port_base
);
852 static int sil24_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
854 static int printed_version
= 0;
855 unsigned int board_id
= (unsigned int)ent
->driver_data
;
856 struct ata_port_info
*pinfo
= &sil24_port_info
[board_id
];
857 struct ata_probe_ent
*probe_ent
= NULL
;
858 struct sil24_host_priv
*hpriv
= NULL
;
859 void __iomem
*host_base
= NULL
;
860 void __iomem
*port_base
= NULL
;
863 if (!printed_version
++)
864 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
866 rc
= pci_enable_device(pdev
);
870 rc
= pci_request_regions(pdev
, DRV_NAME
);
875 /* ioremap mmio registers */
876 host_base
= ioremap(pci_resource_start(pdev
, 0),
877 pci_resource_len(pdev
, 0));
880 port_base
= ioremap(pci_resource_start(pdev
, 2),
881 pci_resource_len(pdev
, 2));
885 /* allocate & init probe_ent and hpriv */
886 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
890 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
894 memset(probe_ent
, 0, sizeof(*probe_ent
));
895 probe_ent
->dev
= pci_dev_to_dev(pdev
);
896 INIT_LIST_HEAD(&probe_ent
->node
);
898 probe_ent
->sht
= pinfo
->sht
;
899 probe_ent
->host_flags
= pinfo
->host_flags
;
900 probe_ent
->pio_mask
= pinfo
->pio_mask
;
901 probe_ent
->mwdma_mask
= pinfo
->mwdma_mask
;
902 probe_ent
->udma_mask
= pinfo
->udma_mask
;
903 probe_ent
->port_ops
= pinfo
->port_ops
;
904 probe_ent
->n_ports
= SIL24_FLAG2NPORTS(pinfo
->host_flags
);
906 probe_ent
->irq
= pdev
->irq
;
907 probe_ent
->irq_flags
= SA_SHIRQ
;
908 probe_ent
->mmio_base
= port_base
;
909 probe_ent
->private_data
= hpriv
;
911 memset(hpriv
, 0, sizeof(*hpriv
));
912 hpriv
->host_base
= host_base
;
913 hpriv
->port_base
= port_base
;
916 * Configure the device
919 * FIXME: This device is certainly 64-bit capable. We just
920 * don't know how to use it. After fixing 32bit activation in
921 * this function, enable 64bit masks here.
923 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
925 dev_printk(KERN_ERR
, &pdev
->dev
,
926 "32-bit DMA enable failed\n");
929 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
931 dev_printk(KERN_ERR
, &pdev
->dev
,
932 "32-bit consistent DMA enable failed\n");
937 writel(0, host_base
+ HOST_FLASH_CMD
);
939 /* Mask interrupts during initialization */
940 writel(0, host_base
+ HOST_CTRL
);
942 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
943 void __iomem
*port
= port_base
+ i
* PORT_REGS_SIZE
;
944 unsigned long portu
= (unsigned long)port
;
948 probe_ent
->port
[i
].cmd_addr
= portu
+ PORT_PRB
;
949 probe_ent
->port
[i
].scr_addr
= portu
+ PORT_SCONTROL
;
951 ata_std_ports(&probe_ent
->port
[i
]);
953 /* Initial PHY setting */
954 writel(0x20c, port
+ PORT_PHY_CFG
);
957 tmp
= readl(port
+ PORT_CTRL_STAT
);
958 if (tmp
& PORT_CS_PORT_RST
) {
959 writel(PORT_CS_PORT_RST
, port
+ PORT_CTRL_CLR
);
960 readl(port
+ PORT_CTRL_STAT
); /* sync */
961 for (cnt
= 0; cnt
< 10; cnt
++) {
963 tmp
= readl(port
+ PORT_CTRL_STAT
);
964 if (!(tmp
& PORT_CS_PORT_RST
))
967 if (tmp
& PORT_CS_PORT_RST
)
968 dev_printk(KERN_ERR
, &pdev
->dev
,
969 "failed to clear port RST\n");
972 /* Zero error counters. */
973 writel(0x8000, port
+ PORT_DECODE_ERR_THRESH
);
974 writel(0x8000, port
+ PORT_CRC_ERR_THRESH
);
975 writel(0x8000, port
+ PORT_HSHK_ERR_THRESH
);
976 writel(0x0000, port
+ PORT_DECODE_ERR_CNT
);
977 writel(0x0000, port
+ PORT_CRC_ERR_CNT
);
978 writel(0x0000, port
+ PORT_HSHK_ERR_CNT
);
980 /* FIXME: 32bit activation? */
981 writel(0, port
+ PORT_ACTIVATE_UPPER_ADDR
);
982 writel(PORT_CS_32BIT_ACTV
, port
+ PORT_CTRL_STAT
);
984 /* Configure interrupts */
985 writel(0xffff, port
+ PORT_IRQ_ENABLE_CLR
);
986 writel(PORT_IRQ_COMPLETE
| PORT_IRQ_ERROR
| PORT_IRQ_SDB_FIS
,
987 port
+ PORT_IRQ_ENABLE_SET
);
989 /* Clear interrupts */
990 writel(0x0fff0fff, port
+ PORT_IRQ_STAT
);
991 writel(PORT_CS_IRQ_WOC
, port
+ PORT_CTRL_CLR
);
993 /* Clear port multiplier enable and resume bits */
994 writel(PORT_CS_PM_EN
| PORT_CS_RESUME
, port
+ PORT_CTRL_CLR
);
997 if (__sil24_reset_controller(port
))
998 dev_printk(KERN_ERR
, &pdev
->dev
,
999 "failed to reset controller\n");
1002 /* Turn on interrupts */
1003 writel(IRQ_STAT_4PORTS
, host_base
+ HOST_CTRL
);
1005 pci_set_master(pdev
);
1007 /* FIXME: check ata_device_add return value */
1008 ata_device_add(probe_ent
);
1020 pci_release_regions(pdev
);
1022 pci_disable_device(pdev
);
1026 static int __init
sil24_init(void)
1028 return pci_module_init(&sil24_pci_driver
);
1031 static void __exit
sil24_exit(void)
1033 pci_unregister_driver(&sil24_pci_driver
);
1036 MODULE_AUTHOR("Tejun Heo");
1037 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1038 MODULE_LICENSE("GPL");
1039 MODULE_DEVICE_TABLE(pci
, sil24_pci_tbl
);
1041 module_init(sil24_init
);
1042 module_exit(sil24_exit
);