2 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/time.h>
17 #include <linux/platform_device.h>
18 #include <linux/phy/phy.h>
19 #include <linux/reset-controller.h>
22 #include "ufshcd-pltfrm.h"
26 #include "ufs_quirks.h"
27 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
28 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
46 static struct ufs_qcom_host
*ufs_qcom_hosts
[MAX_UFS_QCOM_HOSTS
];
48 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host
*host
, int vote
);
49 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host
*host
);
50 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba
*hba
,
53 static struct ufs_qcom_host
*rcdev_to_ufs_host(struct reset_controller_dev
*rcd
)
55 return container_of(rcd
, struct ufs_qcom_host
, rcdev
);
58 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba
*hba
, int offset
, int len
,
59 const char *prefix
, void *priv
)
61 ufshcd_dump_regs(hba
, offset
, len
* 4, prefix
);
64 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba
*hba
, u32
*tx_lanes
)
68 err
= ufshcd_dme_get(hba
,
69 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES
), tx_lanes
);
71 dev_err(hba
->dev
, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
77 static int ufs_qcom_host_clk_get(struct device
*dev
,
78 const char *name
, struct clk
**clk_out
, bool optional
)
83 clk
= devm_clk_get(dev
, name
);
91 if (optional
&& err
== -ENOENT
) {
96 if (err
!= -EPROBE_DEFER
)
97 dev_err(dev
, "failed to get %s err %d\n", name
, err
);
102 static int ufs_qcom_host_clk_enable(struct device
*dev
,
103 const char *name
, struct clk
*clk
)
107 err
= clk_prepare_enable(clk
);
109 dev_err(dev
, "%s: %s enable failed %d\n", __func__
, name
, err
);
114 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host
*host
)
116 if (!host
->is_lane_clks_enabled
)
119 clk_disable_unprepare(host
->tx_l1_sync_clk
);
120 clk_disable_unprepare(host
->tx_l0_sync_clk
);
121 clk_disable_unprepare(host
->rx_l1_sync_clk
);
122 clk_disable_unprepare(host
->rx_l0_sync_clk
);
124 host
->is_lane_clks_enabled
= false;
127 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host
*host
)
130 struct device
*dev
= host
->hba
->dev
;
132 if (host
->is_lane_clks_enabled
)
135 err
= ufs_qcom_host_clk_enable(dev
, "rx_lane0_sync_clk",
136 host
->rx_l0_sync_clk
);
140 err
= ufs_qcom_host_clk_enable(dev
, "tx_lane0_sync_clk",
141 host
->tx_l0_sync_clk
);
145 err
= ufs_qcom_host_clk_enable(dev
, "rx_lane1_sync_clk",
146 host
->rx_l1_sync_clk
);
150 err
= ufs_qcom_host_clk_enable(dev
, "tx_lane1_sync_clk",
151 host
->tx_l1_sync_clk
);
155 host
->is_lane_clks_enabled
= true;
159 clk_disable_unprepare(host
->rx_l1_sync_clk
);
161 clk_disable_unprepare(host
->tx_l0_sync_clk
);
163 clk_disable_unprepare(host
->rx_l0_sync_clk
);
168 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host
*host
)
171 struct device
*dev
= host
->hba
->dev
;
173 err
= ufs_qcom_host_clk_get(dev
, "rx_lane0_sync_clk",
174 &host
->rx_l0_sync_clk
, false);
178 err
= ufs_qcom_host_clk_get(dev
, "tx_lane0_sync_clk",
179 &host
->tx_l0_sync_clk
, false);
183 /* In case of single lane per direction, don't read lane1 clocks */
184 if (host
->hba
->lanes_per_direction
> 1) {
185 err
= ufs_qcom_host_clk_get(dev
, "rx_lane1_sync_clk",
186 &host
->rx_l1_sync_clk
, false);
190 err
= ufs_qcom_host_clk_get(dev
, "tx_lane1_sync_clk",
191 &host
->tx_l1_sync_clk
, true);
197 static int ufs_qcom_link_startup_post_change(struct ufs_hba
*hba
)
201 return ufs_qcom_get_connected_tx_lanes(hba
, &tx_lanes
);
204 static int ufs_qcom_check_hibern8(struct ufs_hba
*hba
)
208 unsigned long timeout
= jiffies
+ msecs_to_jiffies(HBRN8_POLL_TOUT_MS
);
211 err
= ufshcd_dme_get(hba
,
212 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE
,
213 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
215 if (err
|| tx_fsm_val
== TX_FSM_HIBERN8
)
218 /* sleep for max. 200us */
219 usleep_range(100, 200);
220 } while (time_before(jiffies
, timeout
));
223 * we might have scheduled out for long during polling so
224 * check the state again.
226 if (time_after(jiffies
, timeout
))
227 err
= ufshcd_dme_get(hba
,
228 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE
,
229 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
233 dev_err(hba
->dev
, "%s: unable to get TX_FSM_STATE, err %d\n",
235 } else if (tx_fsm_val
!= TX_FSM_HIBERN8
) {
237 dev_err(hba
->dev
, "%s: invalid TX_FSM_STATE = %d\n",
244 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host
*host
)
246 ufshcd_rmwl(host
->hba
, QUNIPRO_SEL
,
247 ufs_qcom_cap_qunipro(host
) ? QUNIPRO_SEL
: 0,
249 /* make sure above configuration is applied before we return */
253 static int ufs_qcom_power_up_sequence(struct ufs_hba
*hba
)
255 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
256 struct phy
*phy
= host
->generic_phy
;
258 bool is_rate_B
= (UFS_QCOM_LIMIT_HS_RATE
== PA_HS_MODE_B
)
262 phy_set_mode(phy
, PHY_MODE_UFS_HS_B
);
264 /* phy initialization - calibrate the phy */
267 dev_err(hba
->dev
, "%s: phy init failed, ret = %d\n",
272 /* power on phy - start serdes and phy's power and clocks */
273 ret
= phy_power_on(phy
);
275 dev_err(hba
->dev
, "%s: phy power on failed, ret = %d\n",
277 goto out_disable_phy
;
280 ufs_qcom_select_unipro_mode(host
);
291 * The UTP controller has a number of internal clock gating cells (CGCs).
292 * Internal hardware sub-modules within the UTP controller control the CGCs.
293 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
294 * in a specific operation, UTP controller CGCs are by default disabled and
295 * this function enables them (after every UFS link startup) to save some power
298 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba
*hba
)
301 ufshcd_readl(hba
, REG_UFS_CFG2
) | REG_UFS_CFG2_CGC_EN_ALL
,
304 /* Ensure that HW clock gating is enabled before next operations */
308 static int ufs_qcom_hce_enable_notify(struct ufs_hba
*hba
,
309 enum ufs_notify_change_status status
)
311 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
316 ufs_qcom_power_up_sequence(hba
);
318 * The PHY PLL output is the source of tx/rx lane symbol
319 * clocks, hence, enable the lane clocks only after PHY
322 err
= ufs_qcom_enable_lane_clks(host
);
325 /* check if UFS PHY moved from DISABLED to HIBERN8 */
326 err
= ufs_qcom_check_hibern8(hba
);
327 ufs_qcom_enable_hw_clk_gating(hba
);
331 dev_err(hba
->dev
, "%s: invalid status %d\n", __func__
, status
);
339 * Returns zero for success and non-zero in case of a failure
341 static int ufs_qcom_cfg_timers(struct ufs_hba
*hba
, u32 gear
,
342 u32 hs
, u32 rate
, bool update_link_startup_timer
)
345 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
346 struct ufs_clk_info
*clki
;
347 u32 core_clk_period_in_ns
;
348 u32 tx_clk_cycles_per_us
= 0;
349 unsigned long core_clk_rate
= 0;
350 u32 core_clk_cycles_per_us
= 0;
352 static u32 pwm_fr_table
[][2] = {
359 static u32 hs_fr_table_rA
[][2] = {
365 static u32 hs_fr_table_rB
[][2] = {
372 * The Qunipro controller does not use following registers:
373 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
374 * UFS_REG_PA_LINK_STARTUP_TIMER
375 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
378 if (ufs_qcom_cap_qunipro(host
) && !ufshcd_is_intr_aggr_allowed(hba
))
382 dev_err(hba
->dev
, "%s: invalid gear = %d\n", __func__
, gear
);
386 list_for_each_entry(clki
, &hba
->clk_list_head
, list
) {
387 if (!strcmp(clki
->name
, "core_clk"))
388 core_clk_rate
= clk_get_rate(clki
->clk
);
391 /* If frequency is smaller than 1MHz, set to 1MHz */
392 if (core_clk_rate
< DEFAULT_CLK_RATE_HZ
)
393 core_clk_rate
= DEFAULT_CLK_RATE_HZ
;
395 core_clk_cycles_per_us
= core_clk_rate
/ USEC_PER_SEC
;
396 if (ufshcd_readl(hba
, REG_UFS_SYS1CLK_1US
) != core_clk_cycles_per_us
) {
397 ufshcd_writel(hba
, core_clk_cycles_per_us
, REG_UFS_SYS1CLK_1US
);
399 * make sure above write gets applied before we return from
405 if (ufs_qcom_cap_qunipro(host
))
408 core_clk_period_in_ns
= NSEC_PER_SEC
/ core_clk_rate
;
409 core_clk_period_in_ns
<<= OFFSET_CLK_NS_REG
;
410 core_clk_period_in_ns
&= MASK_CLK_NS_REG
;
415 if (rate
== PA_HS_MODE_A
) {
416 if (gear
> ARRAY_SIZE(hs_fr_table_rA
)) {
418 "%s: index %d exceeds table size %zu\n",
420 ARRAY_SIZE(hs_fr_table_rA
));
423 tx_clk_cycles_per_us
= hs_fr_table_rA
[gear
-1][1];
424 } else if (rate
== PA_HS_MODE_B
) {
425 if (gear
> ARRAY_SIZE(hs_fr_table_rB
)) {
427 "%s: index %d exceeds table size %zu\n",
429 ARRAY_SIZE(hs_fr_table_rB
));
432 tx_clk_cycles_per_us
= hs_fr_table_rB
[gear
-1][1];
434 dev_err(hba
->dev
, "%s: invalid rate = %d\n",
441 if (gear
> ARRAY_SIZE(pwm_fr_table
)) {
443 "%s: index %d exceeds table size %zu\n",
445 ARRAY_SIZE(pwm_fr_table
));
448 tx_clk_cycles_per_us
= pwm_fr_table
[gear
-1][1];
452 dev_err(hba
->dev
, "%s: invalid mode = %d\n", __func__
, hs
);
456 if (ufshcd_readl(hba
, REG_UFS_TX_SYMBOL_CLK_NS_US
) !=
457 (core_clk_period_in_ns
| tx_clk_cycles_per_us
)) {
458 /* this register 2 fields shall be written at once */
459 ufshcd_writel(hba
, core_clk_period_in_ns
| tx_clk_cycles_per_us
,
460 REG_UFS_TX_SYMBOL_CLK_NS_US
);
462 * make sure above write gets applied before we return from
468 if (update_link_startup_timer
) {
469 ufshcd_writel(hba
, ((core_clk_rate
/ MSEC_PER_SEC
) * 100),
470 REG_UFS_PA_LINK_STARTUP_TIMER
);
472 * make sure that this configuration is applied before
485 static int ufs_qcom_link_startup_notify(struct ufs_hba
*hba
,
486 enum ufs_notify_change_status status
)
489 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
493 if (ufs_qcom_cfg_timers(hba
, UFS_PWM_G1
, SLOWAUTO_MODE
,
495 dev_err(hba
->dev
, "%s: ufs_qcom_cfg_timers() failed\n",
501 if (ufs_qcom_cap_qunipro(host
))
503 * set unipro core clock cycles to 150 & clear clock
506 err
= ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba
,
510 * Some UFS devices (and may be host) have issues if LCC is
511 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
512 * before link startup which will make sure that both host
513 * and device TX LCC are disabled once link startup is
516 if (ufshcd_get_local_unipro_ver(hba
) != UFS_UNIPRO_VER_1_41
)
517 err
= ufshcd_dme_set(hba
,
518 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE
),
523 ufs_qcom_link_startup_post_change(hba
);
533 static int ufs_qcom_suspend(struct ufs_hba
*hba
, enum ufs_pm_op pm_op
)
535 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
536 struct phy
*phy
= host
->generic_phy
;
539 if (ufs_qcom_is_link_off(hba
)) {
541 * Disable the tx/rx lane symbol clocks before PHY is
542 * powered down as the PLL source should be disabled
543 * after downstream clocks are disabled.
545 ufs_qcom_disable_lane_clks(host
);
548 } else if (!ufs_qcom_is_link_active(hba
)) {
549 ufs_qcom_disable_lane_clks(host
);
555 static int ufs_qcom_resume(struct ufs_hba
*hba
, enum ufs_pm_op pm_op
)
557 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
558 struct phy
*phy
= host
->generic_phy
;
561 if (ufs_qcom_is_link_off(hba
)) {
562 err
= phy_power_on(phy
);
564 dev_err(hba
->dev
, "%s: failed PHY power on: %d\n",
569 err
= ufs_qcom_enable_lane_clks(host
);
573 } else if (!ufs_qcom_is_link_active(hba
)) {
574 err
= ufs_qcom_enable_lane_clks(host
);
579 hba
->is_sys_suspended
= false;
583 #ifdef CONFIG_MSM_BUS_SCALING
584 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host
*host
,
585 const char *speed_mode
)
587 struct device
*dev
= host
->hba
->dev
;
588 struct device_node
*np
= dev
->of_node
;
590 const char *key
= "qcom,bus-vector-names";
597 if (host
->bus_vote
.is_max_bw_needed
&& !!strcmp(speed_mode
, "MIN"))
598 err
= of_property_match_string(np
, key
, "MAX");
600 err
= of_property_match_string(np
, key
, speed_mode
);
604 dev_err(dev
, "%s: Invalid %s mode %d\n",
605 __func__
, speed_mode
, err
);
609 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr
*p
, char *result
)
611 int gear
= max_t(u32
, p
->gear_rx
, p
->gear_tx
);
612 int lanes
= max_t(u32
, p
->lane_rx
, p
->lane_tx
);
615 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
622 if (!p
->pwr_rx
&& !p
->pwr_tx
) {
624 snprintf(result
, BUS_VECTOR_NAME_LEN
, "MIN");
625 } else if (p
->pwr_rx
== FAST_MODE
|| p
->pwr_rx
== FASTAUTO_MODE
||
626 p
->pwr_tx
== FAST_MODE
|| p
->pwr_tx
== FASTAUTO_MODE
) {
628 snprintf(result
, BUS_VECTOR_NAME_LEN
, "%s_R%s_G%d_L%d", "HS",
629 p
->hs_rate
== PA_HS_MODE_B
? "B" : "A", gear
, lanes
);
632 snprintf(result
, BUS_VECTOR_NAME_LEN
, "%s_G%d_L%d",
637 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host
*host
, int vote
)
641 if (vote
!= host
->bus_vote
.curr_vote
) {
642 err
= msm_bus_scale_client_update_request(
643 host
->bus_vote
.client_handle
, vote
);
645 dev_err(host
->hba
->dev
,
646 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
647 __func__
, host
->bus_vote
.client_handle
,
652 host
->bus_vote
.curr_vote
= vote
;
658 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host
*host
)
662 char mode
[BUS_VECTOR_NAME_LEN
];
664 ufs_qcom_get_speed_mode(&host
->dev_req_params
, mode
);
666 vote
= ufs_qcom_get_bus_vote(host
, mode
);
668 err
= ufs_qcom_set_bus_vote(host
, vote
);
673 dev_err(host
->hba
->dev
, "%s: failed %d\n", __func__
, err
);
675 host
->bus_vote
.saved_vote
= vote
;
680 show_ufs_to_mem_max_bus_bw(struct device
*dev
, struct device_attribute
*attr
,
683 struct ufs_hba
*hba
= dev_get_drvdata(dev
);
684 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
686 return snprintf(buf
, PAGE_SIZE
, "%u\n",
687 host
->bus_vote
.is_max_bw_needed
);
691 store_ufs_to_mem_max_bus_bw(struct device
*dev
, struct device_attribute
*attr
,
692 const char *buf
, size_t count
)
694 struct ufs_hba
*hba
= dev_get_drvdata(dev
);
695 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
698 if (!kstrtou32(buf
, 0, &value
)) {
699 host
->bus_vote
.is_max_bw_needed
= !!value
;
700 ufs_qcom_update_bus_bw_vote(host
);
706 static int ufs_qcom_bus_register(struct ufs_qcom_host
*host
)
709 struct msm_bus_scale_pdata
*bus_pdata
;
710 struct device
*dev
= host
->hba
->dev
;
711 struct platform_device
*pdev
= to_platform_device(dev
);
712 struct device_node
*np
= dev
->of_node
;
714 bus_pdata
= msm_bus_cl_get_pdata(pdev
);
716 dev_err(dev
, "%s: failed to get bus vectors\n", __func__
);
721 err
= of_property_count_strings(np
, "qcom,bus-vector-names");
722 if (err
< 0 || err
!= bus_pdata
->num_usecases
) {
723 dev_err(dev
, "%s: qcom,bus-vector-names not specified correctly %d\n",
728 host
->bus_vote
.client_handle
= msm_bus_scale_register_client(bus_pdata
);
729 if (!host
->bus_vote
.client_handle
) {
730 dev_err(dev
, "%s: msm_bus_scale_register_client failed\n",
736 /* cache the vote index for minimum and maximum bandwidth */
737 host
->bus_vote
.min_bw_vote
= ufs_qcom_get_bus_vote(host
, "MIN");
738 host
->bus_vote
.max_bw_vote
= ufs_qcom_get_bus_vote(host
, "MAX");
740 host
->bus_vote
.max_bus_bw
.show
= show_ufs_to_mem_max_bus_bw
;
741 host
->bus_vote
.max_bus_bw
.store
= store_ufs_to_mem_max_bus_bw
;
742 sysfs_attr_init(&host
->bus_vote
.max_bus_bw
.attr
);
743 host
->bus_vote
.max_bus_bw
.attr
.name
= "max_bus_bw";
744 host
->bus_vote
.max_bus_bw
.attr
.mode
= S_IRUGO
| S_IWUSR
;
745 err
= device_create_file(dev
, &host
->bus_vote
.max_bus_bw
);
749 #else /* CONFIG_MSM_BUS_SCALING */
750 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host
*host
)
755 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host
*host
, int vote
)
760 static int ufs_qcom_bus_register(struct ufs_qcom_host
*host
)
764 #endif /* CONFIG_MSM_BUS_SCALING */
766 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host
*host
, bool enable
)
768 if (host
->dev_ref_clk_ctrl_mmio
&&
769 (enable
^ host
->is_dev_ref_clk_enabled
)) {
770 u32 temp
= readl_relaxed(host
->dev_ref_clk_ctrl_mmio
);
773 temp
|= host
->dev_ref_clk_en_mask
;
775 temp
&= ~host
->dev_ref_clk_en_mask
;
778 * If we are here to disable this clock it might be immediately
779 * after entering into hibern8 in which case we need to make
780 * sure that device ref_clk is active at least 1us after the
786 writel_relaxed(temp
, host
->dev_ref_clk_ctrl_mmio
);
788 /* ensure that ref_clk is enabled/disabled before we return */
792 * If we call hibern8 exit after this, we need to make sure that
793 * device ref_clk is stable for at least 1us before the hibern8
799 host
->is_dev_ref_clk_enabled
= enable
;
803 static int ufs_qcom_pwr_change_notify(struct ufs_hba
*hba
,
804 enum ufs_notify_change_status status
,
805 struct ufs_pa_layer_attr
*dev_max_params
,
806 struct ufs_pa_layer_attr
*dev_req_params
)
809 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
810 struct ufs_dev_params ufs_qcom_cap
;
813 if (!dev_req_params
) {
814 pr_err("%s: incoming dev_req_params is NULL\n", __func__
);
821 ufs_qcom_cap
.tx_lanes
= UFS_QCOM_LIMIT_NUM_LANES_TX
;
822 ufs_qcom_cap
.rx_lanes
= UFS_QCOM_LIMIT_NUM_LANES_RX
;
823 ufs_qcom_cap
.hs_rx_gear
= UFS_QCOM_LIMIT_HSGEAR_RX
;
824 ufs_qcom_cap
.hs_tx_gear
= UFS_QCOM_LIMIT_HSGEAR_TX
;
825 ufs_qcom_cap
.pwm_rx_gear
= UFS_QCOM_LIMIT_PWMGEAR_RX
;
826 ufs_qcom_cap
.pwm_tx_gear
= UFS_QCOM_LIMIT_PWMGEAR_TX
;
827 ufs_qcom_cap
.rx_pwr_pwm
= UFS_QCOM_LIMIT_RX_PWR_PWM
;
828 ufs_qcom_cap
.tx_pwr_pwm
= UFS_QCOM_LIMIT_TX_PWR_PWM
;
829 ufs_qcom_cap
.rx_pwr_hs
= UFS_QCOM_LIMIT_RX_PWR_HS
;
830 ufs_qcom_cap
.tx_pwr_hs
= UFS_QCOM_LIMIT_TX_PWR_HS
;
831 ufs_qcom_cap
.hs_rate
= UFS_QCOM_LIMIT_HS_RATE
;
832 ufs_qcom_cap
.desired_working_mode
=
833 UFS_QCOM_LIMIT_DESIRED_MODE
;
835 if (host
->hw_ver
.major
== 0x1) {
837 * HS-G3 operations may not reliably work on legacy QCOM
838 * UFS host controller hardware even though capability
839 * exchange during link startup phase may end up
840 * negotiating maximum supported gear as G3.
841 * Hence downgrade the maximum supported gear to HS-G2.
843 if (ufs_qcom_cap
.hs_tx_gear
> UFS_HS_G2
)
844 ufs_qcom_cap
.hs_tx_gear
= UFS_HS_G2
;
845 if (ufs_qcom_cap
.hs_rx_gear
> UFS_HS_G2
)
846 ufs_qcom_cap
.hs_rx_gear
= UFS_HS_G2
;
849 ret
= ufshcd_get_pwr_dev_param(&ufs_qcom_cap
,
853 pr_err("%s: failed to determine capabilities\n",
858 /* enable the device ref clock before changing to HS mode */
859 if (!ufshcd_is_hs_mode(&hba
->pwr_info
) &&
860 ufshcd_is_hs_mode(dev_req_params
))
861 ufs_qcom_dev_ref_clk_ctrl(host
, true);
864 if (ufs_qcom_cfg_timers(hba
, dev_req_params
->gear_rx
,
865 dev_req_params
->pwr_rx
,
866 dev_req_params
->hs_rate
, false)) {
867 dev_err(hba
->dev
, "%s: ufs_qcom_cfg_timers() failed\n",
870 * we return error code at the end of the routine,
871 * but continue to configure UFS_PHY_TX_LANE_ENABLE
872 * and bus voting as usual
877 val
= ~(MAX_U32
<< dev_req_params
->lane_tx
);
879 /* cache the power mode parameters to use internally */
880 memcpy(&host
->dev_req_params
,
881 dev_req_params
, sizeof(*dev_req_params
));
882 ufs_qcom_update_bus_bw_vote(host
);
884 /* disable the device ref clock if entered PWM mode */
885 if (ufshcd_is_hs_mode(&hba
->pwr_info
) &&
886 !ufshcd_is_hs_mode(dev_req_params
))
887 ufs_qcom_dev_ref_clk_ctrl(host
, false);
897 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba
*hba
)
900 u32 pa_vs_config_reg1
;
902 err
= ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_VS_CONFIG_REG1
),
907 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
908 err
= ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_VS_CONFIG_REG1
),
909 (pa_vs_config_reg1
| (1 << 12)));
915 static int ufs_qcom_apply_dev_quirks(struct ufs_hba
*hba
)
919 if (hba
->dev_quirks
& UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME
)
920 err
= ufs_qcom_quirk_host_pa_saveconfigtime(hba
);
925 static u32
ufs_qcom_get_ufs_hci_version(struct ufs_hba
*hba
)
927 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
929 if (host
->hw_ver
.major
== 0x1)
930 return UFSHCI_VERSION_11
;
932 return UFSHCI_VERSION_20
;
936 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
937 * @hba: host controller instance
939 * QCOM UFS host controller might have some non standard behaviours (quirks)
940 * than what is specified by UFSHCI specification. Advertise all such
941 * quirks to standard UFS host controller driver so standard takes them into
944 static void ufs_qcom_advertise_quirks(struct ufs_hba
*hba
)
946 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
948 if (host
->hw_ver
.major
== 0x01) {
949 hba
->quirks
|= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
950 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
951 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
;
953 if (host
->hw_ver
.minor
== 0x0001 && host
->hw_ver
.step
== 0x0001)
954 hba
->quirks
|= UFSHCD_QUIRK_BROKEN_INTR_AGGR
;
956 hba
->quirks
|= UFSHCD_QUIRK_BROKEN_LCC
;
959 if (host
->hw_ver
.major
== 0x2) {
960 hba
->quirks
|= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION
;
962 if (!ufs_qcom_cap_qunipro(host
))
963 /* Legacy UniPro mode still need following quirks */
964 hba
->quirks
|= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
965 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
966 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
);
970 static void ufs_qcom_set_caps(struct ufs_hba
*hba
)
972 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
974 hba
->caps
|= UFSHCD_CAP_CLK_GATING
| UFSHCD_CAP_HIBERN8_WITH_CLK_GATING
;
975 hba
->caps
|= UFSHCD_CAP_CLK_SCALING
;
976 hba
->caps
|= UFSHCD_CAP_AUTO_BKOPS_SUSPEND
;
978 if (host
->hw_ver
.major
>= 0x2) {
979 host
->caps
= UFS_QCOM_CAP_QUNIPRO
|
980 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE
;
985 * ufs_qcom_setup_clocks - enables/disable clocks
986 * @hba: host controller instance
987 * @on: If true, enable clocks else disable them.
988 * @status: PRE_CHANGE or POST_CHANGE notify
990 * Returns 0 on success, non-zero on failure.
992 static int ufs_qcom_setup_clocks(struct ufs_hba
*hba
, bool on
,
993 enum ufs_notify_change_status status
)
995 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
1000 * In case ufs_qcom_init() is not yet done, simply ignore.
1001 * This ufs_qcom_setup_clocks() shall be called from
1002 * ufs_qcom_init() after init is done.
1007 if (on
&& (status
== POST_CHANGE
)) {
1008 /* enable the device ref clock for HS mode*/
1009 if (ufshcd_is_hs_mode(&hba
->pwr_info
))
1010 ufs_qcom_dev_ref_clk_ctrl(host
, true);
1011 vote
= host
->bus_vote
.saved_vote
;
1012 if (vote
== host
->bus_vote
.min_bw_vote
)
1013 ufs_qcom_update_bus_bw_vote(host
);
1015 } else if (!on
&& (status
== PRE_CHANGE
)) {
1016 if (!ufs_qcom_is_link_active(hba
)) {
1017 /* disable device ref_clk */
1018 ufs_qcom_dev_ref_clk_ctrl(host
, false);
1021 vote
= host
->bus_vote
.min_bw_vote
;
1024 err
= ufs_qcom_set_bus_vote(host
, vote
);
1026 dev_err(hba
->dev
, "%s: set bus vote failed %d\n",
1033 ufs_qcom_reset_assert(struct reset_controller_dev
*rcdev
, unsigned long id
)
1035 struct ufs_qcom_host
*host
= rcdev_to_ufs_host(rcdev
);
1037 /* Currently this code only knows about a single reset. */
1039 ufs_qcom_assert_reset(host
->hba
);
1040 /* provide 1ms delay to let the reset pulse propagate. */
1041 usleep_range(1000, 1100);
1046 ufs_qcom_reset_deassert(struct reset_controller_dev
*rcdev
, unsigned long id
)
1048 struct ufs_qcom_host
*host
= rcdev_to_ufs_host(rcdev
);
1050 /* Currently this code only knows about a single reset. */
1052 ufs_qcom_deassert_reset(host
->hba
);
1055 * after reset deassertion, phy will need all ref clocks,
1056 * voltage, current to settle down before starting serdes.
1058 usleep_range(1000, 1100);
1062 static const struct reset_control_ops ufs_qcom_reset_ops
= {
1063 .assert = ufs_qcom_reset_assert
,
1064 .deassert
= ufs_qcom_reset_deassert
,
1067 #define ANDROID_BOOT_DEV_MAX 30
1068 static char android_boot_dev
[ANDROID_BOOT_DEV_MAX
];
1071 static int __init
get_android_boot_dev(char *str
)
1073 strlcpy(android_boot_dev
, str
, ANDROID_BOOT_DEV_MAX
);
1076 __setup("androidboot.bootdevice=", get_android_boot_dev
);
1080 * ufs_qcom_init - bind phy with controller
1081 * @hba: host controller instance
1083 * Binds PHY with controller and powers up PHY enabling clocks
1086 * Returns -EPROBE_DEFER if binding fails, returns negative error
1087 * on phy power up failure and returns zero on success.
1089 static int ufs_qcom_init(struct ufs_hba
*hba
)
1092 struct device
*dev
= hba
->dev
;
1093 struct platform_device
*pdev
= to_platform_device(dev
);
1094 struct ufs_qcom_host
*host
;
1095 struct resource
*res
;
1097 if (strlen(android_boot_dev
) && strcmp(android_boot_dev
, dev_name(dev
)))
1100 host
= devm_kzalloc(dev
, sizeof(*host
), GFP_KERNEL
);
1103 dev_err(dev
, "%s: no memory for qcom ufs host\n", __func__
);
1107 /* Make a two way bind between the qcom host and the hba */
1109 ufshcd_set_variant(hba
, host
);
1111 /* Fire up the reset controller. Failure here is non-fatal. */
1112 host
->rcdev
.of_node
= dev
->of_node
;
1113 host
->rcdev
.ops
= &ufs_qcom_reset_ops
;
1114 host
->rcdev
.owner
= dev
->driver
->owner
;
1115 host
->rcdev
.nr_resets
= 1;
1116 err
= devm_reset_controller_register(dev
, &host
->rcdev
);
1118 dev_warn(dev
, "Failed to register reset controller\n");
1123 * voting/devoting device ref_clk source is time consuming hence
1124 * skip devoting it during aggressive clock gating. This clock
1125 * will still be gated off during runtime suspend.
1127 host
->generic_phy
= devm_phy_get(dev
, "ufsphy");
1129 if (host
->generic_phy
== ERR_PTR(-EPROBE_DEFER
)) {
1131 * UFS driver might be probed before the phy driver does.
1132 * In that case we would like to return EPROBE_DEFER code.
1134 err
= -EPROBE_DEFER
;
1135 dev_warn(dev
, "%s: required phy device. hasn't probed yet. err = %d\n",
1137 goto out_variant_clear
;
1138 } else if (IS_ERR(host
->generic_phy
)) {
1139 err
= PTR_ERR(host
->generic_phy
);
1140 dev_err(dev
, "%s: PHY get failed %d\n", __func__
, err
);
1141 goto out_variant_clear
;
1144 err
= ufs_qcom_bus_register(host
);
1146 goto out_variant_clear
;
1148 ufs_qcom_get_controller_revision(hba
, &host
->hw_ver
.major
,
1149 &host
->hw_ver
.minor
, &host
->hw_ver
.step
);
1152 * for newer controllers, device reference clock control bit has
1153 * moved inside UFS controller register address space itself.
1155 if (host
->hw_ver
.major
>= 0x02) {
1156 host
->dev_ref_clk_ctrl_mmio
= hba
->mmio_base
+ REG_UFS_CFG1
;
1157 host
->dev_ref_clk_en_mask
= BIT(26);
1159 /* "dev_ref_clk_ctrl_mem" is optional resource */
1160 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1162 host
->dev_ref_clk_ctrl_mmio
=
1163 devm_ioremap_resource(dev
, res
);
1164 if (IS_ERR(host
->dev_ref_clk_ctrl_mmio
)) {
1166 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1168 PTR_ERR(host
->dev_ref_clk_ctrl_mmio
));
1169 host
->dev_ref_clk_ctrl_mmio
= NULL
;
1171 host
->dev_ref_clk_en_mask
= BIT(5);
1175 err
= ufs_qcom_init_lane_clks(host
);
1177 goto out_variant_clear
;
1179 ufs_qcom_set_caps(hba
);
1180 ufs_qcom_advertise_quirks(hba
);
1182 ufs_qcom_setup_clocks(hba
, true, POST_CHANGE
);
1184 if (hba
->dev
->id
< MAX_UFS_QCOM_HOSTS
)
1185 ufs_qcom_hosts
[hba
->dev
->id
] = host
;
1187 host
->dbg_print_en
|= UFS_QCOM_DEFAULT_DBG_PRINT_EN
;
1188 ufs_qcom_get_default_testbus_cfg(host
);
1189 err
= ufs_qcom_testbus_config(host
);
1191 dev_warn(dev
, "%s: failed to configure the testbus %d\n",
1199 ufshcd_set_variant(hba
, NULL
);
1204 static void ufs_qcom_exit(struct ufs_hba
*hba
)
1206 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
1208 ufs_qcom_disable_lane_clks(host
);
1209 phy_power_off(host
->generic_phy
);
1210 phy_exit(host
->generic_phy
);
1213 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba
*hba
,
1217 u32 core_clk_ctrl_reg
;
1219 if (clk_cycles
> DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK
)
1222 err
= ufshcd_dme_get(hba
,
1223 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL
),
1224 &core_clk_ctrl_reg
);
1228 core_clk_ctrl_reg
&= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK
;
1229 core_clk_ctrl_reg
|= clk_cycles
;
1231 /* Clear CORE_CLK_DIV_EN */
1232 core_clk_ctrl_reg
&= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT
;
1234 err
= ufshcd_dme_set(hba
,
1235 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL
),
1241 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba
*hba
)
1243 /* nothing to do as of now */
1247 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba
*hba
)
1249 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
1251 if (!ufs_qcom_cap_qunipro(host
))
1254 /* set unipro core clock cycles to 150 and clear clock divider */
1255 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba
, 150);
1258 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba
*hba
)
1260 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
1262 u32 core_clk_ctrl_reg
;
1264 if (!ufs_qcom_cap_qunipro(host
))
1267 err
= ufshcd_dme_get(hba
,
1268 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL
),
1269 &core_clk_ctrl_reg
);
1271 /* make sure CORE_CLK_DIV_EN is cleared */
1273 (core_clk_ctrl_reg
& DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT
)) {
1274 core_clk_ctrl_reg
&= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT
;
1275 err
= ufshcd_dme_set(hba
,
1276 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL
),
1283 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba
*hba
)
1285 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
1287 if (!ufs_qcom_cap_qunipro(host
))
1290 /* set unipro core clock cycles to 75 and clear clock divider */
1291 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba
, 75);
1294 static int ufs_qcom_clk_scale_notify(struct ufs_hba
*hba
,
1295 bool scale_up
, enum ufs_notify_change_status status
)
1297 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
1298 struct ufs_pa_layer_attr
*dev_req_params
= &host
->dev_req_params
;
1301 if (status
== PRE_CHANGE
) {
1303 err
= ufs_qcom_clk_scale_up_pre_change(hba
);
1305 err
= ufs_qcom_clk_scale_down_pre_change(hba
);
1308 err
= ufs_qcom_clk_scale_up_post_change(hba
);
1310 err
= ufs_qcom_clk_scale_down_post_change(hba
);
1312 if (err
|| !dev_req_params
)
1315 ufs_qcom_cfg_timers(hba
,
1316 dev_req_params
->gear_rx
,
1317 dev_req_params
->pwr_rx
,
1318 dev_req_params
->hs_rate
,
1320 ufs_qcom_update_bus_bw_vote(host
);
1327 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba
*hba
,
1328 void *priv
, void (*print_fn
)(struct ufs_hba
*hba
,
1329 int offset
, int num_regs
, const char *str
, void *priv
))
1332 struct ufs_qcom_host
*host
;
1334 if (unlikely(!hba
)) {
1335 pr_err("%s: hba is NULL\n", __func__
);
1338 if (unlikely(!print_fn
)) {
1339 dev_err(hba
->dev
, "%s: print_fn is NULL\n", __func__
);
1343 host
= ufshcd_get_variant(hba
);
1344 if (!(host
->dbg_print_en
& UFS_QCOM_DBG_PRINT_REGS_EN
))
1347 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_UFS_DBG_RD_REG_OCSC
);
1348 print_fn(hba
, reg
, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv
);
1350 reg
= ufshcd_readl(hba
, REG_UFS_CFG1
);
1351 reg
|= UTP_DBG_RAMS_EN
;
1352 ufshcd_writel(hba
, reg
, REG_UFS_CFG1
);
1354 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_UFS_DBG_RD_EDTL_RAM
);
1355 print_fn(hba
, reg
, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv
);
1357 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_UFS_DBG_RD_DESC_RAM
);
1358 print_fn(hba
, reg
, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv
);
1360 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_UFS_DBG_RD_PRDT_RAM
);
1361 print_fn(hba
, reg
, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv
);
1363 /* clear bit 17 - UTP_DBG_RAMS_EN */
1364 ufshcd_rmwl(hba
, UTP_DBG_RAMS_EN
, 0, REG_UFS_CFG1
);
1366 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_DBG_RD_REG_UAWM
);
1367 print_fn(hba
, reg
, 4, "UFS_DBG_RD_REG_UAWM ", priv
);
1369 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_DBG_RD_REG_UARM
);
1370 print_fn(hba
, reg
, 4, "UFS_DBG_RD_REG_UARM ", priv
);
1372 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_DBG_RD_REG_TXUC
);
1373 print_fn(hba
, reg
, 48, "UFS_DBG_RD_REG_TXUC ", priv
);
1375 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_DBG_RD_REG_RXUC
);
1376 print_fn(hba
, reg
, 27, "UFS_DBG_RD_REG_RXUC ", priv
);
1378 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_DBG_RD_REG_DFC
);
1379 print_fn(hba
, reg
, 19, "UFS_DBG_RD_REG_DFC ", priv
);
1381 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_DBG_RD_REG_TRLUT
);
1382 print_fn(hba
, reg
, 34, "UFS_DBG_RD_REG_TRLUT ", priv
);
1384 reg
= ufs_qcom_get_debug_reg_offset(host
, UFS_DBG_RD_REG_TMRLUT
);
1385 print_fn(hba
, reg
, 9, "UFS_DBG_RD_REG_TMRLUT ", priv
);
1388 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host
*host
)
1390 if (host
->dbg_print_en
& UFS_QCOM_DBG_PRINT_TEST_BUS_EN
) {
1391 ufshcd_rmwl(host
->hba
, UFS_REG_TEST_BUS_EN
,
1392 UFS_REG_TEST_BUS_EN
, REG_UFS_CFG1
);
1393 ufshcd_rmwl(host
->hba
, TEST_BUS_EN
, TEST_BUS_EN
, REG_UFS_CFG1
);
1395 ufshcd_rmwl(host
->hba
, UFS_REG_TEST_BUS_EN
, 0, REG_UFS_CFG1
);
1396 ufshcd_rmwl(host
->hba
, TEST_BUS_EN
, 0, REG_UFS_CFG1
);
1400 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host
*host
)
1402 /* provide a legal default configuration */
1403 host
->testbus
.select_major
= TSTBUS_UNIPRO
;
1404 host
->testbus
.select_minor
= 37;
1407 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host
*host
)
1409 if (host
->testbus
.select_major
>= TSTBUS_MAX
) {
1410 dev_err(host
->hba
->dev
,
1411 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1412 __func__
, host
->testbus
.select_major
);
1419 int ufs_qcom_testbus_config(struct ufs_qcom_host
*host
)
1423 u32 mask
= TEST_BUS_SUB_SEL_MASK
;
1428 if (!ufs_qcom_testbus_cfg_is_ok(host
))
1431 switch (host
->testbus
.select_major
) {
1433 reg
= UFS_TEST_BUS_CTRL_0
;
1437 reg
= UFS_TEST_BUS_CTRL_0
;
1441 reg
= UFS_TEST_BUS_CTRL_0
;
1445 reg
= UFS_TEST_BUS_CTRL_0
;
1449 reg
= UFS_TEST_BUS_CTRL_1
;
1453 reg
= UFS_TEST_BUS_CTRL_1
;
1457 reg
= UFS_TEST_BUS_CTRL_1
;
1461 reg
= UFS_TEST_BUS_CTRL_1
;
1464 case TSTBUS_WRAPPER
:
1465 reg
= UFS_TEST_BUS_CTRL_2
;
1468 case TSTBUS_COMBINED
:
1469 reg
= UFS_TEST_BUS_CTRL_2
;
1472 case TSTBUS_UTP_HCI
:
1473 reg
= UFS_TEST_BUS_CTRL_2
;
1477 reg
= UFS_UNIPRO_CFG
;
1482 * No need for a default case, since
1483 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1489 pm_runtime_get_sync(host
->hba
->dev
);
1490 ufshcd_hold(host
->hba
, false);
1491 ufshcd_rmwl(host
->hba
, TEST_BUS_SEL
,
1492 (u32
)host
->testbus
.select_major
<< 19,
1494 ufshcd_rmwl(host
->hba
, mask
,
1495 (u32
)host
->testbus
.select_minor
<< offset
,
1497 ufs_qcom_enable_test_bus(host
);
1499 * Make sure the test bus configuration is
1500 * committed before returning.
1503 ufshcd_release(host
->hba
);
1504 pm_runtime_put_sync(host
->hba
->dev
);
1509 static void ufs_qcom_testbus_read(struct ufs_hba
*hba
)
1511 ufshcd_dump_regs(hba
, UFS_TEST_BUS
, 4, "UFS_TEST_BUS ");
1514 static void ufs_qcom_print_unipro_testbus(struct ufs_hba
*hba
)
1516 struct ufs_qcom_host
*host
= ufshcd_get_variant(hba
);
1517 u32
*testbus
= NULL
;
1518 int i
, nminor
= 256, testbus_len
= nminor
* sizeof(u32
);
1520 testbus
= kmalloc(testbus_len
, GFP_KERNEL
);
1524 host
->testbus
.select_major
= TSTBUS_UNIPRO
;
1525 for (i
= 0; i
< nminor
; i
++) {
1526 host
->testbus
.select_minor
= i
;
1527 ufs_qcom_testbus_config(host
);
1528 testbus
[i
] = ufshcd_readl(hba
, UFS_TEST_BUS
);
1530 print_hex_dump(KERN_ERR
, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET
,
1531 16, 4, testbus
, testbus_len
, false);
1535 static void ufs_qcom_dump_dbg_regs(struct ufs_hba
*hba
)
1537 ufshcd_dump_regs(hba
, REG_UFS_SYS1CLK_1US
, 16 * 4,
1538 "HCI Vendor Specific Registers ");
1540 /* sleep a bit intermittently as we are dumping too much data */
1541 ufs_qcom_print_hw_debug_reg_all(hba
, NULL
, ufs_qcom_dump_regs_wrapper
);
1542 usleep_range(1000, 1100);
1543 ufs_qcom_testbus_read(hba
);
1544 usleep_range(1000, 1100);
1545 ufs_qcom_print_unipro_testbus(hba
);
1546 usleep_range(1000, 1100);
1550 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1552 * The variant operations configure the necessary controller and PHY
1553 * handshake during initialization.
1555 static struct ufs_hba_variant_ops ufs_hba_qcom_vops
= {
1557 .init
= ufs_qcom_init
,
1558 .exit
= ufs_qcom_exit
,
1559 .get_ufs_hci_version
= ufs_qcom_get_ufs_hci_version
,
1560 .clk_scale_notify
= ufs_qcom_clk_scale_notify
,
1561 .setup_clocks
= ufs_qcom_setup_clocks
,
1562 .hce_enable_notify
= ufs_qcom_hce_enable_notify
,
1563 .link_startup_notify
= ufs_qcom_link_startup_notify
,
1564 .pwr_change_notify
= ufs_qcom_pwr_change_notify
,
1565 .apply_dev_quirks
= ufs_qcom_apply_dev_quirks
,
1566 .suspend
= ufs_qcom_suspend
,
1567 .resume
= ufs_qcom_resume
,
1568 .dbg_register_dump
= ufs_qcom_dump_dbg_regs
,
1572 * ufs_qcom_probe - probe routine of the driver
1573 * @pdev: pointer to Platform device handle
1575 * Return zero for success and non-zero for failure
1577 static int ufs_qcom_probe(struct platform_device
*pdev
)
1580 struct device
*dev
= &pdev
->dev
;
1582 /* Perform generic probe */
1583 err
= ufshcd_pltfrm_init(pdev
, &ufs_hba_qcom_vops
);
1585 dev_err(dev
, "ufshcd_pltfrm_init() failed %d\n", err
);
1591 * ufs_qcom_remove - set driver_data of the device to NULL
1592 * @pdev: pointer to platform device handle
1596 static int ufs_qcom_remove(struct platform_device
*pdev
)
1598 struct ufs_hba
*hba
= platform_get_drvdata(pdev
);
1600 pm_runtime_get_sync(&(pdev
)->dev
);
1605 static const struct of_device_id ufs_qcom_of_match
[] = {
1606 { .compatible
= "qcom,ufshc"},
1609 MODULE_DEVICE_TABLE(of
, ufs_qcom_of_match
);
1611 static const struct dev_pm_ops ufs_qcom_pm_ops
= {
1612 .suspend
= ufshcd_pltfrm_suspend
,
1613 .resume
= ufshcd_pltfrm_resume
,
1614 .runtime_suspend
= ufshcd_pltfrm_runtime_suspend
,
1615 .runtime_resume
= ufshcd_pltfrm_runtime_resume
,
1616 .runtime_idle
= ufshcd_pltfrm_runtime_idle
,
1619 static struct platform_driver ufs_qcom_pltform
= {
1620 .probe
= ufs_qcom_probe
,
1621 .remove
= ufs_qcom_remove
,
1622 .shutdown
= ufshcd_pltfrm_shutdown
,
1624 .name
= "ufshcd-qcom",
1625 .pm
= &ufs_qcom_pm_ops
,
1626 .of_match_table
= of_match_ptr(ufs_qcom_of_match
),
1629 module_platform_driver(ufs_qcom_pltform
);
1631 MODULE_LICENSE("GPL v2");