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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / ufs / ufs-qcom.c
1 /*
2 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15 #include <linux/time.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/phy/phy.h>
19 #include <linux/phy/phy-qcom-ufs.h>
20
21 #include "ufshcd.h"
22 #include "ufshcd-pltfrm.h"
23 #include "unipro.h"
24 #include "ufs-qcom.h"
25 #include "ufshci.h"
26 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
27 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
28
29 enum {
30 TSTBUS_UAWM,
31 TSTBUS_UARM,
32 TSTBUS_TXUC,
33 TSTBUS_RXUC,
34 TSTBUS_DFC,
35 TSTBUS_TRLUT,
36 TSTBUS_TMRLUT,
37 TSTBUS_OCSC,
38 TSTBUS_UTP_HCI,
39 TSTBUS_COMBINED,
40 TSTBUS_WRAPPER,
41 TSTBUS_UNIPRO,
42 TSTBUS_MAX,
43 };
44
45 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
46
47 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
48 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
49 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
50 u32 clk_cycles);
51
52 static void ufs_qcom_dump_regs(struct ufs_hba *hba, int offset, int len,
53 char *prefix)
54 {
55 print_hex_dump(KERN_ERR, prefix,
56 len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,
57 16, 4, (void __force *)hba->mmio_base + offset,
58 len * 4, false);
59 }
60
61 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
62 char *prefix, void *priv)
63 {
64 ufs_qcom_dump_regs(hba, offset, len, prefix);
65 }
66
67 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
68 {
69 int err = 0;
70
71 err = ufshcd_dme_get(hba,
72 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
73 if (err)
74 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
75 __func__, err);
76
77 return err;
78 }
79
80 static int ufs_qcom_host_clk_get(struct device *dev,
81 const char *name, struct clk **clk_out)
82 {
83 struct clk *clk;
84 int err = 0;
85
86 clk = devm_clk_get(dev, name);
87 if (IS_ERR(clk)) {
88 err = PTR_ERR(clk);
89 dev_err(dev, "%s: failed to get %s err %d",
90 __func__, name, err);
91 } else {
92 *clk_out = clk;
93 }
94
95 return err;
96 }
97
98 static int ufs_qcom_host_clk_enable(struct device *dev,
99 const char *name, struct clk *clk)
100 {
101 int err = 0;
102
103 err = clk_prepare_enable(clk);
104 if (err)
105 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
106
107 return err;
108 }
109
110 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
111 {
112 if (!host->is_lane_clks_enabled)
113 return;
114
115 if (host->hba->lanes_per_direction > 1)
116 clk_disable_unprepare(host->tx_l1_sync_clk);
117 clk_disable_unprepare(host->tx_l0_sync_clk);
118 if (host->hba->lanes_per_direction > 1)
119 clk_disable_unprepare(host->rx_l1_sync_clk);
120 clk_disable_unprepare(host->rx_l0_sync_clk);
121
122 host->is_lane_clks_enabled = false;
123 }
124
125 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
126 {
127 int err = 0;
128 struct device *dev = host->hba->dev;
129
130 if (host->is_lane_clks_enabled)
131 return 0;
132
133 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
134 host->rx_l0_sync_clk);
135 if (err)
136 goto out;
137
138 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
139 host->tx_l0_sync_clk);
140 if (err)
141 goto disable_rx_l0;
142
143 if (host->hba->lanes_per_direction > 1) {
144 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
145 host->rx_l1_sync_clk);
146 if (err)
147 goto disable_tx_l0;
148
149 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
150 host->tx_l1_sync_clk);
151 if (err)
152 goto disable_rx_l1;
153 }
154
155 host->is_lane_clks_enabled = true;
156 goto out;
157
158 disable_rx_l1:
159 if (host->hba->lanes_per_direction > 1)
160 clk_disable_unprepare(host->rx_l1_sync_clk);
161 disable_tx_l0:
162 clk_disable_unprepare(host->tx_l0_sync_clk);
163 disable_rx_l0:
164 clk_disable_unprepare(host->rx_l0_sync_clk);
165 out:
166 return err;
167 }
168
169 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
170 {
171 int err = 0;
172 struct device *dev = host->hba->dev;
173
174 err = ufs_qcom_host_clk_get(dev,
175 "rx_lane0_sync_clk", &host->rx_l0_sync_clk);
176 if (err)
177 goto out;
178
179 err = ufs_qcom_host_clk_get(dev,
180 "tx_lane0_sync_clk", &host->tx_l0_sync_clk);
181 if (err)
182 goto out;
183
184 /* In case of single lane per direction, don't read lane1 clocks */
185 if (host->hba->lanes_per_direction > 1) {
186 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
187 &host->rx_l1_sync_clk);
188 if (err)
189 goto out;
190
191 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
192 &host->tx_l1_sync_clk);
193 }
194 out:
195 return err;
196 }
197
198 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
199 {
200 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
201 struct phy *phy = host->generic_phy;
202 u32 tx_lanes;
203 int err = 0;
204
205 err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
206 if (err)
207 goto out;
208
209 err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes);
210 if (err)
211 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n",
212 __func__);
213
214 out:
215 return err;
216 }
217
218 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
219 {
220 int err;
221 u32 tx_fsm_val = 0;
222 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
223
224 do {
225 err = ufshcd_dme_get(hba,
226 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
227 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
228 &tx_fsm_val);
229 if (err || tx_fsm_val == TX_FSM_HIBERN8)
230 break;
231
232 /* sleep for max. 200us */
233 usleep_range(100, 200);
234 } while (time_before(jiffies, timeout));
235
236 /*
237 * we might have scheduled out for long during polling so
238 * check the state again.
239 */
240 if (time_after(jiffies, timeout))
241 err = ufshcd_dme_get(hba,
242 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
243 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
244 &tx_fsm_val);
245
246 if (err) {
247 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
248 __func__, err);
249 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
250 err = tx_fsm_val;
251 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
252 __func__, err);
253 }
254
255 return err;
256 }
257
258 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
259 {
260 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
261 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
262 REG_UFS_CFG1);
263 /* make sure above configuration is applied before we return */
264 mb();
265 }
266
267 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
268 {
269 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
270 struct phy *phy = host->generic_phy;
271 int ret = 0;
272 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
273 ? true : false;
274
275 /* Assert PHY reset and apply PHY calibration values */
276 ufs_qcom_assert_reset(hba);
277 /* provide 1ms delay to let the reset pulse propagate */
278 usleep_range(1000, 1100);
279
280 ret = ufs_qcom_phy_calibrate_phy(phy, is_rate_B);
281
282 if (ret) {
283 dev_err(hba->dev, "%s: ufs_qcom_phy_calibrate_phy() failed, ret = %d\n",
284 __func__, ret);
285 goto out;
286 }
287
288 /* De-assert PHY reset and start serdes */
289 ufs_qcom_deassert_reset(hba);
290
291 /*
292 * after reset deassertion, phy will need all ref clocks,
293 * voltage, current to settle down before starting serdes.
294 */
295 usleep_range(1000, 1100);
296 ret = ufs_qcom_phy_start_serdes(phy);
297 if (ret) {
298 dev_err(hba->dev, "%s: ufs_qcom_phy_start_serdes() failed, ret = %d\n",
299 __func__, ret);
300 goto out;
301 }
302
303 ret = ufs_qcom_phy_is_pcs_ready(phy);
304 if (ret)
305 dev_err(hba->dev,
306 "%s: is_physical_coding_sublayer_ready() failed, ret = %d\n",
307 __func__, ret);
308
309 ufs_qcom_select_unipro_mode(host);
310
311 out:
312 return ret;
313 }
314
315 /*
316 * The UTP controller has a number of internal clock gating cells (CGCs).
317 * Internal hardware sub-modules within the UTP controller control the CGCs.
318 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
319 * in a specific operation, UTP controller CGCs are by default disabled and
320 * this function enables them (after every UFS link startup) to save some power
321 * leakage.
322 */
323 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
324 {
325 ufshcd_writel(hba,
326 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
327 REG_UFS_CFG2);
328
329 /* Ensure that HW clock gating is enabled before next operations */
330 mb();
331 }
332
333 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
334 enum ufs_notify_change_status status)
335 {
336 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
337 int err = 0;
338
339 switch (status) {
340 case PRE_CHANGE:
341 ufs_qcom_power_up_sequence(hba);
342 /*
343 * The PHY PLL output is the source of tx/rx lane symbol
344 * clocks, hence, enable the lane clocks only after PHY
345 * is initialized.
346 */
347 err = ufs_qcom_enable_lane_clks(host);
348 break;
349 case POST_CHANGE:
350 /* check if UFS PHY moved from DISABLED to HIBERN8 */
351 err = ufs_qcom_check_hibern8(hba);
352 ufs_qcom_enable_hw_clk_gating(hba);
353
354 break;
355 default:
356 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
357 err = -EINVAL;
358 break;
359 }
360 return err;
361 }
362
363 /**
364 * Returns zero for success and non-zero in case of a failure
365 */
366 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
367 u32 hs, u32 rate, bool update_link_startup_timer)
368 {
369 int ret = 0;
370 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
371 struct ufs_clk_info *clki;
372 u32 core_clk_period_in_ns;
373 u32 tx_clk_cycles_per_us = 0;
374 unsigned long core_clk_rate = 0;
375 u32 core_clk_cycles_per_us = 0;
376
377 static u32 pwm_fr_table[][2] = {
378 {UFS_PWM_G1, 0x1},
379 {UFS_PWM_G2, 0x1},
380 {UFS_PWM_G3, 0x1},
381 {UFS_PWM_G4, 0x1},
382 };
383
384 static u32 hs_fr_table_rA[][2] = {
385 {UFS_HS_G1, 0x1F},
386 {UFS_HS_G2, 0x3e},
387 {UFS_HS_G3, 0x7D},
388 };
389
390 static u32 hs_fr_table_rB[][2] = {
391 {UFS_HS_G1, 0x24},
392 {UFS_HS_G2, 0x49},
393 {UFS_HS_G3, 0x92},
394 };
395
396 /*
397 * The Qunipro controller does not use following registers:
398 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
399 * UFS_REG_PA_LINK_STARTUP_TIMER
400 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
401 * Aggregation logic.
402 */
403 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
404 goto out;
405
406 if (gear == 0) {
407 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
408 goto out_error;
409 }
410
411 list_for_each_entry(clki, &hba->clk_list_head, list) {
412 if (!strcmp(clki->name, "core_clk"))
413 core_clk_rate = clk_get_rate(clki->clk);
414 }
415
416 /* If frequency is smaller than 1MHz, set to 1MHz */
417 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
418 core_clk_rate = DEFAULT_CLK_RATE_HZ;
419
420 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
421 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
422 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
423 /*
424 * make sure above write gets applied before we return from
425 * this function.
426 */
427 mb();
428 }
429
430 if (ufs_qcom_cap_qunipro(host))
431 goto out;
432
433 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
434 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
435 core_clk_period_in_ns &= MASK_CLK_NS_REG;
436
437 switch (hs) {
438 case FASTAUTO_MODE:
439 case FAST_MODE:
440 if (rate == PA_HS_MODE_A) {
441 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
442 dev_err(hba->dev,
443 "%s: index %d exceeds table size %zu\n",
444 __func__, gear,
445 ARRAY_SIZE(hs_fr_table_rA));
446 goto out_error;
447 }
448 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
449 } else if (rate == PA_HS_MODE_B) {
450 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
451 dev_err(hba->dev,
452 "%s: index %d exceeds table size %zu\n",
453 __func__, gear,
454 ARRAY_SIZE(hs_fr_table_rB));
455 goto out_error;
456 }
457 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
458 } else {
459 dev_err(hba->dev, "%s: invalid rate = %d\n",
460 __func__, rate);
461 goto out_error;
462 }
463 break;
464 case SLOWAUTO_MODE:
465 case SLOW_MODE:
466 if (gear > ARRAY_SIZE(pwm_fr_table)) {
467 dev_err(hba->dev,
468 "%s: index %d exceeds table size %zu\n",
469 __func__, gear,
470 ARRAY_SIZE(pwm_fr_table));
471 goto out_error;
472 }
473 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
474 break;
475 case UNCHANGED:
476 default:
477 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
478 goto out_error;
479 }
480
481 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
482 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
483 /* this register 2 fields shall be written at once */
484 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
485 REG_UFS_TX_SYMBOL_CLK_NS_US);
486 /*
487 * make sure above write gets applied before we return from
488 * this function.
489 */
490 mb();
491 }
492
493 if (update_link_startup_timer) {
494 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
495 REG_UFS_PA_LINK_STARTUP_TIMER);
496 /*
497 * make sure that this configuration is applied before
498 * we return
499 */
500 mb();
501 }
502 goto out;
503
504 out_error:
505 ret = -EINVAL;
506 out:
507 return ret;
508 }
509
510 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
511 enum ufs_notify_change_status status)
512 {
513 int err = 0;
514 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
515
516 switch (status) {
517 case PRE_CHANGE:
518 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
519 0, true)) {
520 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
521 __func__);
522 err = -EINVAL;
523 goto out;
524 }
525
526 if (ufs_qcom_cap_qunipro(host))
527 /*
528 * set unipro core clock cycles to 150 & clear clock
529 * divider
530 */
531 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
532 150);
533
534 /*
535 * Some UFS devices (and may be host) have issues if LCC is
536 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
537 * before link startup which will make sure that both host
538 * and device TX LCC are disabled once link startup is
539 * completed.
540 */
541 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
542 err = ufshcd_dme_set(hba,
543 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
544 0);
545
546 break;
547 case POST_CHANGE:
548 ufs_qcom_link_startup_post_change(hba);
549 break;
550 default:
551 break;
552 }
553
554 out:
555 return err;
556 }
557
558 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
559 {
560 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
561 struct phy *phy = host->generic_phy;
562 int ret = 0;
563
564 if (ufs_qcom_is_link_off(hba)) {
565 /*
566 * Disable the tx/rx lane symbol clocks before PHY is
567 * powered down as the PLL source should be disabled
568 * after downstream clocks are disabled.
569 */
570 ufs_qcom_disable_lane_clks(host);
571 phy_power_off(phy);
572
573 /* Assert PHY soft reset */
574 ufs_qcom_assert_reset(hba);
575 goto out;
576 }
577
578 /*
579 * If UniPro link is not active, PHY ref_clk, main PHY analog power
580 * rail and low noise analog power rail for PLL can be switched off.
581 */
582 if (!ufs_qcom_is_link_active(hba)) {
583 ufs_qcom_disable_lane_clks(host);
584 phy_power_off(phy);
585 }
586
587 out:
588 return ret;
589 }
590
591 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
592 {
593 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
594 struct phy *phy = host->generic_phy;
595 int err;
596
597 err = phy_power_on(phy);
598 if (err) {
599 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
600 __func__, err);
601 goto out;
602 }
603
604 err = ufs_qcom_enable_lane_clks(host);
605 if (err)
606 goto out;
607
608 hba->is_sys_suspended = false;
609
610 out:
611 return err;
612 }
613
614 struct ufs_qcom_dev_params {
615 u32 pwm_rx_gear; /* pwm rx gear to work in */
616 u32 pwm_tx_gear; /* pwm tx gear to work in */
617 u32 hs_rx_gear; /* hs rx gear to work in */
618 u32 hs_tx_gear; /* hs tx gear to work in */
619 u32 rx_lanes; /* number of rx lanes */
620 u32 tx_lanes; /* number of tx lanes */
621 u32 rx_pwr_pwm; /* rx pwm working pwr */
622 u32 tx_pwr_pwm; /* tx pwm working pwr */
623 u32 rx_pwr_hs; /* rx hs working pwr */
624 u32 tx_pwr_hs; /* tx hs working pwr */
625 u32 hs_rate; /* rate A/B to work in HS */
626 u32 desired_working_mode;
627 };
628
629 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
630 struct ufs_pa_layer_attr *dev_max,
631 struct ufs_pa_layer_attr *agreed_pwr)
632 {
633 int min_qcom_gear;
634 int min_dev_gear;
635 bool is_dev_sup_hs = false;
636 bool is_qcom_max_hs = false;
637
638 if (dev_max->pwr_rx == FAST_MODE)
639 is_dev_sup_hs = true;
640
641 if (qcom_param->desired_working_mode == FAST) {
642 is_qcom_max_hs = true;
643 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
644 qcom_param->hs_tx_gear);
645 } else {
646 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
647 qcom_param->pwm_tx_gear);
648 }
649
650 /*
651 * device doesn't support HS but qcom_param->desired_working_mode is
652 * HS, thus device and qcom_param don't agree
653 */
654 if (!is_dev_sup_hs && is_qcom_max_hs) {
655 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
656 __func__);
657 return -ENOTSUPP;
658 } else if (is_dev_sup_hs && is_qcom_max_hs) {
659 /*
660 * since device supports HS, it supports FAST_MODE.
661 * since qcom_param->desired_working_mode is also HS
662 * then final decision (FAST/FASTAUTO) is done according
663 * to qcom_params as it is the restricting factor
664 */
665 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
666 qcom_param->rx_pwr_hs;
667 } else {
668 /*
669 * here qcom_param->desired_working_mode is PWM.
670 * it doesn't matter whether device supports HS or PWM,
671 * in both cases qcom_param->desired_working_mode will
672 * determine the mode
673 */
674 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
675 qcom_param->rx_pwr_pwm;
676 }
677
678 /*
679 * we would like tx to work in the minimum number of lanes
680 * between device capability and vendor preferences.
681 * the same decision will be made for rx
682 */
683 agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
684 qcom_param->tx_lanes);
685 agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
686 qcom_param->rx_lanes);
687
688 /* device maximum gear is the minimum between device rx and tx gears */
689 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
690
691 /*
692 * if both device capabilities and vendor pre-defined preferences are
693 * both HS or both PWM then set the minimum gear to be the chosen
694 * working gear.
695 * if one is PWM and one is HS then the one that is PWM get to decide
696 * what is the gear, as it is the one that also decided previously what
697 * pwr the device will be configured to.
698 */
699 if ((is_dev_sup_hs && is_qcom_max_hs) ||
700 (!is_dev_sup_hs && !is_qcom_max_hs))
701 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
702 min_t(u32, min_dev_gear, min_qcom_gear);
703 else if (!is_dev_sup_hs)
704 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
705 else
706 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
707
708 agreed_pwr->hs_rate = qcom_param->hs_rate;
709 return 0;
710 }
711
712 #ifdef CONFIG_MSM_BUS_SCALING
713 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
714 const char *speed_mode)
715 {
716 struct device *dev = host->hba->dev;
717 struct device_node *np = dev->of_node;
718 int err;
719 const char *key = "qcom,bus-vector-names";
720
721 if (!speed_mode) {
722 err = -EINVAL;
723 goto out;
724 }
725
726 if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
727 err = of_property_match_string(np, key, "MAX");
728 else
729 err = of_property_match_string(np, key, speed_mode);
730
731 out:
732 if (err < 0)
733 dev_err(dev, "%s: Invalid %s mode %d\n",
734 __func__, speed_mode, err);
735 return err;
736 }
737
738 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
739 {
740 int gear = max_t(u32, p->gear_rx, p->gear_tx);
741 int lanes = max_t(u32, p->lane_rx, p->lane_tx);
742 int pwr;
743
744 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
745 if (!gear)
746 gear = 1;
747
748 if (!lanes)
749 lanes = 1;
750
751 if (!p->pwr_rx && !p->pwr_tx) {
752 pwr = SLOWAUTO_MODE;
753 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
754 } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
755 p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
756 pwr = FAST_MODE;
757 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
758 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
759 } else {
760 pwr = SLOW_MODE;
761 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
762 "PWM", gear, lanes);
763 }
764 }
765
766 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
767 {
768 int err = 0;
769
770 if (vote != host->bus_vote.curr_vote) {
771 err = msm_bus_scale_client_update_request(
772 host->bus_vote.client_handle, vote);
773 if (err) {
774 dev_err(host->hba->dev,
775 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
776 __func__, host->bus_vote.client_handle,
777 vote, err);
778 goto out;
779 }
780
781 host->bus_vote.curr_vote = vote;
782 }
783 out:
784 return err;
785 }
786
787 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
788 {
789 int vote;
790 int err = 0;
791 char mode[BUS_VECTOR_NAME_LEN];
792
793 ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
794
795 vote = ufs_qcom_get_bus_vote(host, mode);
796 if (vote >= 0)
797 err = ufs_qcom_set_bus_vote(host, vote);
798 else
799 err = vote;
800
801 if (err)
802 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
803 else
804 host->bus_vote.saved_vote = vote;
805 return err;
806 }
807
808 static ssize_t
809 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
810 char *buf)
811 {
812 struct ufs_hba *hba = dev_get_drvdata(dev);
813 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
814
815 return snprintf(buf, PAGE_SIZE, "%u\n",
816 host->bus_vote.is_max_bw_needed);
817 }
818
819 static ssize_t
820 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
821 const char *buf, size_t count)
822 {
823 struct ufs_hba *hba = dev_get_drvdata(dev);
824 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
825 uint32_t value;
826
827 if (!kstrtou32(buf, 0, &value)) {
828 host->bus_vote.is_max_bw_needed = !!value;
829 ufs_qcom_update_bus_bw_vote(host);
830 }
831
832 return count;
833 }
834
835 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
836 {
837 int err;
838 struct msm_bus_scale_pdata *bus_pdata;
839 struct device *dev = host->hba->dev;
840 struct platform_device *pdev = to_platform_device(dev);
841 struct device_node *np = dev->of_node;
842
843 bus_pdata = msm_bus_cl_get_pdata(pdev);
844 if (!bus_pdata) {
845 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
846 err = -ENODATA;
847 goto out;
848 }
849
850 err = of_property_count_strings(np, "qcom,bus-vector-names");
851 if (err < 0 || err != bus_pdata->num_usecases) {
852 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
853 __func__, err);
854 goto out;
855 }
856
857 host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
858 if (!host->bus_vote.client_handle) {
859 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
860 __func__);
861 err = -EFAULT;
862 goto out;
863 }
864
865 /* cache the vote index for minimum and maximum bandwidth */
866 host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
867 host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
868
869 host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
870 host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
871 sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
872 host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
873 host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
874 err = device_create_file(dev, &host->bus_vote.max_bus_bw);
875 out:
876 return err;
877 }
878 #else /* CONFIG_MSM_BUS_SCALING */
879 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
880 {
881 return 0;
882 }
883
884 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
885 {
886 return 0;
887 }
888
889 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
890 {
891 return 0;
892 }
893 #endif /* CONFIG_MSM_BUS_SCALING */
894
895 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
896 {
897 if (host->dev_ref_clk_ctrl_mmio &&
898 (enable ^ host->is_dev_ref_clk_enabled)) {
899 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
900
901 if (enable)
902 temp |= host->dev_ref_clk_en_mask;
903 else
904 temp &= ~host->dev_ref_clk_en_mask;
905
906 /*
907 * If we are here to disable this clock it might be immediately
908 * after entering into hibern8 in which case we need to make
909 * sure that device ref_clk is active at least 1us after the
910 * hibern8 enter.
911 */
912 if (!enable)
913 udelay(1);
914
915 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
916
917 /* ensure that ref_clk is enabled/disabled before we return */
918 wmb();
919
920 /*
921 * If we call hibern8 exit after this, we need to make sure that
922 * device ref_clk is stable for at least 1us before the hibern8
923 * exit command.
924 */
925 if (enable)
926 udelay(1);
927
928 host->is_dev_ref_clk_enabled = enable;
929 }
930 }
931
932 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
933 enum ufs_notify_change_status status,
934 struct ufs_pa_layer_attr *dev_max_params,
935 struct ufs_pa_layer_attr *dev_req_params)
936 {
937 u32 val;
938 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
939 struct phy *phy = host->generic_phy;
940 struct ufs_qcom_dev_params ufs_qcom_cap;
941 int ret = 0;
942 int res = 0;
943
944 if (!dev_req_params) {
945 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
946 ret = -EINVAL;
947 goto out;
948 }
949
950 switch (status) {
951 case PRE_CHANGE:
952 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
953 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
954 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
955 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
956 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
957 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
958 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
959 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
960 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
961 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
962 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
963 ufs_qcom_cap.desired_working_mode =
964 UFS_QCOM_LIMIT_DESIRED_MODE;
965
966 if (host->hw_ver.major == 0x1) {
967 /*
968 * HS-G3 operations may not reliably work on legacy QCOM
969 * UFS host controller hardware even though capability
970 * exchange during link startup phase may end up
971 * negotiating maximum supported gear as G3.
972 * Hence downgrade the maximum supported gear to HS-G2.
973 */
974 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
975 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
976 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
977 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
978 }
979
980 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
981 dev_max_params,
982 dev_req_params);
983 if (ret) {
984 pr_err("%s: failed to determine capabilities\n",
985 __func__);
986 goto out;
987 }
988
989 /* enable the device ref clock before changing to HS mode */
990 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
991 ufshcd_is_hs_mode(dev_req_params))
992 ufs_qcom_dev_ref_clk_ctrl(host, true);
993 break;
994 case POST_CHANGE:
995 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
996 dev_req_params->pwr_rx,
997 dev_req_params->hs_rate, false)) {
998 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
999 __func__);
1000 /*
1001 * we return error code at the end of the routine,
1002 * but continue to configure UFS_PHY_TX_LANE_ENABLE
1003 * and bus voting as usual
1004 */
1005 ret = -EINVAL;
1006 }
1007
1008 val = ~(MAX_U32 << dev_req_params->lane_tx);
1009 res = ufs_qcom_phy_set_tx_lane_enable(phy, val);
1010 if (res) {
1011 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable() failed res = %d\n",
1012 __func__, res);
1013 ret = res;
1014 }
1015
1016 /* cache the power mode parameters to use internally */
1017 memcpy(&host->dev_req_params,
1018 dev_req_params, sizeof(*dev_req_params));
1019 ufs_qcom_update_bus_bw_vote(host);
1020
1021 /* disable the device ref clock if entered PWM mode */
1022 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
1023 !ufshcd_is_hs_mode(dev_req_params))
1024 ufs_qcom_dev_ref_clk_ctrl(host, false);
1025 break;
1026 default:
1027 ret = -EINVAL;
1028 break;
1029 }
1030 out:
1031 return ret;
1032 }
1033
1034 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1035 {
1036 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1037
1038 if (host->hw_ver.major == 0x1)
1039 return UFSHCI_VERSION_11;
1040 else
1041 return UFSHCI_VERSION_20;
1042 }
1043
1044 /**
1045 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1046 * @hba: host controller instance
1047 *
1048 * QCOM UFS host controller might have some non standard behaviours (quirks)
1049 * than what is specified by UFSHCI specification. Advertise all such
1050 * quirks to standard UFS host controller driver so standard takes them into
1051 * account.
1052 */
1053 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1054 {
1055 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1056
1057 if (host->hw_ver.major == 0x01) {
1058 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1059 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1060 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1061
1062 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1063 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1064
1065 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1066 }
1067
1068 if (host->hw_ver.major >= 0x2) {
1069 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1070
1071 if (!ufs_qcom_cap_qunipro(host))
1072 /* Legacy UniPro mode still need following quirks */
1073 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1074 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1075 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1076 }
1077 }
1078
1079 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1080 {
1081 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1082
1083 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1084 hba->caps |= UFSHCD_CAP_CLK_SCALING;
1085 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1086
1087 if (host->hw_ver.major >= 0x2) {
1088 host->caps = UFS_QCOM_CAP_QUNIPRO |
1089 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1090 }
1091 }
1092
1093 /**
1094 * ufs_qcom_setup_clocks - enables/disable clocks
1095 * @hba: host controller instance
1096 * @on: If true, enable clocks else disable them.
1097 *
1098 * Returns 0 on success, non-zero on failure.
1099 */
1100 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on)
1101 {
1102 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1103 int err;
1104 int vote = 0;
1105
1106 /*
1107 * In case ufs_qcom_init() is not yet done, simply ignore.
1108 * This ufs_qcom_setup_clocks() shall be called from
1109 * ufs_qcom_init() after init is done.
1110 */
1111 if (!host)
1112 return 0;
1113
1114 if (on) {
1115 err = ufs_qcom_phy_enable_iface_clk(host->generic_phy);
1116 if (err)
1117 goto out;
1118
1119 err = ufs_qcom_phy_enable_ref_clk(host->generic_phy);
1120 if (err) {
1121 dev_err(hba->dev, "%s enable phy ref clock failed, err=%d\n",
1122 __func__, err);
1123 ufs_qcom_phy_disable_iface_clk(host->generic_phy);
1124 goto out;
1125 }
1126 /* enable the device ref clock for HS mode*/
1127 if (ufshcd_is_hs_mode(&hba->pwr_info))
1128 ufs_qcom_dev_ref_clk_ctrl(host, true);
1129 vote = host->bus_vote.saved_vote;
1130 if (vote == host->bus_vote.min_bw_vote)
1131 ufs_qcom_update_bus_bw_vote(host);
1132
1133 } else {
1134
1135 /* M-PHY RMMI interface clocks can be turned off */
1136 ufs_qcom_phy_disable_iface_clk(host->generic_phy);
1137 if (!ufs_qcom_is_link_active(hba))
1138 /* disable device ref_clk */
1139 ufs_qcom_dev_ref_clk_ctrl(host, false);
1140
1141 vote = host->bus_vote.min_bw_vote;
1142 }
1143
1144 err = ufs_qcom_set_bus_vote(host, vote);
1145 if (err)
1146 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1147 __func__, err);
1148
1149 out:
1150 return err;
1151 }
1152
1153 #define ANDROID_BOOT_DEV_MAX 30
1154 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1155
1156 #ifndef MODULE
1157 static int __init get_android_boot_dev(char *str)
1158 {
1159 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1160 return 1;
1161 }
1162 __setup("androidboot.bootdevice=", get_android_boot_dev);
1163 #endif
1164
1165 /**
1166 * ufs_qcom_init - bind phy with controller
1167 * @hba: host controller instance
1168 *
1169 * Binds PHY with controller and powers up PHY enabling clocks
1170 * and regulators.
1171 *
1172 * Returns -EPROBE_DEFER if binding fails, returns negative error
1173 * on phy power up failure and returns zero on success.
1174 */
1175 static int ufs_qcom_init(struct ufs_hba *hba)
1176 {
1177 int err;
1178 struct device *dev = hba->dev;
1179 struct platform_device *pdev = to_platform_device(dev);
1180 struct ufs_qcom_host *host;
1181 struct resource *res;
1182
1183 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1184 return -ENODEV;
1185
1186 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1187 if (!host) {
1188 err = -ENOMEM;
1189 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1190 goto out;
1191 }
1192
1193 /* Make a two way bind between the qcom host and the hba */
1194 host->hba = hba;
1195 ufshcd_set_variant(hba, host);
1196
1197 /*
1198 * voting/devoting device ref_clk source is time consuming hence
1199 * skip devoting it during aggressive clock gating. This clock
1200 * will still be gated off during runtime suspend.
1201 */
1202 host->generic_phy = devm_phy_get(dev, "ufsphy");
1203
1204 if (IS_ERR(host->generic_phy)) {
1205 err = PTR_ERR(host->generic_phy);
1206 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1207 goto out;
1208 }
1209
1210 err = ufs_qcom_bus_register(host);
1211 if (err)
1212 goto out_host_free;
1213
1214 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1215 &host->hw_ver.minor, &host->hw_ver.step);
1216
1217 /*
1218 * for newer controllers, device reference clock control bit has
1219 * moved inside UFS controller register address space itself.
1220 */
1221 if (host->hw_ver.major >= 0x02) {
1222 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1223 host->dev_ref_clk_en_mask = BIT(26);
1224 } else {
1225 /* "dev_ref_clk_ctrl_mem" is optional resource */
1226 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1227 if (res) {
1228 host->dev_ref_clk_ctrl_mmio =
1229 devm_ioremap_resource(dev, res);
1230 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1231 dev_warn(dev,
1232 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1233 __func__,
1234 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1235 host->dev_ref_clk_ctrl_mmio = NULL;
1236 }
1237 host->dev_ref_clk_en_mask = BIT(5);
1238 }
1239 }
1240
1241 /* update phy revision information before calling phy_init() */
1242 ufs_qcom_phy_save_controller_version(host->generic_phy,
1243 host->hw_ver.major, host->hw_ver.minor, host->hw_ver.step);
1244
1245 phy_init(host->generic_phy);
1246 err = phy_power_on(host->generic_phy);
1247 if (err)
1248 goto out_unregister_bus;
1249
1250 err = ufs_qcom_init_lane_clks(host);
1251 if (err)
1252 goto out_disable_phy;
1253
1254 ufs_qcom_set_caps(hba);
1255 ufs_qcom_advertise_quirks(hba);
1256
1257 ufs_qcom_setup_clocks(hba, true);
1258
1259 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1260 ufs_qcom_hosts[hba->dev->id] = host;
1261
1262 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1263 ufs_qcom_get_default_testbus_cfg(host);
1264 err = ufs_qcom_testbus_config(host);
1265 if (err) {
1266 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1267 __func__, err);
1268 err = 0;
1269 }
1270
1271 goto out;
1272
1273 out_disable_phy:
1274 phy_power_off(host->generic_phy);
1275 out_unregister_bus:
1276 phy_exit(host->generic_phy);
1277 out_host_free:
1278 devm_kfree(dev, host);
1279 ufshcd_set_variant(hba, NULL);
1280 out:
1281 return err;
1282 }
1283
1284 static void ufs_qcom_exit(struct ufs_hba *hba)
1285 {
1286 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1287
1288 ufs_qcom_disable_lane_clks(host);
1289 phy_power_off(host->generic_phy);
1290 }
1291
1292 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1293 u32 clk_cycles)
1294 {
1295 int err;
1296 u32 core_clk_ctrl_reg;
1297
1298 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1299 return -EINVAL;
1300
1301 err = ufshcd_dme_get(hba,
1302 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1303 &core_clk_ctrl_reg);
1304 if (err)
1305 goto out;
1306
1307 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1308 core_clk_ctrl_reg |= clk_cycles;
1309
1310 /* Clear CORE_CLK_DIV_EN */
1311 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1312
1313 err = ufshcd_dme_set(hba,
1314 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1315 core_clk_ctrl_reg);
1316 out:
1317 return err;
1318 }
1319
1320 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1321 {
1322 /* nothing to do as of now */
1323 return 0;
1324 }
1325
1326 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1327 {
1328 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1329
1330 if (!ufs_qcom_cap_qunipro(host))
1331 return 0;
1332
1333 /* set unipro core clock cycles to 150 and clear clock divider */
1334 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1335 }
1336
1337 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1338 {
1339 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1340 int err;
1341 u32 core_clk_ctrl_reg;
1342
1343 if (!ufs_qcom_cap_qunipro(host))
1344 return 0;
1345
1346 err = ufshcd_dme_get(hba,
1347 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1348 &core_clk_ctrl_reg);
1349
1350 /* make sure CORE_CLK_DIV_EN is cleared */
1351 if (!err &&
1352 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1353 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1354 err = ufshcd_dme_set(hba,
1355 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1356 core_clk_ctrl_reg);
1357 }
1358
1359 return err;
1360 }
1361
1362 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1363 {
1364 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1365
1366 if (!ufs_qcom_cap_qunipro(host))
1367 return 0;
1368
1369 /* set unipro core clock cycles to 75 and clear clock divider */
1370 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1371 }
1372
1373 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1374 bool scale_up, enum ufs_notify_change_status status)
1375 {
1376 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1377 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1378 int err = 0;
1379
1380 if (status == PRE_CHANGE) {
1381 if (scale_up)
1382 err = ufs_qcom_clk_scale_up_pre_change(hba);
1383 else
1384 err = ufs_qcom_clk_scale_down_pre_change(hba);
1385 } else {
1386 if (scale_up)
1387 err = ufs_qcom_clk_scale_up_post_change(hba);
1388 else
1389 err = ufs_qcom_clk_scale_down_post_change(hba);
1390
1391 if (err || !dev_req_params)
1392 goto out;
1393
1394 ufs_qcom_cfg_timers(hba,
1395 dev_req_params->gear_rx,
1396 dev_req_params->pwr_rx,
1397 dev_req_params->hs_rate,
1398 false);
1399 ufs_qcom_update_bus_bw_vote(host);
1400 }
1401
1402 out:
1403 return err;
1404 }
1405
1406 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1407 void *priv, void (*print_fn)(struct ufs_hba *hba,
1408 int offset, int num_regs, char *str, void *priv))
1409 {
1410 u32 reg;
1411 struct ufs_qcom_host *host;
1412
1413 if (unlikely(!hba)) {
1414 pr_err("%s: hba is NULL\n", __func__);
1415 return;
1416 }
1417 if (unlikely(!print_fn)) {
1418 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1419 return;
1420 }
1421
1422 host = ufshcd_get_variant(hba);
1423 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1424 return;
1425
1426 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1427 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1428
1429 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1430 reg |= UFS_BIT(17);
1431 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1432
1433 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1434 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1435
1436 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1437 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1438
1439 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1440 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1441
1442 ufshcd_writel(hba, (reg & ~UFS_BIT(17)), REG_UFS_CFG1);
1443
1444 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1445 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1446
1447 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1448 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1449
1450 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1451 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1452
1453 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1454 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1455
1456 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1457 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1458
1459 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1460 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1461
1462 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1463 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1464 }
1465
1466 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1467 {
1468 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
1469 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1470 else
1471 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1472 }
1473
1474 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1475 {
1476 /* provide a legal default configuration */
1477 host->testbus.select_major = TSTBUS_UAWM;
1478 host->testbus.select_minor = 1;
1479 }
1480
1481 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1482 {
1483 if (host->testbus.select_major >= TSTBUS_MAX) {
1484 dev_err(host->hba->dev,
1485 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1486 __func__, host->testbus.select_major);
1487 return false;
1488 }
1489
1490 /*
1491 * Not performing check for each individual select_major
1492 * mappings of select_minor, since there is no harm in
1493 * configuring a non-existent select_minor
1494 */
1495 if (host->testbus.select_minor > 0x1F) {
1496 dev_err(host->hba->dev,
1497 "%s: 0x%05X is not a legal testbus option\n",
1498 __func__, host->testbus.select_minor);
1499 return false;
1500 }
1501
1502 return true;
1503 }
1504
1505 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1506 {
1507 int reg;
1508 int offset;
1509 u32 mask = TEST_BUS_SUB_SEL_MASK;
1510
1511 if (!host)
1512 return -EINVAL;
1513
1514 if (!ufs_qcom_testbus_cfg_is_ok(host))
1515 return -EPERM;
1516
1517 switch (host->testbus.select_major) {
1518 case TSTBUS_UAWM:
1519 reg = UFS_TEST_BUS_CTRL_0;
1520 offset = 24;
1521 break;
1522 case TSTBUS_UARM:
1523 reg = UFS_TEST_BUS_CTRL_0;
1524 offset = 16;
1525 break;
1526 case TSTBUS_TXUC:
1527 reg = UFS_TEST_BUS_CTRL_0;
1528 offset = 8;
1529 break;
1530 case TSTBUS_RXUC:
1531 reg = UFS_TEST_BUS_CTRL_0;
1532 offset = 0;
1533 break;
1534 case TSTBUS_DFC:
1535 reg = UFS_TEST_BUS_CTRL_1;
1536 offset = 24;
1537 break;
1538 case TSTBUS_TRLUT:
1539 reg = UFS_TEST_BUS_CTRL_1;
1540 offset = 16;
1541 break;
1542 case TSTBUS_TMRLUT:
1543 reg = UFS_TEST_BUS_CTRL_1;
1544 offset = 8;
1545 break;
1546 case TSTBUS_OCSC:
1547 reg = UFS_TEST_BUS_CTRL_1;
1548 offset = 0;
1549 break;
1550 case TSTBUS_WRAPPER:
1551 reg = UFS_TEST_BUS_CTRL_2;
1552 offset = 16;
1553 break;
1554 case TSTBUS_COMBINED:
1555 reg = UFS_TEST_BUS_CTRL_2;
1556 offset = 8;
1557 break;
1558 case TSTBUS_UTP_HCI:
1559 reg = UFS_TEST_BUS_CTRL_2;
1560 offset = 0;
1561 break;
1562 case TSTBUS_UNIPRO:
1563 reg = UFS_UNIPRO_CFG;
1564 offset = 1;
1565 break;
1566 /*
1567 * No need for a default case, since
1568 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1569 * is legal
1570 */
1571 }
1572 mask <<= offset;
1573
1574 pm_runtime_get_sync(host->hba->dev);
1575 ufshcd_hold(host->hba, false);
1576 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1577 (u32)host->testbus.select_major << 19,
1578 REG_UFS_CFG1);
1579 ufshcd_rmwl(host->hba, mask,
1580 (u32)host->testbus.select_minor << offset,
1581 reg);
1582 ufs_qcom_enable_test_bus(host);
1583 ufshcd_release(host->hba);
1584 pm_runtime_put_sync(host->hba->dev);
1585
1586 return 0;
1587 }
1588
1589 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1590 {
1591 ufs_qcom_dump_regs(hba, UFS_TEST_BUS, 1, "UFS_TEST_BUS ");
1592 }
1593
1594 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1595 {
1596 ufs_qcom_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16,
1597 "HCI Vendor Specific Registers ");
1598
1599 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1600 ufs_qcom_testbus_read(hba);
1601 }
1602
1603 /**
1604 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1605 *
1606 * The variant operations configure the necessary controller and PHY
1607 * handshake during initialization.
1608 */
1609 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1610 .name = "qcom",
1611 .init = ufs_qcom_init,
1612 .exit = ufs_qcom_exit,
1613 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1614 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1615 .setup_clocks = ufs_qcom_setup_clocks,
1616 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1617 .link_startup_notify = ufs_qcom_link_startup_notify,
1618 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1619 .suspend = ufs_qcom_suspend,
1620 .resume = ufs_qcom_resume,
1621 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1622 };
1623
1624 /**
1625 * ufs_qcom_probe - probe routine of the driver
1626 * @pdev: pointer to Platform device handle
1627 *
1628 * Return zero for success and non-zero for failure
1629 */
1630 static int ufs_qcom_probe(struct platform_device *pdev)
1631 {
1632 int err;
1633 struct device *dev = &pdev->dev;
1634
1635 /* Perform generic probe */
1636 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1637 if (err)
1638 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1639
1640 return err;
1641 }
1642
1643 /**
1644 * ufs_qcom_remove - set driver_data of the device to NULL
1645 * @pdev: pointer to platform device handle
1646 *
1647 * Always returns 0
1648 */
1649 static int ufs_qcom_remove(struct platform_device *pdev)
1650 {
1651 struct ufs_hba *hba = platform_get_drvdata(pdev);
1652
1653 pm_runtime_get_sync(&(pdev)->dev);
1654 ufshcd_remove(hba);
1655 return 0;
1656 }
1657
1658 static const struct of_device_id ufs_qcom_of_match[] = {
1659 { .compatible = "qcom,ufshc"},
1660 {},
1661 };
1662
1663 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1664 .suspend = ufshcd_pltfrm_suspend,
1665 .resume = ufshcd_pltfrm_resume,
1666 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1667 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1668 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1669 };
1670
1671 static struct platform_driver ufs_qcom_pltform = {
1672 .probe = ufs_qcom_probe,
1673 .remove = ufs_qcom_remove,
1674 .shutdown = ufshcd_pltfrm_shutdown,
1675 .driver = {
1676 .name = "ufshcd-qcom",
1677 .pm = &ufs_qcom_pm_ops,
1678 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1679 },
1680 };
1681 module_platform_driver(ufs_qcom_pltform);
1682
1683 MODULE_LICENSE("GPL v2");
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