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Merge tag 'backlight-next-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/lee...
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / ufs / ufs-qcom.c
1 /*
2 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15 #include <linux/time.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/phy/phy.h>
19 #include <linux/reset-controller.h>
20
21 #include "ufshcd.h"
22 #include "ufshcd-pltfrm.h"
23 #include "unipro.h"
24 #include "ufs-qcom.h"
25 #include "ufshci.h"
26 #include "ufs_quirks.h"
27 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
28 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
29
30 enum {
31 TSTBUS_UAWM,
32 TSTBUS_UARM,
33 TSTBUS_TXUC,
34 TSTBUS_RXUC,
35 TSTBUS_DFC,
36 TSTBUS_TRLUT,
37 TSTBUS_TMRLUT,
38 TSTBUS_OCSC,
39 TSTBUS_UTP_HCI,
40 TSTBUS_COMBINED,
41 TSTBUS_WRAPPER,
42 TSTBUS_UNIPRO,
43 TSTBUS_MAX,
44 };
45
46 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
47
48 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
49 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
50 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
51 u32 clk_cycles);
52
53 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
54 {
55 return container_of(rcd, struct ufs_qcom_host, rcdev);
56 }
57
58 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
59 const char *prefix, void *priv)
60 {
61 ufshcd_dump_regs(hba, offset, len * 4, prefix);
62 }
63
64 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
65 {
66 int err = 0;
67
68 err = ufshcd_dme_get(hba,
69 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
70 if (err)
71 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
72 __func__, err);
73
74 return err;
75 }
76
77 static int ufs_qcom_host_clk_get(struct device *dev,
78 const char *name, struct clk **clk_out, bool optional)
79 {
80 struct clk *clk;
81 int err = 0;
82
83 clk = devm_clk_get(dev, name);
84 if (!IS_ERR(clk)) {
85 *clk_out = clk;
86 return 0;
87 }
88
89 err = PTR_ERR(clk);
90
91 if (optional && err == -ENOENT) {
92 *clk_out = NULL;
93 return 0;
94 }
95
96 if (err != -EPROBE_DEFER)
97 dev_err(dev, "failed to get %s err %d\n", name, err);
98
99 return err;
100 }
101
102 static int ufs_qcom_host_clk_enable(struct device *dev,
103 const char *name, struct clk *clk)
104 {
105 int err = 0;
106
107 err = clk_prepare_enable(clk);
108 if (err)
109 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
110
111 return err;
112 }
113
114 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
115 {
116 if (!host->is_lane_clks_enabled)
117 return;
118
119 clk_disable_unprepare(host->tx_l1_sync_clk);
120 clk_disable_unprepare(host->tx_l0_sync_clk);
121 clk_disable_unprepare(host->rx_l1_sync_clk);
122 clk_disable_unprepare(host->rx_l0_sync_clk);
123
124 host->is_lane_clks_enabled = false;
125 }
126
127 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
128 {
129 int err = 0;
130 struct device *dev = host->hba->dev;
131
132 if (host->is_lane_clks_enabled)
133 return 0;
134
135 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
136 host->rx_l0_sync_clk);
137 if (err)
138 goto out;
139
140 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
141 host->tx_l0_sync_clk);
142 if (err)
143 goto disable_rx_l0;
144
145 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
146 host->rx_l1_sync_clk);
147 if (err)
148 goto disable_tx_l0;
149
150 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
151 host->tx_l1_sync_clk);
152 if (err)
153 goto disable_rx_l1;
154
155 host->is_lane_clks_enabled = true;
156 goto out;
157
158 disable_rx_l1:
159 clk_disable_unprepare(host->rx_l1_sync_clk);
160 disable_tx_l0:
161 clk_disable_unprepare(host->tx_l0_sync_clk);
162 disable_rx_l0:
163 clk_disable_unprepare(host->rx_l0_sync_clk);
164 out:
165 return err;
166 }
167
168 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
169 {
170 int err = 0;
171 struct device *dev = host->hba->dev;
172
173 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
174 &host->rx_l0_sync_clk, false);
175 if (err)
176 goto out;
177
178 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
179 &host->tx_l0_sync_clk, false);
180 if (err)
181 goto out;
182
183 /* In case of single lane per direction, don't read lane1 clocks */
184 if (host->hba->lanes_per_direction > 1) {
185 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
186 &host->rx_l1_sync_clk, false);
187 if (err)
188 goto out;
189
190 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
191 &host->tx_l1_sync_clk, true);
192 }
193 out:
194 return err;
195 }
196
197 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
198 {
199 u32 tx_lanes;
200
201 return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
202 }
203
204 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
205 {
206 int err;
207 u32 tx_fsm_val = 0;
208 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
209
210 do {
211 err = ufshcd_dme_get(hba,
212 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
213 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
214 &tx_fsm_val);
215 if (err || tx_fsm_val == TX_FSM_HIBERN8)
216 break;
217
218 /* sleep for max. 200us */
219 usleep_range(100, 200);
220 } while (time_before(jiffies, timeout));
221
222 /*
223 * we might have scheduled out for long during polling so
224 * check the state again.
225 */
226 if (time_after(jiffies, timeout))
227 err = ufshcd_dme_get(hba,
228 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
229 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
230 &tx_fsm_val);
231
232 if (err) {
233 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
234 __func__, err);
235 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
236 err = tx_fsm_val;
237 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
238 __func__, err);
239 }
240
241 return err;
242 }
243
244 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
245 {
246 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
247 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
248 REG_UFS_CFG1);
249 /* make sure above configuration is applied before we return */
250 mb();
251 }
252
253 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
254 {
255 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
256 struct phy *phy = host->generic_phy;
257 int ret = 0;
258 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
259 ? true : false;
260
261 if (is_rate_B)
262 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
263
264 /* phy initialization - calibrate the phy */
265 ret = phy_init(phy);
266 if (ret) {
267 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
268 __func__, ret);
269 goto out;
270 }
271
272 /* power on phy - start serdes and phy's power and clocks */
273 ret = phy_power_on(phy);
274 if (ret) {
275 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
276 __func__, ret);
277 goto out_disable_phy;
278 }
279
280 ufs_qcom_select_unipro_mode(host);
281
282 return 0;
283
284 out_disable_phy:
285 phy_exit(phy);
286 out:
287 return ret;
288 }
289
290 /*
291 * The UTP controller has a number of internal clock gating cells (CGCs).
292 * Internal hardware sub-modules within the UTP controller control the CGCs.
293 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
294 * in a specific operation, UTP controller CGCs are by default disabled and
295 * this function enables them (after every UFS link startup) to save some power
296 * leakage.
297 */
298 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
299 {
300 ufshcd_writel(hba,
301 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
302 REG_UFS_CFG2);
303
304 /* Ensure that HW clock gating is enabled before next operations */
305 mb();
306 }
307
308 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
309 enum ufs_notify_change_status status)
310 {
311 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
312 int err = 0;
313
314 switch (status) {
315 case PRE_CHANGE:
316 ufs_qcom_power_up_sequence(hba);
317 /*
318 * The PHY PLL output is the source of tx/rx lane symbol
319 * clocks, hence, enable the lane clocks only after PHY
320 * is initialized.
321 */
322 err = ufs_qcom_enable_lane_clks(host);
323 break;
324 case POST_CHANGE:
325 /* check if UFS PHY moved from DISABLED to HIBERN8 */
326 err = ufs_qcom_check_hibern8(hba);
327 ufs_qcom_enable_hw_clk_gating(hba);
328
329 break;
330 default:
331 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
332 err = -EINVAL;
333 break;
334 }
335 return err;
336 }
337
338 /**
339 * Returns zero for success and non-zero in case of a failure
340 */
341 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
342 u32 hs, u32 rate, bool update_link_startup_timer)
343 {
344 int ret = 0;
345 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
346 struct ufs_clk_info *clki;
347 u32 core_clk_period_in_ns;
348 u32 tx_clk_cycles_per_us = 0;
349 unsigned long core_clk_rate = 0;
350 u32 core_clk_cycles_per_us = 0;
351
352 static u32 pwm_fr_table[][2] = {
353 {UFS_PWM_G1, 0x1},
354 {UFS_PWM_G2, 0x1},
355 {UFS_PWM_G3, 0x1},
356 {UFS_PWM_G4, 0x1},
357 };
358
359 static u32 hs_fr_table_rA[][2] = {
360 {UFS_HS_G1, 0x1F},
361 {UFS_HS_G2, 0x3e},
362 {UFS_HS_G3, 0x7D},
363 };
364
365 static u32 hs_fr_table_rB[][2] = {
366 {UFS_HS_G1, 0x24},
367 {UFS_HS_G2, 0x49},
368 {UFS_HS_G3, 0x92},
369 };
370
371 /*
372 * The Qunipro controller does not use following registers:
373 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
374 * UFS_REG_PA_LINK_STARTUP_TIMER
375 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
376 * Aggregation logic.
377 */
378 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
379 goto out;
380
381 if (gear == 0) {
382 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
383 goto out_error;
384 }
385
386 list_for_each_entry(clki, &hba->clk_list_head, list) {
387 if (!strcmp(clki->name, "core_clk"))
388 core_clk_rate = clk_get_rate(clki->clk);
389 }
390
391 /* If frequency is smaller than 1MHz, set to 1MHz */
392 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
393 core_clk_rate = DEFAULT_CLK_RATE_HZ;
394
395 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
396 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
397 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
398 /*
399 * make sure above write gets applied before we return from
400 * this function.
401 */
402 mb();
403 }
404
405 if (ufs_qcom_cap_qunipro(host))
406 goto out;
407
408 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
409 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
410 core_clk_period_in_ns &= MASK_CLK_NS_REG;
411
412 switch (hs) {
413 case FASTAUTO_MODE:
414 case FAST_MODE:
415 if (rate == PA_HS_MODE_A) {
416 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
417 dev_err(hba->dev,
418 "%s: index %d exceeds table size %zu\n",
419 __func__, gear,
420 ARRAY_SIZE(hs_fr_table_rA));
421 goto out_error;
422 }
423 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
424 } else if (rate == PA_HS_MODE_B) {
425 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
426 dev_err(hba->dev,
427 "%s: index %d exceeds table size %zu\n",
428 __func__, gear,
429 ARRAY_SIZE(hs_fr_table_rB));
430 goto out_error;
431 }
432 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
433 } else {
434 dev_err(hba->dev, "%s: invalid rate = %d\n",
435 __func__, rate);
436 goto out_error;
437 }
438 break;
439 case SLOWAUTO_MODE:
440 case SLOW_MODE:
441 if (gear > ARRAY_SIZE(pwm_fr_table)) {
442 dev_err(hba->dev,
443 "%s: index %d exceeds table size %zu\n",
444 __func__, gear,
445 ARRAY_SIZE(pwm_fr_table));
446 goto out_error;
447 }
448 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
449 break;
450 case UNCHANGED:
451 default:
452 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
453 goto out_error;
454 }
455
456 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
457 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
458 /* this register 2 fields shall be written at once */
459 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
460 REG_UFS_TX_SYMBOL_CLK_NS_US);
461 /*
462 * make sure above write gets applied before we return from
463 * this function.
464 */
465 mb();
466 }
467
468 if (update_link_startup_timer) {
469 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
470 REG_UFS_PA_LINK_STARTUP_TIMER);
471 /*
472 * make sure that this configuration is applied before
473 * we return
474 */
475 mb();
476 }
477 goto out;
478
479 out_error:
480 ret = -EINVAL;
481 out:
482 return ret;
483 }
484
485 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
486 enum ufs_notify_change_status status)
487 {
488 int err = 0;
489 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
490
491 switch (status) {
492 case PRE_CHANGE:
493 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
494 0, true)) {
495 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
496 __func__);
497 err = -EINVAL;
498 goto out;
499 }
500
501 if (ufs_qcom_cap_qunipro(host))
502 /*
503 * set unipro core clock cycles to 150 & clear clock
504 * divider
505 */
506 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
507 150);
508
509 /*
510 * Some UFS devices (and may be host) have issues if LCC is
511 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
512 * before link startup which will make sure that both host
513 * and device TX LCC are disabled once link startup is
514 * completed.
515 */
516 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
517 err = ufshcd_dme_set(hba,
518 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
519 0);
520
521 break;
522 case POST_CHANGE:
523 ufs_qcom_link_startup_post_change(hba);
524 break;
525 default:
526 break;
527 }
528
529 out:
530 return err;
531 }
532
533 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
534 {
535 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
536 struct phy *phy = host->generic_phy;
537 int ret = 0;
538
539 if (ufs_qcom_is_link_off(hba)) {
540 /*
541 * Disable the tx/rx lane symbol clocks before PHY is
542 * powered down as the PLL source should be disabled
543 * after downstream clocks are disabled.
544 */
545 ufs_qcom_disable_lane_clks(host);
546 phy_power_off(phy);
547
548 } else if (!ufs_qcom_is_link_active(hba)) {
549 ufs_qcom_disable_lane_clks(host);
550 }
551
552 return ret;
553 }
554
555 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
556 {
557 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
558 struct phy *phy = host->generic_phy;
559 int err;
560
561 if (ufs_qcom_is_link_off(hba)) {
562 err = phy_power_on(phy);
563 if (err) {
564 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
565 __func__, err);
566 return err;
567 }
568
569 err = ufs_qcom_enable_lane_clks(host);
570 if (err)
571 return err;
572
573 } else if (!ufs_qcom_is_link_active(hba)) {
574 err = ufs_qcom_enable_lane_clks(host);
575 if (err)
576 return err;
577 }
578
579 hba->is_sys_suspended = false;
580 return 0;
581 }
582
583 #ifdef CONFIG_MSM_BUS_SCALING
584 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
585 const char *speed_mode)
586 {
587 struct device *dev = host->hba->dev;
588 struct device_node *np = dev->of_node;
589 int err;
590 const char *key = "qcom,bus-vector-names";
591
592 if (!speed_mode) {
593 err = -EINVAL;
594 goto out;
595 }
596
597 if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
598 err = of_property_match_string(np, key, "MAX");
599 else
600 err = of_property_match_string(np, key, speed_mode);
601
602 out:
603 if (err < 0)
604 dev_err(dev, "%s: Invalid %s mode %d\n",
605 __func__, speed_mode, err);
606 return err;
607 }
608
609 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
610 {
611 int gear = max_t(u32, p->gear_rx, p->gear_tx);
612 int lanes = max_t(u32, p->lane_rx, p->lane_tx);
613 int pwr;
614
615 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
616 if (!gear)
617 gear = 1;
618
619 if (!lanes)
620 lanes = 1;
621
622 if (!p->pwr_rx && !p->pwr_tx) {
623 pwr = SLOWAUTO_MODE;
624 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
625 } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
626 p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
627 pwr = FAST_MODE;
628 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
629 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
630 } else {
631 pwr = SLOW_MODE;
632 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
633 "PWM", gear, lanes);
634 }
635 }
636
637 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
638 {
639 int err = 0;
640
641 if (vote != host->bus_vote.curr_vote) {
642 err = msm_bus_scale_client_update_request(
643 host->bus_vote.client_handle, vote);
644 if (err) {
645 dev_err(host->hba->dev,
646 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
647 __func__, host->bus_vote.client_handle,
648 vote, err);
649 goto out;
650 }
651
652 host->bus_vote.curr_vote = vote;
653 }
654 out:
655 return err;
656 }
657
658 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
659 {
660 int vote;
661 int err = 0;
662 char mode[BUS_VECTOR_NAME_LEN];
663
664 ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
665
666 vote = ufs_qcom_get_bus_vote(host, mode);
667 if (vote >= 0)
668 err = ufs_qcom_set_bus_vote(host, vote);
669 else
670 err = vote;
671
672 if (err)
673 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
674 else
675 host->bus_vote.saved_vote = vote;
676 return err;
677 }
678
679 static ssize_t
680 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
681 char *buf)
682 {
683 struct ufs_hba *hba = dev_get_drvdata(dev);
684 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
685
686 return snprintf(buf, PAGE_SIZE, "%u\n",
687 host->bus_vote.is_max_bw_needed);
688 }
689
690 static ssize_t
691 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
692 const char *buf, size_t count)
693 {
694 struct ufs_hba *hba = dev_get_drvdata(dev);
695 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
696 uint32_t value;
697
698 if (!kstrtou32(buf, 0, &value)) {
699 host->bus_vote.is_max_bw_needed = !!value;
700 ufs_qcom_update_bus_bw_vote(host);
701 }
702
703 return count;
704 }
705
706 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
707 {
708 int err;
709 struct msm_bus_scale_pdata *bus_pdata;
710 struct device *dev = host->hba->dev;
711 struct platform_device *pdev = to_platform_device(dev);
712 struct device_node *np = dev->of_node;
713
714 bus_pdata = msm_bus_cl_get_pdata(pdev);
715 if (!bus_pdata) {
716 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
717 err = -ENODATA;
718 goto out;
719 }
720
721 err = of_property_count_strings(np, "qcom,bus-vector-names");
722 if (err < 0 || err != bus_pdata->num_usecases) {
723 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
724 __func__, err);
725 goto out;
726 }
727
728 host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
729 if (!host->bus_vote.client_handle) {
730 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
731 __func__);
732 err = -EFAULT;
733 goto out;
734 }
735
736 /* cache the vote index for minimum and maximum bandwidth */
737 host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
738 host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
739
740 host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
741 host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
742 sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
743 host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
744 host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
745 err = device_create_file(dev, &host->bus_vote.max_bus_bw);
746 out:
747 return err;
748 }
749 #else /* CONFIG_MSM_BUS_SCALING */
750 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
751 {
752 return 0;
753 }
754
755 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
756 {
757 return 0;
758 }
759
760 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
761 {
762 return 0;
763 }
764 #endif /* CONFIG_MSM_BUS_SCALING */
765
766 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
767 {
768 if (host->dev_ref_clk_ctrl_mmio &&
769 (enable ^ host->is_dev_ref_clk_enabled)) {
770 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
771
772 if (enable)
773 temp |= host->dev_ref_clk_en_mask;
774 else
775 temp &= ~host->dev_ref_clk_en_mask;
776
777 /*
778 * If we are here to disable this clock it might be immediately
779 * after entering into hibern8 in which case we need to make
780 * sure that device ref_clk is active at least 1us after the
781 * hibern8 enter.
782 */
783 if (!enable)
784 udelay(1);
785
786 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
787
788 /* ensure that ref_clk is enabled/disabled before we return */
789 wmb();
790
791 /*
792 * If we call hibern8 exit after this, we need to make sure that
793 * device ref_clk is stable for at least 1us before the hibern8
794 * exit command.
795 */
796 if (enable)
797 udelay(1);
798
799 host->is_dev_ref_clk_enabled = enable;
800 }
801 }
802
803 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
804 enum ufs_notify_change_status status,
805 struct ufs_pa_layer_attr *dev_max_params,
806 struct ufs_pa_layer_attr *dev_req_params)
807 {
808 u32 val;
809 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
810 struct ufs_dev_params ufs_qcom_cap;
811 int ret = 0;
812
813 if (!dev_req_params) {
814 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
815 ret = -EINVAL;
816 goto out;
817 }
818
819 switch (status) {
820 case PRE_CHANGE:
821 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
822 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
823 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
824 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
825 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
826 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
827 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
828 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
829 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
830 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
831 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
832 ufs_qcom_cap.desired_working_mode =
833 UFS_QCOM_LIMIT_DESIRED_MODE;
834
835 if (host->hw_ver.major == 0x1) {
836 /*
837 * HS-G3 operations may not reliably work on legacy QCOM
838 * UFS host controller hardware even though capability
839 * exchange during link startup phase may end up
840 * negotiating maximum supported gear as G3.
841 * Hence downgrade the maximum supported gear to HS-G2.
842 */
843 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
844 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
845 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
846 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
847 }
848
849 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
850 dev_max_params,
851 dev_req_params);
852 if (ret) {
853 pr_err("%s: failed to determine capabilities\n",
854 __func__);
855 goto out;
856 }
857
858 /* enable the device ref clock before changing to HS mode */
859 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
860 ufshcd_is_hs_mode(dev_req_params))
861 ufs_qcom_dev_ref_clk_ctrl(host, true);
862 break;
863 case POST_CHANGE:
864 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
865 dev_req_params->pwr_rx,
866 dev_req_params->hs_rate, false)) {
867 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
868 __func__);
869 /*
870 * we return error code at the end of the routine,
871 * but continue to configure UFS_PHY_TX_LANE_ENABLE
872 * and bus voting as usual
873 */
874 ret = -EINVAL;
875 }
876
877 val = ~(MAX_U32 << dev_req_params->lane_tx);
878
879 /* cache the power mode parameters to use internally */
880 memcpy(&host->dev_req_params,
881 dev_req_params, sizeof(*dev_req_params));
882 ufs_qcom_update_bus_bw_vote(host);
883
884 /* disable the device ref clock if entered PWM mode */
885 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
886 !ufshcd_is_hs_mode(dev_req_params))
887 ufs_qcom_dev_ref_clk_ctrl(host, false);
888 break;
889 default:
890 ret = -EINVAL;
891 break;
892 }
893 out:
894 return ret;
895 }
896
897 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
898 {
899 int err;
900 u32 pa_vs_config_reg1;
901
902 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
903 &pa_vs_config_reg1);
904 if (err)
905 goto out;
906
907 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
908 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
909 (pa_vs_config_reg1 | (1 << 12)));
910
911 out:
912 return err;
913 }
914
915 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
916 {
917 int err = 0;
918
919 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
920 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
921
922 return err;
923 }
924
925 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
926 {
927 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
928
929 if (host->hw_ver.major == 0x1)
930 return UFSHCI_VERSION_11;
931 else
932 return UFSHCI_VERSION_20;
933 }
934
935 /**
936 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
937 * @hba: host controller instance
938 *
939 * QCOM UFS host controller might have some non standard behaviours (quirks)
940 * than what is specified by UFSHCI specification. Advertise all such
941 * quirks to standard UFS host controller driver so standard takes them into
942 * account.
943 */
944 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
945 {
946 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
947
948 if (host->hw_ver.major == 0x01) {
949 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
950 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
951 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
952
953 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
954 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
955
956 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
957 }
958
959 if (host->hw_ver.major == 0x2) {
960 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
961
962 if (!ufs_qcom_cap_qunipro(host))
963 /* Legacy UniPro mode still need following quirks */
964 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
965 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
966 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
967 }
968 }
969
970 static void ufs_qcom_set_caps(struct ufs_hba *hba)
971 {
972 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
973
974 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
975 hba->caps |= UFSHCD_CAP_CLK_SCALING;
976 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
977
978 if (host->hw_ver.major >= 0x2) {
979 host->caps = UFS_QCOM_CAP_QUNIPRO |
980 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
981 }
982 }
983
984 /**
985 * ufs_qcom_setup_clocks - enables/disable clocks
986 * @hba: host controller instance
987 * @on: If true, enable clocks else disable them.
988 * @status: PRE_CHANGE or POST_CHANGE notify
989 *
990 * Returns 0 on success, non-zero on failure.
991 */
992 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
993 enum ufs_notify_change_status status)
994 {
995 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
996 int err;
997 int vote = 0;
998
999 /*
1000 * In case ufs_qcom_init() is not yet done, simply ignore.
1001 * This ufs_qcom_setup_clocks() shall be called from
1002 * ufs_qcom_init() after init is done.
1003 */
1004 if (!host)
1005 return 0;
1006
1007 if (on && (status == POST_CHANGE)) {
1008 /* enable the device ref clock for HS mode*/
1009 if (ufshcd_is_hs_mode(&hba->pwr_info))
1010 ufs_qcom_dev_ref_clk_ctrl(host, true);
1011 vote = host->bus_vote.saved_vote;
1012 if (vote == host->bus_vote.min_bw_vote)
1013 ufs_qcom_update_bus_bw_vote(host);
1014
1015 } else if (!on && (status == PRE_CHANGE)) {
1016 if (!ufs_qcom_is_link_active(hba)) {
1017 /* disable device ref_clk */
1018 ufs_qcom_dev_ref_clk_ctrl(host, false);
1019 }
1020
1021 vote = host->bus_vote.min_bw_vote;
1022 }
1023
1024 err = ufs_qcom_set_bus_vote(host, vote);
1025 if (err)
1026 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1027 __func__, err);
1028
1029 return err;
1030 }
1031
1032 static int
1033 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1034 {
1035 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1036
1037 /* Currently this code only knows about a single reset. */
1038 WARN_ON(id);
1039 ufs_qcom_assert_reset(host->hba);
1040 /* provide 1ms delay to let the reset pulse propagate. */
1041 usleep_range(1000, 1100);
1042 return 0;
1043 }
1044
1045 static int
1046 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1047 {
1048 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1049
1050 /* Currently this code only knows about a single reset. */
1051 WARN_ON(id);
1052 ufs_qcom_deassert_reset(host->hba);
1053
1054 /*
1055 * after reset deassertion, phy will need all ref clocks,
1056 * voltage, current to settle down before starting serdes.
1057 */
1058 usleep_range(1000, 1100);
1059 return 0;
1060 }
1061
1062 static const struct reset_control_ops ufs_qcom_reset_ops = {
1063 .assert = ufs_qcom_reset_assert,
1064 .deassert = ufs_qcom_reset_deassert,
1065 };
1066
1067 #define ANDROID_BOOT_DEV_MAX 30
1068 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1069
1070 #ifndef MODULE
1071 static int __init get_android_boot_dev(char *str)
1072 {
1073 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1074 return 1;
1075 }
1076 __setup("androidboot.bootdevice=", get_android_boot_dev);
1077 #endif
1078
1079 /**
1080 * ufs_qcom_init - bind phy with controller
1081 * @hba: host controller instance
1082 *
1083 * Binds PHY with controller and powers up PHY enabling clocks
1084 * and regulators.
1085 *
1086 * Returns -EPROBE_DEFER if binding fails, returns negative error
1087 * on phy power up failure and returns zero on success.
1088 */
1089 static int ufs_qcom_init(struct ufs_hba *hba)
1090 {
1091 int err;
1092 struct device *dev = hba->dev;
1093 struct platform_device *pdev = to_platform_device(dev);
1094 struct ufs_qcom_host *host;
1095 struct resource *res;
1096
1097 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1098 return -ENODEV;
1099
1100 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1101 if (!host) {
1102 err = -ENOMEM;
1103 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1104 goto out;
1105 }
1106
1107 /* Make a two way bind between the qcom host and the hba */
1108 host->hba = hba;
1109 ufshcd_set_variant(hba, host);
1110
1111 /* Fire up the reset controller. Failure here is non-fatal. */
1112 host->rcdev.of_node = dev->of_node;
1113 host->rcdev.ops = &ufs_qcom_reset_ops;
1114 host->rcdev.owner = dev->driver->owner;
1115 host->rcdev.nr_resets = 1;
1116 err = devm_reset_controller_register(dev, &host->rcdev);
1117 if (err) {
1118 dev_warn(dev, "Failed to register reset controller\n");
1119 err = 0;
1120 }
1121
1122 /*
1123 * voting/devoting device ref_clk source is time consuming hence
1124 * skip devoting it during aggressive clock gating. This clock
1125 * will still be gated off during runtime suspend.
1126 */
1127 host->generic_phy = devm_phy_get(dev, "ufsphy");
1128
1129 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1130 /*
1131 * UFS driver might be probed before the phy driver does.
1132 * In that case we would like to return EPROBE_DEFER code.
1133 */
1134 err = -EPROBE_DEFER;
1135 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1136 __func__, err);
1137 goto out_variant_clear;
1138 } else if (IS_ERR(host->generic_phy)) {
1139 err = PTR_ERR(host->generic_phy);
1140 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1141 goto out_variant_clear;
1142 }
1143
1144 err = ufs_qcom_bus_register(host);
1145 if (err)
1146 goto out_variant_clear;
1147
1148 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1149 &host->hw_ver.minor, &host->hw_ver.step);
1150
1151 /*
1152 * for newer controllers, device reference clock control bit has
1153 * moved inside UFS controller register address space itself.
1154 */
1155 if (host->hw_ver.major >= 0x02) {
1156 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1157 host->dev_ref_clk_en_mask = BIT(26);
1158 } else {
1159 /* "dev_ref_clk_ctrl_mem" is optional resource */
1160 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1161 if (res) {
1162 host->dev_ref_clk_ctrl_mmio =
1163 devm_ioremap_resource(dev, res);
1164 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1165 dev_warn(dev,
1166 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1167 __func__,
1168 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1169 host->dev_ref_clk_ctrl_mmio = NULL;
1170 }
1171 host->dev_ref_clk_en_mask = BIT(5);
1172 }
1173 }
1174
1175 err = ufs_qcom_init_lane_clks(host);
1176 if (err)
1177 goto out_variant_clear;
1178
1179 ufs_qcom_set_caps(hba);
1180 ufs_qcom_advertise_quirks(hba);
1181
1182 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1183
1184 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1185 ufs_qcom_hosts[hba->dev->id] = host;
1186
1187 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1188 ufs_qcom_get_default_testbus_cfg(host);
1189 err = ufs_qcom_testbus_config(host);
1190 if (err) {
1191 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1192 __func__, err);
1193 err = 0;
1194 }
1195
1196 goto out;
1197
1198 out_variant_clear:
1199 ufshcd_set_variant(hba, NULL);
1200 out:
1201 return err;
1202 }
1203
1204 static void ufs_qcom_exit(struct ufs_hba *hba)
1205 {
1206 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1207
1208 ufs_qcom_disable_lane_clks(host);
1209 phy_power_off(host->generic_phy);
1210 phy_exit(host->generic_phy);
1211 }
1212
1213 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1214 u32 clk_cycles)
1215 {
1216 int err;
1217 u32 core_clk_ctrl_reg;
1218
1219 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1220 return -EINVAL;
1221
1222 err = ufshcd_dme_get(hba,
1223 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1224 &core_clk_ctrl_reg);
1225 if (err)
1226 goto out;
1227
1228 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1229 core_clk_ctrl_reg |= clk_cycles;
1230
1231 /* Clear CORE_CLK_DIV_EN */
1232 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1233
1234 err = ufshcd_dme_set(hba,
1235 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1236 core_clk_ctrl_reg);
1237 out:
1238 return err;
1239 }
1240
1241 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1242 {
1243 /* nothing to do as of now */
1244 return 0;
1245 }
1246
1247 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1248 {
1249 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1250
1251 if (!ufs_qcom_cap_qunipro(host))
1252 return 0;
1253
1254 /* set unipro core clock cycles to 150 and clear clock divider */
1255 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1256 }
1257
1258 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1259 {
1260 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1261 int err;
1262 u32 core_clk_ctrl_reg;
1263
1264 if (!ufs_qcom_cap_qunipro(host))
1265 return 0;
1266
1267 err = ufshcd_dme_get(hba,
1268 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1269 &core_clk_ctrl_reg);
1270
1271 /* make sure CORE_CLK_DIV_EN is cleared */
1272 if (!err &&
1273 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1274 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1275 err = ufshcd_dme_set(hba,
1276 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1277 core_clk_ctrl_reg);
1278 }
1279
1280 return err;
1281 }
1282
1283 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1284 {
1285 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1286
1287 if (!ufs_qcom_cap_qunipro(host))
1288 return 0;
1289
1290 /* set unipro core clock cycles to 75 and clear clock divider */
1291 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1292 }
1293
1294 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1295 bool scale_up, enum ufs_notify_change_status status)
1296 {
1297 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1298 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1299 int err = 0;
1300
1301 if (status == PRE_CHANGE) {
1302 if (scale_up)
1303 err = ufs_qcom_clk_scale_up_pre_change(hba);
1304 else
1305 err = ufs_qcom_clk_scale_down_pre_change(hba);
1306 } else {
1307 if (scale_up)
1308 err = ufs_qcom_clk_scale_up_post_change(hba);
1309 else
1310 err = ufs_qcom_clk_scale_down_post_change(hba);
1311
1312 if (err || !dev_req_params)
1313 goto out;
1314
1315 ufs_qcom_cfg_timers(hba,
1316 dev_req_params->gear_rx,
1317 dev_req_params->pwr_rx,
1318 dev_req_params->hs_rate,
1319 false);
1320 ufs_qcom_update_bus_bw_vote(host);
1321 }
1322
1323 out:
1324 return err;
1325 }
1326
1327 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1328 void *priv, void (*print_fn)(struct ufs_hba *hba,
1329 int offset, int num_regs, const char *str, void *priv))
1330 {
1331 u32 reg;
1332 struct ufs_qcom_host *host;
1333
1334 if (unlikely(!hba)) {
1335 pr_err("%s: hba is NULL\n", __func__);
1336 return;
1337 }
1338 if (unlikely(!print_fn)) {
1339 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1340 return;
1341 }
1342
1343 host = ufshcd_get_variant(hba);
1344 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1345 return;
1346
1347 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1348 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1349
1350 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1351 reg |= UTP_DBG_RAMS_EN;
1352 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1353
1354 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1355 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1356
1357 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1358 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1359
1360 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1361 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1362
1363 /* clear bit 17 - UTP_DBG_RAMS_EN */
1364 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1365
1366 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1367 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1368
1369 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1370 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1371
1372 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1373 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1374
1375 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1376 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1377
1378 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1379 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1380
1381 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1382 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1383
1384 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1385 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1386 }
1387
1388 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1389 {
1390 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1391 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1392 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1393 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1394 } else {
1395 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1396 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1397 }
1398 }
1399
1400 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1401 {
1402 /* provide a legal default configuration */
1403 host->testbus.select_major = TSTBUS_UNIPRO;
1404 host->testbus.select_minor = 37;
1405 }
1406
1407 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1408 {
1409 if (host->testbus.select_major >= TSTBUS_MAX) {
1410 dev_err(host->hba->dev,
1411 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1412 __func__, host->testbus.select_major);
1413 return false;
1414 }
1415
1416 return true;
1417 }
1418
1419 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1420 {
1421 int reg;
1422 int offset;
1423 u32 mask = TEST_BUS_SUB_SEL_MASK;
1424
1425 if (!host)
1426 return -EINVAL;
1427
1428 if (!ufs_qcom_testbus_cfg_is_ok(host))
1429 return -EPERM;
1430
1431 switch (host->testbus.select_major) {
1432 case TSTBUS_UAWM:
1433 reg = UFS_TEST_BUS_CTRL_0;
1434 offset = 24;
1435 break;
1436 case TSTBUS_UARM:
1437 reg = UFS_TEST_BUS_CTRL_0;
1438 offset = 16;
1439 break;
1440 case TSTBUS_TXUC:
1441 reg = UFS_TEST_BUS_CTRL_0;
1442 offset = 8;
1443 break;
1444 case TSTBUS_RXUC:
1445 reg = UFS_TEST_BUS_CTRL_0;
1446 offset = 0;
1447 break;
1448 case TSTBUS_DFC:
1449 reg = UFS_TEST_BUS_CTRL_1;
1450 offset = 24;
1451 break;
1452 case TSTBUS_TRLUT:
1453 reg = UFS_TEST_BUS_CTRL_1;
1454 offset = 16;
1455 break;
1456 case TSTBUS_TMRLUT:
1457 reg = UFS_TEST_BUS_CTRL_1;
1458 offset = 8;
1459 break;
1460 case TSTBUS_OCSC:
1461 reg = UFS_TEST_BUS_CTRL_1;
1462 offset = 0;
1463 break;
1464 case TSTBUS_WRAPPER:
1465 reg = UFS_TEST_BUS_CTRL_2;
1466 offset = 16;
1467 break;
1468 case TSTBUS_COMBINED:
1469 reg = UFS_TEST_BUS_CTRL_2;
1470 offset = 8;
1471 break;
1472 case TSTBUS_UTP_HCI:
1473 reg = UFS_TEST_BUS_CTRL_2;
1474 offset = 0;
1475 break;
1476 case TSTBUS_UNIPRO:
1477 reg = UFS_UNIPRO_CFG;
1478 offset = 20;
1479 mask = 0xFFF;
1480 break;
1481 /*
1482 * No need for a default case, since
1483 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1484 * is legal
1485 */
1486 }
1487 mask <<= offset;
1488
1489 pm_runtime_get_sync(host->hba->dev);
1490 ufshcd_hold(host->hba, false);
1491 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1492 (u32)host->testbus.select_major << 19,
1493 REG_UFS_CFG1);
1494 ufshcd_rmwl(host->hba, mask,
1495 (u32)host->testbus.select_minor << offset,
1496 reg);
1497 ufs_qcom_enable_test_bus(host);
1498 /*
1499 * Make sure the test bus configuration is
1500 * committed before returning.
1501 */
1502 mb();
1503 ufshcd_release(host->hba);
1504 pm_runtime_put_sync(host->hba->dev);
1505
1506 return 0;
1507 }
1508
1509 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1510 {
1511 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1512 }
1513
1514 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1515 {
1516 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1517 u32 *testbus = NULL;
1518 int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1519
1520 testbus = kmalloc(testbus_len, GFP_KERNEL);
1521 if (!testbus)
1522 return;
1523
1524 host->testbus.select_major = TSTBUS_UNIPRO;
1525 for (i = 0; i < nminor; i++) {
1526 host->testbus.select_minor = i;
1527 ufs_qcom_testbus_config(host);
1528 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1529 }
1530 print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1531 16, 4, testbus, testbus_len, false);
1532 kfree(testbus);
1533 }
1534
1535 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1536 {
1537 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1538 "HCI Vendor Specific Registers ");
1539
1540 /* sleep a bit intermittently as we are dumping too much data */
1541 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1542 usleep_range(1000, 1100);
1543 ufs_qcom_testbus_read(hba);
1544 usleep_range(1000, 1100);
1545 ufs_qcom_print_unipro_testbus(hba);
1546 usleep_range(1000, 1100);
1547 }
1548
1549 /**
1550 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1551 *
1552 * The variant operations configure the necessary controller and PHY
1553 * handshake during initialization.
1554 */
1555 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1556 .name = "qcom",
1557 .init = ufs_qcom_init,
1558 .exit = ufs_qcom_exit,
1559 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1560 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1561 .setup_clocks = ufs_qcom_setup_clocks,
1562 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1563 .link_startup_notify = ufs_qcom_link_startup_notify,
1564 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1565 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1566 .suspend = ufs_qcom_suspend,
1567 .resume = ufs_qcom_resume,
1568 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1569 };
1570
1571 /**
1572 * ufs_qcom_probe - probe routine of the driver
1573 * @pdev: pointer to Platform device handle
1574 *
1575 * Return zero for success and non-zero for failure
1576 */
1577 static int ufs_qcom_probe(struct platform_device *pdev)
1578 {
1579 int err;
1580 struct device *dev = &pdev->dev;
1581
1582 /* Perform generic probe */
1583 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1584 if (err)
1585 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1586
1587 return err;
1588 }
1589
1590 /**
1591 * ufs_qcom_remove - set driver_data of the device to NULL
1592 * @pdev: pointer to platform device handle
1593 *
1594 * Always returns 0
1595 */
1596 static int ufs_qcom_remove(struct platform_device *pdev)
1597 {
1598 struct ufs_hba *hba = platform_get_drvdata(pdev);
1599
1600 pm_runtime_get_sync(&(pdev)->dev);
1601 ufshcd_remove(hba);
1602 return 0;
1603 }
1604
1605 static const struct of_device_id ufs_qcom_of_match[] = {
1606 { .compatible = "qcom,ufshc"},
1607 {},
1608 };
1609 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1610
1611 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1612 .suspend = ufshcd_pltfrm_suspend,
1613 .resume = ufshcd_pltfrm_resume,
1614 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1615 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1616 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1617 };
1618
1619 static struct platform_driver ufs_qcom_pltform = {
1620 .probe = ufs_qcom_probe,
1621 .remove = ufs_qcom_remove,
1622 .shutdown = ufshcd_pltfrm_shutdown,
1623 .driver = {
1624 .name = "ufshcd-qcom",
1625 .pm = &ufs_qcom_pm_ops,
1626 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1627 },
1628 };
1629 module_platform_driver(ufs_qcom_pltform);
1630
1631 MODULE_LICENSE("GPL v2");
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