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[mirror_ubuntu-artful-kernel.git] / drivers / scsi / ufs / ufshcd.c
1 /*
2 * Universal Flash Storage Host controller driver Core
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
5 * Copyright (C) 2011-2013 Samsung India Software Operations
6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7 *
8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
38 */
39
40 #include <linux/async.h>
41 #include <linux/devfreq.h>
42 #include <linux/nls.h>
43 #include <linux/of.h>
44 #include "ufshcd.h"
45 #include "ufs_quirks.h"
46 #include "unipro.h"
47
48 #define CREATE_TRACE_POINTS
49 #include <trace/events/ufs.h>
50
51 #define UFSHCD_REQ_SENSE_SIZE 18
52
53 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
54 UTP_TASK_REQ_COMPL |\
55 UFSHCD_ERROR_MASK)
56 /* UIC command timeout, unit: ms */
57 #define UIC_CMD_TIMEOUT 500
58
59 /* NOP OUT retries waiting for NOP IN response */
60 #define NOP_OUT_RETRIES 10
61 /* Timeout after 30 msecs if NOP OUT hangs without response */
62 #define NOP_OUT_TIMEOUT 30 /* msecs */
63
64 /* Query request retries */
65 #define QUERY_REQ_RETRIES 3
66 /* Query request timeout */
67 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68
69 /* Task management command timeout */
70 #define TM_CMD_TIMEOUT 100 /* msecs */
71
72 /* maximum number of retries for a general UIC command */
73 #define UFS_UIC_COMMAND_RETRIES 3
74
75 /* maximum number of link-startup retries */
76 #define DME_LINKSTARTUP_RETRIES 3
77
78 /* Maximum retries for Hibern8 enter */
79 #define UIC_HIBERN8_ENTER_RETRIES 3
80
81 /* maximum number of reset retries before giving up */
82 #define MAX_HOST_RESET_RETRIES 5
83
84 /* Expose the flag value from utp_upiu_query.value */
85 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
86
87 /* Interrupt aggregation default timeout, unit: 40us */
88 #define INT_AGGR_DEF_TO 0x02
89
90 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
91 ({ \
92 int _ret; \
93 if (_on) \
94 _ret = ufshcd_enable_vreg(_dev, _vreg); \
95 else \
96 _ret = ufshcd_disable_vreg(_dev, _vreg); \
97 _ret; \
98 })
99
100 #define ufshcd_hex_dump(prefix_str, buf, len) \
101 print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false)
102
103 static u32 ufs_query_desc_max_size[] = {
104 QUERY_DESC_DEVICE_MAX_SIZE,
105 QUERY_DESC_CONFIGURAION_MAX_SIZE,
106 QUERY_DESC_UNIT_MAX_SIZE,
107 QUERY_DESC_RFU_MAX_SIZE,
108 QUERY_DESC_INTERCONNECT_MAX_SIZE,
109 QUERY_DESC_STRING_MAX_SIZE,
110 QUERY_DESC_RFU_MAX_SIZE,
111 QUERY_DESC_GEOMETRY_MAX_SIZE,
112 QUERY_DESC_POWER_MAX_SIZE,
113 QUERY_DESC_RFU_MAX_SIZE,
114 };
115
116 enum {
117 UFSHCD_MAX_CHANNEL = 0,
118 UFSHCD_MAX_ID = 1,
119 UFSHCD_CMD_PER_LUN = 32,
120 UFSHCD_CAN_QUEUE = 32,
121 };
122
123 /* UFSHCD states */
124 enum {
125 UFSHCD_STATE_RESET,
126 UFSHCD_STATE_ERROR,
127 UFSHCD_STATE_OPERATIONAL,
128 UFSHCD_STATE_EH_SCHEDULED,
129 };
130
131 /* UFSHCD error handling flags */
132 enum {
133 UFSHCD_EH_IN_PROGRESS = (1 << 0),
134 };
135
136 /* UFSHCD UIC layer error flags */
137 enum {
138 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
139 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
140 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
141 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
142 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
143 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
144 };
145
146 /* Interrupt configuration options */
147 enum {
148 UFSHCD_INT_DISABLE,
149 UFSHCD_INT_ENABLE,
150 UFSHCD_INT_CLEAR,
151 };
152
153 #define ufshcd_set_eh_in_progress(h) \
154 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
155 #define ufshcd_eh_in_progress(h) \
156 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
157 #define ufshcd_clear_eh_in_progress(h) \
158 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
159
160 #define ufshcd_set_ufs_dev_active(h) \
161 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
162 #define ufshcd_set_ufs_dev_sleep(h) \
163 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
164 #define ufshcd_set_ufs_dev_poweroff(h) \
165 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
166 #define ufshcd_is_ufs_dev_active(h) \
167 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
168 #define ufshcd_is_ufs_dev_sleep(h) \
169 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
170 #define ufshcd_is_ufs_dev_poweroff(h) \
171 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
172
173 static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
174 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
175 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
176 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
177 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
178 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
179 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
180 };
181
182 static inline enum ufs_dev_pwr_mode
183 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
184 {
185 return ufs_pm_lvl_states[lvl].dev_state;
186 }
187
188 static inline enum uic_link_state
189 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
190 {
191 return ufs_pm_lvl_states[lvl].link_state;
192 }
193
194 static inline enum ufs_pm_level
195 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
196 enum uic_link_state link_state)
197 {
198 enum ufs_pm_level lvl;
199
200 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
201 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
202 (ufs_pm_lvl_states[lvl].link_state == link_state))
203 return lvl;
204 }
205
206 /* if no match found, return the level 0 */
207 return UFS_PM_LVL_0;
208 }
209
210 static struct ufs_dev_fix ufs_fixups[] = {
211 /* UFS cards deviations table */
212 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
213 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
214 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
215 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
216 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
217 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
218 UFS_DEVICE_NO_FASTAUTO),
219 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
220 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
221 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
222 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
223 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
224 UFS_DEVICE_QUIRK_PA_TACTIVATE),
225 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
226 UFS_DEVICE_QUIRK_PA_TACTIVATE),
227 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
228 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
229 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
230
231 END_FIX
232 };
233
234 static void ufshcd_tmc_handler(struct ufs_hba *hba);
235 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
236 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
237 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
238 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
239 static void ufshcd_hba_exit(struct ufs_hba *hba);
240 static int ufshcd_probe_hba(struct ufs_hba *hba);
241 static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
242 bool skip_ref_clk);
243 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
244 static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
245 static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
246 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
247 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
248 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
249 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
250 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
251 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
252 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
253 static irqreturn_t ufshcd_intr(int irq, void *__hba);
254 static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
255 struct ufs_pa_layer_attr *desired_pwr_mode);
256 static int ufshcd_change_power_mode(struct ufs_hba *hba,
257 struct ufs_pa_layer_attr *pwr_mode);
258 static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
259 {
260 return tag >= 0 && tag < hba->nutrs;
261 }
262
263 static inline int ufshcd_enable_irq(struct ufs_hba *hba)
264 {
265 int ret = 0;
266
267 if (!hba->is_irq_enabled) {
268 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
269 hba);
270 if (ret)
271 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
272 __func__, ret);
273 hba->is_irq_enabled = true;
274 }
275
276 return ret;
277 }
278
279 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
280 {
281 if (hba->is_irq_enabled) {
282 free_irq(hba->irq, hba);
283 hba->is_irq_enabled = false;
284 }
285 }
286
287 /* replace non-printable or non-ASCII characters with spaces */
288 static inline void ufshcd_remove_non_printable(char *val)
289 {
290 if (!val)
291 return;
292
293 if (*val < 0x20 || *val > 0x7e)
294 *val = ' ';
295 }
296
297 static void ufshcd_add_command_trace(struct ufs_hba *hba,
298 unsigned int tag, const char *str)
299 {
300 sector_t lba = -1;
301 u8 opcode = 0;
302 u32 intr, doorbell;
303 struct ufshcd_lrb *lrbp;
304 int transfer_len = -1;
305
306 if (!trace_ufshcd_command_enabled())
307 return;
308
309 lrbp = &hba->lrb[tag];
310
311 if (lrbp->cmd) { /* data phase exists */
312 opcode = (u8)(*lrbp->cmd->cmnd);
313 if ((opcode == READ_10) || (opcode == WRITE_10)) {
314 /*
315 * Currently we only fully trace read(10) and write(10)
316 * commands
317 */
318 if (lrbp->cmd->request && lrbp->cmd->request->bio)
319 lba =
320 lrbp->cmd->request->bio->bi_iter.bi_sector;
321 transfer_len = be32_to_cpu(
322 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
323 }
324 }
325
326 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
327 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
328 trace_ufshcd_command(dev_name(hba->dev), str, tag,
329 doorbell, transfer_len, intr, lba, opcode);
330 }
331
332 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
333 {
334 struct ufs_clk_info *clki;
335 struct list_head *head = &hba->clk_list_head;
336
337 if (!head || list_empty(head))
338 return;
339
340 list_for_each_entry(clki, head, list) {
341 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
342 clki->max_freq)
343 dev_err(hba->dev, "clk: %s, rate: %u\n",
344 clki->name, clki->curr_freq);
345 }
346 }
347
348 static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
349 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
350 {
351 int i;
352
353 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
354 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
355
356 if (err_hist->reg[p] == 0)
357 continue;
358 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
359 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
360 }
361 }
362
363 static void ufshcd_print_host_regs(struct ufs_hba *hba)
364 {
365 /*
366 * hex_dump reads its data without the readl macro. This might
367 * cause inconsistency issues on some platform, as the printed
368 * values may be from cache and not the most recent value.
369 * To know whether you are looking at an un-cached version verify
370 * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked
371 * during platform/pci probe function.
372 */
373 ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE);
374 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
375 hba->ufs_version, hba->capabilities);
376 dev_err(hba->dev,
377 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
378 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
379 dev_err(hba->dev,
380 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
381 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
382 hba->ufs_stats.hibern8_exit_cnt);
383
384 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
385 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
386 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
387 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
388 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
389
390 ufshcd_print_clk_freqs(hba);
391
392 if (hba->vops && hba->vops->dbg_register_dump)
393 hba->vops->dbg_register_dump(hba);
394 }
395
396 static
397 void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
398 {
399 struct ufshcd_lrb *lrbp;
400 int prdt_length;
401 int tag;
402
403 for_each_set_bit(tag, &bitmap, hba->nutrs) {
404 lrbp = &hba->lrb[tag];
405
406 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
407 tag, ktime_to_us(lrbp->issue_time_stamp));
408 dev_err(hba->dev,
409 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
410 tag, (u64)lrbp->utrd_dma_addr);
411
412 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
413 sizeof(struct utp_transfer_req_desc));
414 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
415 (u64)lrbp->ucd_req_dma_addr);
416 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
417 sizeof(struct utp_upiu_req));
418 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
419 (u64)lrbp->ucd_rsp_dma_addr);
420 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
421 sizeof(struct utp_upiu_rsp));
422
423 prdt_length = le16_to_cpu(
424 lrbp->utr_descriptor_ptr->prd_table_length);
425 dev_err(hba->dev,
426 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
427 tag, prdt_length,
428 (u64)lrbp->ucd_prdt_dma_addr);
429
430 if (pr_prdt)
431 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
432 sizeof(struct ufshcd_sg_entry) * prdt_length);
433 }
434 }
435
436 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
437 {
438 struct utp_task_req_desc *tmrdp;
439 int tag;
440
441 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
442 tmrdp = &hba->utmrdl_base_addr[tag];
443 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
444 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
445 sizeof(struct request_desc_header));
446 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
447 tag);
448 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
449 sizeof(struct utp_upiu_req));
450 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
451 tag);
452 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
453 sizeof(struct utp_task_req_desc));
454 }
455 }
456
457 static void ufshcd_print_host_state(struct ufs_hba *hba)
458 {
459 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
460 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
461 hba->lrb_in_use, hba->outstanding_tasks, hba->outstanding_reqs);
462 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
463 hba->saved_err, hba->saved_uic_err);
464 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
465 hba->curr_dev_pwr_mode, hba->uic_link_state);
466 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
467 hba->pm_op_in_progress, hba->is_sys_suspended);
468 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
469 hba->auto_bkops_enabled, hba->host->host_self_blocked);
470 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
471 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
472 hba->eh_flags, hba->req_abort_count);
473 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
474 hba->capabilities, hba->caps);
475 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
476 hba->dev_quirks);
477 }
478
479 /**
480 * ufshcd_print_pwr_info - print power params as saved in hba
481 * power info
482 * @hba: per-adapter instance
483 */
484 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
485 {
486 static const char * const names[] = {
487 "INVALID MODE",
488 "FAST MODE",
489 "SLOW_MODE",
490 "INVALID MODE",
491 "FASTAUTO_MODE",
492 "SLOWAUTO_MODE",
493 "INVALID MODE",
494 };
495
496 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
497 __func__,
498 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
499 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
500 names[hba->pwr_info.pwr_rx],
501 names[hba->pwr_info.pwr_tx],
502 hba->pwr_info.hs_rate);
503 }
504
505 /*
506 * ufshcd_wait_for_register - wait for register value to change
507 * @hba - per-adapter interface
508 * @reg - mmio register offset
509 * @mask - mask to apply to read register value
510 * @val - wait condition
511 * @interval_us - polling interval in microsecs
512 * @timeout_ms - timeout in millisecs
513 * @can_sleep - perform sleep or just spin
514 *
515 * Returns -ETIMEDOUT on error, zero on success
516 */
517 int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
518 u32 val, unsigned long interval_us,
519 unsigned long timeout_ms, bool can_sleep)
520 {
521 int err = 0;
522 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
523
524 /* ignore bits that we don't intend to wait on */
525 val = val & mask;
526
527 while ((ufshcd_readl(hba, reg) & mask) != val) {
528 if (can_sleep)
529 usleep_range(interval_us, interval_us + 50);
530 else
531 udelay(interval_us);
532 if (time_after(jiffies, timeout)) {
533 if ((ufshcd_readl(hba, reg) & mask) != val)
534 err = -ETIMEDOUT;
535 break;
536 }
537 }
538
539 return err;
540 }
541
542 /**
543 * ufshcd_get_intr_mask - Get the interrupt bit mask
544 * @hba - Pointer to adapter instance
545 *
546 * Returns interrupt bit mask per version
547 */
548 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
549 {
550 u32 intr_mask = 0;
551
552 switch (hba->ufs_version) {
553 case UFSHCI_VERSION_10:
554 intr_mask = INTERRUPT_MASK_ALL_VER_10;
555 break;
556 /* allow fall through */
557 case UFSHCI_VERSION_11:
558 case UFSHCI_VERSION_20:
559 intr_mask = INTERRUPT_MASK_ALL_VER_11;
560 break;
561 /* allow fall through */
562 case UFSHCI_VERSION_21:
563 default:
564 intr_mask = INTERRUPT_MASK_ALL_VER_21;
565 }
566
567 return intr_mask;
568 }
569
570 /**
571 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
572 * @hba - Pointer to adapter instance
573 *
574 * Returns UFSHCI version supported by the controller
575 */
576 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
577 {
578 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
579 return ufshcd_vops_get_ufs_hci_version(hba);
580
581 return ufshcd_readl(hba, REG_UFS_VERSION);
582 }
583
584 /**
585 * ufshcd_is_device_present - Check if any device connected to
586 * the host controller
587 * @hba: pointer to adapter instance
588 *
589 * Returns 1 if device present, 0 if no device detected
590 */
591 static inline int ufshcd_is_device_present(struct ufs_hba *hba)
592 {
593 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
594 DEVICE_PRESENT) ? 1 : 0;
595 }
596
597 /**
598 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
599 * @lrb: pointer to local command reference block
600 *
601 * This function is used to get the OCS field from UTRD
602 * Returns the OCS field in the UTRD
603 */
604 static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
605 {
606 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
607 }
608
609 /**
610 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
611 * @task_req_descp: pointer to utp_task_req_desc structure
612 *
613 * This function is used to get the OCS field from UTMRD
614 * Returns the OCS field in the UTMRD
615 */
616 static inline int
617 ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
618 {
619 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
620 }
621
622 /**
623 * ufshcd_get_tm_free_slot - get a free slot for task management request
624 * @hba: per adapter instance
625 * @free_slot: pointer to variable with available slot value
626 *
627 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
628 * Returns 0 if free slot is not available, else return 1 with tag value
629 * in @free_slot.
630 */
631 static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
632 {
633 int tag;
634 bool ret = false;
635
636 if (!free_slot)
637 goto out;
638
639 do {
640 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
641 if (tag >= hba->nutmrs)
642 goto out;
643 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
644
645 *free_slot = tag;
646 ret = true;
647 out:
648 return ret;
649 }
650
651 static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
652 {
653 clear_bit_unlock(slot, &hba->tm_slots_in_use);
654 }
655
656 /**
657 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
658 * @hba: per adapter instance
659 * @pos: position of the bit to be cleared
660 */
661 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
662 {
663 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
664 }
665
666 /**
667 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
668 * @hba: per adapter instance
669 * @tag: position of the bit to be cleared
670 */
671 static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
672 {
673 __clear_bit(tag, &hba->outstanding_reqs);
674 }
675
676 /**
677 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
678 * @reg: Register value of host controller status
679 *
680 * Returns integer, 0 on Success and positive value if failed
681 */
682 static inline int ufshcd_get_lists_status(u32 reg)
683 {
684 /*
685 * The mask 0xFF is for the following HCS register bits
686 * Bit Description
687 * 0 Device Present
688 * 1 UTRLRDY
689 * 2 UTMRLRDY
690 * 3 UCRDY
691 * 4-7 reserved
692 */
693 return ((reg & 0xFF) >> 1) ^ 0x07;
694 }
695
696 /**
697 * ufshcd_get_uic_cmd_result - Get the UIC command result
698 * @hba: Pointer to adapter instance
699 *
700 * This function gets the result of UIC command completion
701 * Returns 0 on success, non zero value on error
702 */
703 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
704 {
705 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
706 MASK_UIC_COMMAND_RESULT;
707 }
708
709 /**
710 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
711 * @hba: Pointer to adapter instance
712 *
713 * This function gets UIC command argument3
714 * Returns 0 on success, non zero value on error
715 */
716 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
717 {
718 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
719 }
720
721 /**
722 * ufshcd_get_req_rsp - returns the TR response transaction type
723 * @ucd_rsp_ptr: pointer to response UPIU
724 */
725 static inline int
726 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
727 {
728 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
729 }
730
731 /**
732 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
733 * @ucd_rsp_ptr: pointer to response UPIU
734 *
735 * This function gets the response status and scsi_status from response UPIU
736 * Returns the response result code.
737 */
738 static inline int
739 ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
740 {
741 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
742 }
743
744 /*
745 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
746 * from response UPIU
747 * @ucd_rsp_ptr: pointer to response UPIU
748 *
749 * Return the data segment length.
750 */
751 static inline unsigned int
752 ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
753 {
754 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
755 MASK_RSP_UPIU_DATA_SEG_LEN;
756 }
757
758 /**
759 * ufshcd_is_exception_event - Check if the device raised an exception event
760 * @ucd_rsp_ptr: pointer to response UPIU
761 *
762 * The function checks if the device raised an exception event indicated in
763 * the Device Information field of response UPIU.
764 *
765 * Returns true if exception is raised, false otherwise.
766 */
767 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
768 {
769 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
770 MASK_RSP_EXCEPTION_EVENT ? true : false;
771 }
772
773 /**
774 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
775 * @hba: per adapter instance
776 */
777 static inline void
778 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
779 {
780 ufshcd_writel(hba, INT_AGGR_ENABLE |
781 INT_AGGR_COUNTER_AND_TIMER_RESET,
782 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
783 }
784
785 /**
786 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
787 * @hba: per adapter instance
788 * @cnt: Interrupt aggregation counter threshold
789 * @tmout: Interrupt aggregation timeout value
790 */
791 static inline void
792 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
793 {
794 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
795 INT_AGGR_COUNTER_THLD_VAL(cnt) |
796 INT_AGGR_TIMEOUT_VAL(tmout),
797 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
798 }
799
800 /**
801 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
802 * @hba: per adapter instance
803 */
804 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
805 {
806 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
807 }
808
809 /**
810 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
811 * When run-stop registers are set to 1, it indicates the
812 * host controller that it can process the requests
813 * @hba: per adapter instance
814 */
815 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
816 {
817 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
818 REG_UTP_TASK_REQ_LIST_RUN_STOP);
819 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
820 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
821 }
822
823 /**
824 * ufshcd_hba_start - Start controller initialization sequence
825 * @hba: per adapter instance
826 */
827 static inline void ufshcd_hba_start(struct ufs_hba *hba)
828 {
829 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
830 }
831
832 /**
833 * ufshcd_is_hba_active - Get controller state
834 * @hba: per adapter instance
835 *
836 * Returns zero if controller is active, 1 otherwise
837 */
838 static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
839 {
840 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
841 }
842
843 static const char *ufschd_uic_link_state_to_string(
844 enum uic_link_state state)
845 {
846 switch (state) {
847 case UIC_LINK_OFF_STATE: return "OFF";
848 case UIC_LINK_ACTIVE_STATE: return "ACTIVE";
849 case UIC_LINK_HIBERN8_STATE: return "HIBERN8";
850 default: return "UNKNOWN";
851 }
852 }
853
854 static const char *ufschd_ufs_dev_pwr_mode_to_string(
855 enum ufs_dev_pwr_mode state)
856 {
857 switch (state) {
858 case UFS_ACTIVE_PWR_MODE: return "ACTIVE";
859 case UFS_SLEEP_PWR_MODE: return "SLEEP";
860 case UFS_POWERDOWN_PWR_MODE: return "POWERDOWN";
861 default: return "UNKNOWN";
862 }
863 }
864
865 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
866 {
867 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
868 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
869 (hba->ufs_version == UFSHCI_VERSION_11))
870 return UFS_UNIPRO_VER_1_41;
871 else
872 return UFS_UNIPRO_VER_1_6;
873 }
874 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
875
876 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
877 {
878 /*
879 * If both host and device support UniPro ver1.6 or later, PA layer
880 * parameters tuning happens during link startup itself.
881 *
882 * We can manually tune PA layer parameters if either host or device
883 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
884 * logic simple, we will only do manual tuning if local unipro version
885 * doesn't support ver1.6 or later.
886 */
887 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
888 return true;
889 else
890 return false;
891 }
892
893 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
894 {
895 int ret = 0;
896 struct ufs_clk_info *clki;
897 struct list_head *head = &hba->clk_list_head;
898 ktime_t start = ktime_get();
899 bool clk_state_changed = false;
900
901 if (!head || list_empty(head))
902 goto out;
903
904 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
905 if (ret)
906 return ret;
907
908 list_for_each_entry(clki, head, list) {
909 if (!IS_ERR_OR_NULL(clki->clk)) {
910 if (scale_up && clki->max_freq) {
911 if (clki->curr_freq == clki->max_freq)
912 continue;
913
914 clk_state_changed = true;
915 ret = clk_set_rate(clki->clk, clki->max_freq);
916 if (ret) {
917 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
918 __func__, clki->name,
919 clki->max_freq, ret);
920 break;
921 }
922 trace_ufshcd_clk_scaling(dev_name(hba->dev),
923 "scaled up", clki->name,
924 clki->curr_freq,
925 clki->max_freq);
926
927 clki->curr_freq = clki->max_freq;
928
929 } else if (!scale_up && clki->min_freq) {
930 if (clki->curr_freq == clki->min_freq)
931 continue;
932
933 clk_state_changed = true;
934 ret = clk_set_rate(clki->clk, clki->min_freq);
935 if (ret) {
936 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
937 __func__, clki->name,
938 clki->min_freq, ret);
939 break;
940 }
941 trace_ufshcd_clk_scaling(dev_name(hba->dev),
942 "scaled down", clki->name,
943 clki->curr_freq,
944 clki->min_freq);
945 clki->curr_freq = clki->min_freq;
946 }
947 }
948 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
949 clki->name, clk_get_rate(clki->clk));
950 }
951
952 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
953
954 out:
955 if (clk_state_changed)
956 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
957 (scale_up ? "up" : "down"),
958 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
959 return ret;
960 }
961
962 /**
963 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
964 * @hba: per adapter instance
965 * @scale_up: True if scaling up and false if scaling down
966 *
967 * Returns true if scaling is required, false otherwise.
968 */
969 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
970 bool scale_up)
971 {
972 struct ufs_clk_info *clki;
973 struct list_head *head = &hba->clk_list_head;
974
975 if (!head || list_empty(head))
976 return false;
977
978 list_for_each_entry(clki, head, list) {
979 if (!IS_ERR_OR_NULL(clki->clk)) {
980 if (scale_up && clki->max_freq) {
981 if (clki->curr_freq == clki->max_freq)
982 continue;
983 return true;
984 } else if (!scale_up && clki->min_freq) {
985 if (clki->curr_freq == clki->min_freq)
986 continue;
987 return true;
988 }
989 }
990 }
991
992 return false;
993 }
994
995 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
996 u64 wait_timeout_us)
997 {
998 unsigned long flags;
999 int ret = 0;
1000 u32 tm_doorbell;
1001 u32 tr_doorbell;
1002 bool timeout = false, do_last_check = false;
1003 ktime_t start;
1004
1005 ufshcd_hold(hba, false);
1006 spin_lock_irqsave(hba->host->host_lock, flags);
1007 /*
1008 * Wait for all the outstanding tasks/transfer requests.
1009 * Verify by checking the doorbell registers are clear.
1010 */
1011 start = ktime_get();
1012 do {
1013 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1014 ret = -EBUSY;
1015 goto out;
1016 }
1017
1018 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1019 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1020 if (!tm_doorbell && !tr_doorbell) {
1021 timeout = false;
1022 break;
1023 } else if (do_last_check) {
1024 break;
1025 }
1026
1027 spin_unlock_irqrestore(hba->host->host_lock, flags);
1028 schedule();
1029 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1030 wait_timeout_us) {
1031 timeout = true;
1032 /*
1033 * We might have scheduled out for long time so make
1034 * sure to check if doorbells are cleared by this time
1035 * or not.
1036 */
1037 do_last_check = true;
1038 }
1039 spin_lock_irqsave(hba->host->host_lock, flags);
1040 } while (tm_doorbell || tr_doorbell);
1041
1042 if (timeout) {
1043 dev_err(hba->dev,
1044 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1045 __func__, tm_doorbell, tr_doorbell);
1046 ret = -EBUSY;
1047 }
1048 out:
1049 spin_unlock_irqrestore(hba->host->host_lock, flags);
1050 ufshcd_release(hba);
1051 return ret;
1052 }
1053
1054 /**
1055 * ufshcd_scale_gear - scale up/down UFS gear
1056 * @hba: per adapter instance
1057 * @scale_up: True for scaling up gear and false for scaling down
1058 *
1059 * Returns 0 for success,
1060 * Returns -EBUSY if scaling can't happen at this time
1061 * Returns non-zero for any other errors
1062 */
1063 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1064 {
1065 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1066 int ret = 0;
1067 struct ufs_pa_layer_attr new_pwr_info;
1068
1069 if (scale_up) {
1070 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1071 sizeof(struct ufs_pa_layer_attr));
1072 } else {
1073 memcpy(&new_pwr_info, &hba->pwr_info,
1074 sizeof(struct ufs_pa_layer_attr));
1075
1076 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1077 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1078 /* save the current power mode */
1079 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1080 &hba->pwr_info,
1081 sizeof(struct ufs_pa_layer_attr));
1082
1083 /* scale down gear */
1084 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1085 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1086 }
1087 }
1088
1089 /* check if the power mode needs to be changed or not? */
1090 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1091
1092 if (ret)
1093 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1094 __func__, ret,
1095 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1096 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1097
1098 return ret;
1099 }
1100
1101 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1102 {
1103 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1104 int ret = 0;
1105 /*
1106 * make sure that there are no outstanding requests when
1107 * clock scaling is in progress
1108 */
1109 scsi_block_requests(hba->host);
1110 down_write(&hba->clk_scaling_lock);
1111 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1112 ret = -EBUSY;
1113 up_write(&hba->clk_scaling_lock);
1114 scsi_unblock_requests(hba->host);
1115 }
1116
1117 return ret;
1118 }
1119
1120 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1121 {
1122 up_write(&hba->clk_scaling_lock);
1123 scsi_unblock_requests(hba->host);
1124 }
1125
1126 /**
1127 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1128 * @hba: per adapter instance
1129 * @scale_up: True for scaling up and false for scalin down
1130 *
1131 * Returns 0 for success,
1132 * Returns -EBUSY if scaling can't happen at this time
1133 * Returns non-zero for any other errors
1134 */
1135 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1136 {
1137 int ret = 0;
1138
1139 /* let's not get into low power until clock scaling is completed */
1140 ufshcd_hold(hba, false);
1141
1142 ret = ufshcd_clock_scaling_prepare(hba);
1143 if (ret)
1144 return ret;
1145
1146 /* scale down the gear before scaling down clocks */
1147 if (!scale_up) {
1148 ret = ufshcd_scale_gear(hba, false);
1149 if (ret)
1150 goto out;
1151 }
1152
1153 ret = ufshcd_scale_clks(hba, scale_up);
1154 if (ret) {
1155 if (!scale_up)
1156 ufshcd_scale_gear(hba, true);
1157 goto out;
1158 }
1159
1160 /* scale up the gear after scaling up clocks */
1161 if (scale_up) {
1162 ret = ufshcd_scale_gear(hba, true);
1163 if (ret) {
1164 ufshcd_scale_clks(hba, false);
1165 goto out;
1166 }
1167 }
1168
1169 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1170
1171 out:
1172 ufshcd_clock_scaling_unprepare(hba);
1173 ufshcd_release(hba);
1174 return ret;
1175 }
1176
1177 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1178 {
1179 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1180 clk_scaling.suspend_work);
1181 unsigned long irq_flags;
1182
1183 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1184 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1185 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1186 return;
1187 }
1188 hba->clk_scaling.is_suspended = true;
1189 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1190
1191 __ufshcd_suspend_clkscaling(hba);
1192 }
1193
1194 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1195 {
1196 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1197 clk_scaling.resume_work);
1198 unsigned long irq_flags;
1199
1200 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1201 if (!hba->clk_scaling.is_suspended) {
1202 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1203 return;
1204 }
1205 hba->clk_scaling.is_suspended = false;
1206 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1207
1208 devfreq_resume_device(hba->devfreq);
1209 }
1210
1211 static int ufshcd_devfreq_target(struct device *dev,
1212 unsigned long *freq, u32 flags)
1213 {
1214 int ret = 0;
1215 struct ufs_hba *hba = dev_get_drvdata(dev);
1216 ktime_t start;
1217 bool scale_up, sched_clk_scaling_suspend_work = false;
1218 unsigned long irq_flags;
1219
1220 if (!ufshcd_is_clkscaling_supported(hba))
1221 return -EINVAL;
1222
1223 if ((*freq > 0) && (*freq < UINT_MAX)) {
1224 dev_err(hba->dev, "%s: invalid freq = %lu\n", __func__, *freq);
1225 return -EINVAL;
1226 }
1227
1228 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1229 if (ufshcd_eh_in_progress(hba)) {
1230 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1231 return 0;
1232 }
1233
1234 if (!hba->clk_scaling.active_reqs)
1235 sched_clk_scaling_suspend_work = true;
1236
1237 scale_up = (*freq == UINT_MAX) ? true : false;
1238 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1239 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1240 ret = 0;
1241 goto out; /* no state change required */
1242 }
1243 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1244
1245 start = ktime_get();
1246 ret = ufshcd_devfreq_scale(hba, scale_up);
1247
1248 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1249 (scale_up ? "up" : "down"),
1250 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1251
1252 out:
1253 if (sched_clk_scaling_suspend_work)
1254 queue_work(hba->clk_scaling.workq,
1255 &hba->clk_scaling.suspend_work);
1256
1257 return ret;
1258 }
1259
1260
1261 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1262 struct devfreq_dev_status *stat)
1263 {
1264 struct ufs_hba *hba = dev_get_drvdata(dev);
1265 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1266 unsigned long flags;
1267
1268 if (!ufshcd_is_clkscaling_supported(hba))
1269 return -EINVAL;
1270
1271 memset(stat, 0, sizeof(*stat));
1272
1273 spin_lock_irqsave(hba->host->host_lock, flags);
1274 if (!scaling->window_start_t)
1275 goto start_window;
1276
1277 if (scaling->is_busy_started)
1278 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1279 scaling->busy_start_t));
1280
1281 stat->total_time = jiffies_to_usecs((long)jiffies -
1282 (long)scaling->window_start_t);
1283 stat->busy_time = scaling->tot_busy_t;
1284 start_window:
1285 scaling->window_start_t = jiffies;
1286 scaling->tot_busy_t = 0;
1287
1288 if (hba->outstanding_reqs) {
1289 scaling->busy_start_t = ktime_get();
1290 scaling->is_busy_started = true;
1291 } else {
1292 scaling->busy_start_t = 0;
1293 scaling->is_busy_started = false;
1294 }
1295 spin_unlock_irqrestore(hba->host->host_lock, flags);
1296 return 0;
1297 }
1298
1299 static struct devfreq_dev_profile ufs_devfreq_profile = {
1300 .polling_ms = 100,
1301 .target = ufshcd_devfreq_target,
1302 .get_dev_status = ufshcd_devfreq_get_dev_status,
1303 };
1304
1305 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1306 {
1307 unsigned long flags;
1308
1309 devfreq_suspend_device(hba->devfreq);
1310 spin_lock_irqsave(hba->host->host_lock, flags);
1311 hba->clk_scaling.window_start_t = 0;
1312 spin_unlock_irqrestore(hba->host->host_lock, flags);
1313 }
1314
1315 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1316 {
1317 unsigned long flags;
1318 bool suspend = false;
1319
1320 if (!ufshcd_is_clkscaling_supported(hba))
1321 return;
1322
1323 spin_lock_irqsave(hba->host->host_lock, flags);
1324 if (!hba->clk_scaling.is_suspended) {
1325 suspend = true;
1326 hba->clk_scaling.is_suspended = true;
1327 }
1328 spin_unlock_irqrestore(hba->host->host_lock, flags);
1329
1330 if (suspend)
1331 __ufshcd_suspend_clkscaling(hba);
1332 }
1333
1334 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1335 {
1336 unsigned long flags;
1337 bool resume = false;
1338
1339 if (!ufshcd_is_clkscaling_supported(hba))
1340 return;
1341
1342 spin_lock_irqsave(hba->host->host_lock, flags);
1343 if (hba->clk_scaling.is_suspended) {
1344 resume = true;
1345 hba->clk_scaling.is_suspended = false;
1346 }
1347 spin_unlock_irqrestore(hba->host->host_lock, flags);
1348
1349 if (resume)
1350 devfreq_resume_device(hba->devfreq);
1351 }
1352
1353 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1354 struct device_attribute *attr, char *buf)
1355 {
1356 struct ufs_hba *hba = dev_get_drvdata(dev);
1357
1358 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1359 }
1360
1361 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1362 struct device_attribute *attr, const char *buf, size_t count)
1363 {
1364 struct ufs_hba *hba = dev_get_drvdata(dev);
1365 u32 value;
1366 int err;
1367
1368 if (kstrtou32(buf, 0, &value))
1369 return -EINVAL;
1370
1371 value = !!value;
1372 if (value == hba->clk_scaling.is_allowed)
1373 goto out;
1374
1375 pm_runtime_get_sync(hba->dev);
1376 ufshcd_hold(hba, false);
1377
1378 cancel_work_sync(&hba->clk_scaling.suspend_work);
1379 cancel_work_sync(&hba->clk_scaling.resume_work);
1380
1381 hba->clk_scaling.is_allowed = value;
1382
1383 if (value) {
1384 ufshcd_resume_clkscaling(hba);
1385 } else {
1386 ufshcd_suspend_clkscaling(hba);
1387 err = ufshcd_devfreq_scale(hba, true);
1388 if (err)
1389 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1390 __func__, err);
1391 }
1392
1393 ufshcd_release(hba);
1394 pm_runtime_put_sync(hba->dev);
1395 out:
1396 return count;
1397 }
1398
1399 static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1400 {
1401 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1402 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1403 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1404 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1405 hba->clk_scaling.enable_attr.attr.mode = 0644;
1406 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1407 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1408 }
1409
1410 static void ufshcd_ungate_work(struct work_struct *work)
1411 {
1412 int ret;
1413 unsigned long flags;
1414 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1415 clk_gating.ungate_work);
1416
1417 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1418
1419 spin_lock_irqsave(hba->host->host_lock, flags);
1420 if (hba->clk_gating.state == CLKS_ON) {
1421 spin_unlock_irqrestore(hba->host->host_lock, flags);
1422 goto unblock_reqs;
1423 }
1424
1425 spin_unlock_irqrestore(hba->host->host_lock, flags);
1426 ufshcd_setup_clocks(hba, true);
1427
1428 /* Exit from hibern8 */
1429 if (ufshcd_can_hibern8_during_gating(hba)) {
1430 /* Prevent gating in this path */
1431 hba->clk_gating.is_suspended = true;
1432 if (ufshcd_is_link_hibern8(hba)) {
1433 ret = ufshcd_uic_hibern8_exit(hba);
1434 if (ret)
1435 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1436 __func__, ret);
1437 else
1438 ufshcd_set_link_active(hba);
1439 }
1440 hba->clk_gating.is_suspended = false;
1441 }
1442 unblock_reqs:
1443 scsi_unblock_requests(hba->host);
1444 }
1445
1446 /**
1447 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1448 * Also, exit from hibern8 mode and set the link as active.
1449 * @hba: per adapter instance
1450 * @async: This indicates whether caller should ungate clocks asynchronously.
1451 */
1452 int ufshcd_hold(struct ufs_hba *hba, bool async)
1453 {
1454 int rc = 0;
1455 unsigned long flags;
1456
1457 if (!ufshcd_is_clkgating_allowed(hba))
1458 goto out;
1459 spin_lock_irqsave(hba->host->host_lock, flags);
1460 hba->clk_gating.active_reqs++;
1461
1462 if (ufshcd_eh_in_progress(hba)) {
1463 spin_unlock_irqrestore(hba->host->host_lock, flags);
1464 return 0;
1465 }
1466
1467 start:
1468 switch (hba->clk_gating.state) {
1469 case CLKS_ON:
1470 /*
1471 * Wait for the ungate work to complete if in progress.
1472 * Though the clocks may be in ON state, the link could
1473 * still be in hibner8 state if hibern8 is allowed
1474 * during clock gating.
1475 * Make sure we exit hibern8 state also in addition to
1476 * clocks being ON.
1477 */
1478 if (ufshcd_can_hibern8_during_gating(hba) &&
1479 ufshcd_is_link_hibern8(hba)) {
1480 spin_unlock_irqrestore(hba->host->host_lock, flags);
1481 flush_work(&hba->clk_gating.ungate_work);
1482 spin_lock_irqsave(hba->host->host_lock, flags);
1483 goto start;
1484 }
1485 break;
1486 case REQ_CLKS_OFF:
1487 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1488 hba->clk_gating.state = CLKS_ON;
1489 trace_ufshcd_clk_gating(dev_name(hba->dev),
1490 hba->clk_gating.state);
1491 break;
1492 }
1493 /*
1494 * If we here, it means gating work is either done or
1495 * currently running. Hence, fall through to cancel gating
1496 * work and to enable clocks.
1497 */
1498 case CLKS_OFF:
1499 scsi_block_requests(hba->host);
1500 hba->clk_gating.state = REQ_CLKS_ON;
1501 trace_ufshcd_clk_gating(dev_name(hba->dev),
1502 hba->clk_gating.state);
1503 schedule_work(&hba->clk_gating.ungate_work);
1504 /*
1505 * fall through to check if we should wait for this
1506 * work to be done or not.
1507 */
1508 case REQ_CLKS_ON:
1509 if (async) {
1510 rc = -EAGAIN;
1511 hba->clk_gating.active_reqs--;
1512 break;
1513 }
1514
1515 spin_unlock_irqrestore(hba->host->host_lock, flags);
1516 flush_work(&hba->clk_gating.ungate_work);
1517 /* Make sure state is CLKS_ON before returning */
1518 spin_lock_irqsave(hba->host->host_lock, flags);
1519 goto start;
1520 default:
1521 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1522 __func__, hba->clk_gating.state);
1523 break;
1524 }
1525 spin_unlock_irqrestore(hba->host->host_lock, flags);
1526 out:
1527 return rc;
1528 }
1529 EXPORT_SYMBOL_GPL(ufshcd_hold);
1530
1531 static void ufshcd_gate_work(struct work_struct *work)
1532 {
1533 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1534 clk_gating.gate_work.work);
1535 unsigned long flags;
1536
1537 spin_lock_irqsave(hba->host->host_lock, flags);
1538 /*
1539 * In case you are here to cancel this work the gating state
1540 * would be marked as REQ_CLKS_ON. In this case save time by
1541 * skipping the gating work and exit after changing the clock
1542 * state to CLKS_ON.
1543 */
1544 if (hba->clk_gating.is_suspended ||
1545 (hba->clk_gating.state == REQ_CLKS_ON)) {
1546 hba->clk_gating.state = CLKS_ON;
1547 trace_ufshcd_clk_gating(dev_name(hba->dev),
1548 hba->clk_gating.state);
1549 goto rel_lock;
1550 }
1551
1552 if (hba->clk_gating.active_reqs
1553 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1554 || hba->lrb_in_use || hba->outstanding_tasks
1555 || hba->active_uic_cmd || hba->uic_async_done)
1556 goto rel_lock;
1557
1558 spin_unlock_irqrestore(hba->host->host_lock, flags);
1559
1560 /* put the link into hibern8 mode before turning off clocks */
1561 if (ufshcd_can_hibern8_during_gating(hba)) {
1562 if (ufshcd_uic_hibern8_enter(hba)) {
1563 hba->clk_gating.state = CLKS_ON;
1564 trace_ufshcd_clk_gating(dev_name(hba->dev),
1565 hba->clk_gating.state);
1566 goto out;
1567 }
1568 ufshcd_set_link_hibern8(hba);
1569 }
1570
1571 if (!ufshcd_is_link_active(hba))
1572 ufshcd_setup_clocks(hba, false);
1573 else
1574 /* If link is active, device ref_clk can't be switched off */
1575 __ufshcd_setup_clocks(hba, false, true);
1576
1577 /*
1578 * In case you are here to cancel this work the gating state
1579 * would be marked as REQ_CLKS_ON. In this case keep the state
1580 * as REQ_CLKS_ON which would anyway imply that clocks are off
1581 * and a request to turn them on is pending. By doing this way,
1582 * we keep the state machine in tact and this would ultimately
1583 * prevent from doing cancel work multiple times when there are
1584 * new requests arriving before the current cancel work is done.
1585 */
1586 spin_lock_irqsave(hba->host->host_lock, flags);
1587 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1588 hba->clk_gating.state = CLKS_OFF;
1589 trace_ufshcd_clk_gating(dev_name(hba->dev),
1590 hba->clk_gating.state);
1591 }
1592 rel_lock:
1593 spin_unlock_irqrestore(hba->host->host_lock, flags);
1594 out:
1595 return;
1596 }
1597
1598 /* host lock must be held before calling this variant */
1599 static void __ufshcd_release(struct ufs_hba *hba)
1600 {
1601 if (!ufshcd_is_clkgating_allowed(hba))
1602 return;
1603
1604 hba->clk_gating.active_reqs--;
1605
1606 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1607 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1608 || hba->lrb_in_use || hba->outstanding_tasks
1609 || hba->active_uic_cmd || hba->uic_async_done
1610 || ufshcd_eh_in_progress(hba))
1611 return;
1612
1613 hba->clk_gating.state = REQ_CLKS_OFF;
1614 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1615 schedule_delayed_work(&hba->clk_gating.gate_work,
1616 msecs_to_jiffies(hba->clk_gating.delay_ms));
1617 }
1618
1619 void ufshcd_release(struct ufs_hba *hba)
1620 {
1621 unsigned long flags;
1622
1623 spin_lock_irqsave(hba->host->host_lock, flags);
1624 __ufshcd_release(hba);
1625 spin_unlock_irqrestore(hba->host->host_lock, flags);
1626 }
1627 EXPORT_SYMBOL_GPL(ufshcd_release);
1628
1629 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1630 struct device_attribute *attr, char *buf)
1631 {
1632 struct ufs_hba *hba = dev_get_drvdata(dev);
1633
1634 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1635 }
1636
1637 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1638 struct device_attribute *attr, const char *buf, size_t count)
1639 {
1640 struct ufs_hba *hba = dev_get_drvdata(dev);
1641 unsigned long flags, value;
1642
1643 if (kstrtoul(buf, 0, &value))
1644 return -EINVAL;
1645
1646 spin_lock_irqsave(hba->host->host_lock, flags);
1647 hba->clk_gating.delay_ms = value;
1648 spin_unlock_irqrestore(hba->host->host_lock, flags);
1649 return count;
1650 }
1651
1652 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1653 struct device_attribute *attr, char *buf)
1654 {
1655 struct ufs_hba *hba = dev_get_drvdata(dev);
1656
1657 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1658 }
1659
1660 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1661 struct device_attribute *attr, const char *buf, size_t count)
1662 {
1663 struct ufs_hba *hba = dev_get_drvdata(dev);
1664 unsigned long flags;
1665 u32 value;
1666
1667 if (kstrtou32(buf, 0, &value))
1668 return -EINVAL;
1669
1670 value = !!value;
1671 if (value == hba->clk_gating.is_enabled)
1672 goto out;
1673
1674 if (value) {
1675 ufshcd_release(hba);
1676 } else {
1677 spin_lock_irqsave(hba->host->host_lock, flags);
1678 hba->clk_gating.active_reqs++;
1679 spin_unlock_irqrestore(hba->host->host_lock, flags);
1680 }
1681
1682 hba->clk_gating.is_enabled = value;
1683 out:
1684 return count;
1685 }
1686
1687 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1688 {
1689 if (!ufshcd_is_clkgating_allowed(hba))
1690 return;
1691
1692 hba->clk_gating.delay_ms = 150;
1693 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1694 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1695
1696 hba->clk_gating.is_enabled = true;
1697
1698 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1699 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1700 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1701 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1702 hba->clk_gating.delay_attr.attr.mode = 0644;
1703 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1704 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1705
1706 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1707 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1708 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1709 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1710 hba->clk_gating.enable_attr.attr.mode = 0644;
1711 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1712 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1713 }
1714
1715 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1716 {
1717 if (!ufshcd_is_clkgating_allowed(hba))
1718 return;
1719 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1720 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1721 cancel_work_sync(&hba->clk_gating.ungate_work);
1722 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1723 }
1724
1725 /* Must be called with host lock acquired */
1726 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1727 {
1728 bool queue_resume_work = false;
1729
1730 if (!ufshcd_is_clkscaling_supported(hba))
1731 return;
1732
1733 if (!hba->clk_scaling.active_reqs++)
1734 queue_resume_work = true;
1735
1736 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1737 return;
1738
1739 if (queue_resume_work)
1740 queue_work(hba->clk_scaling.workq,
1741 &hba->clk_scaling.resume_work);
1742
1743 if (!hba->clk_scaling.window_start_t) {
1744 hba->clk_scaling.window_start_t = jiffies;
1745 hba->clk_scaling.tot_busy_t = 0;
1746 hba->clk_scaling.is_busy_started = false;
1747 }
1748
1749 if (!hba->clk_scaling.is_busy_started) {
1750 hba->clk_scaling.busy_start_t = ktime_get();
1751 hba->clk_scaling.is_busy_started = true;
1752 }
1753 }
1754
1755 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1756 {
1757 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1758
1759 if (!ufshcd_is_clkscaling_supported(hba))
1760 return;
1761
1762 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1763 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1764 scaling->busy_start_t));
1765 scaling->busy_start_t = 0;
1766 scaling->is_busy_started = false;
1767 }
1768 }
1769 /**
1770 * ufshcd_send_command - Send SCSI or device management commands
1771 * @hba: per adapter instance
1772 * @task_tag: Task tag of the command
1773 */
1774 static inline
1775 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1776 {
1777 hba->lrb[task_tag].issue_time_stamp = ktime_get();
1778 ufshcd_clk_scaling_start_busy(hba);
1779 __set_bit(task_tag, &hba->outstanding_reqs);
1780 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1781 /* Make sure that doorbell is committed immediately */
1782 wmb();
1783 ufshcd_add_command_trace(hba, task_tag, "send");
1784 }
1785
1786 /**
1787 * ufshcd_copy_sense_data - Copy sense data in case of check condition
1788 * @lrb - pointer to local reference block
1789 */
1790 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1791 {
1792 int len;
1793 if (lrbp->sense_buffer &&
1794 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
1795 int len_to_copy;
1796
1797 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
1798 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1799
1800 memcpy(lrbp->sense_buffer,
1801 lrbp->ucd_rsp_ptr->sr.sense_data,
1802 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
1803 }
1804 }
1805
1806 /**
1807 * ufshcd_copy_query_response() - Copy the Query Response and the data
1808 * descriptor
1809 * @hba: per adapter instance
1810 * @lrb - pointer to local reference block
1811 */
1812 static
1813 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1814 {
1815 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1816
1817 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
1818
1819 /* Get the descriptor */
1820 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
1821 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
1822 GENERAL_UPIU_REQUEST_SIZE;
1823 u16 resp_len;
1824 u16 buf_len;
1825
1826 /* data segment length */
1827 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
1828 MASK_QUERY_DATA_SEG_LEN;
1829 buf_len = be16_to_cpu(
1830 hba->dev_cmd.query.request.upiu_req.length);
1831 if (likely(buf_len >= resp_len)) {
1832 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1833 } else {
1834 dev_warn(hba->dev,
1835 "%s: Response size is bigger than buffer",
1836 __func__);
1837 return -EINVAL;
1838 }
1839 }
1840
1841 return 0;
1842 }
1843
1844 /**
1845 * ufshcd_hba_capabilities - Read controller capabilities
1846 * @hba: per adapter instance
1847 */
1848 static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1849 {
1850 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
1851
1852 /* nutrs and nutmrs are 0 based values */
1853 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1854 hba->nutmrs =
1855 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1856 }
1857
1858 /**
1859 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1860 * to accept UIC commands
1861 * @hba: per adapter instance
1862 * Return true on success, else false
1863 */
1864 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1865 {
1866 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1867 return true;
1868 else
1869 return false;
1870 }
1871
1872 /**
1873 * ufshcd_get_upmcrs - Get the power mode change request status
1874 * @hba: Pointer to adapter instance
1875 *
1876 * This function gets the UPMCRS field of HCS register
1877 * Returns value of UPMCRS field
1878 */
1879 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1880 {
1881 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1882 }
1883
1884 /**
1885 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1886 * @hba: per adapter instance
1887 * @uic_cmd: UIC command
1888 *
1889 * Mutex must be held.
1890 */
1891 static inline void
1892 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1893 {
1894 WARN_ON(hba->active_uic_cmd);
1895
1896 hba->active_uic_cmd = uic_cmd;
1897
1898 /* Write Args */
1899 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1900 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1901 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
1902
1903 /* Write UIC Cmd */
1904 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
1905 REG_UIC_COMMAND);
1906 }
1907
1908 /**
1909 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1910 * @hba: per adapter instance
1911 * @uic_command: UIC command
1912 *
1913 * Must be called with mutex held.
1914 * Returns 0 only if success.
1915 */
1916 static int
1917 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1918 {
1919 int ret;
1920 unsigned long flags;
1921
1922 if (wait_for_completion_timeout(&uic_cmd->done,
1923 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1924 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1925 else
1926 ret = -ETIMEDOUT;
1927
1928 spin_lock_irqsave(hba->host->host_lock, flags);
1929 hba->active_uic_cmd = NULL;
1930 spin_unlock_irqrestore(hba->host->host_lock, flags);
1931
1932 return ret;
1933 }
1934
1935 /**
1936 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1937 * @hba: per adapter instance
1938 * @uic_cmd: UIC command
1939 * @completion: initialize the completion only if this is set to true
1940 *
1941 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
1942 * with mutex held and host_lock locked.
1943 * Returns 0 only if success.
1944 */
1945 static int
1946 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1947 bool completion)
1948 {
1949 if (!ufshcd_ready_for_uic_cmd(hba)) {
1950 dev_err(hba->dev,
1951 "Controller not ready to accept UIC commands\n");
1952 return -EIO;
1953 }
1954
1955 if (completion)
1956 init_completion(&uic_cmd->done);
1957
1958 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
1959
1960 return 0;
1961 }
1962
1963 /**
1964 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1965 * @hba: per adapter instance
1966 * @uic_cmd: UIC command
1967 *
1968 * Returns 0 only if success.
1969 */
1970 static int
1971 ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1972 {
1973 int ret;
1974 unsigned long flags;
1975
1976 ufshcd_hold(hba, false);
1977 mutex_lock(&hba->uic_cmd_mutex);
1978 ufshcd_add_delay_before_dme_cmd(hba);
1979
1980 spin_lock_irqsave(hba->host->host_lock, flags);
1981 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
1982 spin_unlock_irqrestore(hba->host->host_lock, flags);
1983 if (!ret)
1984 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1985
1986 mutex_unlock(&hba->uic_cmd_mutex);
1987
1988 ufshcd_release(hba);
1989 return ret;
1990 }
1991
1992 /**
1993 * ufshcd_map_sg - Map scatter-gather list to prdt
1994 * @lrbp - pointer to local reference block
1995 *
1996 * Returns 0 in case of success, non-zero value in case of failure
1997 */
1998 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1999 {
2000 struct ufshcd_sg_entry *prd_table;
2001 struct scatterlist *sg;
2002 struct scsi_cmnd *cmd;
2003 int sg_segments;
2004 int i;
2005
2006 cmd = lrbp->cmd;
2007 sg_segments = scsi_dma_map(cmd);
2008 if (sg_segments < 0)
2009 return sg_segments;
2010
2011 if (sg_segments) {
2012 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2013 lrbp->utr_descriptor_ptr->prd_table_length =
2014 cpu_to_le16((u16)(sg_segments *
2015 sizeof(struct ufshcd_sg_entry)));
2016 else
2017 lrbp->utr_descriptor_ptr->prd_table_length =
2018 cpu_to_le16((u16) (sg_segments));
2019
2020 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2021
2022 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2023 prd_table[i].size =
2024 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2025 prd_table[i].base_addr =
2026 cpu_to_le32(lower_32_bits(sg->dma_address));
2027 prd_table[i].upper_addr =
2028 cpu_to_le32(upper_32_bits(sg->dma_address));
2029 prd_table[i].reserved = 0;
2030 }
2031 } else {
2032 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2033 }
2034
2035 return 0;
2036 }
2037
2038 /**
2039 * ufshcd_enable_intr - enable interrupts
2040 * @hba: per adapter instance
2041 * @intrs: interrupt bits
2042 */
2043 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2044 {
2045 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2046
2047 if (hba->ufs_version == UFSHCI_VERSION_10) {
2048 u32 rw;
2049 rw = set & INTERRUPT_MASK_RW_VER_10;
2050 set = rw | ((set ^ intrs) & intrs);
2051 } else {
2052 set |= intrs;
2053 }
2054
2055 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2056 }
2057
2058 /**
2059 * ufshcd_disable_intr - disable interrupts
2060 * @hba: per adapter instance
2061 * @intrs: interrupt bits
2062 */
2063 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2064 {
2065 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2066
2067 if (hba->ufs_version == UFSHCI_VERSION_10) {
2068 u32 rw;
2069 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2070 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2071 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2072
2073 } else {
2074 set &= ~intrs;
2075 }
2076
2077 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2078 }
2079
2080 /**
2081 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2082 * descriptor according to request
2083 * @lrbp: pointer to local reference block
2084 * @upiu_flags: flags required in the header
2085 * @cmd_dir: requests data direction
2086 */
2087 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2088 u32 *upiu_flags, enum dma_data_direction cmd_dir)
2089 {
2090 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2091 u32 data_direction;
2092 u32 dword_0;
2093
2094 if (cmd_dir == DMA_FROM_DEVICE) {
2095 data_direction = UTP_DEVICE_TO_HOST;
2096 *upiu_flags = UPIU_CMD_FLAGS_READ;
2097 } else if (cmd_dir == DMA_TO_DEVICE) {
2098 data_direction = UTP_HOST_TO_DEVICE;
2099 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2100 } else {
2101 data_direction = UTP_NO_DATA_TRANSFER;
2102 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2103 }
2104
2105 dword_0 = data_direction | (lrbp->command_type
2106 << UPIU_COMMAND_TYPE_OFFSET);
2107 if (lrbp->intr_cmd)
2108 dword_0 |= UTP_REQ_DESC_INT_CMD;
2109
2110 /* Transfer request descriptor header fields */
2111 req_desc->header.dword_0 = cpu_to_le32(dword_0);
2112 /* dword_1 is reserved, hence it is set to 0 */
2113 req_desc->header.dword_1 = 0;
2114 /*
2115 * assigning invalid value for command status. Controller
2116 * updates OCS on command completion, with the command
2117 * status
2118 */
2119 req_desc->header.dword_2 =
2120 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2121 /* dword_3 is reserved, hence it is set to 0 */
2122 req_desc->header.dword_3 = 0;
2123
2124 req_desc->prd_table_length = 0;
2125 }
2126
2127 /**
2128 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2129 * for scsi commands
2130 * @lrbp - local reference block pointer
2131 * @upiu_flags - flags
2132 */
2133 static
2134 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2135 {
2136 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2137 unsigned short cdb_len;
2138
2139 /* command descriptor fields */
2140 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2141 UPIU_TRANSACTION_COMMAND, upiu_flags,
2142 lrbp->lun, lrbp->task_tag);
2143 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2144 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2145
2146 /* Total EHS length and Data segment length will be zero */
2147 ucd_req_ptr->header.dword_2 = 0;
2148
2149 ucd_req_ptr->sc.exp_data_transfer_len =
2150 cpu_to_be32(lrbp->cmd->sdb.length);
2151
2152 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
2153 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
2154 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2155
2156 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2157 }
2158
2159 /**
2160 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2161 * for query requsts
2162 * @hba: UFS hba
2163 * @lrbp: local reference block pointer
2164 * @upiu_flags: flags
2165 */
2166 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2167 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2168 {
2169 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2170 struct ufs_query *query = &hba->dev_cmd.query;
2171 u16 len = be16_to_cpu(query->request.upiu_req.length);
2172 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2173
2174 /* Query request header */
2175 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2176 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2177 lrbp->lun, lrbp->task_tag);
2178 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2179 0, query->request.query_func, 0, 0);
2180
2181 /* Data segment length only need for WRITE_DESC */
2182 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2183 ucd_req_ptr->header.dword_2 =
2184 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2185 else
2186 ucd_req_ptr->header.dword_2 = 0;
2187
2188 /* Copy the Query Request buffer as is */
2189 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2190 QUERY_OSF_SIZE);
2191
2192 /* Copy the Descriptor */
2193 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2194 memcpy(descp, query->descriptor, len);
2195
2196 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2197 }
2198
2199 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2200 {
2201 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2202
2203 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2204
2205 /* command descriptor fields */
2206 ucd_req_ptr->header.dword_0 =
2207 UPIU_HEADER_DWORD(
2208 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2209 /* clear rest of the fields of basic header */
2210 ucd_req_ptr->header.dword_1 = 0;
2211 ucd_req_ptr->header.dword_2 = 0;
2212
2213 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2214 }
2215
2216 /**
2217 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2218 * for Device Management Purposes
2219 * @hba - per adapter instance
2220 * @lrb - pointer to local reference block
2221 */
2222 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2223 {
2224 u32 upiu_flags;
2225 int ret = 0;
2226
2227 if (hba->ufs_version == UFSHCI_VERSION_20)
2228 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2229 else
2230 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2231
2232 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2233 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2234 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2235 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2236 ufshcd_prepare_utp_nop_upiu(lrbp);
2237 else
2238 ret = -EINVAL;
2239
2240 return ret;
2241 }
2242
2243 /**
2244 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2245 * for SCSI Purposes
2246 * @hba - per adapter instance
2247 * @lrb - pointer to local reference block
2248 */
2249 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2250 {
2251 u32 upiu_flags;
2252 int ret = 0;
2253
2254 if (hba->ufs_version == UFSHCI_VERSION_20)
2255 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2256 else
2257 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2258
2259 if (likely(lrbp->cmd)) {
2260 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2261 lrbp->cmd->sc_data_direction);
2262 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2263 } else {
2264 ret = -EINVAL;
2265 }
2266
2267 return ret;
2268 }
2269
2270 /*
2271 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
2272 * @scsi_lun: scsi LUN id
2273 *
2274 * Returns UPIU LUN id
2275 */
2276 static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
2277 {
2278 if (scsi_is_wlun(scsi_lun))
2279 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
2280 | UFS_UPIU_WLUN_ID;
2281 else
2282 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
2283 }
2284
2285 /**
2286 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2287 * @scsi_lun: UPIU W-LUN id
2288 *
2289 * Returns SCSI W-LUN id
2290 */
2291 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2292 {
2293 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2294 }
2295
2296 /**
2297 * ufshcd_queuecommand - main entry point for SCSI requests
2298 * @cmd: command from SCSI Midlayer
2299 * @done: call back function
2300 *
2301 * Returns 0 for success, non-zero in case of failure
2302 */
2303 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2304 {
2305 struct ufshcd_lrb *lrbp;
2306 struct ufs_hba *hba;
2307 unsigned long flags;
2308 int tag;
2309 int err = 0;
2310
2311 hba = shost_priv(host);
2312
2313 tag = cmd->request->tag;
2314 if (!ufshcd_valid_tag(hba, tag)) {
2315 dev_err(hba->dev,
2316 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2317 __func__, tag, cmd, cmd->request);
2318 BUG();
2319 }
2320
2321 if (!down_read_trylock(&hba->clk_scaling_lock))
2322 return SCSI_MLQUEUE_HOST_BUSY;
2323
2324 spin_lock_irqsave(hba->host->host_lock, flags);
2325 switch (hba->ufshcd_state) {
2326 case UFSHCD_STATE_OPERATIONAL:
2327 break;
2328 case UFSHCD_STATE_EH_SCHEDULED:
2329 case UFSHCD_STATE_RESET:
2330 err = SCSI_MLQUEUE_HOST_BUSY;
2331 goto out_unlock;
2332 case UFSHCD_STATE_ERROR:
2333 set_host_byte(cmd, DID_ERROR);
2334 cmd->scsi_done(cmd);
2335 goto out_unlock;
2336 default:
2337 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2338 __func__, hba->ufshcd_state);
2339 set_host_byte(cmd, DID_BAD_TARGET);
2340 cmd->scsi_done(cmd);
2341 goto out_unlock;
2342 }
2343
2344 /* if error handling is in progress, don't issue commands */
2345 if (ufshcd_eh_in_progress(hba)) {
2346 set_host_byte(cmd, DID_ERROR);
2347 cmd->scsi_done(cmd);
2348 goto out_unlock;
2349 }
2350 spin_unlock_irqrestore(hba->host->host_lock, flags);
2351
2352 hba->req_abort_count = 0;
2353
2354 /* acquire the tag to make sure device cmds don't use it */
2355 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2356 /*
2357 * Dev manage command in progress, requeue the command.
2358 * Requeuing the command helps in cases where the request *may*
2359 * find different tag instead of waiting for dev manage command
2360 * completion.
2361 */
2362 err = SCSI_MLQUEUE_HOST_BUSY;
2363 goto out;
2364 }
2365
2366 err = ufshcd_hold(hba, true);
2367 if (err) {
2368 err = SCSI_MLQUEUE_HOST_BUSY;
2369 clear_bit_unlock(tag, &hba->lrb_in_use);
2370 goto out;
2371 }
2372 WARN_ON(hba->clk_gating.state != CLKS_ON);
2373
2374 lrbp = &hba->lrb[tag];
2375
2376 WARN_ON(lrbp->cmd);
2377 lrbp->cmd = cmd;
2378 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
2379 lrbp->sense_buffer = cmd->sense_buffer;
2380 lrbp->task_tag = tag;
2381 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2382 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
2383 lrbp->req_abort_skip = false;
2384
2385 ufshcd_comp_scsi_upiu(hba, lrbp);
2386
2387 err = ufshcd_map_sg(hba, lrbp);
2388 if (err) {
2389 lrbp->cmd = NULL;
2390 clear_bit_unlock(tag, &hba->lrb_in_use);
2391 goto out;
2392 }
2393 /* Make sure descriptors are ready before ringing the doorbell */
2394 wmb();
2395
2396 /* issue command to the controller */
2397 spin_lock_irqsave(hba->host->host_lock, flags);
2398 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
2399 ufshcd_send_command(hba, tag);
2400 out_unlock:
2401 spin_unlock_irqrestore(hba->host->host_lock, flags);
2402 out:
2403 up_read(&hba->clk_scaling_lock);
2404 return err;
2405 }
2406
2407 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2408 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2409 {
2410 lrbp->cmd = NULL;
2411 lrbp->sense_bufflen = 0;
2412 lrbp->sense_buffer = NULL;
2413 lrbp->task_tag = tag;
2414 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2415 lrbp->intr_cmd = true; /* No interrupt aggregation */
2416 hba->dev_cmd.type = cmd_type;
2417
2418 return ufshcd_comp_devman_upiu(hba, lrbp);
2419 }
2420
2421 static int
2422 ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2423 {
2424 int err = 0;
2425 unsigned long flags;
2426 u32 mask = 1 << tag;
2427
2428 /* clear outstanding transaction before retry */
2429 spin_lock_irqsave(hba->host->host_lock, flags);
2430 ufshcd_utrl_clear(hba, tag);
2431 spin_unlock_irqrestore(hba->host->host_lock, flags);
2432
2433 /*
2434 * wait for for h/w to clear corresponding bit in door-bell.
2435 * max. wait is 1 sec.
2436 */
2437 err = ufshcd_wait_for_register(hba,
2438 REG_UTP_TRANSFER_REQ_DOOR_BELL,
2439 mask, ~mask, 1000, 1000, true);
2440
2441 return err;
2442 }
2443
2444 static int
2445 ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2446 {
2447 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2448
2449 /* Get the UPIU response */
2450 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2451 UPIU_RSP_CODE_OFFSET;
2452 return query_res->response;
2453 }
2454
2455 /**
2456 * ufshcd_dev_cmd_completion() - handles device management command responses
2457 * @hba: per adapter instance
2458 * @lrbp: pointer to local reference block
2459 */
2460 static int
2461 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2462 {
2463 int resp;
2464 int err = 0;
2465
2466 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2467 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2468
2469 switch (resp) {
2470 case UPIU_TRANSACTION_NOP_IN:
2471 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2472 err = -EINVAL;
2473 dev_err(hba->dev, "%s: unexpected response %x\n",
2474 __func__, resp);
2475 }
2476 break;
2477 case UPIU_TRANSACTION_QUERY_RSP:
2478 err = ufshcd_check_query_response(hba, lrbp);
2479 if (!err)
2480 err = ufshcd_copy_query_response(hba, lrbp);
2481 break;
2482 case UPIU_TRANSACTION_REJECT_UPIU:
2483 /* TODO: handle Reject UPIU Response */
2484 err = -EPERM;
2485 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2486 __func__);
2487 break;
2488 default:
2489 err = -EINVAL;
2490 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2491 __func__, resp);
2492 break;
2493 }
2494
2495 return err;
2496 }
2497
2498 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2499 struct ufshcd_lrb *lrbp, int max_timeout)
2500 {
2501 int err = 0;
2502 unsigned long time_left;
2503 unsigned long flags;
2504
2505 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2506 msecs_to_jiffies(max_timeout));
2507
2508 /* Make sure descriptors are ready before ringing the doorbell */
2509 wmb();
2510 spin_lock_irqsave(hba->host->host_lock, flags);
2511 hba->dev_cmd.complete = NULL;
2512 if (likely(time_left)) {
2513 err = ufshcd_get_tr_ocs(lrbp);
2514 if (!err)
2515 err = ufshcd_dev_cmd_completion(hba, lrbp);
2516 }
2517 spin_unlock_irqrestore(hba->host->host_lock, flags);
2518
2519 if (!time_left) {
2520 err = -ETIMEDOUT;
2521 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2522 __func__, lrbp->task_tag);
2523 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
2524 /* successfully cleared the command, retry if needed */
2525 err = -EAGAIN;
2526 /*
2527 * in case of an error, after clearing the doorbell,
2528 * we also need to clear the outstanding_request
2529 * field in hba
2530 */
2531 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
2532 }
2533
2534 return err;
2535 }
2536
2537 /**
2538 * ufshcd_get_dev_cmd_tag - Get device management command tag
2539 * @hba: per-adapter instance
2540 * @tag: pointer to variable with available slot value
2541 *
2542 * Get a free slot and lock it until device management command
2543 * completes.
2544 *
2545 * Returns false if free slot is unavailable for locking, else
2546 * return true with tag value in @tag.
2547 */
2548 static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2549 {
2550 int tag;
2551 bool ret = false;
2552 unsigned long tmp;
2553
2554 if (!tag_out)
2555 goto out;
2556
2557 do {
2558 tmp = ~hba->lrb_in_use;
2559 tag = find_last_bit(&tmp, hba->nutrs);
2560 if (tag >= hba->nutrs)
2561 goto out;
2562 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2563
2564 *tag_out = tag;
2565 ret = true;
2566 out:
2567 return ret;
2568 }
2569
2570 static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2571 {
2572 clear_bit_unlock(tag, &hba->lrb_in_use);
2573 }
2574
2575 /**
2576 * ufshcd_exec_dev_cmd - API for sending device management requests
2577 * @hba - UFS hba
2578 * @cmd_type - specifies the type (NOP, Query...)
2579 * @timeout - time in seconds
2580 *
2581 * NOTE: Since there is only one available tag for device management commands,
2582 * it is expected you hold the hba->dev_cmd.lock mutex.
2583 */
2584 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2585 enum dev_cmd_type cmd_type, int timeout)
2586 {
2587 struct ufshcd_lrb *lrbp;
2588 int err;
2589 int tag;
2590 struct completion wait;
2591 unsigned long flags;
2592
2593 down_read(&hba->clk_scaling_lock);
2594
2595 /*
2596 * Get free slot, sleep if slots are unavailable.
2597 * Even though we use wait_event() which sleeps indefinitely,
2598 * the maximum wait time is bounded by SCSI request timeout.
2599 */
2600 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2601
2602 init_completion(&wait);
2603 lrbp = &hba->lrb[tag];
2604 WARN_ON(lrbp->cmd);
2605 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2606 if (unlikely(err))
2607 goto out_put_tag;
2608
2609 hba->dev_cmd.complete = &wait;
2610
2611 /* Make sure descriptors are ready before ringing the doorbell */
2612 wmb();
2613 spin_lock_irqsave(hba->host->host_lock, flags);
2614 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
2615 ufshcd_send_command(hba, tag);
2616 spin_unlock_irqrestore(hba->host->host_lock, flags);
2617
2618 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2619
2620 out_put_tag:
2621 ufshcd_put_dev_cmd_tag(hba, tag);
2622 wake_up(&hba->dev_cmd.tag_wq);
2623 up_read(&hba->clk_scaling_lock);
2624 return err;
2625 }
2626
2627 /**
2628 * ufshcd_init_query() - init the query response and request parameters
2629 * @hba: per-adapter instance
2630 * @request: address of the request pointer to be initialized
2631 * @response: address of the response pointer to be initialized
2632 * @opcode: operation to perform
2633 * @idn: flag idn to access
2634 * @index: LU number to access
2635 * @selector: query/flag/descriptor further identification
2636 */
2637 static inline void ufshcd_init_query(struct ufs_hba *hba,
2638 struct ufs_query_req **request, struct ufs_query_res **response,
2639 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2640 {
2641 *request = &hba->dev_cmd.query.request;
2642 *response = &hba->dev_cmd.query.response;
2643 memset(*request, 0, sizeof(struct ufs_query_req));
2644 memset(*response, 0, sizeof(struct ufs_query_res));
2645 (*request)->upiu_req.opcode = opcode;
2646 (*request)->upiu_req.idn = idn;
2647 (*request)->upiu_req.index = index;
2648 (*request)->upiu_req.selector = selector;
2649 }
2650
2651 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2652 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2653 {
2654 int ret;
2655 int retries;
2656
2657 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2658 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2659 if (ret)
2660 dev_dbg(hba->dev,
2661 "%s: failed with error %d, retries %d\n",
2662 __func__, ret, retries);
2663 else
2664 break;
2665 }
2666
2667 if (ret)
2668 dev_err(hba->dev,
2669 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2670 __func__, opcode, idn, ret, retries);
2671 return ret;
2672 }
2673
2674 /**
2675 * ufshcd_query_flag() - API function for sending flag query requests
2676 * hba: per-adapter instance
2677 * query_opcode: flag query to perform
2678 * idn: flag idn to access
2679 * flag_res: the flag value after the query request completes
2680 *
2681 * Returns 0 for success, non-zero in case of failure
2682 */
2683 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
2684 enum flag_idn idn, bool *flag_res)
2685 {
2686 struct ufs_query_req *request = NULL;
2687 struct ufs_query_res *response = NULL;
2688 int err, index = 0, selector = 0;
2689 int timeout = QUERY_REQ_TIMEOUT;
2690
2691 BUG_ON(!hba);
2692
2693 ufshcd_hold(hba, false);
2694 mutex_lock(&hba->dev_cmd.lock);
2695 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2696 selector);
2697
2698 switch (opcode) {
2699 case UPIU_QUERY_OPCODE_SET_FLAG:
2700 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2701 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2702 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2703 break;
2704 case UPIU_QUERY_OPCODE_READ_FLAG:
2705 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2706 if (!flag_res) {
2707 /* No dummy reads */
2708 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2709 __func__);
2710 err = -EINVAL;
2711 goto out_unlock;
2712 }
2713 break;
2714 default:
2715 dev_err(hba->dev,
2716 "%s: Expected query flag opcode but got = %d\n",
2717 __func__, opcode);
2718 err = -EINVAL;
2719 goto out_unlock;
2720 }
2721
2722 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
2723
2724 if (err) {
2725 dev_err(hba->dev,
2726 "%s: Sending flag query for idn %d failed, err = %d\n",
2727 __func__, idn, err);
2728 goto out_unlock;
2729 }
2730
2731 if (flag_res)
2732 *flag_res = (be32_to_cpu(response->upiu_res.value) &
2733 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2734
2735 out_unlock:
2736 mutex_unlock(&hba->dev_cmd.lock);
2737 ufshcd_release(hba);
2738 return err;
2739 }
2740
2741 /**
2742 * ufshcd_query_attr - API function for sending attribute requests
2743 * hba: per-adapter instance
2744 * opcode: attribute opcode
2745 * idn: attribute idn to access
2746 * index: index field
2747 * selector: selector field
2748 * attr_val: the attribute value after the query request completes
2749 *
2750 * Returns 0 for success, non-zero in case of failure
2751 */
2752 static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2753 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2754 {
2755 struct ufs_query_req *request = NULL;
2756 struct ufs_query_res *response = NULL;
2757 int err;
2758
2759 BUG_ON(!hba);
2760
2761 ufshcd_hold(hba, false);
2762 if (!attr_val) {
2763 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2764 __func__, opcode);
2765 err = -EINVAL;
2766 goto out;
2767 }
2768
2769 mutex_lock(&hba->dev_cmd.lock);
2770 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2771 selector);
2772
2773 switch (opcode) {
2774 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2775 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2776 request->upiu_req.value = cpu_to_be32(*attr_val);
2777 break;
2778 case UPIU_QUERY_OPCODE_READ_ATTR:
2779 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2780 break;
2781 default:
2782 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2783 __func__, opcode);
2784 err = -EINVAL;
2785 goto out_unlock;
2786 }
2787
2788 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2789
2790 if (err) {
2791 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2792 __func__, opcode, idn, index, err);
2793 goto out_unlock;
2794 }
2795
2796 *attr_val = be32_to_cpu(response->upiu_res.value);
2797
2798 out_unlock:
2799 mutex_unlock(&hba->dev_cmd.lock);
2800 out:
2801 ufshcd_release(hba);
2802 return err;
2803 }
2804
2805 /**
2806 * ufshcd_query_attr_retry() - API function for sending query
2807 * attribute with retries
2808 * @hba: per-adapter instance
2809 * @opcode: attribute opcode
2810 * @idn: attribute idn to access
2811 * @index: index field
2812 * @selector: selector field
2813 * @attr_val: the attribute value after the query request
2814 * completes
2815 *
2816 * Returns 0 for success, non-zero in case of failure
2817 */
2818 static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2819 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2820 u32 *attr_val)
2821 {
2822 int ret = 0;
2823 u32 retries;
2824
2825 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2826 ret = ufshcd_query_attr(hba, opcode, idn, index,
2827 selector, attr_val);
2828 if (ret)
2829 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2830 __func__, ret, retries);
2831 else
2832 break;
2833 }
2834
2835 if (ret)
2836 dev_err(hba->dev,
2837 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2838 __func__, idn, ret, QUERY_REQ_RETRIES);
2839 return ret;
2840 }
2841
2842 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
2843 enum query_opcode opcode, enum desc_idn idn, u8 index,
2844 u8 selector, u8 *desc_buf, int *buf_len)
2845 {
2846 struct ufs_query_req *request = NULL;
2847 struct ufs_query_res *response = NULL;
2848 int err;
2849
2850 BUG_ON(!hba);
2851
2852 ufshcd_hold(hba, false);
2853 if (!desc_buf) {
2854 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2855 __func__, opcode);
2856 err = -EINVAL;
2857 goto out;
2858 }
2859
2860 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
2861 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2862 __func__, *buf_len);
2863 err = -EINVAL;
2864 goto out;
2865 }
2866
2867 mutex_lock(&hba->dev_cmd.lock);
2868 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2869 selector);
2870 hba->dev_cmd.query.descriptor = desc_buf;
2871 request->upiu_req.length = cpu_to_be16(*buf_len);
2872
2873 switch (opcode) {
2874 case UPIU_QUERY_OPCODE_WRITE_DESC:
2875 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2876 break;
2877 case UPIU_QUERY_OPCODE_READ_DESC:
2878 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2879 break;
2880 default:
2881 dev_err(hba->dev,
2882 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2883 __func__, opcode);
2884 err = -EINVAL;
2885 goto out_unlock;
2886 }
2887
2888 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2889
2890 if (err) {
2891 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2892 __func__, opcode, idn, index, err);
2893 goto out_unlock;
2894 }
2895
2896 hba->dev_cmd.query.descriptor = NULL;
2897 *buf_len = be16_to_cpu(response->upiu_res.length);
2898
2899 out_unlock:
2900 mutex_unlock(&hba->dev_cmd.lock);
2901 out:
2902 ufshcd_release(hba);
2903 return err;
2904 }
2905
2906 /**
2907 * ufshcd_query_descriptor_retry - API function for sending descriptor
2908 * requests
2909 * hba: per-adapter instance
2910 * opcode: attribute opcode
2911 * idn: attribute idn to access
2912 * index: index field
2913 * selector: selector field
2914 * desc_buf: the buffer that contains the descriptor
2915 * buf_len: length parameter passed to the device
2916 *
2917 * Returns 0 for success, non-zero in case of failure.
2918 * The buf_len parameter will contain, on return, the length parameter
2919 * received on the response.
2920 */
2921 static int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2922 enum query_opcode opcode,
2923 enum desc_idn idn, u8 index,
2924 u8 selector,
2925 u8 *desc_buf, int *buf_len)
2926 {
2927 int err;
2928 int retries;
2929
2930 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2931 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2932 selector, desc_buf, buf_len);
2933 if (!err || err == -EINVAL)
2934 break;
2935 }
2936
2937 return err;
2938 }
2939
2940 /**
2941 * ufshcd_read_desc_param - read the specified descriptor parameter
2942 * @hba: Pointer to adapter instance
2943 * @desc_id: descriptor idn value
2944 * @desc_index: descriptor index
2945 * @param_offset: offset of the parameter to read
2946 * @param_read_buf: pointer to buffer where parameter would be read
2947 * @param_size: sizeof(param_read_buf)
2948 *
2949 * Return 0 in case of success, non-zero otherwise
2950 */
2951 static int ufshcd_read_desc_param(struct ufs_hba *hba,
2952 enum desc_idn desc_id,
2953 int desc_index,
2954 u32 param_offset,
2955 u8 *param_read_buf,
2956 u32 param_size)
2957 {
2958 int ret;
2959 u8 *desc_buf;
2960 u32 buff_len;
2961 bool is_kmalloc = true;
2962
2963 /* safety checks */
2964 if (desc_id >= QUERY_DESC_IDN_MAX)
2965 return -EINVAL;
2966
2967 buff_len = ufs_query_desc_max_size[desc_id];
2968 if ((param_offset + param_size) > buff_len)
2969 return -EINVAL;
2970
2971 if (!param_offset && (param_size == buff_len)) {
2972 /* memory space already available to hold full descriptor */
2973 desc_buf = param_read_buf;
2974 is_kmalloc = false;
2975 } else {
2976 /* allocate memory to hold full descriptor */
2977 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2978 if (!desc_buf)
2979 return -ENOMEM;
2980 }
2981
2982 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2983 desc_id, desc_index, 0, desc_buf,
2984 &buff_len);
2985
2986 if (ret) {
2987 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
2988 __func__, desc_id, desc_index, param_offset, ret);
2989
2990 goto out;
2991 }
2992
2993 /* Sanity check */
2994 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
2995 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
2996 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
2997 ret = -EINVAL;
2998 goto out;
2999 }
3000
3001 /*
3002 * While reading variable size descriptors (like string descriptor),
3003 * some UFS devices may report the "LENGTH" (field in "Transaction
3004 * Specific fields" of Query Response UPIU) same as what was requested
3005 * in Query Request UPIU instead of reporting the actual size of the
3006 * variable size descriptor.
3007 * Although it's safe to ignore the "LENGTH" field for variable size
3008 * descriptors as we can always derive the length of the descriptor from
3009 * the descriptor header fields. Hence this change impose the length
3010 * match check only for fixed size descriptors (for which we always
3011 * request the correct size as part of Query Request UPIU).
3012 */
3013 if ((desc_id != QUERY_DESC_IDN_STRING) &&
3014 (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) {
3015 dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d",
3016 __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]);
3017 ret = -EINVAL;
3018 goto out;
3019 }
3020
3021 if (is_kmalloc)
3022 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3023 out:
3024 if (is_kmalloc)
3025 kfree(desc_buf);
3026 return ret;
3027 }
3028
3029 static inline int ufshcd_read_desc(struct ufs_hba *hba,
3030 enum desc_idn desc_id,
3031 int desc_index,
3032 u8 *buf,
3033 u32 size)
3034 {
3035 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3036 }
3037
3038 static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3039 u8 *buf,
3040 u32 size)
3041 {
3042 int err = 0;
3043 int retries;
3044
3045 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3046 /* Read descriptor*/
3047 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
3048 if (!err)
3049 break;
3050 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3051 }
3052
3053 return err;
3054 }
3055
3056 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
3057 {
3058 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3059 }
3060
3061 /**
3062 * ufshcd_read_string_desc - read string descriptor
3063 * @hba: pointer to adapter instance
3064 * @desc_index: descriptor index
3065 * @buf: pointer to buffer where descriptor would be read
3066 * @size: size of buf
3067 * @ascii: if true convert from unicode to ascii characters
3068 *
3069 * Return 0 in case of success, non-zero otherwise
3070 */
3071 #define ASCII_STD true
3072 static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3073 u8 *buf, u32 size, bool ascii)
3074 {
3075 int err = 0;
3076
3077 err = ufshcd_read_desc(hba,
3078 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3079
3080 if (err) {
3081 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3082 __func__, QUERY_REQ_RETRIES, err);
3083 goto out;
3084 }
3085
3086 if (ascii) {
3087 int desc_len;
3088 int ascii_len;
3089 int i;
3090 char *buff_ascii;
3091
3092 desc_len = buf[0];
3093 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3094 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3095 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3096 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3097 __func__);
3098 err = -ENOMEM;
3099 goto out;
3100 }
3101
3102 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3103 if (!buff_ascii) {
3104 err = -ENOMEM;
3105 goto out;
3106 }
3107
3108 /*
3109 * the descriptor contains string in UTF16 format
3110 * we need to convert to utf-8 so it can be displayed
3111 */
3112 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3113 desc_len - QUERY_DESC_HDR_SIZE,
3114 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3115
3116 /* replace non-printable or non-ASCII characters with spaces */
3117 for (i = 0; i < ascii_len; i++)
3118 ufshcd_remove_non_printable(&buff_ascii[i]);
3119
3120 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3121 size - QUERY_DESC_HDR_SIZE);
3122 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3123 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
3124 kfree(buff_ascii);
3125 }
3126 out:
3127 return err;
3128 }
3129
3130 /**
3131 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3132 * @hba: Pointer to adapter instance
3133 * @lun: lun id
3134 * @param_offset: offset of the parameter to read
3135 * @param_read_buf: pointer to buffer where parameter would be read
3136 * @param_size: sizeof(param_read_buf)
3137 *
3138 * Return 0 in case of success, non-zero otherwise
3139 */
3140 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3141 int lun,
3142 enum unit_desc_param param_offset,
3143 u8 *param_read_buf,
3144 u32 param_size)
3145 {
3146 /*
3147 * Unit descriptors are only available for general purpose LUs (LUN id
3148 * from 0 to 7) and RPMB Well known LU.
3149 */
3150 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
3151 return -EOPNOTSUPP;
3152
3153 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3154 param_offset, param_read_buf, param_size);
3155 }
3156
3157 /**
3158 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3159 * @hba: per adapter instance
3160 *
3161 * 1. Allocate DMA memory for Command Descriptor array
3162 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3163 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3164 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3165 * (UTMRDL)
3166 * 4. Allocate memory for local reference block(lrb).
3167 *
3168 * Returns 0 for success, non-zero in case of failure
3169 */
3170 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3171 {
3172 size_t utmrdl_size, utrdl_size, ucdl_size;
3173
3174 /* Allocate memory for UTP command descriptors */
3175 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3176 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3177 ucdl_size,
3178 &hba->ucdl_dma_addr,
3179 GFP_KERNEL);
3180
3181 /*
3182 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3183 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3184 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3185 * be aligned to 128 bytes as well
3186 */
3187 if (!hba->ucdl_base_addr ||
3188 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3189 dev_err(hba->dev,
3190 "Command Descriptor Memory allocation failed\n");
3191 goto out;
3192 }
3193
3194 /*
3195 * Allocate memory for UTP Transfer descriptors
3196 * UFSHCI requires 1024 byte alignment of UTRD
3197 */
3198 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3199 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3200 utrdl_size,
3201 &hba->utrdl_dma_addr,
3202 GFP_KERNEL);
3203 if (!hba->utrdl_base_addr ||
3204 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3205 dev_err(hba->dev,
3206 "Transfer Descriptor Memory allocation failed\n");
3207 goto out;
3208 }
3209
3210 /*
3211 * Allocate memory for UTP Task Management descriptors
3212 * UFSHCI requires 1024 byte alignment of UTMRD
3213 */
3214 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3215 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3216 utmrdl_size,
3217 &hba->utmrdl_dma_addr,
3218 GFP_KERNEL);
3219 if (!hba->utmrdl_base_addr ||
3220 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3221 dev_err(hba->dev,
3222 "Task Management Descriptor Memory allocation failed\n");
3223 goto out;
3224 }
3225
3226 /* Allocate memory for local reference block */
3227 hba->lrb = devm_kzalloc(hba->dev,
3228 hba->nutrs * sizeof(struct ufshcd_lrb),
3229 GFP_KERNEL);
3230 if (!hba->lrb) {
3231 dev_err(hba->dev, "LRB Memory allocation failed\n");
3232 goto out;
3233 }
3234 return 0;
3235 out:
3236 return -ENOMEM;
3237 }
3238
3239 /**
3240 * ufshcd_host_memory_configure - configure local reference block with
3241 * memory offsets
3242 * @hba: per adapter instance
3243 *
3244 * Configure Host memory space
3245 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3246 * address.
3247 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3248 * and PRDT offset.
3249 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3250 * into local reference block.
3251 */
3252 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3253 {
3254 struct utp_transfer_cmd_desc *cmd_descp;
3255 struct utp_transfer_req_desc *utrdlp;
3256 dma_addr_t cmd_desc_dma_addr;
3257 dma_addr_t cmd_desc_element_addr;
3258 u16 response_offset;
3259 u16 prdt_offset;
3260 int cmd_desc_size;
3261 int i;
3262
3263 utrdlp = hba->utrdl_base_addr;
3264 cmd_descp = hba->ucdl_base_addr;
3265
3266 response_offset =
3267 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3268 prdt_offset =
3269 offsetof(struct utp_transfer_cmd_desc, prd_table);
3270
3271 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3272 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3273
3274 for (i = 0; i < hba->nutrs; i++) {
3275 /* Configure UTRD with command descriptor base address */
3276 cmd_desc_element_addr =
3277 (cmd_desc_dma_addr + (cmd_desc_size * i));
3278 utrdlp[i].command_desc_base_addr_lo =
3279 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3280 utrdlp[i].command_desc_base_addr_hi =
3281 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3282
3283 /* Response upiu and prdt offset should be in double words */
3284 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3285 utrdlp[i].response_upiu_offset =
3286 cpu_to_le16(response_offset);
3287 utrdlp[i].prd_table_offset =
3288 cpu_to_le16(prdt_offset);
3289 utrdlp[i].response_upiu_length =
3290 cpu_to_le16(ALIGNED_UPIU_SIZE);
3291 } else {
3292 utrdlp[i].response_upiu_offset =
3293 cpu_to_le16((response_offset >> 2));
3294 utrdlp[i].prd_table_offset =
3295 cpu_to_le16((prdt_offset >> 2));
3296 utrdlp[i].response_upiu_length =
3297 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3298 }
3299
3300 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
3301 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3302 (i * sizeof(struct utp_transfer_req_desc));
3303 hba->lrb[i].ucd_req_ptr =
3304 (struct utp_upiu_req *)(cmd_descp + i);
3305 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
3306 hba->lrb[i].ucd_rsp_ptr =
3307 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
3308 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3309 response_offset;
3310 hba->lrb[i].ucd_prdt_ptr =
3311 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
3312 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3313 prdt_offset;
3314 }
3315 }
3316
3317 /**
3318 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3319 * @hba: per adapter instance
3320 *
3321 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3322 * in order to initialize the Unipro link startup procedure.
3323 * Once the Unipro links are up, the device connected to the controller
3324 * is detected.
3325 *
3326 * Returns 0 on success, non-zero value on failure
3327 */
3328 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3329 {
3330 struct uic_command uic_cmd = {0};
3331 int ret;
3332
3333 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3334
3335 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3336 if (ret)
3337 dev_dbg(hba->dev,
3338 "dme-link-startup: error code %d\n", ret);
3339 return ret;
3340 }
3341
3342 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3343 {
3344 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3345 unsigned long min_sleep_time_us;
3346
3347 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3348 return;
3349
3350 /*
3351 * last_dme_cmd_tstamp will be 0 only for 1st call to
3352 * this function
3353 */
3354 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3355 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3356 } else {
3357 unsigned long delta =
3358 (unsigned long) ktime_to_us(
3359 ktime_sub(ktime_get(),
3360 hba->last_dme_cmd_tstamp));
3361
3362 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3363 min_sleep_time_us =
3364 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3365 else
3366 return; /* no more delay required */
3367 }
3368
3369 /* allow sleep for extra 50us if needed */
3370 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3371 }
3372
3373 /**
3374 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3375 * @hba: per adapter instance
3376 * @attr_sel: uic command argument1
3377 * @attr_set: attribute set type as uic command argument2
3378 * @mib_val: setting value as uic command argument3
3379 * @peer: indicate whether peer or local
3380 *
3381 * Returns 0 on success, non-zero value on failure
3382 */
3383 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3384 u8 attr_set, u32 mib_val, u8 peer)
3385 {
3386 struct uic_command uic_cmd = {0};
3387 static const char *const action[] = {
3388 "dme-set",
3389 "dme-peer-set"
3390 };
3391 const char *set = action[!!peer];
3392 int ret;
3393 int retries = UFS_UIC_COMMAND_RETRIES;
3394
3395 uic_cmd.command = peer ?
3396 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3397 uic_cmd.argument1 = attr_sel;
3398 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3399 uic_cmd.argument3 = mib_val;
3400
3401 do {
3402 /* for peer attributes we retry upon failure */
3403 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3404 if (ret)
3405 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3406 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3407 } while (ret && peer && --retries);
3408
3409 if (ret)
3410 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3411 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3412 UFS_UIC_COMMAND_RETRIES - retries);
3413
3414 return ret;
3415 }
3416 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3417
3418 /**
3419 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3420 * @hba: per adapter instance
3421 * @attr_sel: uic command argument1
3422 * @mib_val: the value of the attribute as returned by the UIC command
3423 * @peer: indicate whether peer or local
3424 *
3425 * Returns 0 on success, non-zero value on failure
3426 */
3427 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3428 u32 *mib_val, u8 peer)
3429 {
3430 struct uic_command uic_cmd = {0};
3431 static const char *const action[] = {
3432 "dme-get",
3433 "dme-peer-get"
3434 };
3435 const char *get = action[!!peer];
3436 int ret;
3437 int retries = UFS_UIC_COMMAND_RETRIES;
3438 struct ufs_pa_layer_attr orig_pwr_info;
3439 struct ufs_pa_layer_attr temp_pwr_info;
3440 bool pwr_mode_change = false;
3441
3442 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3443 orig_pwr_info = hba->pwr_info;
3444 temp_pwr_info = orig_pwr_info;
3445
3446 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3447 orig_pwr_info.pwr_rx == FAST_MODE) {
3448 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3449 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3450 pwr_mode_change = true;
3451 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3452 orig_pwr_info.pwr_rx == SLOW_MODE) {
3453 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3454 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3455 pwr_mode_change = true;
3456 }
3457 if (pwr_mode_change) {
3458 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3459 if (ret)
3460 goto out;
3461 }
3462 }
3463
3464 uic_cmd.command = peer ?
3465 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3466 uic_cmd.argument1 = attr_sel;
3467
3468 do {
3469 /* for peer attributes we retry upon failure */
3470 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3471 if (ret)
3472 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3473 get, UIC_GET_ATTR_ID(attr_sel), ret);
3474 } while (ret && peer && --retries);
3475
3476 if (ret)
3477 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
3478 get, UIC_GET_ATTR_ID(attr_sel),
3479 UFS_UIC_COMMAND_RETRIES - retries);
3480
3481 if (mib_val && !ret)
3482 *mib_val = uic_cmd.argument3;
3483
3484 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3485 && pwr_mode_change)
3486 ufshcd_change_power_mode(hba, &orig_pwr_info);
3487 out:
3488 return ret;
3489 }
3490 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3491
3492 /**
3493 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3494 * state) and waits for it to take effect.
3495 *
3496 * @hba: per adapter instance
3497 * @cmd: UIC command to execute
3498 *
3499 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3500 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3501 * and device UniPro link and hence it's final completion would be indicated by
3502 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3503 * addition to normal UIC command completion Status (UCCS). This function only
3504 * returns after the relevant status bits indicate the completion.
3505 *
3506 * Returns 0 on success, non-zero value on failure
3507 */
3508 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
3509 {
3510 struct completion uic_async_done;
3511 unsigned long flags;
3512 u8 status;
3513 int ret;
3514 bool reenable_intr = false;
3515
3516 mutex_lock(&hba->uic_cmd_mutex);
3517 init_completion(&uic_async_done);
3518 ufshcd_add_delay_before_dme_cmd(hba);
3519
3520 spin_lock_irqsave(hba->host->host_lock, flags);
3521 hba->uic_async_done = &uic_async_done;
3522 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3523 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3524 /*
3525 * Make sure UIC command completion interrupt is disabled before
3526 * issuing UIC command.
3527 */
3528 wmb();
3529 reenable_intr = true;
3530 }
3531 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3532 spin_unlock_irqrestore(hba->host->host_lock, flags);
3533 if (ret) {
3534 dev_err(hba->dev,
3535 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3536 cmd->command, cmd->argument3, ret);
3537 goto out;
3538 }
3539
3540 if (!wait_for_completion_timeout(hba->uic_async_done,
3541 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3542 dev_err(hba->dev,
3543 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3544 cmd->command, cmd->argument3);
3545 ret = -ETIMEDOUT;
3546 goto out;
3547 }
3548
3549 status = ufshcd_get_upmcrs(hba);
3550 if (status != PWR_LOCAL) {
3551 dev_err(hba->dev,
3552 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
3553 cmd->command, status);
3554 ret = (status != PWR_OK) ? status : -1;
3555 }
3556 out:
3557 if (ret) {
3558 ufshcd_print_host_state(hba);
3559 ufshcd_print_pwr_info(hba);
3560 ufshcd_print_host_regs(hba);
3561 }
3562
3563 spin_lock_irqsave(hba->host->host_lock, flags);
3564 hba->active_uic_cmd = NULL;
3565 hba->uic_async_done = NULL;
3566 if (reenable_intr)
3567 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
3568 spin_unlock_irqrestore(hba->host->host_lock, flags);
3569 mutex_unlock(&hba->uic_cmd_mutex);
3570
3571 return ret;
3572 }
3573
3574 /**
3575 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3576 * using DME_SET primitives.
3577 * @hba: per adapter instance
3578 * @mode: powr mode value
3579 *
3580 * Returns 0 on success, non-zero value on failure
3581 */
3582 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3583 {
3584 struct uic_command uic_cmd = {0};
3585 int ret;
3586
3587 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3588 ret = ufshcd_dme_set(hba,
3589 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3590 if (ret) {
3591 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3592 __func__, ret);
3593 goto out;
3594 }
3595 }
3596
3597 uic_cmd.command = UIC_CMD_DME_SET;
3598 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3599 uic_cmd.argument3 = mode;
3600 ufshcd_hold(hba, false);
3601 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3602 ufshcd_release(hba);
3603
3604 out:
3605 return ret;
3606 }
3607
3608 static int ufshcd_link_recovery(struct ufs_hba *hba)
3609 {
3610 int ret;
3611 unsigned long flags;
3612
3613 spin_lock_irqsave(hba->host->host_lock, flags);
3614 hba->ufshcd_state = UFSHCD_STATE_RESET;
3615 ufshcd_set_eh_in_progress(hba);
3616 spin_unlock_irqrestore(hba->host->host_lock, flags);
3617
3618 ret = ufshcd_host_reset_and_restore(hba);
3619
3620 spin_lock_irqsave(hba->host->host_lock, flags);
3621 if (ret)
3622 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3623 ufshcd_clear_eh_in_progress(hba);
3624 spin_unlock_irqrestore(hba->host->host_lock, flags);
3625
3626 if (ret)
3627 dev_err(hba->dev, "%s: link recovery failed, err %d",
3628 __func__, ret);
3629
3630 return ret;
3631 }
3632
3633 static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3634 {
3635 int ret;
3636 struct uic_command uic_cmd = {0};
3637 ktime_t start = ktime_get();
3638
3639 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3640
3641 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
3642 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3643 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3644 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3645
3646 if (ret) {
3647 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3648 __func__, ret);
3649
3650 /*
3651 * If link recovery fails then return error so that caller
3652 * don't retry the hibern8 enter again.
3653 */
3654 if (ufshcd_link_recovery(hba))
3655 ret = -ENOLINK;
3656 } else
3657 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3658 POST_CHANGE);
3659
3660 return ret;
3661 }
3662
3663 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3664 {
3665 int ret = 0, retries;
3666
3667 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3668 ret = __ufshcd_uic_hibern8_enter(hba);
3669 if (!ret || ret == -ENOLINK)
3670 goto out;
3671 }
3672 out:
3673 return ret;
3674 }
3675
3676 static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3677 {
3678 struct uic_command uic_cmd = {0};
3679 int ret;
3680 ktime_t start = ktime_get();
3681
3682 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3683
3684 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3685 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3686 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3687 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3688
3689 if (ret) {
3690 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3691 __func__, ret);
3692 ret = ufshcd_link_recovery(hba);
3693 } else {
3694 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3695 POST_CHANGE);
3696 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3697 hba->ufs_stats.hibern8_exit_cnt++;
3698 }
3699
3700 return ret;
3701 }
3702
3703 /**
3704 * ufshcd_init_pwr_info - setting the POR (power on reset)
3705 * values in hba power info
3706 * @hba: per-adapter instance
3707 */
3708 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3709 {
3710 hba->pwr_info.gear_rx = UFS_PWM_G1;
3711 hba->pwr_info.gear_tx = UFS_PWM_G1;
3712 hba->pwr_info.lane_rx = 1;
3713 hba->pwr_info.lane_tx = 1;
3714 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3715 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3716 hba->pwr_info.hs_rate = 0;
3717 }
3718
3719 /**
3720 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3721 * @hba: per-adapter instance
3722 */
3723 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
3724 {
3725 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3726
3727 if (hba->max_pwr_info.is_valid)
3728 return 0;
3729
3730 pwr_info->pwr_tx = FAST_MODE;
3731 pwr_info->pwr_rx = FAST_MODE;
3732 pwr_info->hs_rate = PA_HS_MODE_B;
3733
3734 /* Get the connected lane count */
3735 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3736 &pwr_info->lane_rx);
3737 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3738 &pwr_info->lane_tx);
3739
3740 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3741 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3742 __func__,
3743 pwr_info->lane_rx,
3744 pwr_info->lane_tx);
3745 return -EINVAL;
3746 }
3747
3748 /*
3749 * First, get the maximum gears of HS speed.
3750 * If a zero value, it means there is no HSGEAR capability.
3751 * Then, get the maximum gears of PWM speed.
3752 */
3753 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3754 if (!pwr_info->gear_rx) {
3755 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3756 &pwr_info->gear_rx);
3757 if (!pwr_info->gear_rx) {
3758 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3759 __func__, pwr_info->gear_rx);
3760 return -EINVAL;
3761 }
3762 pwr_info->pwr_rx = SLOW_MODE;
3763 }
3764
3765 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3766 &pwr_info->gear_tx);
3767 if (!pwr_info->gear_tx) {
3768 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3769 &pwr_info->gear_tx);
3770 if (!pwr_info->gear_tx) {
3771 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3772 __func__, pwr_info->gear_tx);
3773 return -EINVAL;
3774 }
3775 pwr_info->pwr_tx = SLOW_MODE;
3776 }
3777
3778 hba->max_pwr_info.is_valid = true;
3779 return 0;
3780 }
3781
3782 static int ufshcd_change_power_mode(struct ufs_hba *hba,
3783 struct ufs_pa_layer_attr *pwr_mode)
3784 {
3785 int ret;
3786
3787 /* if already configured to the requested pwr_mode */
3788 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3789 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3790 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3791 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
3792 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
3793 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
3794 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
3795 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
3796 return 0;
3797 }
3798
3799 /*
3800 * Configure attributes for power mode change with below.
3801 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
3802 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
3803 * - PA_HSSERIES
3804 */
3805 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
3806 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
3807 pwr_mode->lane_rx);
3808 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3809 pwr_mode->pwr_rx == FAST_MODE)
3810 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
3811 else
3812 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
3813
3814 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
3815 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
3816 pwr_mode->lane_tx);
3817 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
3818 pwr_mode->pwr_tx == FAST_MODE)
3819 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
3820 else
3821 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
3822
3823 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3824 pwr_mode->pwr_tx == FASTAUTO_MODE ||
3825 pwr_mode->pwr_rx == FAST_MODE ||
3826 pwr_mode->pwr_tx == FAST_MODE)
3827 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
3828 pwr_mode->hs_rate);
3829
3830 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
3831 | pwr_mode->pwr_tx);
3832
3833 if (ret) {
3834 dev_err(hba->dev,
3835 "%s: power mode change failed %d\n", __func__, ret);
3836 } else {
3837 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
3838 pwr_mode);
3839
3840 memcpy(&hba->pwr_info, pwr_mode,
3841 sizeof(struct ufs_pa_layer_attr));
3842 }
3843
3844 return ret;
3845 }
3846
3847 /**
3848 * ufshcd_config_pwr_mode - configure a new power mode
3849 * @hba: per-adapter instance
3850 * @desired_pwr_mode: desired power configuration
3851 */
3852 static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
3853 struct ufs_pa_layer_attr *desired_pwr_mode)
3854 {
3855 struct ufs_pa_layer_attr final_params = { 0 };
3856 int ret;
3857
3858 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
3859 desired_pwr_mode, &final_params);
3860
3861 if (ret)
3862 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
3863
3864 ret = ufshcd_change_power_mode(hba, &final_params);
3865 if (!ret)
3866 ufshcd_print_pwr_info(hba);
3867
3868 return ret;
3869 }
3870
3871 /**
3872 * ufshcd_complete_dev_init() - checks device readiness
3873 * hba: per-adapter instance
3874 *
3875 * Set fDeviceInit flag and poll until device toggles it.
3876 */
3877 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
3878 {
3879 int i;
3880 int err;
3881 bool flag_res = 1;
3882
3883 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3884 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
3885 if (err) {
3886 dev_err(hba->dev,
3887 "%s setting fDeviceInit flag failed with error %d\n",
3888 __func__, err);
3889 goto out;
3890 }
3891
3892 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
3893 for (i = 0; i < 1000 && !err && flag_res; i++)
3894 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
3895 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
3896
3897 if (err)
3898 dev_err(hba->dev,
3899 "%s reading fDeviceInit flag failed with error %d\n",
3900 __func__, err);
3901 else if (flag_res)
3902 dev_err(hba->dev,
3903 "%s fDeviceInit was not cleared by the device\n",
3904 __func__);
3905
3906 out:
3907 return err;
3908 }
3909
3910 /**
3911 * ufshcd_make_hba_operational - Make UFS controller operational
3912 * @hba: per adapter instance
3913 *
3914 * To bring UFS host controller to operational state,
3915 * 1. Enable required interrupts
3916 * 2. Configure interrupt aggregation
3917 * 3. Program UTRL and UTMRL base address
3918 * 4. Configure run-stop-registers
3919 *
3920 * Returns 0 on success, non-zero value on failure
3921 */
3922 static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3923 {
3924 int err = 0;
3925 u32 reg;
3926
3927 /* Enable required interrupts */
3928 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3929
3930 /* Configure interrupt aggregation */
3931 if (ufshcd_is_intr_aggr_allowed(hba))
3932 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3933 else
3934 ufshcd_disable_intr_aggr(hba);
3935
3936 /* Configure UTRL and UTMRL base address registers */
3937 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3938 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3939 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3940 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3941 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3942 REG_UTP_TASK_REQ_LIST_BASE_L);
3943 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3944 REG_UTP_TASK_REQ_LIST_BASE_H);
3945
3946 /*
3947 * Make sure base address and interrupt setup are updated before
3948 * enabling the run/stop registers below.
3949 */
3950 wmb();
3951
3952 /*
3953 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
3954 */
3955 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
3956 if (!(ufshcd_get_lists_status(reg))) {
3957 ufshcd_enable_run_stop_reg(hba);
3958 } else {
3959 dev_err(hba->dev,
3960 "Host controller not ready to process requests");
3961 err = -EIO;
3962 goto out;
3963 }
3964
3965 out:
3966 return err;
3967 }
3968
3969 /**
3970 * ufshcd_hba_stop - Send controller to reset state
3971 * @hba: per adapter instance
3972 * @can_sleep: perform sleep or just spin
3973 */
3974 static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3975 {
3976 int err;
3977
3978 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3979 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3980 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3981 10, 1, can_sleep);
3982 if (err)
3983 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3984 }
3985
3986 /**
3987 * ufshcd_hba_enable - initialize the controller
3988 * @hba: per adapter instance
3989 *
3990 * The controller resets itself and controller firmware initialization
3991 * sequence kicks off. When controller is ready it will set
3992 * the Host Controller Enable bit to 1.
3993 *
3994 * Returns 0 on success, non-zero value on failure
3995 */
3996 static int ufshcd_hba_enable(struct ufs_hba *hba)
3997 {
3998 int retry;
3999
4000 /*
4001 * msleep of 1 and 5 used in this function might result in msleep(20),
4002 * but it was necessary to send the UFS FPGA to reset mode during
4003 * development and testing of this driver. msleep can be changed to
4004 * mdelay and retry count can be reduced based on the controller.
4005 */
4006 if (!ufshcd_is_hba_active(hba))
4007 /* change controller state to "reset state" */
4008 ufshcd_hba_stop(hba, true);
4009
4010 /* UniPro link is disabled at this point */
4011 ufshcd_set_link_off(hba);
4012
4013 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4014
4015 /* start controller initialization sequence */
4016 ufshcd_hba_start(hba);
4017
4018 /*
4019 * To initialize a UFS host controller HCE bit must be set to 1.
4020 * During initialization the HCE bit value changes from 1->0->1.
4021 * When the host controller completes initialization sequence
4022 * it sets the value of HCE bit to 1. The same HCE bit is read back
4023 * to check if the controller has completed initialization sequence.
4024 * So without this delay the value HCE = 1, set in the previous
4025 * instruction might be read back.
4026 * This delay can be changed based on the controller.
4027 */
4028 msleep(1);
4029
4030 /* wait for the host controller to complete initialization */
4031 retry = 10;
4032 while (ufshcd_is_hba_active(hba)) {
4033 if (retry) {
4034 retry--;
4035 } else {
4036 dev_err(hba->dev,
4037 "Controller enable failed\n");
4038 return -EIO;
4039 }
4040 msleep(5);
4041 }
4042
4043 /* enable UIC related interrupts */
4044 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4045
4046 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4047
4048 return 0;
4049 }
4050
4051 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4052 {
4053 int tx_lanes, i, err = 0;
4054
4055 if (!peer)
4056 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4057 &tx_lanes);
4058 else
4059 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4060 &tx_lanes);
4061 for (i = 0; i < tx_lanes; i++) {
4062 if (!peer)
4063 err = ufshcd_dme_set(hba,
4064 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4065 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4066 0);
4067 else
4068 err = ufshcd_dme_peer_set(hba,
4069 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4070 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4071 0);
4072 if (err) {
4073 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4074 __func__, peer, i, err);
4075 break;
4076 }
4077 }
4078
4079 return err;
4080 }
4081
4082 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4083 {
4084 return ufshcd_disable_tx_lcc(hba, true);
4085 }
4086
4087 /**
4088 * ufshcd_link_startup - Initialize unipro link startup
4089 * @hba: per adapter instance
4090 *
4091 * Returns 0 for success, non-zero in case of failure
4092 */
4093 static int ufshcd_link_startup(struct ufs_hba *hba)
4094 {
4095 int ret;
4096 int retries = DME_LINKSTARTUP_RETRIES;
4097 bool link_startup_again = false;
4098
4099 /*
4100 * If UFS device isn't active then we will have to issue link startup
4101 * 2 times to make sure the device state move to active.
4102 */
4103 if (!ufshcd_is_ufs_dev_active(hba))
4104 link_startup_again = true;
4105
4106 link_startup:
4107 do {
4108 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4109
4110 ret = ufshcd_dme_link_startup(hba);
4111
4112 /* check if device is detected by inter-connect layer */
4113 if (!ret && !ufshcd_is_device_present(hba)) {
4114 dev_err(hba->dev, "%s: Device not present\n", __func__);
4115 ret = -ENXIO;
4116 goto out;
4117 }
4118
4119 /*
4120 * DME link lost indication is only received when link is up,
4121 * but we can't be sure if the link is up until link startup
4122 * succeeds. So reset the local Uni-Pro and try again.
4123 */
4124 if (ret && ufshcd_hba_enable(hba))
4125 goto out;
4126 } while (ret && retries--);
4127
4128 if (ret)
4129 /* failed to get the link up... retire */
4130 goto out;
4131
4132 if (link_startup_again) {
4133 link_startup_again = false;
4134 retries = DME_LINKSTARTUP_RETRIES;
4135 goto link_startup;
4136 }
4137
4138 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4139 ufshcd_init_pwr_info(hba);
4140 ufshcd_print_pwr_info(hba);
4141
4142 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4143 ret = ufshcd_disable_device_tx_lcc(hba);
4144 if (ret)
4145 goto out;
4146 }
4147
4148 /* Include any host controller configuration via UIC commands */
4149 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4150 if (ret)
4151 goto out;
4152
4153 ret = ufshcd_make_hba_operational(hba);
4154 out:
4155 if (ret) {
4156 dev_err(hba->dev, "link startup failed %d\n", ret);
4157 ufshcd_print_host_state(hba);
4158 ufshcd_print_pwr_info(hba);
4159 ufshcd_print_host_regs(hba);
4160 }
4161 return ret;
4162 }
4163
4164 /**
4165 * ufshcd_verify_dev_init() - Verify device initialization
4166 * @hba: per-adapter instance
4167 *
4168 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4169 * device Transport Protocol (UTP) layer is ready after a reset.
4170 * If the UTP layer at the device side is not initialized, it may
4171 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4172 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4173 */
4174 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4175 {
4176 int err = 0;
4177 int retries;
4178
4179 ufshcd_hold(hba, false);
4180 mutex_lock(&hba->dev_cmd.lock);
4181 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4182 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4183 NOP_OUT_TIMEOUT);
4184
4185 if (!err || err == -ETIMEDOUT)
4186 break;
4187
4188 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4189 }
4190 mutex_unlock(&hba->dev_cmd.lock);
4191 ufshcd_release(hba);
4192
4193 if (err)
4194 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4195 return err;
4196 }
4197
4198 /**
4199 * ufshcd_set_queue_depth - set lun queue depth
4200 * @sdev: pointer to SCSI device
4201 *
4202 * Read bLUQueueDepth value and activate scsi tagged command
4203 * queueing. For WLUN, queue depth is set to 1. For best-effort
4204 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4205 * value that host can queue.
4206 */
4207 static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4208 {
4209 int ret = 0;
4210 u8 lun_qdepth;
4211 int retries;
4212 struct ufs_hba *hba;
4213
4214 hba = shost_priv(sdev->host);
4215
4216 lun_qdepth = hba->nutrs;
4217 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
4218 /* Read descriptor*/
4219 ret = ufshcd_read_unit_desc_param(hba,
4220 ufshcd_scsi_to_upiu_lun(sdev->lun),
4221 UNIT_DESC_PARAM_LU_Q_DEPTH,
4222 &lun_qdepth,
4223 sizeof(lun_qdepth));
4224 if (!ret || ret == -ENOTSUPP)
4225 break;
4226
4227 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, ret);
4228 }
4229
4230 /* Some WLUN doesn't support unit descriptor */
4231 if (ret == -EOPNOTSUPP)
4232 lun_qdepth = 1;
4233 else if (!lun_qdepth)
4234 /* eventually, we can figure out the real queue depth */
4235 lun_qdepth = hba->nutrs;
4236 else
4237 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4238
4239 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4240 __func__, lun_qdepth);
4241 scsi_change_queue_depth(sdev, lun_qdepth);
4242 }
4243
4244 /*
4245 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4246 * @hba: per-adapter instance
4247 * @lun: UFS device lun id
4248 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4249 *
4250 * Returns 0 in case of success and b_lu_write_protect status would be returned
4251 * @b_lu_write_protect parameter.
4252 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4253 * Returns -EINVAL in case of invalid parameters passed to this function.
4254 */
4255 static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4256 u8 lun,
4257 u8 *b_lu_write_protect)
4258 {
4259 int ret;
4260
4261 if (!b_lu_write_protect)
4262 ret = -EINVAL;
4263 /*
4264 * According to UFS device spec, RPMB LU can't be write
4265 * protected so skip reading bLUWriteProtect parameter for
4266 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4267 */
4268 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4269 ret = -ENOTSUPP;
4270 else
4271 ret = ufshcd_read_unit_desc_param(hba,
4272 lun,
4273 UNIT_DESC_PARAM_LU_WR_PROTECT,
4274 b_lu_write_protect,
4275 sizeof(*b_lu_write_protect));
4276 return ret;
4277 }
4278
4279 /**
4280 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4281 * status
4282 * @hba: per-adapter instance
4283 * @sdev: pointer to SCSI device
4284 *
4285 */
4286 static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4287 struct scsi_device *sdev)
4288 {
4289 if (hba->dev_info.f_power_on_wp_en &&
4290 !hba->dev_info.is_lu_power_on_wp) {
4291 u8 b_lu_write_protect;
4292
4293 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4294 &b_lu_write_protect) &&
4295 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4296 hba->dev_info.is_lu_power_on_wp = true;
4297 }
4298 }
4299
4300 /**
4301 * ufshcd_slave_alloc - handle initial SCSI device configurations
4302 * @sdev: pointer to SCSI device
4303 *
4304 * Returns success
4305 */
4306 static int ufshcd_slave_alloc(struct scsi_device *sdev)
4307 {
4308 struct ufs_hba *hba;
4309
4310 hba = shost_priv(sdev->host);
4311
4312 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4313 sdev->use_10_for_ms = 1;
4314
4315 /* allow SCSI layer to restart the device in case of errors */
4316 sdev->allow_restart = 1;
4317
4318 /* REPORT SUPPORTED OPERATION CODES is not supported */
4319 sdev->no_report_opcodes = 1;
4320
4321
4322 ufshcd_set_queue_depth(sdev);
4323
4324 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4325
4326 return 0;
4327 }
4328
4329 /**
4330 * ufshcd_change_queue_depth - change queue depth
4331 * @sdev: pointer to SCSI device
4332 * @depth: required depth to set
4333 *
4334 * Change queue depth and make sure the max. limits are not crossed.
4335 */
4336 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4337 {
4338 struct ufs_hba *hba = shost_priv(sdev->host);
4339
4340 if (depth > hba->nutrs)
4341 depth = hba->nutrs;
4342 return scsi_change_queue_depth(sdev, depth);
4343 }
4344
4345 /**
4346 * ufshcd_slave_configure - adjust SCSI device configurations
4347 * @sdev: pointer to SCSI device
4348 */
4349 static int ufshcd_slave_configure(struct scsi_device *sdev)
4350 {
4351 struct request_queue *q = sdev->request_queue;
4352
4353 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4354 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4355
4356 return 0;
4357 }
4358
4359 /**
4360 * ufshcd_slave_destroy - remove SCSI device configurations
4361 * @sdev: pointer to SCSI device
4362 */
4363 static void ufshcd_slave_destroy(struct scsi_device *sdev)
4364 {
4365 struct ufs_hba *hba;
4366
4367 hba = shost_priv(sdev->host);
4368 /* Drop the reference as it won't be needed anymore */
4369 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4370 unsigned long flags;
4371
4372 spin_lock_irqsave(hba->host->host_lock, flags);
4373 hba->sdev_ufs_device = NULL;
4374 spin_unlock_irqrestore(hba->host->host_lock, flags);
4375 }
4376 }
4377
4378 /**
4379 * ufshcd_task_req_compl - handle task management request completion
4380 * @hba: per adapter instance
4381 * @index: index of the completed request
4382 * @resp: task management service response
4383 *
4384 * Returns non-zero value on error, zero on success
4385 */
4386 static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
4387 {
4388 struct utp_task_req_desc *task_req_descp;
4389 struct utp_upiu_task_rsp *task_rsp_upiup;
4390 unsigned long flags;
4391 int ocs_value;
4392 int task_result;
4393
4394 spin_lock_irqsave(hba->host->host_lock, flags);
4395
4396 /* Clear completed tasks from outstanding_tasks */
4397 __clear_bit(index, &hba->outstanding_tasks);
4398
4399 task_req_descp = hba->utmrdl_base_addr;
4400 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
4401
4402 if (ocs_value == OCS_SUCCESS) {
4403 task_rsp_upiup = (struct utp_upiu_task_rsp *)
4404 task_req_descp[index].task_rsp_upiu;
4405 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
4406 task_result = task_result & MASK_TM_SERVICE_RESP;
4407 if (resp)
4408 *resp = (u8)task_result;
4409 } else {
4410 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
4411 __func__, ocs_value);
4412 }
4413 spin_unlock_irqrestore(hba->host->host_lock, flags);
4414
4415 return ocs_value;
4416 }
4417
4418 /**
4419 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
4420 * @lrb: pointer to local reference block of completed command
4421 * @scsi_status: SCSI command status
4422 *
4423 * Returns value base on SCSI command status
4424 */
4425 static inline int
4426 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4427 {
4428 int result = 0;
4429
4430 switch (scsi_status) {
4431 case SAM_STAT_CHECK_CONDITION:
4432 ufshcd_copy_sense_data(lrbp);
4433 case SAM_STAT_GOOD:
4434 result |= DID_OK << 16 |
4435 COMMAND_COMPLETE << 8 |
4436 scsi_status;
4437 break;
4438 case SAM_STAT_TASK_SET_FULL:
4439 case SAM_STAT_BUSY:
4440 case SAM_STAT_TASK_ABORTED:
4441 ufshcd_copy_sense_data(lrbp);
4442 result |= scsi_status;
4443 break;
4444 default:
4445 result |= DID_ERROR << 16;
4446 break;
4447 } /* end of switch */
4448
4449 return result;
4450 }
4451
4452 /**
4453 * ufshcd_transfer_rsp_status - Get overall status of the response
4454 * @hba: per adapter instance
4455 * @lrb: pointer to local reference block of completed command
4456 *
4457 * Returns result of the command to notify SCSI midlayer
4458 */
4459 static inline int
4460 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4461 {
4462 int result = 0;
4463 int scsi_status;
4464 int ocs;
4465
4466 /* overall command status of utrd */
4467 ocs = ufshcd_get_tr_ocs(lrbp);
4468
4469 switch (ocs) {
4470 case OCS_SUCCESS:
4471 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
4472 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
4473 switch (result) {
4474 case UPIU_TRANSACTION_RESPONSE:
4475 /*
4476 * get the response UPIU result to extract
4477 * the SCSI command status
4478 */
4479 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4480
4481 /*
4482 * get the result based on SCSI status response
4483 * to notify the SCSI midlayer of the command status
4484 */
4485 scsi_status = result & MASK_SCSI_STATUS;
4486 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
4487
4488 /*
4489 * Currently we are only supporting BKOPs exception
4490 * events hence we can ignore BKOPs exception event
4491 * during power management callbacks. BKOPs exception
4492 * event is not expected to be raised in runtime suspend
4493 * callback as it allows the urgent bkops.
4494 * During system suspend, we are anyway forcefully
4495 * disabling the bkops and if urgent bkops is needed
4496 * it will be enabled on system resume. Long term
4497 * solution could be to abort the system suspend if
4498 * UFS device needs urgent BKOPs.
4499 */
4500 if (!hba->pm_op_in_progress &&
4501 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
4502 schedule_work(&hba->eeh_work);
4503 break;
4504 case UPIU_TRANSACTION_REJECT_UPIU:
4505 /* TODO: handle Reject UPIU Response */
4506 result = DID_ERROR << 16;
4507 dev_err(hba->dev,
4508 "Reject UPIU not fully implemented\n");
4509 break;
4510 default:
4511 result = DID_ERROR << 16;
4512 dev_err(hba->dev,
4513 "Unexpected request response code = %x\n",
4514 result);
4515 break;
4516 }
4517 break;
4518 case OCS_ABORTED:
4519 result |= DID_ABORT << 16;
4520 break;
4521 case OCS_INVALID_COMMAND_STATUS:
4522 result |= DID_REQUEUE << 16;
4523 break;
4524 case OCS_INVALID_CMD_TABLE_ATTR:
4525 case OCS_INVALID_PRDT_ATTR:
4526 case OCS_MISMATCH_DATA_BUF_SIZE:
4527 case OCS_MISMATCH_RESP_UPIU_SIZE:
4528 case OCS_PEER_COMM_FAILURE:
4529 case OCS_FATAL_ERROR:
4530 default:
4531 result |= DID_ERROR << 16;
4532 dev_err(hba->dev,
4533 "OCS error from controller = %x for tag %d\n",
4534 ocs, lrbp->task_tag);
4535 ufshcd_print_host_regs(hba);
4536 ufshcd_print_host_state(hba);
4537 break;
4538 } /* end of switch */
4539
4540 if (host_byte(result) != DID_OK)
4541 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
4542 return result;
4543 }
4544
4545 /**
4546 * ufshcd_uic_cmd_compl - handle completion of uic command
4547 * @hba: per adapter instance
4548 * @intr_status: interrupt status generated by the controller
4549 */
4550 static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
4551 {
4552 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
4553 hba->active_uic_cmd->argument2 |=
4554 ufshcd_get_uic_cmd_result(hba);
4555 hba->active_uic_cmd->argument3 =
4556 ufshcd_get_dme_attr_val(hba);
4557 complete(&hba->active_uic_cmd->done);
4558 }
4559
4560 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4561 complete(hba->uic_async_done);
4562 }
4563
4564 /**
4565 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
4566 * @hba: per adapter instance
4567 * @completed_reqs: requests to complete
4568 */
4569 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4570 unsigned long completed_reqs)
4571 {
4572 struct ufshcd_lrb *lrbp;
4573 struct scsi_cmnd *cmd;
4574 int result;
4575 int index;
4576
4577 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4578 lrbp = &hba->lrb[index];
4579 cmd = lrbp->cmd;
4580 if (cmd) {
4581 ufshcd_add_command_trace(hba, index, "complete");
4582 result = ufshcd_transfer_rsp_status(hba, lrbp);
4583 scsi_dma_unmap(cmd);
4584 cmd->result = result;
4585 /* Mark completed command as NULL in LRB */
4586 lrbp->cmd = NULL;
4587 clear_bit_unlock(index, &hba->lrb_in_use);
4588 /* Do not touch lrbp after scsi done */
4589 cmd->scsi_done(cmd);
4590 __ufshcd_release(hba);
4591 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4592 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
4593 if (hba->dev_cmd.complete) {
4594 ufshcd_add_command_trace(hba, index,
4595 "dev_complete");
4596 complete(hba->dev_cmd.complete);
4597 }
4598 }
4599 if (ufshcd_is_clkscaling_supported(hba))
4600 hba->clk_scaling.active_reqs--;
4601 if (ufshcd_is_clkscaling_supported(hba))
4602 hba->clk_scaling.active_reqs--;
4603 }
4604
4605 /* clear corresponding bits of completed commands */
4606 hba->outstanding_reqs ^= completed_reqs;
4607
4608 ufshcd_clk_scaling_update_busy(hba);
4609
4610 /* we might have free'd some tags above */
4611 wake_up(&hba->dev_cmd.tag_wq);
4612 }
4613
4614 /**
4615 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4616 * @hba: per adapter instance
4617 */
4618 static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4619 {
4620 unsigned long completed_reqs;
4621 u32 tr_doorbell;
4622
4623 /* Resetting interrupt aggregation counters first and reading the
4624 * DOOR_BELL afterward allows us to handle all the completed requests.
4625 * In order to prevent other interrupts starvation the DB is read once
4626 * after reset. The down side of this solution is the possibility of
4627 * false interrupt if device completes another request after resetting
4628 * aggregation and before reading the DB.
4629 */
4630 if (ufshcd_is_intr_aggr_allowed(hba))
4631 ufshcd_reset_intr_aggr(hba);
4632
4633 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4634 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4635
4636 __ufshcd_transfer_req_compl(hba, completed_reqs);
4637 }
4638
4639 /**
4640 * ufshcd_disable_ee - disable exception event
4641 * @hba: per-adapter instance
4642 * @mask: exception event to disable
4643 *
4644 * Disables exception event in the device so that the EVENT_ALERT
4645 * bit is not set.
4646 *
4647 * Returns zero on success, non-zero error value on failure.
4648 */
4649 static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4650 {
4651 int err = 0;
4652 u32 val;
4653
4654 if (!(hba->ee_ctrl_mask & mask))
4655 goto out;
4656
4657 val = hba->ee_ctrl_mask & ~mask;
4658 val &= 0xFFFF; /* 2 bytes */
4659 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4660 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4661 if (!err)
4662 hba->ee_ctrl_mask &= ~mask;
4663 out:
4664 return err;
4665 }
4666
4667 /**
4668 * ufshcd_enable_ee - enable exception event
4669 * @hba: per-adapter instance
4670 * @mask: exception event to enable
4671 *
4672 * Enable corresponding exception event in the device to allow
4673 * device to alert host in critical scenarios.
4674 *
4675 * Returns zero on success, non-zero error value on failure.
4676 */
4677 static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4678 {
4679 int err = 0;
4680 u32 val;
4681
4682 if (hba->ee_ctrl_mask & mask)
4683 goto out;
4684
4685 val = hba->ee_ctrl_mask | mask;
4686 val &= 0xFFFF; /* 2 bytes */
4687 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4688 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4689 if (!err)
4690 hba->ee_ctrl_mask |= mask;
4691 out:
4692 return err;
4693 }
4694
4695 /**
4696 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4697 * @hba: per-adapter instance
4698 *
4699 * Allow device to manage background operations on its own. Enabling
4700 * this might lead to inconsistent latencies during normal data transfers
4701 * as the device is allowed to manage its own way of handling background
4702 * operations.
4703 *
4704 * Returns zero on success, non-zero on failure.
4705 */
4706 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4707 {
4708 int err = 0;
4709
4710 if (hba->auto_bkops_enabled)
4711 goto out;
4712
4713 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4714 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4715 if (err) {
4716 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4717 __func__, err);
4718 goto out;
4719 }
4720
4721 hba->auto_bkops_enabled = true;
4722 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
4723
4724 /* No need of URGENT_BKOPS exception from the device */
4725 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4726 if (err)
4727 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4728 __func__, err);
4729 out:
4730 return err;
4731 }
4732
4733 /**
4734 * ufshcd_disable_auto_bkops - block device in doing background operations
4735 * @hba: per-adapter instance
4736 *
4737 * Disabling background operations improves command response latency but
4738 * has drawback of device moving into critical state where the device is
4739 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4740 * host is idle so that BKOPS are managed effectively without any negative
4741 * impacts.
4742 *
4743 * Returns zero on success, non-zero on failure.
4744 */
4745 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4746 {
4747 int err = 0;
4748
4749 if (!hba->auto_bkops_enabled)
4750 goto out;
4751
4752 /*
4753 * If host assisted BKOPs is to be enabled, make sure
4754 * urgent bkops exception is allowed.
4755 */
4756 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4757 if (err) {
4758 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4759 __func__, err);
4760 goto out;
4761 }
4762
4763 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
4764 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4765 if (err) {
4766 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4767 __func__, err);
4768 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4769 goto out;
4770 }
4771
4772 hba->auto_bkops_enabled = false;
4773 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
4774 out:
4775 return err;
4776 }
4777
4778 /**
4779 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
4780 * @hba: per adapter instance
4781 *
4782 * After a device reset the device may toggle the BKOPS_EN flag
4783 * to default value. The s/w tracking variables should be updated
4784 * as well. This function would change the auto-bkops state based on
4785 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
4786 */
4787 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
4788 {
4789 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4790 hba->auto_bkops_enabled = false;
4791 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4792 ufshcd_enable_auto_bkops(hba);
4793 } else {
4794 hba->auto_bkops_enabled = true;
4795 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4796 ufshcd_disable_auto_bkops(hba);
4797 }
4798 }
4799
4800 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4801 {
4802 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
4803 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
4804 }
4805
4806 /**
4807 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
4808 * @hba: per-adapter instance
4809 * @status: bkops_status value
4810 *
4811 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
4812 * flag in the device to permit background operations if the device
4813 * bkops_status is greater than or equal to "status" argument passed to
4814 * this function, disable otherwise.
4815 *
4816 * Returns 0 for success, non-zero in case of failure.
4817 *
4818 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
4819 * to know whether auto bkops is enabled or disabled after this function
4820 * returns control to it.
4821 */
4822 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
4823 enum bkops_status status)
4824 {
4825 int err;
4826 u32 curr_status = 0;
4827
4828 err = ufshcd_get_bkops_status(hba, &curr_status);
4829 if (err) {
4830 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4831 __func__, err);
4832 goto out;
4833 } else if (curr_status > BKOPS_STATUS_MAX) {
4834 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
4835 __func__, curr_status);
4836 err = -EINVAL;
4837 goto out;
4838 }
4839
4840 if (curr_status >= status)
4841 err = ufshcd_enable_auto_bkops(hba);
4842 else
4843 err = ufshcd_disable_auto_bkops(hba);
4844 out:
4845 return err;
4846 }
4847
4848 /**
4849 * ufshcd_urgent_bkops - handle urgent bkops exception event
4850 * @hba: per-adapter instance
4851 *
4852 * Enable fBackgroundOpsEn flag in the device to permit background
4853 * operations.
4854 *
4855 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
4856 * and negative error value for any other failure.
4857 */
4858 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
4859 {
4860 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
4861 }
4862
4863 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
4864 {
4865 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
4866 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
4867 }
4868
4869 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
4870 {
4871 int err;
4872 u32 curr_status = 0;
4873
4874 if (hba->is_urgent_bkops_lvl_checked)
4875 goto enable_auto_bkops;
4876
4877 err = ufshcd_get_bkops_status(hba, &curr_status);
4878 if (err) {
4879 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4880 __func__, err);
4881 goto out;
4882 }
4883
4884 /*
4885 * We are seeing that some devices are raising the urgent bkops
4886 * exception events even when BKOPS status doesn't indicate performace
4887 * impacted or critical. Handle these device by determining their urgent
4888 * bkops status at runtime.
4889 */
4890 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
4891 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
4892 __func__, curr_status);
4893 /* update the current status as the urgent bkops level */
4894 hba->urgent_bkops_lvl = curr_status;
4895 hba->is_urgent_bkops_lvl_checked = true;
4896 }
4897
4898 enable_auto_bkops:
4899 err = ufshcd_enable_auto_bkops(hba);
4900 out:
4901 if (err < 0)
4902 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
4903 __func__, err);
4904 }
4905
4906 /**
4907 * ufshcd_exception_event_handler - handle exceptions raised by device
4908 * @work: pointer to work data
4909 *
4910 * Read bExceptionEventStatus attribute from the device and handle the
4911 * exception event accordingly.
4912 */
4913 static void ufshcd_exception_event_handler(struct work_struct *work)
4914 {
4915 struct ufs_hba *hba;
4916 int err;
4917 u32 status = 0;
4918 hba = container_of(work, struct ufs_hba, eeh_work);
4919
4920 pm_runtime_get_sync(hba->dev);
4921 err = ufshcd_get_ee_status(hba, &status);
4922 if (err) {
4923 dev_err(hba->dev, "%s: failed to get exception status %d\n",
4924 __func__, err);
4925 goto out;
4926 }
4927
4928 status &= hba->ee_ctrl_mask;
4929
4930 if (status & MASK_EE_URGENT_BKOPS)
4931 ufshcd_bkops_exception_event_handler(hba);
4932
4933 out:
4934 pm_runtime_put_sync(hba->dev);
4935 return;
4936 }
4937
4938 /* Complete requests that have door-bell cleared */
4939 static void ufshcd_complete_requests(struct ufs_hba *hba)
4940 {
4941 ufshcd_transfer_req_compl(hba);
4942 ufshcd_tmc_handler(hba);
4943 }
4944
4945 /**
4946 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
4947 * to recover from the DL NAC errors or not.
4948 * @hba: per-adapter instance
4949 *
4950 * Returns true if error handling is required, false otherwise
4951 */
4952 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
4953 {
4954 unsigned long flags;
4955 bool err_handling = true;
4956
4957 spin_lock_irqsave(hba->host->host_lock, flags);
4958 /*
4959 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
4960 * device fatal error and/or DL NAC & REPLAY timeout errors.
4961 */
4962 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
4963 goto out;
4964
4965 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
4966 ((hba->saved_err & UIC_ERROR) &&
4967 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
4968 goto out;
4969
4970 if ((hba->saved_err & UIC_ERROR) &&
4971 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
4972 int err;
4973 /*
4974 * wait for 50ms to see if we can get any other errors or not.
4975 */
4976 spin_unlock_irqrestore(hba->host->host_lock, flags);
4977 msleep(50);
4978 spin_lock_irqsave(hba->host->host_lock, flags);
4979
4980 /*
4981 * now check if we have got any other severe errors other than
4982 * DL NAC error?
4983 */
4984 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4985 ((hba->saved_err & UIC_ERROR) &&
4986 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
4987 goto out;
4988
4989 /*
4990 * As DL NAC is the only error received so far, send out NOP
4991 * command to confirm if link is still active or not.
4992 * - If we don't get any response then do error recovery.
4993 * - If we get response then clear the DL NAC error bit.
4994 */
4995
4996 spin_unlock_irqrestore(hba->host->host_lock, flags);
4997 err = ufshcd_verify_dev_init(hba);
4998 spin_lock_irqsave(hba->host->host_lock, flags);
4999
5000 if (err)
5001 goto out;
5002
5003 /* Link seems to be alive hence ignore the DL NAC errors */
5004 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5005 hba->saved_err &= ~UIC_ERROR;
5006 /* clear NAC error */
5007 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5008 if (!hba->saved_uic_err) {
5009 err_handling = false;
5010 goto out;
5011 }
5012 }
5013 out:
5014 spin_unlock_irqrestore(hba->host->host_lock, flags);
5015 return err_handling;
5016 }
5017
5018 /**
5019 * ufshcd_err_handler - handle UFS errors that require s/w attention
5020 * @work: pointer to work structure
5021 */
5022 static void ufshcd_err_handler(struct work_struct *work)
5023 {
5024 struct ufs_hba *hba;
5025 unsigned long flags;
5026 u32 err_xfer = 0;
5027 u32 err_tm = 0;
5028 int err = 0;
5029 int tag;
5030 bool needs_reset = false;
5031
5032 hba = container_of(work, struct ufs_hba, eh_work);
5033
5034 pm_runtime_get_sync(hba->dev);
5035 ufshcd_hold(hba, false);
5036
5037 spin_lock_irqsave(hba->host->host_lock, flags);
5038 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
5039 goto out;
5040
5041 hba->ufshcd_state = UFSHCD_STATE_RESET;
5042 ufshcd_set_eh_in_progress(hba);
5043
5044 /* Complete requests that have door-bell cleared by h/w */
5045 ufshcd_complete_requests(hba);
5046
5047 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5048 bool ret;
5049
5050 spin_unlock_irqrestore(hba->host->host_lock, flags);
5051 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5052 ret = ufshcd_quirk_dl_nac_errors(hba);
5053 spin_lock_irqsave(hba->host->host_lock, flags);
5054 if (!ret)
5055 goto skip_err_handling;
5056 }
5057 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5058 ((hba->saved_err & UIC_ERROR) &&
5059 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5060 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5061 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5062 needs_reset = true;
5063
5064 /*
5065 * if host reset is required then skip clearing the pending
5066 * transfers forcefully because they will automatically get
5067 * cleared after link startup.
5068 */
5069 if (needs_reset)
5070 goto skip_pending_xfer_clear;
5071
5072 /* release lock as clear command might sleep */
5073 spin_unlock_irqrestore(hba->host->host_lock, flags);
5074 /* Clear pending transfer requests */
5075 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5076 if (ufshcd_clear_cmd(hba, tag)) {
5077 err_xfer = true;
5078 goto lock_skip_pending_xfer_clear;
5079 }
5080 }
5081
5082 /* Clear pending task management requests */
5083 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5084 if (ufshcd_clear_tm_cmd(hba, tag)) {
5085 err_tm = true;
5086 goto lock_skip_pending_xfer_clear;
5087 }
5088 }
5089
5090 lock_skip_pending_xfer_clear:
5091 spin_lock_irqsave(hba->host->host_lock, flags);
5092
5093 /* Complete the requests that are cleared by s/w */
5094 ufshcd_complete_requests(hba);
5095
5096 if (err_xfer || err_tm)
5097 needs_reset = true;
5098
5099 skip_pending_xfer_clear:
5100 /* Fatal errors need reset */
5101 if (needs_reset) {
5102 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5103
5104 /*
5105 * ufshcd_reset_and_restore() does the link reinitialization
5106 * which will need atleast one empty doorbell slot to send the
5107 * device management commands (NOP and query commands).
5108 * If there is no slot empty at this moment then free up last
5109 * slot forcefully.
5110 */
5111 if (hba->outstanding_reqs == max_doorbells)
5112 __ufshcd_transfer_req_compl(hba,
5113 (1UL << (hba->nutrs - 1)));
5114
5115 spin_unlock_irqrestore(hba->host->host_lock, flags);
5116 err = ufshcd_reset_and_restore(hba);
5117 spin_lock_irqsave(hba->host->host_lock, flags);
5118 if (err) {
5119 dev_err(hba->dev, "%s: reset and restore failed\n",
5120 __func__);
5121 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5122 }
5123 /*
5124 * Inform scsi mid-layer that we did reset and allow to handle
5125 * Unit Attention properly.
5126 */
5127 scsi_report_bus_reset(hba->host, 0);
5128 hba->saved_err = 0;
5129 hba->saved_uic_err = 0;
5130 }
5131
5132 skip_err_handling:
5133 if (!needs_reset) {
5134 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5135 if (hba->saved_err || hba->saved_uic_err)
5136 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5137 __func__, hba->saved_err, hba->saved_uic_err);
5138 }
5139
5140 ufshcd_clear_eh_in_progress(hba);
5141
5142 out:
5143 spin_unlock_irqrestore(hba->host->host_lock, flags);
5144 scsi_unblock_requests(hba->host);
5145 ufshcd_release(hba);
5146 pm_runtime_put_sync(hba->dev);
5147 }
5148
5149 static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5150 u32 reg)
5151 {
5152 reg_hist->reg[reg_hist->pos] = reg;
5153 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5154 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5155 }
5156
5157 /**
5158 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5159 * @hba: per-adapter instance
5160 */
5161 static void ufshcd_update_uic_error(struct ufs_hba *hba)
5162 {
5163 u32 reg;
5164
5165 /* PHY layer lane error */
5166 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5167 /* Ignore LINERESET indication, as this is not an error */
5168 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
5169 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
5170 /*
5171 * To know whether this error is fatal or not, DB timeout
5172 * must be checked but this error is handled separately.
5173 */
5174 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
5175 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5176 }
5177
5178 /* PA_INIT_ERROR is fatal and needs UIC reset */
5179 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
5180 if (reg)
5181 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5182
5183 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5184 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
5185 else if (hba->dev_quirks &
5186 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5187 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5188 hba->uic_error |=
5189 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5190 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5191 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5192 }
5193
5194 /* UIC NL/TL/DME errors needs software retry */
5195 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
5196 if (reg) {
5197 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
5198 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
5199 }
5200
5201 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
5202 if (reg) {
5203 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
5204 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
5205 }
5206
5207 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
5208 if (reg) {
5209 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
5210 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
5211 }
5212
5213 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5214 __func__, hba->uic_error);
5215 }
5216
5217 /**
5218 * ufshcd_check_errors - Check for errors that need s/w attention
5219 * @hba: per-adapter instance
5220 */
5221 static void ufshcd_check_errors(struct ufs_hba *hba)
5222 {
5223 bool queue_eh_work = false;
5224
5225 if (hba->errors & INT_FATAL_ERRORS)
5226 queue_eh_work = true;
5227
5228 if (hba->errors & UIC_ERROR) {
5229 hba->uic_error = 0;
5230 ufshcd_update_uic_error(hba);
5231 if (hba->uic_error)
5232 queue_eh_work = true;
5233 }
5234
5235 if (queue_eh_work) {
5236 /*
5237 * update the transfer error masks to sticky bits, let's do this
5238 * irrespective of current ufshcd_state.
5239 */
5240 hba->saved_err |= hba->errors;
5241 hba->saved_uic_err |= hba->uic_error;
5242
5243 /* handle fatal errors only when link is functional */
5244 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5245 /* block commands from scsi mid-layer */
5246 scsi_block_requests(hba->host);
5247
5248 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
5249
5250 /* dump controller state before resetting */
5251 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5252 bool pr_prdt = !!(hba->saved_err &
5253 SYSTEM_BUS_FATAL_ERROR);
5254
5255 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5256 __func__, hba->saved_err,
5257 hba->saved_uic_err);
5258
5259 ufshcd_print_host_regs(hba);
5260 ufshcd_print_pwr_info(hba);
5261 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5262 ufshcd_print_trs(hba, hba->outstanding_reqs,
5263 pr_prdt);
5264 }
5265 schedule_work(&hba->eh_work);
5266 }
5267 }
5268 /*
5269 * if (!queue_eh_work) -
5270 * Other errors are either non-fatal where host recovers
5271 * itself without s/w intervention or errors that will be
5272 * handled by the SCSI core layer.
5273 */
5274 }
5275
5276 /**
5277 * ufshcd_tmc_handler - handle task management function completion
5278 * @hba: per adapter instance
5279 */
5280 static void ufshcd_tmc_handler(struct ufs_hba *hba)
5281 {
5282 u32 tm_doorbell;
5283
5284 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
5285 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
5286 wake_up(&hba->tm_wq);
5287 }
5288
5289 /**
5290 * ufshcd_sl_intr - Interrupt service routine
5291 * @hba: per adapter instance
5292 * @intr_status: contains interrupts generated by the controller
5293 */
5294 static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5295 {
5296 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5297 if (hba->errors)
5298 ufshcd_check_errors(hba);
5299
5300 if (intr_status & UFSHCD_UIC_MASK)
5301 ufshcd_uic_cmd_compl(hba, intr_status);
5302
5303 if (intr_status & UTP_TASK_REQ_COMPL)
5304 ufshcd_tmc_handler(hba);
5305
5306 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5307 ufshcd_transfer_req_compl(hba);
5308 }
5309
5310 /**
5311 * ufshcd_intr - Main interrupt service routine
5312 * @irq: irq number
5313 * @__hba: pointer to adapter instance
5314 *
5315 * Returns IRQ_HANDLED - If interrupt is valid
5316 * IRQ_NONE - If invalid interrupt
5317 */
5318 static irqreturn_t ufshcd_intr(int irq, void *__hba)
5319 {
5320 u32 intr_status, enabled_intr_status;
5321 irqreturn_t retval = IRQ_NONE;
5322 struct ufs_hba *hba = __hba;
5323
5324 spin_lock(hba->host->host_lock);
5325 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5326 enabled_intr_status =
5327 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5328
5329 if (intr_status)
5330 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
5331
5332 if (enabled_intr_status) {
5333 ufshcd_sl_intr(hba, enabled_intr_status);
5334 retval = IRQ_HANDLED;
5335 }
5336 spin_unlock(hba->host->host_lock);
5337 return retval;
5338 }
5339
5340 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5341 {
5342 int err = 0;
5343 u32 mask = 1 << tag;
5344 unsigned long flags;
5345
5346 if (!test_bit(tag, &hba->outstanding_tasks))
5347 goto out;
5348
5349 spin_lock_irqsave(hba->host->host_lock, flags);
5350 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
5351 spin_unlock_irqrestore(hba->host->host_lock, flags);
5352
5353 /* poll for max. 1 sec to clear door bell register by h/w */
5354 err = ufshcd_wait_for_register(hba,
5355 REG_UTP_TASK_REQ_DOOR_BELL,
5356 mask, 0, 1000, 1000, true);
5357 out:
5358 return err;
5359 }
5360
5361 /**
5362 * ufshcd_issue_tm_cmd - issues task management commands to controller
5363 * @hba: per adapter instance
5364 * @lun_id: LUN ID to which TM command is sent
5365 * @task_id: task ID to which the TM command is applicable
5366 * @tm_function: task management function opcode
5367 * @tm_response: task management service response return value
5368 *
5369 * Returns non-zero value on error, zero on success.
5370 */
5371 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5372 u8 tm_function, u8 *tm_response)
5373 {
5374 struct utp_task_req_desc *task_req_descp;
5375 struct utp_upiu_task_req *task_req_upiup;
5376 struct Scsi_Host *host;
5377 unsigned long flags;
5378 int free_slot;
5379 int err;
5380 int task_tag;
5381
5382 host = hba->host;
5383
5384 /*
5385 * Get free slot, sleep if slots are unavailable.
5386 * Even though we use wait_event() which sleeps indefinitely,
5387 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5388 */
5389 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
5390 ufshcd_hold(hba, false);
5391
5392 spin_lock_irqsave(host->host_lock, flags);
5393 task_req_descp = hba->utmrdl_base_addr;
5394 task_req_descp += free_slot;
5395
5396 /* Configure task request descriptor */
5397 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5398 task_req_descp->header.dword_2 =
5399 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5400
5401 /* Configure task request UPIU */
5402 task_req_upiup =
5403 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
5404 task_tag = hba->nutrs + free_slot;
5405 task_req_upiup->header.dword_0 =
5406 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
5407 lun_id, task_tag);
5408 task_req_upiup->header.dword_1 =
5409 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
5410 /*
5411 * The host shall provide the same value for LUN field in the basic
5412 * header and for Input Parameter.
5413 */
5414 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
5415 task_req_upiup->input_param2 = cpu_to_be32(task_id);
5416
5417 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5418
5419 /* send command to the controller */
5420 __set_bit(free_slot, &hba->outstanding_tasks);
5421
5422 /* Make sure descriptors are ready before ringing the task doorbell */
5423 wmb();
5424
5425 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
5426 /* Make sure that doorbell is committed immediately */
5427 wmb();
5428
5429 spin_unlock_irqrestore(host->host_lock, flags);
5430
5431 /* wait until the task management command is completed */
5432 err = wait_event_timeout(hba->tm_wq,
5433 test_bit(free_slot, &hba->tm_condition),
5434 msecs_to_jiffies(TM_CMD_TIMEOUT));
5435 if (!err) {
5436 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5437 __func__, tm_function);
5438 if (ufshcd_clear_tm_cmd(hba, free_slot))
5439 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5440 __func__, free_slot);
5441 err = -ETIMEDOUT;
5442 } else {
5443 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
5444 }
5445
5446 clear_bit(free_slot, &hba->tm_condition);
5447 ufshcd_put_tm_slot(hba, free_slot);
5448 wake_up(&hba->tm_tag_wq);
5449
5450 ufshcd_release(hba);
5451 return err;
5452 }
5453
5454 /**
5455 * ufshcd_eh_device_reset_handler - device reset handler registered to
5456 * scsi layer.
5457 * @cmd: SCSI command pointer
5458 *
5459 * Returns SUCCESS/FAILED
5460 */
5461 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
5462 {
5463 struct Scsi_Host *host;
5464 struct ufs_hba *hba;
5465 unsigned int tag;
5466 u32 pos;
5467 int err;
5468 u8 resp = 0xF;
5469 struct ufshcd_lrb *lrbp;
5470 unsigned long flags;
5471
5472 host = cmd->device->host;
5473 hba = shost_priv(host);
5474 tag = cmd->request->tag;
5475
5476 lrbp = &hba->lrb[tag];
5477 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5478 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
5479 if (!err)
5480 err = resp;
5481 goto out;
5482 }
5483
5484 /* clear the commands that were pending for corresponding LUN */
5485 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5486 if (hba->lrb[pos].lun == lrbp->lun) {
5487 err = ufshcd_clear_cmd(hba, pos);
5488 if (err)
5489 break;
5490 }
5491 }
5492 spin_lock_irqsave(host->host_lock, flags);
5493 ufshcd_transfer_req_compl(hba);
5494 spin_unlock_irqrestore(host->host_lock, flags);
5495
5496 out:
5497 hba->req_abort_count = 0;
5498 if (!err) {
5499 err = SUCCESS;
5500 } else {
5501 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5502 err = FAILED;
5503 }
5504 return err;
5505 }
5506
5507 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5508 {
5509 struct ufshcd_lrb *lrbp;
5510 int tag;
5511
5512 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5513 lrbp = &hba->lrb[tag];
5514 lrbp->req_abort_skip = true;
5515 }
5516 }
5517
5518 /**
5519 * ufshcd_abort - abort a specific command
5520 * @cmd: SCSI command pointer
5521 *
5522 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5523 * command, and in host controller by clearing the door-bell register. There can
5524 * be race between controller sending the command to the device while abort is
5525 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5526 * really issued and then try to abort it.
5527 *
5528 * Returns SUCCESS/FAILED
5529 */
5530 static int ufshcd_abort(struct scsi_cmnd *cmd)
5531 {
5532 struct Scsi_Host *host;
5533 struct ufs_hba *hba;
5534 unsigned long flags;
5535 unsigned int tag;
5536 int err = 0;
5537 int poll_cnt;
5538 u8 resp = 0xF;
5539 struct ufshcd_lrb *lrbp;
5540 u32 reg;
5541
5542 host = cmd->device->host;
5543 hba = shost_priv(host);
5544 tag = cmd->request->tag;
5545 lrbp = &hba->lrb[tag];
5546 if (!ufshcd_valid_tag(hba, tag)) {
5547 dev_err(hba->dev,
5548 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5549 __func__, tag, cmd, cmd->request);
5550 BUG();
5551 }
5552
5553 /*
5554 * Task abort to the device W-LUN is illegal. When this command
5555 * will fail, due to spec violation, scsi err handling next step
5556 * will be to send LU reset which, again, is a spec violation.
5557 * To avoid these unnecessary/illegal step we skip to the last error
5558 * handling stage: reset and restore.
5559 */
5560 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5561 return ufshcd_eh_host_reset_handler(cmd);
5562
5563 ufshcd_hold(hba, false);
5564 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5565 /* If command is already aborted/completed, return SUCCESS */
5566 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5567 dev_err(hba->dev,
5568 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5569 __func__, tag, hba->outstanding_reqs, reg);
5570 goto out;
5571 }
5572
5573 if (!(reg & (1 << tag))) {
5574 dev_err(hba->dev,
5575 "%s: cmd was completed, but without a notifying intr, tag = %d",
5576 __func__, tag);
5577 }
5578
5579 /* Print Transfer Request of aborted task */
5580 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
5581
5582 /*
5583 * Print detailed info about aborted request.
5584 * As more than one request might get aborted at the same time,
5585 * print full information only for the first aborted request in order
5586 * to reduce repeated printouts. For other aborted requests only print
5587 * basic details.
5588 */
5589 scsi_print_command(hba->lrb[tag].cmd);
5590 if (!hba->req_abort_count) {
5591 ufshcd_print_host_regs(hba);
5592 ufshcd_print_host_state(hba);
5593 ufshcd_print_pwr_info(hba);
5594 ufshcd_print_trs(hba, 1 << tag, true);
5595 } else {
5596 ufshcd_print_trs(hba, 1 << tag, false);
5597 }
5598 hba->req_abort_count++;
5599
5600 /* Skip task abort in case previous aborts failed and report failure */
5601 if (lrbp->req_abort_skip) {
5602 err = -EIO;
5603 goto out;
5604 }
5605
5606 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
5607 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5608 UFS_QUERY_TASK, &resp);
5609 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
5610 /* cmd pending in the device */
5611 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
5612 __func__, tag);
5613 break;
5614 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
5615 /*
5616 * cmd not pending in the device, check if it is
5617 * in transition.
5618 */
5619 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
5620 __func__, tag);
5621 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5622 if (reg & (1 << tag)) {
5623 /* sleep for max. 200us to stabilize */
5624 usleep_range(100, 200);
5625 continue;
5626 }
5627 /* command completed already */
5628 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
5629 __func__, tag);
5630 goto out;
5631 } else {
5632 dev_err(hba->dev,
5633 "%s: no response from device. tag = %d, err %d\n",
5634 __func__, tag, err);
5635 if (!err)
5636 err = resp; /* service response error */
5637 goto out;
5638 }
5639 }
5640
5641 if (!poll_cnt) {
5642 err = -EBUSY;
5643 goto out;
5644 }
5645
5646 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5647 UFS_ABORT_TASK, &resp);
5648 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
5649 if (!err) {
5650 err = resp; /* service response error */
5651 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
5652 __func__, tag, err);
5653 }
5654 goto out;
5655 }
5656
5657 err = ufshcd_clear_cmd(hba, tag);
5658 if (err) {
5659 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
5660 __func__, tag, err);
5661 goto out;
5662 }
5663
5664 scsi_dma_unmap(cmd);
5665
5666 spin_lock_irqsave(host->host_lock, flags);
5667 ufshcd_outstanding_req_clear(hba, tag);
5668 hba->lrb[tag].cmd = NULL;
5669 spin_unlock_irqrestore(host->host_lock, flags);
5670
5671 clear_bit_unlock(tag, &hba->lrb_in_use);
5672 wake_up(&hba->dev_cmd.tag_wq);
5673
5674 out:
5675 if (!err) {
5676 err = SUCCESS;
5677 } else {
5678 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5679 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
5680 err = FAILED;
5681 }
5682
5683 /*
5684 * This ufshcd_release() corresponds to the original scsi cmd that got
5685 * aborted here (as we won't get any IRQ for it).
5686 */
5687 ufshcd_release(hba);
5688 return err;
5689 }
5690
5691 /**
5692 * ufshcd_host_reset_and_restore - reset and restore host controller
5693 * @hba: per-adapter instance
5694 *
5695 * Note that host controller reset may issue DME_RESET to
5696 * local and remote (device) Uni-Pro stack and the attributes
5697 * are reset to default state.
5698 *
5699 * Returns zero on success, non-zero on failure
5700 */
5701 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
5702 {
5703 int err;
5704 unsigned long flags;
5705
5706 /* Reset the host controller */
5707 spin_lock_irqsave(hba->host->host_lock, flags);
5708 ufshcd_hba_stop(hba, false);
5709 spin_unlock_irqrestore(hba->host->host_lock, flags);
5710
5711 /* scale up clocks to max frequency before full reinitialization */
5712 ufshcd_scale_clks(hba, true);
5713
5714 err = ufshcd_hba_enable(hba);
5715 if (err)
5716 goto out;
5717
5718 /* Establish the link again and restore the device */
5719 err = ufshcd_probe_hba(hba);
5720
5721 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
5722 err = -EIO;
5723 out:
5724 if (err)
5725 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
5726
5727 return err;
5728 }
5729
5730 /**
5731 * ufshcd_reset_and_restore - reset and re-initialize host/device
5732 * @hba: per-adapter instance
5733 *
5734 * Reset and recover device, host and re-establish link. This
5735 * is helpful to recover the communication in fatal error conditions.
5736 *
5737 * Returns zero on success, non-zero on failure
5738 */
5739 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
5740 {
5741 int err = 0;
5742 unsigned long flags;
5743 int retries = MAX_HOST_RESET_RETRIES;
5744
5745 do {
5746 err = ufshcd_host_reset_and_restore(hba);
5747 } while (err && --retries);
5748
5749 /*
5750 * After reset the door-bell might be cleared, complete
5751 * outstanding requests in s/w here.
5752 */
5753 spin_lock_irqsave(hba->host->host_lock, flags);
5754 ufshcd_transfer_req_compl(hba);
5755 ufshcd_tmc_handler(hba);
5756 spin_unlock_irqrestore(hba->host->host_lock, flags);
5757
5758 return err;
5759 }
5760
5761 /**
5762 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
5763 * @cmd - SCSI command pointer
5764 *
5765 * Returns SUCCESS/FAILED
5766 */
5767 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
5768 {
5769 int err;
5770 unsigned long flags;
5771 struct ufs_hba *hba;
5772
5773 hba = shost_priv(cmd->device->host);
5774
5775 ufshcd_hold(hba, false);
5776 /*
5777 * Check if there is any race with fatal error handling.
5778 * If so, wait for it to complete. Even though fatal error
5779 * handling does reset and restore in some cases, don't assume
5780 * anything out of it. We are just avoiding race here.
5781 */
5782 do {
5783 spin_lock_irqsave(hba->host->host_lock, flags);
5784 if (!(work_pending(&hba->eh_work) ||
5785 hba->ufshcd_state == UFSHCD_STATE_RESET))
5786 break;
5787 spin_unlock_irqrestore(hba->host->host_lock, flags);
5788 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
5789 flush_work(&hba->eh_work);
5790 } while (1);
5791
5792 hba->ufshcd_state = UFSHCD_STATE_RESET;
5793 ufshcd_set_eh_in_progress(hba);
5794 spin_unlock_irqrestore(hba->host->host_lock, flags);
5795
5796 err = ufshcd_reset_and_restore(hba);
5797
5798 spin_lock_irqsave(hba->host->host_lock, flags);
5799 if (!err) {
5800 err = SUCCESS;
5801 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5802 } else {
5803 err = FAILED;
5804 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5805 }
5806 ufshcd_clear_eh_in_progress(hba);
5807 spin_unlock_irqrestore(hba->host->host_lock, flags);
5808
5809 ufshcd_release(hba);
5810 return err;
5811 }
5812
5813 /**
5814 * ufshcd_get_max_icc_level - calculate the ICC level
5815 * @sup_curr_uA: max. current supported by the regulator
5816 * @start_scan: row at the desc table to start scan from
5817 * @buff: power descriptor buffer
5818 *
5819 * Returns calculated max ICC level for specific regulator
5820 */
5821 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
5822 {
5823 int i;
5824 int curr_uA;
5825 u16 data;
5826 u16 unit;
5827
5828 for (i = start_scan; i >= 0; i--) {
5829 data = be16_to_cpup((__be16 *)&buff[2 * i]);
5830 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
5831 ATTR_ICC_LVL_UNIT_OFFSET;
5832 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
5833 switch (unit) {
5834 case UFSHCD_NANO_AMP:
5835 curr_uA = curr_uA / 1000;
5836 break;
5837 case UFSHCD_MILI_AMP:
5838 curr_uA = curr_uA * 1000;
5839 break;
5840 case UFSHCD_AMP:
5841 curr_uA = curr_uA * 1000 * 1000;
5842 break;
5843 case UFSHCD_MICRO_AMP:
5844 default:
5845 break;
5846 }
5847 if (sup_curr_uA >= curr_uA)
5848 break;
5849 }
5850 if (i < 0) {
5851 i = 0;
5852 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
5853 }
5854
5855 return (u32)i;
5856 }
5857
5858 /**
5859 * ufshcd_calc_icc_level - calculate the max ICC level
5860 * In case regulators are not initialized we'll return 0
5861 * @hba: per-adapter instance
5862 * @desc_buf: power descriptor buffer to extract ICC levels from.
5863 * @len: length of desc_buff
5864 *
5865 * Returns calculated ICC level
5866 */
5867 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
5868 u8 *desc_buf, int len)
5869 {
5870 u32 icc_level = 0;
5871
5872 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
5873 !hba->vreg_info.vccq2) {
5874 dev_err(hba->dev,
5875 "%s: Regulator capability was not set, actvIccLevel=%d",
5876 __func__, icc_level);
5877 goto out;
5878 }
5879
5880 if (hba->vreg_info.vcc)
5881 icc_level = ufshcd_get_max_icc_level(
5882 hba->vreg_info.vcc->max_uA,
5883 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
5884 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
5885
5886 if (hba->vreg_info.vccq)
5887 icc_level = ufshcd_get_max_icc_level(
5888 hba->vreg_info.vccq->max_uA,
5889 icc_level,
5890 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
5891
5892 if (hba->vreg_info.vccq2)
5893 icc_level = ufshcd_get_max_icc_level(
5894 hba->vreg_info.vccq2->max_uA,
5895 icc_level,
5896 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
5897 out:
5898 return icc_level;
5899 }
5900
5901 static int ufshcd_set_icc_levels_attr(struct ufs_hba *hba, u32 icc_level)
5902 {
5903 int ret = 0;
5904 int retries;
5905
5906 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5907 /* write attribute */
5908 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5909 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
5910 if (!ret)
5911 break;
5912
5913 dev_dbg(hba->dev, "%s: failed with error %d\n", __func__, ret);
5914 }
5915
5916 return ret;
5917 }
5918
5919 static void ufshcd_init_icc_levels(struct ufs_hba *hba)
5920 {
5921 int ret;
5922 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
5923 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
5924
5925 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
5926 if (ret) {
5927 dev_err(hba->dev,
5928 "%s: Failed reading power descriptor.len = %d ret = %d",
5929 __func__, buff_len, ret);
5930 return;
5931 }
5932
5933 hba->init_prefetch_data.icc_level =
5934 ufshcd_find_max_sup_active_icc_level(hba,
5935 desc_buf, buff_len);
5936 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
5937 __func__, hba->init_prefetch_data.icc_level);
5938
5939 ret = ufshcd_set_icc_levels_attr(hba,
5940 hba->init_prefetch_data.icc_level);
5941
5942 if (ret)
5943 dev_err(hba->dev,
5944 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
5945 __func__, hba->init_prefetch_data.icc_level , ret);
5946
5947 }
5948
5949 /**
5950 * ufshcd_scsi_add_wlus - Adds required W-LUs
5951 * @hba: per-adapter instance
5952 *
5953 * UFS device specification requires the UFS devices to support 4 well known
5954 * logical units:
5955 * "REPORT_LUNS" (address: 01h)
5956 * "UFS Device" (address: 50h)
5957 * "RPMB" (address: 44h)
5958 * "BOOT" (address: 30h)
5959 * UFS device's power management needs to be controlled by "POWER CONDITION"
5960 * field of SSU (START STOP UNIT) command. But this "power condition" field
5961 * will take effect only when its sent to "UFS device" well known logical unit
5962 * hence we require the scsi_device instance to represent this logical unit in
5963 * order for the UFS host driver to send the SSU command for power management.
5964
5965 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
5966 * Block) LU so user space process can control this LU. User space may also
5967 * want to have access to BOOT LU.
5968
5969 * This function adds scsi device instances for each of all well known LUs
5970 * (except "REPORT LUNS" LU).
5971 *
5972 * Returns zero on success (all required W-LUs are added successfully),
5973 * non-zero error value on failure (if failed to add any of the required W-LU).
5974 */
5975 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
5976 {
5977 int ret = 0;
5978 struct scsi_device *sdev_rpmb;
5979 struct scsi_device *sdev_boot;
5980
5981 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
5982 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
5983 if (IS_ERR(hba->sdev_ufs_device)) {
5984 ret = PTR_ERR(hba->sdev_ufs_device);
5985 hba->sdev_ufs_device = NULL;
5986 goto out;
5987 }
5988 scsi_device_put(hba->sdev_ufs_device);
5989
5990 sdev_boot = __scsi_add_device(hba->host, 0, 0,
5991 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
5992 if (IS_ERR(sdev_boot)) {
5993 ret = PTR_ERR(sdev_boot);
5994 goto remove_sdev_ufs_device;
5995 }
5996 scsi_device_put(sdev_boot);
5997
5998 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
5999 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
6000 if (IS_ERR(sdev_rpmb)) {
6001 ret = PTR_ERR(sdev_rpmb);
6002 goto remove_sdev_boot;
6003 }
6004 scsi_device_put(sdev_rpmb);
6005 goto out;
6006
6007 remove_sdev_boot:
6008 scsi_remove_device(sdev_boot);
6009 remove_sdev_ufs_device:
6010 scsi_remove_device(hba->sdev_ufs_device);
6011 out:
6012 return ret;
6013 }
6014
6015 static int ufs_get_device_desc(struct ufs_hba *hba,
6016 struct ufs_dev_desc *dev_desc)
6017 {
6018 int err;
6019 u8 model_index;
6020 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
6021 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
6022
6023 err = ufshcd_read_device_desc(hba, desc_buf,
6024 QUERY_DESC_DEVICE_MAX_SIZE);
6025 if (err) {
6026 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6027 __func__, err);
6028 goto out;
6029 }
6030
6031 /*
6032 * getting vendor (manufacturerID) and Bank Index in big endian
6033 * format
6034 */
6035 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
6036 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6037
6038 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6039
6040 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
6041 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
6042 if (err) {
6043 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6044 __func__, err);
6045 goto out;
6046 }
6047
6048 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
6049 strlcpy(dev_desc->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
6050 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
6051 MAX_MODEL_LEN));
6052
6053 /* Null terminate the model string */
6054 dev_desc->model[MAX_MODEL_LEN] = '\0';
6055
6056 out:
6057 return err;
6058 }
6059
6060 static void ufs_fixup_device_setup(struct ufs_hba *hba,
6061 struct ufs_dev_desc *dev_desc)
6062 {
6063 struct ufs_dev_fix *f;
6064
6065 for (f = ufs_fixups; f->quirk; f++) {
6066 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6067 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6068 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
6069 !strcmp(f->card.model, UFS_ANY_MODEL)))
6070 hba->dev_quirks |= f->quirk;
6071 }
6072 }
6073
6074 /**
6075 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6076 * @hba: per-adapter instance
6077 *
6078 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6079 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6080 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6081 * the hibern8 exit latency.
6082 *
6083 * Returns zero on success, non-zero error value on failure.
6084 */
6085 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6086 {
6087 int ret = 0;
6088 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6089
6090 ret = ufshcd_dme_peer_get(hba,
6091 UIC_ARG_MIB_SEL(
6092 RX_MIN_ACTIVATETIME_CAPABILITY,
6093 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6094 &peer_rx_min_activatetime);
6095 if (ret)
6096 goto out;
6097
6098 /* make sure proper unit conversion is applied */
6099 tuned_pa_tactivate =
6100 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6101 / PA_TACTIVATE_TIME_UNIT_US);
6102 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6103 tuned_pa_tactivate);
6104
6105 out:
6106 return ret;
6107 }
6108
6109 /**
6110 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6111 * @hba: per-adapter instance
6112 *
6113 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6114 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6115 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6116 * This optimal value can help reduce the hibern8 exit latency.
6117 *
6118 * Returns zero on success, non-zero error value on failure.
6119 */
6120 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6121 {
6122 int ret = 0;
6123 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6124 u32 max_hibern8_time, tuned_pa_hibern8time;
6125
6126 ret = ufshcd_dme_get(hba,
6127 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6128 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6129 &local_tx_hibern8_time_cap);
6130 if (ret)
6131 goto out;
6132
6133 ret = ufshcd_dme_peer_get(hba,
6134 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6135 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6136 &peer_rx_hibern8_time_cap);
6137 if (ret)
6138 goto out;
6139
6140 max_hibern8_time = max(local_tx_hibern8_time_cap,
6141 peer_rx_hibern8_time_cap);
6142 /* make sure proper unit conversion is applied */
6143 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6144 / PA_HIBERN8_TIME_UNIT_US);
6145 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6146 tuned_pa_hibern8time);
6147 out:
6148 return ret;
6149 }
6150
6151 /**
6152 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6153 * less than device PA_TACTIVATE time.
6154 * @hba: per-adapter instance
6155 *
6156 * Some UFS devices require host PA_TACTIVATE to be lower than device
6157 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6158 * for such devices.
6159 *
6160 * Returns zero on success, non-zero error value on failure.
6161 */
6162 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6163 {
6164 int ret = 0;
6165 u32 granularity, peer_granularity;
6166 u32 pa_tactivate, peer_pa_tactivate;
6167 u32 pa_tactivate_us, peer_pa_tactivate_us;
6168 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6169
6170 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6171 &granularity);
6172 if (ret)
6173 goto out;
6174
6175 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6176 &peer_granularity);
6177 if (ret)
6178 goto out;
6179
6180 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6181 (granularity > PA_GRANULARITY_MAX_VAL)) {
6182 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6183 __func__, granularity);
6184 return -EINVAL;
6185 }
6186
6187 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6188 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6189 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6190 __func__, peer_granularity);
6191 return -EINVAL;
6192 }
6193
6194 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6195 if (ret)
6196 goto out;
6197
6198 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6199 &peer_pa_tactivate);
6200 if (ret)
6201 goto out;
6202
6203 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6204 peer_pa_tactivate_us = peer_pa_tactivate *
6205 gran_to_us_table[peer_granularity - 1];
6206
6207 if (pa_tactivate_us > peer_pa_tactivate_us) {
6208 u32 new_peer_pa_tactivate;
6209
6210 new_peer_pa_tactivate = pa_tactivate_us /
6211 gran_to_us_table[peer_granularity - 1];
6212 new_peer_pa_tactivate++;
6213 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6214 new_peer_pa_tactivate);
6215 }
6216
6217 out:
6218 return ret;
6219 }
6220
6221 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6222 {
6223 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6224 ufshcd_tune_pa_tactivate(hba);
6225 ufshcd_tune_pa_hibern8time(hba);
6226 }
6227
6228 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6229 /* set 1ms timeout for PA_TACTIVATE */
6230 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
6231
6232 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6233 ufshcd_quirk_tune_host_pa_tactivate(hba);
6234
6235 ufshcd_vops_apply_dev_quirks(hba);
6236 }
6237
6238 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6239 {
6240 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6241
6242 hba->ufs_stats.hibern8_exit_cnt = 0;
6243 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6244
6245 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6246 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6247 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6248 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6249 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
6250
6251 hba->req_abort_count = 0;
6252 }
6253
6254 /**
6255 * ufshcd_probe_hba - probe hba to detect device and initialize
6256 * @hba: per-adapter instance
6257 *
6258 * Execute link-startup and verify device initialization
6259 */
6260 static int ufshcd_probe_hba(struct ufs_hba *hba)
6261 {
6262 struct ufs_dev_desc card = {0};
6263 int ret;
6264 ktime_t start = ktime_get();
6265
6266 ret = ufshcd_link_startup(hba);
6267 if (ret)
6268 goto out;
6269
6270 /* set the default level for urgent bkops */
6271 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6272 hba->is_urgent_bkops_lvl_checked = false;
6273
6274 /* Debug counters initialization */
6275 ufshcd_clear_dbg_ufs_stats(hba);
6276
6277 /* UniPro link is active now */
6278 ufshcd_set_link_active(hba);
6279
6280 ret = ufshcd_verify_dev_init(hba);
6281 if (ret)
6282 goto out;
6283
6284 ret = ufshcd_complete_dev_init(hba);
6285 if (ret)
6286 goto out;
6287
6288 ret = ufs_get_device_desc(hba, &card);
6289 if (ret) {
6290 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6291 __func__, ret);
6292 goto out;
6293 }
6294
6295 ufs_fixup_device_setup(hba, &card);
6296 ufshcd_tune_unipro_params(hba);
6297
6298 ret = ufshcd_set_vccq_rail_unused(hba,
6299 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6300 if (ret)
6301 goto out;
6302
6303 /* UFS device is also active now */
6304 ufshcd_set_ufs_dev_active(hba);
6305 ufshcd_force_reset_auto_bkops(hba);
6306 hba->wlun_dev_clr_ua = true;
6307
6308 if (ufshcd_get_max_pwr_mode(hba)) {
6309 dev_err(hba->dev,
6310 "%s: Failed getting max supported power mode\n",
6311 __func__);
6312 } else {
6313 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
6314 if (ret) {
6315 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6316 __func__, ret);
6317 goto out;
6318 }
6319 }
6320
6321 /* set the state as operational after switching to desired gear */
6322 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6323 /*
6324 * If we are in error handling context or in power management callbacks
6325 * context, no need to scan the host
6326 */
6327 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6328 bool flag;
6329
6330 /* clear any previous UFS device information */
6331 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
6332 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6333 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
6334 hba->dev_info.f_power_on_wp_en = flag;
6335
6336 if (!hba->is_init_prefetch)
6337 ufshcd_init_icc_levels(hba);
6338
6339 /* Add required well known logical units to scsi mid layer */
6340 if (ufshcd_scsi_add_wlus(hba))
6341 goto out;
6342
6343 /* Initialize devfreq after UFS device is detected */
6344 if (ufshcd_is_clkscaling_supported(hba)) {
6345 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6346 &hba->pwr_info,
6347 sizeof(struct ufs_pa_layer_attr));
6348 hba->clk_scaling.saved_pwr_info.is_valid = true;
6349 if (!hba->devfreq) {
6350 hba->devfreq = devm_devfreq_add_device(hba->dev,
6351 &ufs_devfreq_profile,
6352 "simple_ondemand",
6353 NULL);
6354 if (IS_ERR(hba->devfreq)) {
6355 ret = PTR_ERR(hba->devfreq);
6356 dev_err(hba->dev, "Unable to register with devfreq %d\n",
6357 ret);
6358 goto out;
6359 }
6360 }
6361 hba->clk_scaling.is_allowed = true;
6362 }
6363
6364 scsi_scan_host(hba->host);
6365 pm_runtime_put_sync(hba->dev);
6366 }
6367
6368 if (!hba->is_init_prefetch)
6369 hba->is_init_prefetch = true;
6370
6371 out:
6372 /*
6373 * If we failed to initialize the device or the device is not
6374 * present, turn off the power/clocks etc.
6375 */
6376 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6377 pm_runtime_put_sync(hba->dev);
6378 ufshcd_hba_exit(hba);
6379 }
6380
6381 trace_ufshcd_init(dev_name(hba->dev), ret,
6382 ktime_to_us(ktime_sub(ktime_get(), start)),
6383 hba->curr_dev_pwr_mode, hba->uic_link_state);
6384 return ret;
6385 }
6386
6387 /**
6388 * ufshcd_async_scan - asynchronous execution for probing hba
6389 * @data: data pointer to pass to this function
6390 * @cookie: cookie data
6391 */
6392 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6393 {
6394 struct ufs_hba *hba = (struct ufs_hba *)data;
6395
6396 ufshcd_probe_hba(hba);
6397 }
6398
6399 static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6400 {
6401 unsigned long flags;
6402 struct Scsi_Host *host;
6403 struct ufs_hba *hba;
6404 int index;
6405 bool found = false;
6406
6407 if (!scmd || !scmd->device || !scmd->device->host)
6408 return BLK_EH_NOT_HANDLED;
6409
6410 host = scmd->device->host;
6411 hba = shost_priv(host);
6412 if (!hba)
6413 return BLK_EH_NOT_HANDLED;
6414
6415 spin_lock_irqsave(host->host_lock, flags);
6416
6417 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6418 if (hba->lrb[index].cmd == scmd) {
6419 found = true;
6420 break;
6421 }
6422 }
6423
6424 spin_unlock_irqrestore(host->host_lock, flags);
6425
6426 /*
6427 * Bypass SCSI error handling and reset the block layer timer if this
6428 * SCSI command was not actually dispatched to UFS driver, otherwise
6429 * let SCSI layer handle the error as usual.
6430 */
6431 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
6432 }
6433
6434 static struct scsi_host_template ufshcd_driver_template = {
6435 .module = THIS_MODULE,
6436 .name = UFSHCD,
6437 .proc_name = UFSHCD,
6438 .queuecommand = ufshcd_queuecommand,
6439 .slave_alloc = ufshcd_slave_alloc,
6440 .slave_configure = ufshcd_slave_configure,
6441 .slave_destroy = ufshcd_slave_destroy,
6442 .change_queue_depth = ufshcd_change_queue_depth,
6443 .eh_abort_handler = ufshcd_abort,
6444 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6445 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
6446 .eh_timed_out = ufshcd_eh_timed_out,
6447 .this_id = -1,
6448 .sg_tablesize = SG_ALL,
6449 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6450 .can_queue = UFSHCD_CAN_QUEUE,
6451 .max_host_blocked = 1,
6452 .track_queue_depth = 1,
6453 };
6454
6455 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6456 int ua)
6457 {
6458 int ret;
6459
6460 if (!vreg)
6461 return 0;
6462
6463 ret = regulator_set_load(vreg->reg, ua);
6464 if (ret < 0) {
6465 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6466 __func__, vreg->name, ua, ret);
6467 }
6468
6469 return ret;
6470 }
6471
6472 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6473 struct ufs_vreg *vreg)
6474 {
6475 if (!vreg)
6476 return 0;
6477 else if (vreg->unused)
6478 return 0;
6479 else
6480 return ufshcd_config_vreg_load(hba->dev, vreg,
6481 UFS_VREG_LPM_LOAD_UA);
6482 }
6483
6484 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6485 struct ufs_vreg *vreg)
6486 {
6487 if (!vreg)
6488 return 0;
6489 else if (vreg->unused)
6490 return 0;
6491 else
6492 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
6493 }
6494
6495 static int ufshcd_config_vreg(struct device *dev,
6496 struct ufs_vreg *vreg, bool on)
6497 {
6498 int ret = 0;
6499 struct regulator *reg = vreg->reg;
6500 const char *name = vreg->name;
6501 int min_uV, uA_load;
6502
6503 BUG_ON(!vreg);
6504
6505 if (regulator_count_voltages(reg) > 0) {
6506 min_uV = on ? vreg->min_uV : 0;
6507 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6508 if (ret) {
6509 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6510 __func__, name, ret);
6511 goto out;
6512 }
6513
6514 uA_load = on ? vreg->max_uA : 0;
6515 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6516 if (ret)
6517 goto out;
6518 }
6519 out:
6520 return ret;
6521 }
6522
6523 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6524 {
6525 int ret = 0;
6526
6527 if (!vreg)
6528 goto out;
6529 else if (vreg->enabled || vreg->unused)
6530 goto out;
6531
6532 ret = ufshcd_config_vreg(dev, vreg, true);
6533 if (!ret)
6534 ret = regulator_enable(vreg->reg);
6535
6536 if (!ret)
6537 vreg->enabled = true;
6538 else
6539 dev_err(dev, "%s: %s enable failed, err=%d\n",
6540 __func__, vreg->name, ret);
6541 out:
6542 return ret;
6543 }
6544
6545 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
6546 {
6547 int ret = 0;
6548
6549 if (!vreg)
6550 goto out;
6551 else if (!vreg->enabled || vreg->unused)
6552 goto out;
6553
6554 ret = regulator_disable(vreg->reg);
6555
6556 if (!ret) {
6557 /* ignore errors on applying disable config */
6558 ufshcd_config_vreg(dev, vreg, false);
6559 vreg->enabled = false;
6560 } else {
6561 dev_err(dev, "%s: %s disable failed, err=%d\n",
6562 __func__, vreg->name, ret);
6563 }
6564 out:
6565 return ret;
6566 }
6567
6568 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
6569 {
6570 int ret = 0;
6571 struct device *dev = hba->dev;
6572 struct ufs_vreg_info *info = &hba->vreg_info;
6573
6574 if (!info)
6575 goto out;
6576
6577 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
6578 if (ret)
6579 goto out;
6580
6581 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
6582 if (ret)
6583 goto out;
6584
6585 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
6586 if (ret)
6587 goto out;
6588
6589 out:
6590 if (ret) {
6591 ufshcd_toggle_vreg(dev, info->vccq2, false);
6592 ufshcd_toggle_vreg(dev, info->vccq, false);
6593 ufshcd_toggle_vreg(dev, info->vcc, false);
6594 }
6595 return ret;
6596 }
6597
6598 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
6599 {
6600 struct ufs_vreg_info *info = &hba->vreg_info;
6601
6602 if (info)
6603 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6604
6605 return 0;
6606 }
6607
6608 static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
6609 {
6610 int ret = 0;
6611
6612 if (!vreg)
6613 goto out;
6614
6615 vreg->reg = devm_regulator_get(dev, vreg->name);
6616 if (IS_ERR(vreg->reg)) {
6617 ret = PTR_ERR(vreg->reg);
6618 dev_err(dev, "%s: %s get failed, err=%d\n",
6619 __func__, vreg->name, ret);
6620 }
6621 out:
6622 return ret;
6623 }
6624
6625 static int ufshcd_init_vreg(struct ufs_hba *hba)
6626 {
6627 int ret = 0;
6628 struct device *dev = hba->dev;
6629 struct ufs_vreg_info *info = &hba->vreg_info;
6630
6631 if (!info)
6632 goto out;
6633
6634 ret = ufshcd_get_vreg(dev, info->vcc);
6635 if (ret)
6636 goto out;
6637
6638 ret = ufshcd_get_vreg(dev, info->vccq);
6639 if (ret)
6640 goto out;
6641
6642 ret = ufshcd_get_vreg(dev, info->vccq2);
6643 out:
6644 return ret;
6645 }
6646
6647 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
6648 {
6649 struct ufs_vreg_info *info = &hba->vreg_info;
6650
6651 if (info)
6652 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
6653
6654 return 0;
6655 }
6656
6657 static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
6658 {
6659 int ret = 0;
6660 struct ufs_vreg_info *info = &hba->vreg_info;
6661
6662 if (!info)
6663 goto out;
6664 else if (!info->vccq)
6665 goto out;
6666
6667 if (unused) {
6668 /* shut off the rail here */
6669 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
6670 /*
6671 * Mark this rail as no longer used, so it doesn't get enabled
6672 * later by mistake
6673 */
6674 if (!ret)
6675 info->vccq->unused = true;
6676 } else {
6677 /*
6678 * rail should have been already enabled hence just make sure
6679 * that unused flag is cleared.
6680 */
6681 info->vccq->unused = false;
6682 }
6683 out:
6684 return ret;
6685 }
6686
6687 static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
6688 bool skip_ref_clk)
6689 {
6690 int ret = 0;
6691 struct ufs_clk_info *clki;
6692 struct list_head *head = &hba->clk_list_head;
6693 unsigned long flags;
6694 ktime_t start = ktime_get();
6695 bool clk_state_changed = false;
6696
6697 if (!head || list_empty(head))
6698 goto out;
6699
6700 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
6701 if (ret)
6702 return ret;
6703
6704 list_for_each_entry(clki, head, list) {
6705 if (!IS_ERR_OR_NULL(clki->clk)) {
6706 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
6707 continue;
6708
6709 clk_state_changed = on ^ clki->enabled;
6710 if (on && !clki->enabled) {
6711 ret = clk_prepare_enable(clki->clk);
6712 if (ret) {
6713 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
6714 __func__, clki->name, ret);
6715 goto out;
6716 }
6717 } else if (!on && clki->enabled) {
6718 clk_disable_unprepare(clki->clk);
6719 }
6720 clki->enabled = on;
6721 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
6722 clki->name, on ? "en" : "dis");
6723 }
6724 }
6725
6726 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
6727 if (ret)
6728 return ret;
6729
6730 out:
6731 if (ret) {
6732 list_for_each_entry(clki, head, list) {
6733 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
6734 clk_disable_unprepare(clki->clk);
6735 }
6736 } else if (!ret && on) {
6737 spin_lock_irqsave(hba->host->host_lock, flags);
6738 hba->clk_gating.state = CLKS_ON;
6739 trace_ufshcd_clk_gating(dev_name(hba->dev),
6740 hba->clk_gating.state);
6741 spin_unlock_irqrestore(hba->host->host_lock, flags);
6742 }
6743
6744 if (clk_state_changed)
6745 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
6746 (on ? "on" : "off"),
6747 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
6748 return ret;
6749 }
6750
6751 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
6752 {
6753 return __ufshcd_setup_clocks(hba, on, false);
6754 }
6755
6756 static int ufshcd_init_clocks(struct ufs_hba *hba)
6757 {
6758 int ret = 0;
6759 struct ufs_clk_info *clki;
6760 struct device *dev = hba->dev;
6761 struct list_head *head = &hba->clk_list_head;
6762
6763 if (!head || list_empty(head))
6764 goto out;
6765
6766 list_for_each_entry(clki, head, list) {
6767 if (!clki->name)
6768 continue;
6769
6770 clki->clk = devm_clk_get(dev, clki->name);
6771 if (IS_ERR(clki->clk)) {
6772 ret = PTR_ERR(clki->clk);
6773 dev_err(dev, "%s: %s clk get failed, %d\n",
6774 __func__, clki->name, ret);
6775 goto out;
6776 }
6777
6778 if (clki->max_freq) {
6779 ret = clk_set_rate(clki->clk, clki->max_freq);
6780 if (ret) {
6781 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6782 __func__, clki->name,
6783 clki->max_freq, ret);
6784 goto out;
6785 }
6786 clki->curr_freq = clki->max_freq;
6787 }
6788 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
6789 clki->name, clk_get_rate(clki->clk));
6790 }
6791 out:
6792 return ret;
6793 }
6794
6795 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
6796 {
6797 int err = 0;
6798
6799 if (!hba->vops)
6800 goto out;
6801
6802 err = ufshcd_vops_init(hba);
6803 if (err)
6804 goto out;
6805
6806 err = ufshcd_vops_setup_regulators(hba, true);
6807 if (err)
6808 goto out_exit;
6809
6810 goto out;
6811
6812 out_exit:
6813 ufshcd_vops_exit(hba);
6814 out:
6815 if (err)
6816 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
6817 __func__, ufshcd_get_var_name(hba), err);
6818 return err;
6819 }
6820
6821 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
6822 {
6823 if (!hba->vops)
6824 return;
6825
6826 ufshcd_vops_setup_regulators(hba, false);
6827
6828 ufshcd_vops_exit(hba);
6829 }
6830
6831 static int ufshcd_hba_init(struct ufs_hba *hba)
6832 {
6833 int err;
6834
6835 /*
6836 * Handle host controller power separately from the UFS device power
6837 * rails as it will help controlling the UFS host controller power
6838 * collapse easily which is different than UFS device power collapse.
6839 * Also, enable the host controller power before we go ahead with rest
6840 * of the initialization here.
6841 */
6842 err = ufshcd_init_hba_vreg(hba);
6843 if (err)
6844 goto out;
6845
6846 err = ufshcd_setup_hba_vreg(hba, true);
6847 if (err)
6848 goto out;
6849
6850 err = ufshcd_init_clocks(hba);
6851 if (err)
6852 goto out_disable_hba_vreg;
6853
6854 err = ufshcd_setup_clocks(hba, true);
6855 if (err)
6856 goto out_disable_hba_vreg;
6857
6858 err = ufshcd_init_vreg(hba);
6859 if (err)
6860 goto out_disable_clks;
6861
6862 err = ufshcd_setup_vreg(hba, true);
6863 if (err)
6864 goto out_disable_clks;
6865
6866 err = ufshcd_variant_hba_init(hba);
6867 if (err)
6868 goto out_disable_vreg;
6869
6870 hba->is_powered = true;
6871 goto out;
6872
6873 out_disable_vreg:
6874 ufshcd_setup_vreg(hba, false);
6875 out_disable_clks:
6876 ufshcd_setup_clocks(hba, false);
6877 out_disable_hba_vreg:
6878 ufshcd_setup_hba_vreg(hba, false);
6879 out:
6880 return err;
6881 }
6882
6883 static void ufshcd_hba_exit(struct ufs_hba *hba)
6884 {
6885 if (hba->is_powered) {
6886 ufshcd_variant_hba_exit(hba);
6887 ufshcd_setup_vreg(hba, false);
6888 ufshcd_suspend_clkscaling(hba);
6889 if (ufshcd_is_clkscaling_supported(hba)) {
6890 if (hba->devfreq)
6891 ufshcd_suspend_clkscaling(hba);
6892 destroy_workqueue(hba->clk_scaling.workq);
6893 }
6894 ufshcd_setup_clocks(hba, false);
6895 ufshcd_setup_hba_vreg(hba, false);
6896 hba->is_powered = false;
6897 }
6898 }
6899
6900 static int
6901 ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
6902 {
6903 unsigned char cmd[6] = {REQUEST_SENSE,
6904 0,
6905 0,
6906 0,
6907 UFSHCD_REQ_SENSE_SIZE,
6908 0};
6909 char *buffer;
6910 int ret;
6911
6912 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
6913 if (!buffer) {
6914 ret = -ENOMEM;
6915 goto out;
6916 }
6917
6918 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
6919 UFSHCD_REQ_SENSE_SIZE, NULL,
6920 msecs_to_jiffies(1000), 3, NULL, 0, RQF_PM);
6921 if (ret)
6922 pr_err("%s: failed with err %d\n", __func__, ret);
6923
6924 kfree(buffer);
6925 out:
6926 return ret;
6927 }
6928
6929 /**
6930 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
6931 * power mode
6932 * @hba: per adapter instance
6933 * @pwr_mode: device power mode to set
6934 *
6935 * Returns 0 if requested power mode is set successfully
6936 * Returns non-zero if failed to set the requested power mode
6937 */
6938 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
6939 enum ufs_dev_pwr_mode pwr_mode)
6940 {
6941 unsigned char cmd[6] = { START_STOP };
6942 struct scsi_sense_hdr sshdr;
6943 struct scsi_device *sdp;
6944 unsigned long flags;
6945 int ret;
6946
6947 spin_lock_irqsave(hba->host->host_lock, flags);
6948 sdp = hba->sdev_ufs_device;
6949 if (sdp) {
6950 ret = scsi_device_get(sdp);
6951 if (!ret && !scsi_device_online(sdp)) {
6952 ret = -ENODEV;
6953 scsi_device_put(sdp);
6954 }
6955 } else {
6956 ret = -ENODEV;
6957 }
6958 spin_unlock_irqrestore(hba->host->host_lock, flags);
6959
6960 if (ret)
6961 return ret;
6962
6963 /*
6964 * If scsi commands fail, the scsi mid-layer schedules scsi error-
6965 * handling, which would wait for host to be resumed. Since we know
6966 * we are functional while we are here, skip host resume in error
6967 * handling context.
6968 */
6969 hba->host->eh_noresume = 1;
6970 if (hba->wlun_dev_clr_ua) {
6971 ret = ufshcd_send_request_sense(hba, sdp);
6972 if (ret)
6973 goto out;
6974 /* Unit attention condition is cleared now */
6975 hba->wlun_dev_clr_ua = false;
6976 }
6977
6978 cmd[4] = pwr_mode << 4;
6979
6980 /*
6981 * Current function would be generally called from the power management
6982 * callbacks hence set the RQF_PM flag so that it doesn't resume the
6983 * already suspended childs.
6984 */
6985 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
6986 START_STOP_TIMEOUT, 0, NULL, 0, RQF_PM);
6987 if (ret) {
6988 sdev_printk(KERN_WARNING, sdp,
6989 "START_STOP failed for power mode: %d, result %x\n",
6990 pwr_mode, ret);
6991 if (driver_byte(ret) & DRIVER_SENSE)
6992 scsi_print_sense_hdr(sdp, NULL, &sshdr);
6993 }
6994
6995 if (!ret)
6996 hba->curr_dev_pwr_mode = pwr_mode;
6997 out:
6998 scsi_device_put(sdp);
6999 hba->host->eh_noresume = 0;
7000 return ret;
7001 }
7002
7003 static int ufshcd_link_state_transition(struct ufs_hba *hba,
7004 enum uic_link_state req_link_state,
7005 int check_for_bkops)
7006 {
7007 int ret = 0;
7008
7009 if (req_link_state == hba->uic_link_state)
7010 return 0;
7011
7012 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7013 ret = ufshcd_uic_hibern8_enter(hba);
7014 if (!ret)
7015 ufshcd_set_link_hibern8(hba);
7016 else
7017 goto out;
7018 }
7019 /*
7020 * If autobkops is enabled, link can't be turned off because
7021 * turning off the link would also turn off the device.
7022 */
7023 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7024 (!check_for_bkops || (check_for_bkops &&
7025 !hba->auto_bkops_enabled))) {
7026 /*
7027 * Let's make sure that link is in low power mode, we are doing
7028 * this currently by putting the link in Hibern8. Otherway to
7029 * put the link in low power mode is to send the DME end point
7030 * to device and then send the DME reset command to local
7031 * unipro. But putting the link in hibern8 is much faster.
7032 */
7033 ret = ufshcd_uic_hibern8_enter(hba);
7034 if (ret)
7035 goto out;
7036 /*
7037 * Change controller state to "reset state" which
7038 * should also put the link in off/reset state
7039 */
7040 ufshcd_hba_stop(hba, true);
7041 /*
7042 * TODO: Check if we need any delay to make sure that
7043 * controller is reset
7044 */
7045 ufshcd_set_link_off(hba);
7046 }
7047
7048 out:
7049 return ret;
7050 }
7051
7052 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7053 {
7054 /*
7055 * It seems some UFS devices may keep drawing more than sleep current
7056 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7057 * To avoid this situation, add 2ms delay before putting these UFS
7058 * rails in LPM mode.
7059 */
7060 if (!ufshcd_is_link_active(hba) &&
7061 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7062 usleep_range(2000, 2100);
7063
7064 /*
7065 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7066 * power.
7067 *
7068 * If UFS device and link is in OFF state, all power supplies (VCC,
7069 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7070 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7071 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7072 *
7073 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7074 * in low power state which would save some power.
7075 */
7076 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7077 !hba->dev_info.is_lu_power_on_wp) {
7078 ufshcd_setup_vreg(hba, false);
7079 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7080 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7081 if (!ufshcd_is_link_active(hba)) {
7082 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7083 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7084 }
7085 }
7086 }
7087
7088 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7089 {
7090 int ret = 0;
7091
7092 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7093 !hba->dev_info.is_lu_power_on_wp) {
7094 ret = ufshcd_setup_vreg(hba, true);
7095 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7096 if (!ret && !ufshcd_is_link_active(hba)) {
7097 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7098 if (ret)
7099 goto vcc_disable;
7100 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7101 if (ret)
7102 goto vccq_lpm;
7103 }
7104 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
7105 }
7106 goto out;
7107
7108 vccq_lpm:
7109 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7110 vcc_disable:
7111 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7112 out:
7113 return ret;
7114 }
7115
7116 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7117 {
7118 if (ufshcd_is_link_off(hba))
7119 ufshcd_setup_hba_vreg(hba, false);
7120 }
7121
7122 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7123 {
7124 if (ufshcd_is_link_off(hba))
7125 ufshcd_setup_hba_vreg(hba, true);
7126 }
7127
7128 /**
7129 * ufshcd_suspend - helper function for suspend operations
7130 * @hba: per adapter instance
7131 * @pm_op: desired low power operation type
7132 *
7133 * This function will try to put the UFS device and link into low power
7134 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7135 * (System PM level).
7136 *
7137 * If this function is called during shutdown, it will make sure that
7138 * both UFS device and UFS link is powered off.
7139 *
7140 * NOTE: UFS device & link must be active before we enter in this function.
7141 *
7142 * Returns 0 for success and non-zero for failure
7143 */
7144 static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7145 {
7146 int ret = 0;
7147 enum ufs_pm_level pm_lvl;
7148 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7149 enum uic_link_state req_link_state;
7150
7151 hba->pm_op_in_progress = 1;
7152 if (!ufshcd_is_shutdown_pm(pm_op)) {
7153 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7154 hba->rpm_lvl : hba->spm_lvl;
7155 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7156 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7157 } else {
7158 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7159 req_link_state = UIC_LINK_OFF_STATE;
7160 }
7161
7162 /*
7163 * If we can't transition into any of the low power modes
7164 * just gate the clocks.
7165 */
7166 ufshcd_hold(hba, false);
7167 hba->clk_gating.is_suspended = true;
7168
7169 if (hba->clk_scaling.is_allowed) {
7170 cancel_work_sync(&hba->clk_scaling.suspend_work);
7171 cancel_work_sync(&hba->clk_scaling.resume_work);
7172 ufshcd_suspend_clkscaling(hba);
7173 }
7174
7175 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7176 req_link_state == UIC_LINK_ACTIVE_STATE) {
7177 goto disable_clks;
7178 }
7179
7180 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7181 (req_link_state == hba->uic_link_state))
7182 goto enable_gating;
7183
7184 /* UFS device & link must be active before we enter in this function */
7185 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7186 ret = -EINVAL;
7187 goto enable_gating;
7188 }
7189
7190 if (ufshcd_is_runtime_pm(pm_op)) {
7191 if (ufshcd_can_autobkops_during_suspend(hba)) {
7192 /*
7193 * The device is idle with no requests in the queue,
7194 * allow background operations if bkops status shows
7195 * that performance might be impacted.
7196 */
7197 ret = ufshcd_urgent_bkops(hba);
7198 if (ret)
7199 goto enable_gating;
7200 } else {
7201 /* make sure that auto bkops is disabled */
7202 ufshcd_disable_auto_bkops(hba);
7203 }
7204 }
7205
7206 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7207 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7208 !ufshcd_is_runtime_pm(pm_op))) {
7209 /* ensure that bkops is disabled */
7210 ufshcd_disable_auto_bkops(hba);
7211 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7212 if (ret)
7213 goto enable_gating;
7214 }
7215
7216 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7217 if (ret)
7218 goto set_dev_active;
7219
7220 ufshcd_vreg_set_lpm(hba);
7221
7222 disable_clks:
7223 /*
7224 * Call vendor specific suspend callback. As these callbacks may access
7225 * vendor specific host controller register space call them before the
7226 * host clocks are ON.
7227 */
7228 ret = ufshcd_vops_suspend(hba, pm_op);
7229 if (ret)
7230 goto set_link_active;
7231
7232 if (!ufshcd_is_link_active(hba))
7233 ufshcd_setup_clocks(hba, false);
7234 else
7235 /* If link is active, device ref_clk can't be switched off */
7236 __ufshcd_setup_clocks(hba, false, true);
7237
7238 hba->clk_gating.state = CLKS_OFF;
7239 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
7240 /*
7241 * Disable the host irq as host controller as there won't be any
7242 * host controller transaction expected till resume.
7243 */
7244 ufshcd_disable_irq(hba);
7245 /* Put the host controller in low power mode if possible */
7246 ufshcd_hba_vreg_set_lpm(hba);
7247 goto out;
7248
7249 set_link_active:
7250 if (hba->clk_scaling.is_allowed)
7251 ufshcd_resume_clkscaling(hba);
7252 ufshcd_vreg_set_hpm(hba);
7253 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7254 ufshcd_set_link_active(hba);
7255 else if (ufshcd_is_link_off(hba))
7256 ufshcd_host_reset_and_restore(hba);
7257 set_dev_active:
7258 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7259 ufshcd_disable_auto_bkops(hba);
7260 enable_gating:
7261 if (hba->clk_scaling.is_allowed)
7262 ufshcd_resume_clkscaling(hba);
7263 hba->clk_gating.is_suspended = false;
7264 ufshcd_release(hba);
7265 out:
7266 hba->pm_op_in_progress = 0;
7267 return ret;
7268 }
7269
7270 /**
7271 * ufshcd_resume - helper function for resume operations
7272 * @hba: per adapter instance
7273 * @pm_op: runtime PM or system PM
7274 *
7275 * This function basically brings the UFS device, UniPro link and controller
7276 * to active state.
7277 *
7278 * Returns 0 for success and non-zero for failure
7279 */
7280 static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7281 {
7282 int ret;
7283 enum uic_link_state old_link_state;
7284
7285 hba->pm_op_in_progress = 1;
7286 old_link_state = hba->uic_link_state;
7287
7288 ufshcd_hba_vreg_set_hpm(hba);
7289 /* Make sure clocks are enabled before accessing controller */
7290 ret = ufshcd_setup_clocks(hba, true);
7291 if (ret)
7292 goto out;
7293
7294 /* enable the host irq as host controller would be active soon */
7295 ret = ufshcd_enable_irq(hba);
7296 if (ret)
7297 goto disable_irq_and_vops_clks;
7298
7299 ret = ufshcd_vreg_set_hpm(hba);
7300 if (ret)
7301 goto disable_irq_and_vops_clks;
7302
7303 /*
7304 * Call vendor specific resume callback. As these callbacks may access
7305 * vendor specific host controller register space call them when the
7306 * host clocks are ON.
7307 */
7308 ret = ufshcd_vops_resume(hba, pm_op);
7309 if (ret)
7310 goto disable_vreg;
7311
7312 if (ufshcd_is_link_hibern8(hba)) {
7313 ret = ufshcd_uic_hibern8_exit(hba);
7314 if (!ret)
7315 ufshcd_set_link_active(hba);
7316 else
7317 goto vendor_suspend;
7318 } else if (ufshcd_is_link_off(hba)) {
7319 ret = ufshcd_host_reset_and_restore(hba);
7320 /*
7321 * ufshcd_host_reset_and_restore() should have already
7322 * set the link state as active
7323 */
7324 if (ret || !ufshcd_is_link_active(hba))
7325 goto vendor_suspend;
7326 }
7327
7328 if (!ufshcd_is_ufs_dev_active(hba)) {
7329 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7330 if (ret)
7331 goto set_old_link_state;
7332 }
7333
7334 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7335 ufshcd_enable_auto_bkops(hba);
7336 else
7337 /*
7338 * If BKOPs operations are urgently needed at this moment then
7339 * keep auto-bkops enabled or else disable it.
7340 */
7341 ufshcd_urgent_bkops(hba);
7342
7343 hba->clk_gating.is_suspended = false;
7344
7345 if (hba->clk_scaling.is_allowed)
7346 ufshcd_resume_clkscaling(hba);
7347
7348 /* Schedule clock gating in case of no access to UFS device yet */
7349 ufshcd_release(hba);
7350 goto out;
7351
7352 set_old_link_state:
7353 ufshcd_link_state_transition(hba, old_link_state, 0);
7354 vendor_suspend:
7355 ufshcd_vops_suspend(hba, pm_op);
7356 disable_vreg:
7357 ufshcd_vreg_set_lpm(hba);
7358 disable_irq_and_vops_clks:
7359 ufshcd_disable_irq(hba);
7360 if (hba->clk_scaling.is_allowed)
7361 ufshcd_suspend_clkscaling(hba);
7362 ufshcd_setup_clocks(hba, false);
7363 out:
7364 hba->pm_op_in_progress = 0;
7365 return ret;
7366 }
7367
7368 /**
7369 * ufshcd_system_suspend - system suspend routine
7370 * @hba: per adapter instance
7371 * @pm_op: runtime PM or system PM
7372 *
7373 * Check the description of ufshcd_suspend() function for more details.
7374 *
7375 * Returns 0 for success and non-zero for failure
7376 */
7377 int ufshcd_system_suspend(struct ufs_hba *hba)
7378 {
7379 int ret = 0;
7380 ktime_t start = ktime_get();
7381
7382 if (!hba || !hba->is_powered)
7383 return 0;
7384
7385 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7386 hba->curr_dev_pwr_mode) &&
7387 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7388 hba->uic_link_state))
7389 goto out;
7390
7391 if (pm_runtime_suspended(hba->dev)) {
7392 /*
7393 * UFS device and/or UFS link low power states during runtime
7394 * suspend seems to be different than what is expected during
7395 * system suspend. Hence runtime resume the devic & link and
7396 * let the system suspend low power states to take effect.
7397 * TODO: If resume takes longer time, we might have optimize
7398 * it in future by not resuming everything if possible.
7399 */
7400 ret = ufshcd_runtime_resume(hba);
7401 if (ret)
7402 goto out;
7403 }
7404
7405 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7406 out:
7407 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7408 ktime_to_us(ktime_sub(ktime_get(), start)),
7409 hba->curr_dev_pwr_mode, hba->uic_link_state);
7410 if (!ret)
7411 hba->is_sys_suspended = true;
7412 return ret;
7413 }
7414 EXPORT_SYMBOL(ufshcd_system_suspend);
7415
7416 /**
7417 * ufshcd_system_resume - system resume routine
7418 * @hba: per adapter instance
7419 *
7420 * Returns 0 for success and non-zero for failure
7421 */
7422
7423 int ufshcd_system_resume(struct ufs_hba *hba)
7424 {
7425 int ret = 0;
7426 ktime_t start = ktime_get();
7427
7428 if (!hba)
7429 return -EINVAL;
7430
7431 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
7432 /*
7433 * Let the runtime resume take care of resuming
7434 * if runtime suspended.
7435 */
7436 goto out;
7437 else
7438 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7439 out:
7440 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7441 ktime_to_us(ktime_sub(ktime_get(), start)),
7442 hba->curr_dev_pwr_mode, hba->uic_link_state);
7443 return ret;
7444 }
7445 EXPORT_SYMBOL(ufshcd_system_resume);
7446
7447 /**
7448 * ufshcd_runtime_suspend - runtime suspend routine
7449 * @hba: per adapter instance
7450 *
7451 * Check the description of ufshcd_suspend() function for more details.
7452 *
7453 * Returns 0 for success and non-zero for failure
7454 */
7455 int ufshcd_runtime_suspend(struct ufs_hba *hba)
7456 {
7457 int ret = 0;
7458 ktime_t start = ktime_get();
7459
7460 if (!hba)
7461 return -EINVAL;
7462
7463 if (!hba->is_powered)
7464 goto out;
7465 else
7466 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7467 out:
7468 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7469 ktime_to_us(ktime_sub(ktime_get(), start)),
7470 hba->curr_dev_pwr_mode, hba->uic_link_state);
7471 return ret;
7472 }
7473 EXPORT_SYMBOL(ufshcd_runtime_suspend);
7474
7475 /**
7476 * ufshcd_runtime_resume - runtime resume routine
7477 * @hba: per adapter instance
7478 *
7479 * This function basically brings the UFS device, UniPro link and controller
7480 * to active state. Following operations are done in this function:
7481 *
7482 * 1. Turn on all the controller related clocks
7483 * 2. Bring the UniPro link out of Hibernate state
7484 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7485 * to active state.
7486 * 4. If auto-bkops is enabled on the device, disable it.
7487 *
7488 * So following would be the possible power state after this function return
7489 * successfully:
7490 * S1: UFS device in Active state with VCC rail ON
7491 * UniPro link in Active state
7492 * All the UFS/UniPro controller clocks are ON
7493 *
7494 * Returns 0 for success and non-zero for failure
7495 */
7496 int ufshcd_runtime_resume(struct ufs_hba *hba)
7497 {
7498 int ret = 0;
7499 ktime_t start = ktime_get();
7500
7501 if (!hba)
7502 return -EINVAL;
7503
7504 if (!hba->is_powered)
7505 goto out;
7506 else
7507 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7508 out:
7509 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7510 ktime_to_us(ktime_sub(ktime_get(), start)),
7511 hba->curr_dev_pwr_mode, hba->uic_link_state);
7512 return ret;
7513 }
7514 EXPORT_SYMBOL(ufshcd_runtime_resume);
7515
7516 int ufshcd_runtime_idle(struct ufs_hba *hba)
7517 {
7518 return 0;
7519 }
7520 EXPORT_SYMBOL(ufshcd_runtime_idle);
7521
7522 static inline ssize_t ufshcd_pm_lvl_store(struct device *dev,
7523 struct device_attribute *attr,
7524 const char *buf, size_t count,
7525 bool rpm)
7526 {
7527 struct ufs_hba *hba = dev_get_drvdata(dev);
7528 unsigned long flags, value;
7529
7530 if (kstrtoul(buf, 0, &value))
7531 return -EINVAL;
7532
7533 if ((value < UFS_PM_LVL_0) || (value >= UFS_PM_LVL_MAX))
7534 return -EINVAL;
7535
7536 spin_lock_irqsave(hba->host->host_lock, flags);
7537 if (rpm)
7538 hba->rpm_lvl = value;
7539 else
7540 hba->spm_lvl = value;
7541 spin_unlock_irqrestore(hba->host->host_lock, flags);
7542 return count;
7543 }
7544
7545 static ssize_t ufshcd_rpm_lvl_show(struct device *dev,
7546 struct device_attribute *attr, char *buf)
7547 {
7548 struct ufs_hba *hba = dev_get_drvdata(dev);
7549 int curr_len;
7550 u8 lvl;
7551
7552 curr_len = snprintf(buf, PAGE_SIZE,
7553 "\nCurrent Runtime PM level [%d] => dev_state [%s] link_state [%s]\n",
7554 hba->rpm_lvl,
7555 ufschd_ufs_dev_pwr_mode_to_string(
7556 ufs_pm_lvl_states[hba->rpm_lvl].dev_state),
7557 ufschd_uic_link_state_to_string(
7558 ufs_pm_lvl_states[hba->rpm_lvl].link_state));
7559
7560 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7561 "\nAll available Runtime PM levels info:\n");
7562 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7563 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7564 "\tRuntime PM level [%d] => dev_state [%s] link_state [%s]\n",
7565 lvl,
7566 ufschd_ufs_dev_pwr_mode_to_string(
7567 ufs_pm_lvl_states[lvl].dev_state),
7568 ufschd_uic_link_state_to_string(
7569 ufs_pm_lvl_states[lvl].link_state));
7570
7571 return curr_len;
7572 }
7573
7574 static ssize_t ufshcd_rpm_lvl_store(struct device *dev,
7575 struct device_attribute *attr, const char *buf, size_t count)
7576 {
7577 return ufshcd_pm_lvl_store(dev, attr, buf, count, true);
7578 }
7579
7580 static void ufshcd_add_rpm_lvl_sysfs_nodes(struct ufs_hba *hba)
7581 {
7582 hba->rpm_lvl_attr.show = ufshcd_rpm_lvl_show;
7583 hba->rpm_lvl_attr.store = ufshcd_rpm_lvl_store;
7584 sysfs_attr_init(&hba->rpm_lvl_attr.attr);
7585 hba->rpm_lvl_attr.attr.name = "rpm_lvl";
7586 hba->rpm_lvl_attr.attr.mode = 0644;
7587 if (device_create_file(hba->dev, &hba->rpm_lvl_attr))
7588 dev_err(hba->dev, "Failed to create sysfs for rpm_lvl\n");
7589 }
7590
7591 static ssize_t ufshcd_spm_lvl_show(struct device *dev,
7592 struct device_attribute *attr, char *buf)
7593 {
7594 struct ufs_hba *hba = dev_get_drvdata(dev);
7595 int curr_len;
7596 u8 lvl;
7597
7598 curr_len = snprintf(buf, PAGE_SIZE,
7599 "\nCurrent System PM level [%d] => dev_state [%s] link_state [%s]\n",
7600 hba->spm_lvl,
7601 ufschd_ufs_dev_pwr_mode_to_string(
7602 ufs_pm_lvl_states[hba->spm_lvl].dev_state),
7603 ufschd_uic_link_state_to_string(
7604 ufs_pm_lvl_states[hba->spm_lvl].link_state));
7605
7606 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7607 "\nAll available System PM levels info:\n");
7608 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7609 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7610 "\tSystem PM level [%d] => dev_state [%s] link_state [%s]\n",
7611 lvl,
7612 ufschd_ufs_dev_pwr_mode_to_string(
7613 ufs_pm_lvl_states[lvl].dev_state),
7614 ufschd_uic_link_state_to_string(
7615 ufs_pm_lvl_states[lvl].link_state));
7616
7617 return curr_len;
7618 }
7619
7620 static ssize_t ufshcd_spm_lvl_store(struct device *dev,
7621 struct device_attribute *attr, const char *buf, size_t count)
7622 {
7623 return ufshcd_pm_lvl_store(dev, attr, buf, count, false);
7624 }
7625
7626 static void ufshcd_add_spm_lvl_sysfs_nodes(struct ufs_hba *hba)
7627 {
7628 hba->spm_lvl_attr.show = ufshcd_spm_lvl_show;
7629 hba->spm_lvl_attr.store = ufshcd_spm_lvl_store;
7630 sysfs_attr_init(&hba->spm_lvl_attr.attr);
7631 hba->spm_lvl_attr.attr.name = "spm_lvl";
7632 hba->spm_lvl_attr.attr.mode = 0644;
7633 if (device_create_file(hba->dev, &hba->spm_lvl_attr))
7634 dev_err(hba->dev, "Failed to create sysfs for spm_lvl\n");
7635 }
7636
7637 static inline void ufshcd_add_sysfs_nodes(struct ufs_hba *hba)
7638 {
7639 ufshcd_add_rpm_lvl_sysfs_nodes(hba);
7640 ufshcd_add_spm_lvl_sysfs_nodes(hba);
7641 }
7642
7643 /**
7644 * ufshcd_shutdown - shutdown routine
7645 * @hba: per adapter instance
7646 *
7647 * This function would power off both UFS device and UFS link.
7648 *
7649 * Returns 0 always to allow force shutdown even in case of errors.
7650 */
7651 int ufshcd_shutdown(struct ufs_hba *hba)
7652 {
7653 int ret = 0;
7654
7655 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
7656 goto out;
7657
7658 if (pm_runtime_suspended(hba->dev)) {
7659 ret = ufshcd_runtime_resume(hba);
7660 if (ret)
7661 goto out;
7662 }
7663
7664 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
7665 out:
7666 if (ret)
7667 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
7668 /* allow force shutdown even in case of errors */
7669 return 0;
7670 }
7671 EXPORT_SYMBOL(ufshcd_shutdown);
7672
7673 /**
7674 * ufshcd_remove - de-allocate SCSI host and host memory space
7675 * data structure memory
7676 * @hba - per adapter instance
7677 */
7678 void ufshcd_remove(struct ufs_hba *hba)
7679 {
7680 scsi_remove_host(hba->host);
7681 /* disable interrupts */
7682 ufshcd_disable_intr(hba, hba->intr_mask);
7683 ufshcd_hba_stop(hba, true);
7684
7685 ufshcd_exit_clk_gating(hba);
7686 if (ufshcd_is_clkscaling_supported(hba))
7687 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
7688 ufshcd_hba_exit(hba);
7689 }
7690 EXPORT_SYMBOL_GPL(ufshcd_remove);
7691
7692 /**
7693 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
7694 * @hba: pointer to Host Bus Adapter (HBA)
7695 */
7696 void ufshcd_dealloc_host(struct ufs_hba *hba)
7697 {
7698 scsi_host_put(hba->host);
7699 }
7700 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
7701
7702 /**
7703 * ufshcd_set_dma_mask - Set dma mask based on the controller
7704 * addressing capability
7705 * @hba: per adapter instance
7706 *
7707 * Returns 0 for success, non-zero for failure
7708 */
7709 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
7710 {
7711 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
7712 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
7713 return 0;
7714 }
7715 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
7716 }
7717
7718 /**
7719 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
7720 * @dev: pointer to device handle
7721 * @hba_handle: driver private handle
7722 * Returns 0 on success, non-zero value on failure
7723 */
7724 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7725 {
7726 struct Scsi_Host *host;
7727 struct ufs_hba *hba;
7728 int err = 0;
7729
7730 if (!dev) {
7731 dev_err(dev,
7732 "Invalid memory reference for dev is NULL\n");
7733 err = -ENODEV;
7734 goto out_error;
7735 }
7736
7737 host = scsi_host_alloc(&ufshcd_driver_template,
7738 sizeof(struct ufs_hba));
7739 if (!host) {
7740 dev_err(dev, "scsi_host_alloc failed\n");
7741 err = -ENOMEM;
7742 goto out_error;
7743 }
7744 hba = shost_priv(host);
7745 hba->host = host;
7746 hba->dev = dev;
7747 *hba_handle = hba;
7748
7749 out_error:
7750 return err;
7751 }
7752 EXPORT_SYMBOL(ufshcd_alloc_host);
7753
7754 /**
7755 * ufshcd_init - Driver initialization routine
7756 * @hba: per-adapter instance
7757 * @mmio_base: base register address
7758 * @irq: Interrupt line of device
7759 * Returns 0 on success, non-zero value on failure
7760 */
7761 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
7762 {
7763 int err;
7764 struct Scsi_Host *host = hba->host;
7765 struct device *dev = hba->dev;
7766
7767 if (!mmio_base) {
7768 dev_err(hba->dev,
7769 "Invalid memory reference for mmio_base is NULL\n");
7770 err = -ENODEV;
7771 goto out_error;
7772 }
7773
7774 hba->mmio_base = mmio_base;
7775 hba->irq = irq;
7776
7777 err = ufshcd_hba_init(hba);
7778 if (err)
7779 goto out_error;
7780
7781 /* Read capabilities registers */
7782 ufshcd_hba_capabilities(hba);
7783
7784 /* Get UFS version supported by the controller */
7785 hba->ufs_version = ufshcd_get_ufs_version(hba);
7786
7787 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
7788 (hba->ufs_version != UFSHCI_VERSION_11) &&
7789 (hba->ufs_version != UFSHCI_VERSION_20) &&
7790 (hba->ufs_version != UFSHCI_VERSION_21))
7791 dev_err(hba->dev, "invalid UFS version 0x%x\n",
7792 hba->ufs_version);
7793
7794 /* Get Interrupt bit mask per version */
7795 hba->intr_mask = ufshcd_get_intr_mask(hba);
7796
7797 err = ufshcd_set_dma_mask(hba);
7798 if (err) {
7799 dev_err(hba->dev, "set dma mask failed\n");
7800 goto out_disable;
7801 }
7802
7803 /* Allocate memory for host memory space */
7804 err = ufshcd_memory_alloc(hba);
7805 if (err) {
7806 dev_err(hba->dev, "Memory allocation failed\n");
7807 goto out_disable;
7808 }
7809
7810 /* Configure LRB */
7811 ufshcd_host_memory_configure(hba);
7812
7813 host->can_queue = hba->nutrs;
7814 host->cmd_per_lun = hba->nutrs;
7815 host->max_id = UFSHCD_MAX_ID;
7816 host->max_lun = UFS_MAX_LUNS;
7817 host->max_channel = UFSHCD_MAX_CHANNEL;
7818 host->unique_id = host->host_no;
7819 host->max_cmd_len = MAX_CDB_SIZE;
7820
7821 hba->max_pwr_info.is_valid = false;
7822
7823 /* Initailize wait queue for task management */
7824 init_waitqueue_head(&hba->tm_wq);
7825 init_waitqueue_head(&hba->tm_tag_wq);
7826
7827 /* Initialize work queues */
7828 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
7829 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7830
7831 /* Initialize UIC command mutex */
7832 mutex_init(&hba->uic_cmd_mutex);
7833
7834 /* Initialize mutex for device management commands */
7835 mutex_init(&hba->dev_cmd.lock);
7836
7837 init_rwsem(&hba->clk_scaling_lock);
7838
7839 /* Initialize device management tag acquire wait queue */
7840 init_waitqueue_head(&hba->dev_cmd.tag_wq);
7841
7842 ufshcd_init_clk_gating(hba);
7843
7844 /*
7845 * In order to avoid any spurious interrupt immediately after
7846 * registering UFS controller interrupt handler, clear any pending UFS
7847 * interrupt status and disable all the UFS interrupts.
7848 */
7849 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
7850 REG_INTERRUPT_STATUS);
7851 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
7852 /*
7853 * Make sure that UFS interrupts are disabled and any pending interrupt
7854 * status is cleared before registering UFS interrupt handler.
7855 */
7856 mb();
7857
7858 /* IRQ registration */
7859 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7860 if (err) {
7861 dev_err(hba->dev, "request irq failed\n");
7862 goto exit_gating;
7863 } else {
7864 hba->is_irq_enabled = true;
7865 }
7866
7867 err = scsi_add_host(host, hba->dev);
7868 if (err) {
7869 dev_err(hba->dev, "scsi_add_host failed\n");
7870 goto exit_gating;
7871 }
7872
7873 /* Host controller enable */
7874 err = ufshcd_hba_enable(hba);
7875 if (err) {
7876 dev_err(hba->dev, "Host controller enable failed\n");
7877 ufshcd_print_host_regs(hba);
7878 ufshcd_print_host_state(hba);
7879 goto out_remove_scsi_host;
7880 }
7881
7882 if (ufshcd_is_clkscaling_supported(hba)) {
7883 char wq_name[sizeof("ufs_clkscaling_00")];
7884
7885 INIT_WORK(&hba->clk_scaling.suspend_work,
7886 ufshcd_clk_scaling_suspend_work);
7887 INIT_WORK(&hba->clk_scaling.resume_work,
7888 ufshcd_clk_scaling_resume_work);
7889
7890 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clkscaling_%d",
7891 host->host_no);
7892 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
7893
7894 ufshcd_clkscaling_init_sysfs(hba);
7895 }
7896
7897 /*
7898 * Set the default power management level for runtime and system PM.
7899 * Default power saving mode is to keep UFS link in Hibern8 state
7900 * and UFS device in sleep state.
7901 */
7902 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7903 UFS_SLEEP_PWR_MODE,
7904 UIC_LINK_HIBERN8_STATE);
7905 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7906 UFS_SLEEP_PWR_MODE,
7907 UIC_LINK_HIBERN8_STATE);
7908
7909 /* Hold auto suspend until async scan completes */
7910 pm_runtime_get_sync(dev);
7911
7912 /*
7913 * We are assuming that device wasn't put in sleep/power-down
7914 * state exclusively during the boot stage before kernel.
7915 * This assumption helps avoid doing link startup twice during
7916 * ufshcd_probe_hba().
7917 */
7918 ufshcd_set_ufs_dev_active(hba);
7919
7920 async_schedule(ufshcd_async_scan, hba);
7921 ufshcd_add_sysfs_nodes(hba);
7922
7923 return 0;
7924
7925 out_remove_scsi_host:
7926 scsi_remove_host(hba->host);
7927 exit_gating:
7928 ufshcd_exit_clk_gating(hba);
7929 out_disable:
7930 hba->is_irq_enabled = false;
7931 ufshcd_hba_exit(hba);
7932 out_error:
7933 return err;
7934 }
7935 EXPORT_SYMBOL_GPL(ufshcd_init);
7936
7937 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
7938 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
7939 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7940 MODULE_LICENSE("GPL");
7941 MODULE_VERSION(UFSHCD_DRIVER_VERSION);