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8250_pci: duplicate initializer in array ([pbn_b0_8_115200])
[mirror_ubuntu-artful-kernel.git] / drivers / serial / 8250_pci.c
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/tty.h>
24 #include <linux/serial_core.h>
25 #include <linux/8250_pci.h>
26 #include <linux/bitops.h>
27
28 #include <asm/byteorder.h>
29 #include <asm/io.h>
30
31 #include "8250.h"
32
33 #undef SERIAL_DEBUG_PCI
34
35 /*
36 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41 struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
46 int (*init)(struct pci_dev *dev);
47 int (*setup)(struct serial_private *, struct pciserial_board *,
48 struct uart_port *, int);
49 void (*exit)(struct pci_dev *dev);
50 };
51
52 #define PCI_NUM_BAR_RESOURCES 6
53
54 struct serial_private {
55 struct pci_dev *dev;
56 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 int line[0];
60 };
61
62 static void moan_device(const char *str, struct pci_dev *dev)
63 {
64 printk(KERN_WARNING "%s: %s\n"
65 KERN_WARNING "Please send the output of lspci -vv, this\n"
66 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 KERN_WARNING "manufacturer and name of serial board or\n"
68 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71 }
72
73 static int
74 setup_port(struct serial_private *priv, struct uart_port *port,
75 int bar, int offset, int regshift)
76 {
77 struct pci_dev *dev = priv->dev;
78 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
83 base = pci_resource_start(dev, bar);
84
85 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
86 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
94 port->iobase = 0;
95 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
99 port->iotype = UPIO_PORT;
100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
104 }
105 return 0;
106 }
107
108 /*
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 */
111 static int addidata_apci7800_setup(struct serial_private *priv,
112 struct pciserial_board *board,
113 struct uart_port *port, int idx)
114 {
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
117
118 if (idx < 2) {
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
121 bar += 1;
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
124 bar += 2;
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
127 bar += 3;
128 offset += ((idx - 6) * board->uart_offset);
129 }
130
131 return setup_port(priv, port, bar, offset, board->reg_shift);
132 }
133
134 /*
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138 static int
139 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
140 struct uart_port *port, int idx)
141 {
142 unsigned int bar, offset = board->first_offset;
143
144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
152 return setup_port(priv, port, bar, offset, board->reg_shift);
153 }
154
155 /*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
162 static int pci_hp_diva_init(struct pci_dev *dev)
163 {
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
181 rc = 1;
182 break;
183 }
184
185 return rc;
186 }
187
188 /*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192 static int
193 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
194 struct uart_port *port, int idx)
195 {
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
199 switch (priv->dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
216 return setup_port(priv, port, bar, offset, board->reg_shift);
217 }
218
219 /*
220 * Added for EKF Intel i960 serial boards
221 */
222 static int pci_inteli960ni_init(struct pci_dev *dev)
223 {
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236 }
237
238 /*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
244 static int pci_plx9050_init(struct pci_dev *dev)
245 {
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
257 irq_config = 0x43;
258
259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
270 /*
271 * enable/disable interrupts
272 */
273 p = ioremap(pci_resource_start(dev, 0), 0x80);
274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285 }
286
287 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288 {
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
297 p = ioremap(pci_resource_start(dev, 0), 0x80);
298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307 }
308
309 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310 static int
311 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
312 struct uart_port *port, int idx)
313 {
314 unsigned int bar, offset = board->first_offset;
315
316 bar = 0;
317
318 if (idx < 4) {
319 /* first four channels map to 0, 0x100, 0x200, 0x300 */
320 offset += idx * board->uart_offset;
321 } else if (idx < 8) {
322 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
323 offset += idx * board->uart_offset + 0xC00;
324 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return 1;
326
327 return setup_port(priv, port, bar, offset, board->reg_shift);
328 }
329
330 /*
331 * This does initialization for PMC OCTALPRO cards:
332 * maps the device memory, resets the UARTs (needed, bc
333 * if the module is removed and inserted again, the card
334 * is in the sleep mode) and enables global interrupt.
335 */
336
337 /* global control register offset for SBS PMC-OctalPro */
338 #define OCT_REG_CR_OFF 0x500
339
340 static int sbs_init(struct pci_dev *dev)
341 {
342 u8 __iomem *p;
343
344 p = ioremap(pci_resource_start(dev, 0), pci_resource_len(dev, 0));
345
346 if (p == NULL)
347 return -ENOMEM;
348 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
349 writeb(0x10, p + OCT_REG_CR_OFF);
350 udelay(50);
351 writeb(0x0, p + OCT_REG_CR_OFF);
352
353 /* Set bit-2 (INTENABLE) of Control Register */
354 writeb(0x4, p + OCT_REG_CR_OFF);
355 iounmap(p);
356
357 return 0;
358 }
359
360 /*
361 * Disables the global interrupt of PMC-OctalPro
362 */
363
364 static void __devexit sbs_exit(struct pci_dev *dev)
365 {
366 u8 __iomem *p;
367
368 p = ioremap(pci_resource_start(dev, 0), pci_resource_len(dev, 0));
369 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
370 if (p != NULL)
371 writeb(0, p + OCT_REG_CR_OFF);
372 iounmap(p);
373 }
374
375 /*
376 * SIIG serial cards have an PCI interface chip which also controls
377 * the UART clocking frequency. Each UART can be clocked independently
378 * (except cards equiped with 4 UARTs) and initial clocking settings
379 * are stored in the EEPROM chip. It can cause problems because this
380 * version of serial driver doesn't support differently clocked UART's
381 * on single PCI card. To prevent this, initialization functions set
382 * high frequency clocking for all UART's on given card. It is safe (I
383 * hope) because it doesn't touch EEPROM settings to prevent conflicts
384 * with other OSes (like M$ DOS).
385 *
386 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
387 *
388 * There is two family of SIIG serial cards with different PCI
389 * interface chip and different configuration methods:
390 * - 10x cards have control registers in IO and/or memory space;
391 * - 20x cards have control registers in standard PCI configuration space.
392 *
393 * Note: all 10x cards have PCI device ids 0x10..
394 * all 20x cards have PCI device ids 0x20..
395 *
396 * There are also Quartet Serial cards which use Oxford Semiconductor
397 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
398 *
399 * Note: some SIIG cards are probed by the parport_serial object.
400 */
401
402 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
403 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
404
405 static int pci_siig10x_init(struct pci_dev *dev)
406 {
407 u16 data;
408 void __iomem *p;
409
410 switch (dev->device & 0xfff8) {
411 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
412 data = 0xffdf;
413 break;
414 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
415 data = 0xf7ff;
416 break;
417 default: /* 1S1P, 4S */
418 data = 0xfffb;
419 break;
420 }
421
422 p = ioremap(pci_resource_start(dev, 0), 0x80);
423 if (p == NULL)
424 return -ENOMEM;
425
426 writew(readw(p + 0x28) & data, p + 0x28);
427 readw(p + 0x28);
428 iounmap(p);
429 return 0;
430 }
431
432 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
433 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
434
435 static int pci_siig20x_init(struct pci_dev *dev)
436 {
437 u8 data;
438
439 /* Change clock frequency for the first UART. */
440 pci_read_config_byte(dev, 0x6f, &data);
441 pci_write_config_byte(dev, 0x6f, data & 0xef);
442
443 /* If this card has 2 UART, we have to do the same with second UART. */
444 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
445 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
446 pci_read_config_byte(dev, 0x73, &data);
447 pci_write_config_byte(dev, 0x73, data & 0xef);
448 }
449 return 0;
450 }
451
452 static int pci_siig_init(struct pci_dev *dev)
453 {
454 unsigned int type = dev->device & 0xff00;
455
456 if (type == 0x1000)
457 return pci_siig10x_init(dev);
458 else if (type == 0x2000)
459 return pci_siig20x_init(dev);
460
461 moan_device("Unknown SIIG card", dev);
462 return -ENODEV;
463 }
464
465 static int pci_siig_setup(struct serial_private *priv,
466 struct pciserial_board *board,
467 struct uart_port *port, int idx)
468 {
469 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
470
471 if (idx > 3) {
472 bar = 4;
473 offset = (idx - 4) * 8;
474 }
475
476 return setup_port(priv, port, bar, offset, 0);
477 }
478
479 /*
480 * Timedia has an explosion of boards, and to avoid the PCI table from
481 * growing *huge*, we use this function to collapse some 70 entries
482 * in the PCI table into one, for sanity's and compactness's sake.
483 */
484 static const unsigned short timedia_single_port[] = {
485 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
486 };
487
488 static const unsigned short timedia_dual_port[] = {
489 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
490 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
491 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
492 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
493 0xD079, 0
494 };
495
496 static const unsigned short timedia_quad_port[] = {
497 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
498 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
499 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
500 0xB157, 0
501 };
502
503 static const unsigned short timedia_eight_port[] = {
504 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
505 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
506 };
507
508 static const struct timedia_struct {
509 int num;
510 const unsigned short *ids;
511 } timedia_data[] = {
512 { 1, timedia_single_port },
513 { 2, timedia_dual_port },
514 { 4, timedia_quad_port },
515 { 8, timedia_eight_port }
516 };
517
518 static int pci_timedia_init(struct pci_dev *dev)
519 {
520 const unsigned short *ids;
521 int i, j;
522
523 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
524 ids = timedia_data[i].ids;
525 for (j = 0; ids[j]; j++)
526 if (dev->subsystem_device == ids[j])
527 return timedia_data[i].num;
528 }
529 return 0;
530 }
531
532 /*
533 * Timedia/SUNIX uses a mixture of BARs and offsets
534 * Ugh, this is ugly as all hell --- TYT
535 */
536 static int
537 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
538 struct uart_port *port, int idx)
539 {
540 unsigned int bar = 0, offset = board->first_offset;
541
542 switch (idx) {
543 case 0:
544 bar = 0;
545 break;
546 case 1:
547 offset = board->uart_offset;
548 bar = 0;
549 break;
550 case 2:
551 bar = 1;
552 break;
553 case 3:
554 offset = board->uart_offset;
555 /* FALLTHROUGH */
556 case 4: /* BAR 2 */
557 case 5: /* BAR 3 */
558 case 6: /* BAR 4 */
559 case 7: /* BAR 5 */
560 bar = idx - 2;
561 }
562
563 return setup_port(priv, port, bar, offset, board->reg_shift);
564 }
565
566 /*
567 * Some Titan cards are also a little weird
568 */
569 static int
570 titan_400l_800l_setup(struct serial_private *priv,
571 struct pciserial_board *board,
572 struct uart_port *port, int idx)
573 {
574 unsigned int bar, offset = board->first_offset;
575
576 switch (idx) {
577 case 0:
578 bar = 1;
579 break;
580 case 1:
581 bar = 2;
582 break;
583 default:
584 bar = 4;
585 offset = (idx - 2) * board->uart_offset;
586 }
587
588 return setup_port(priv, port, bar, offset, board->reg_shift);
589 }
590
591 static int pci_xircom_init(struct pci_dev *dev)
592 {
593 msleep(100);
594 return 0;
595 }
596
597 static int pci_netmos_init(struct pci_dev *dev)
598 {
599 /* subdevice 0x00PS means <P> parallel, <S> serial */
600 unsigned int num_serial = dev->subsystem_device & 0xf;
601
602 if (num_serial == 0)
603 return -ENODEV;
604 return num_serial;
605 }
606
607 /*
608 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
609 *
610 * These chips are available with optionally one parallel port and up to
611 * two serial ports. Unfortunately they all have the same product id.
612 *
613 * Basic configuration is done over a region of 32 I/O ports. The base
614 * ioport is called INTA or INTC, depending on docs/other drivers.
615 *
616 * The region of the 32 I/O ports is configured in POSIO0R...
617 */
618
619 /* registers */
620 #define ITE_887x_MISCR 0x9c
621 #define ITE_887x_INTCBAR 0x78
622 #define ITE_887x_UARTBAR 0x7c
623 #define ITE_887x_PS0BAR 0x10
624 #define ITE_887x_POSIO0 0x60
625
626 /* I/O space size */
627 #define ITE_887x_IOSIZE 32
628 /* I/O space size (bits 26-24; 8 bytes = 011b) */
629 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
630 /* I/O space size (bits 26-24; 32 bytes = 101b) */
631 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
632 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
633 #define ITE_887x_POSIO_SPEED (3 << 29)
634 /* enable IO_Space bit */
635 #define ITE_887x_POSIO_ENABLE (1 << 31)
636
637 static int pci_ite887x_init(struct pci_dev *dev)
638 {
639 /* inta_addr are the configuration addresses of the ITE */
640 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
641 0x200, 0x280, 0 };
642 int ret, i, type;
643 struct resource *iobase = NULL;
644 u32 miscr, uartbar, ioport;
645
646 /* search for the base-ioport */
647 i = 0;
648 while (inta_addr[i] && iobase == NULL) {
649 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
650 "ite887x");
651 if (iobase != NULL) {
652 /* write POSIO0R - speed | size | ioport */
653 pci_write_config_dword(dev, ITE_887x_POSIO0,
654 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
655 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
656 /* write INTCBAR - ioport */
657 pci_write_config_dword(dev, ITE_887x_INTCBAR,
658 inta_addr[i]);
659 ret = inb(inta_addr[i]);
660 if (ret != 0xff) {
661 /* ioport connected */
662 break;
663 }
664 release_region(iobase->start, ITE_887x_IOSIZE);
665 iobase = NULL;
666 }
667 i++;
668 }
669
670 if (!inta_addr[i]) {
671 printk(KERN_ERR "ite887x: could not find iobase\n");
672 return -ENODEV;
673 }
674
675 /* start of undocumented type checking (see parport_pc.c) */
676 type = inb(iobase->start + 0x18) & 0x0f;
677
678 switch (type) {
679 case 0x2: /* ITE8871 (1P) */
680 case 0xa: /* ITE8875 (1P) */
681 ret = 0;
682 break;
683 case 0xe: /* ITE8872 (2S1P) */
684 ret = 2;
685 break;
686 case 0x6: /* ITE8873 (1S) */
687 ret = 1;
688 break;
689 case 0x8: /* ITE8874 (2S) */
690 ret = 2;
691 break;
692 default:
693 moan_device("Unknown ITE887x", dev);
694 ret = -ENODEV;
695 }
696
697 /* configure all serial ports */
698 for (i = 0; i < ret; i++) {
699 /* read the I/O port from the device */
700 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
701 &ioport);
702 ioport &= 0x0000FF00; /* the actual base address */
703 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
704 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
705 ITE_887x_POSIO_IOSIZE_8 | ioport);
706
707 /* write the ioport to the UARTBAR */
708 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
709 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
710 uartbar |= (ioport << (16 * i)); /* set the ioport */
711 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
712
713 /* get current config */
714 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
715 /* disable interrupts (UARTx_Routing[3:0]) */
716 miscr &= ~(0xf << (12 - 4 * i));
717 /* activate the UART (UARTx_En) */
718 miscr |= 1 << (23 - i);
719 /* write new config with activated UART */
720 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
721 }
722
723 if (ret <= 0) {
724 /* the device has no UARTs if we get here */
725 release_region(iobase->start, ITE_887x_IOSIZE);
726 }
727
728 return ret;
729 }
730
731 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
732 {
733 u32 ioport;
734 /* the ioport is bit 0-15 in POSIO0R */
735 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
736 ioport &= 0xffff;
737 release_region(ioport, ITE_887x_IOSIZE);
738 }
739
740 static int
741 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
742 struct uart_port *port, int idx)
743 {
744 unsigned int bar, offset = board->first_offset, maxnr;
745
746 bar = FL_GET_BASE(board->flags);
747 if (board->flags & FL_BASE_BARS)
748 bar += idx;
749 else
750 offset += idx * board->uart_offset;
751
752 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
753 (board->reg_shift + 3);
754
755 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
756 return 1;
757
758 return setup_port(priv, port, bar, offset, board->reg_shift);
759 }
760
761 /* This should be in linux/pci_ids.h */
762 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
763 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
764 #define PCI_DEVICE_ID_OCTPRO 0x0001
765 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
766 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
767 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
768 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
769
770 /*
771 * Master list of serial port init/setup/exit quirks.
772 * This does not describe the general nature of the port.
773 * (ie, baud base, number and location of ports, etc)
774 *
775 * This list is ordered alphabetically by vendor then device.
776 * Specific entries must come before more generic entries.
777 */
778 static struct pci_serial_quirk pci_serial_quirks[] = {
779 /*
780 * ADDI-DATA GmbH communication cards <info@addi-data.com>
781 */
782 {
783 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
784 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
785 .subvendor = PCI_ANY_ID,
786 .subdevice = PCI_ANY_ID,
787 .setup = addidata_apci7800_setup,
788 },
789 /*
790 * AFAVLAB cards - these may be called via parport_serial
791 * It is not clear whether this applies to all products.
792 */
793 {
794 .vendor = PCI_VENDOR_ID_AFAVLAB,
795 .device = PCI_ANY_ID,
796 .subvendor = PCI_ANY_ID,
797 .subdevice = PCI_ANY_ID,
798 .setup = afavlab_setup,
799 },
800 /*
801 * HP Diva
802 */
803 {
804 .vendor = PCI_VENDOR_ID_HP,
805 .device = PCI_DEVICE_ID_HP_DIVA,
806 .subvendor = PCI_ANY_ID,
807 .subdevice = PCI_ANY_ID,
808 .init = pci_hp_diva_init,
809 .setup = pci_hp_diva_setup,
810 },
811 /*
812 * Intel
813 */
814 {
815 .vendor = PCI_VENDOR_ID_INTEL,
816 .device = PCI_DEVICE_ID_INTEL_80960_RP,
817 .subvendor = 0xe4bf,
818 .subdevice = PCI_ANY_ID,
819 .init = pci_inteli960ni_init,
820 .setup = pci_default_setup,
821 },
822 /*
823 * ITE
824 */
825 {
826 .vendor = PCI_VENDOR_ID_ITE,
827 .device = PCI_DEVICE_ID_ITE_8872,
828 .subvendor = PCI_ANY_ID,
829 .subdevice = PCI_ANY_ID,
830 .init = pci_ite887x_init,
831 .setup = pci_default_setup,
832 .exit = __devexit_p(pci_ite887x_exit),
833 },
834 /*
835 * Panacom
836 */
837 {
838 .vendor = PCI_VENDOR_ID_PANACOM,
839 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
840 .subvendor = PCI_ANY_ID,
841 .subdevice = PCI_ANY_ID,
842 .init = pci_plx9050_init,
843 .setup = pci_default_setup,
844 .exit = __devexit_p(pci_plx9050_exit),
845 },
846 {
847 .vendor = PCI_VENDOR_ID_PANACOM,
848 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
849 .subvendor = PCI_ANY_ID,
850 .subdevice = PCI_ANY_ID,
851 .init = pci_plx9050_init,
852 .setup = pci_default_setup,
853 .exit = __devexit_p(pci_plx9050_exit),
854 },
855 /*
856 * PLX
857 */
858 {
859 .vendor = PCI_VENDOR_ID_PLX,
860 .device = PCI_DEVICE_ID_PLX_9030,
861 .subvendor = PCI_SUBVENDOR_ID_PERLE,
862 .subdevice = PCI_ANY_ID,
863 .setup = pci_default_setup,
864 },
865 {
866 .vendor = PCI_VENDOR_ID_PLX,
867 .device = PCI_DEVICE_ID_PLX_9050,
868 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
869 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
870 .init = pci_plx9050_init,
871 .setup = pci_default_setup,
872 .exit = __devexit_p(pci_plx9050_exit),
873 },
874 {
875 .vendor = PCI_VENDOR_ID_PLX,
876 .device = PCI_DEVICE_ID_PLX_9050,
877 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
878 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
879 .init = pci_plx9050_init,
880 .setup = pci_default_setup,
881 .exit = __devexit_p(pci_plx9050_exit),
882 },
883 {
884 .vendor = PCI_VENDOR_ID_PLX,
885 .device = PCI_DEVICE_ID_PLX_ROMULUS,
886 .subvendor = PCI_VENDOR_ID_PLX,
887 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
888 .init = pci_plx9050_init,
889 .setup = pci_default_setup,
890 .exit = __devexit_p(pci_plx9050_exit),
891 },
892 /*
893 * SBS Technologies, Inc., PMC-OCTALPRO 232
894 */
895 {
896 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
897 .device = PCI_DEVICE_ID_OCTPRO,
898 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
899 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
900 .init = sbs_init,
901 .setup = sbs_setup,
902 .exit = __devexit_p(sbs_exit),
903 },
904 /*
905 * SBS Technologies, Inc., PMC-OCTALPRO 422
906 */
907 {
908 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
909 .device = PCI_DEVICE_ID_OCTPRO,
910 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
911 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
912 .init = sbs_init,
913 .setup = sbs_setup,
914 .exit = __devexit_p(sbs_exit),
915 },
916 /*
917 * SBS Technologies, Inc., P-Octal 232
918 */
919 {
920 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
921 .device = PCI_DEVICE_ID_OCTPRO,
922 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
923 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
924 .init = sbs_init,
925 .setup = sbs_setup,
926 .exit = __devexit_p(sbs_exit),
927 },
928 /*
929 * SBS Technologies, Inc., P-Octal 422
930 */
931 {
932 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
933 .device = PCI_DEVICE_ID_OCTPRO,
934 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
935 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
936 .init = sbs_init,
937 .setup = sbs_setup,
938 .exit = __devexit_p(sbs_exit),
939 },
940 /*
941 * SIIG cards - these may be called via parport_serial
942 */
943 {
944 .vendor = PCI_VENDOR_ID_SIIG,
945 .device = PCI_ANY_ID,
946 .subvendor = PCI_ANY_ID,
947 .subdevice = PCI_ANY_ID,
948 .init = pci_siig_init,
949 .setup = pci_siig_setup,
950 },
951 /*
952 * Titan cards
953 */
954 {
955 .vendor = PCI_VENDOR_ID_TITAN,
956 .device = PCI_DEVICE_ID_TITAN_400L,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
959 .setup = titan_400l_800l_setup,
960 },
961 {
962 .vendor = PCI_VENDOR_ID_TITAN,
963 .device = PCI_DEVICE_ID_TITAN_800L,
964 .subvendor = PCI_ANY_ID,
965 .subdevice = PCI_ANY_ID,
966 .setup = titan_400l_800l_setup,
967 },
968 /*
969 * Timedia cards
970 */
971 {
972 .vendor = PCI_VENDOR_ID_TIMEDIA,
973 .device = PCI_DEVICE_ID_TIMEDIA_1889,
974 .subvendor = PCI_VENDOR_ID_TIMEDIA,
975 .subdevice = PCI_ANY_ID,
976 .init = pci_timedia_init,
977 .setup = pci_timedia_setup,
978 },
979 {
980 .vendor = PCI_VENDOR_ID_TIMEDIA,
981 .device = PCI_ANY_ID,
982 .subvendor = PCI_ANY_ID,
983 .subdevice = PCI_ANY_ID,
984 .setup = pci_timedia_setup,
985 },
986 /*
987 * Xircom cards
988 */
989 {
990 .vendor = PCI_VENDOR_ID_XIRCOM,
991 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
992 .subvendor = PCI_ANY_ID,
993 .subdevice = PCI_ANY_ID,
994 .init = pci_xircom_init,
995 .setup = pci_default_setup,
996 },
997 /*
998 * Netmos cards - these may be called via parport_serial
999 */
1000 {
1001 .vendor = PCI_VENDOR_ID_NETMOS,
1002 .device = PCI_ANY_ID,
1003 .subvendor = PCI_ANY_ID,
1004 .subdevice = PCI_ANY_ID,
1005 .init = pci_netmos_init,
1006 .setup = pci_default_setup,
1007 },
1008 /*
1009 * Default "match everything" terminator entry
1010 */
1011 {
1012 .vendor = PCI_ANY_ID,
1013 .device = PCI_ANY_ID,
1014 .subvendor = PCI_ANY_ID,
1015 .subdevice = PCI_ANY_ID,
1016 .setup = pci_default_setup,
1017 }
1018 };
1019
1020 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1021 {
1022 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1023 }
1024
1025 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1026 {
1027 struct pci_serial_quirk *quirk;
1028
1029 for (quirk = pci_serial_quirks; ; quirk++)
1030 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1031 quirk_id_matches(quirk->device, dev->device) &&
1032 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1033 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1034 break;
1035 return quirk;
1036 }
1037
1038 static inline int get_pci_irq(struct pci_dev *dev,
1039 struct pciserial_board *board)
1040 {
1041 if (board->flags & FL_NOIRQ)
1042 return 0;
1043 else
1044 return dev->irq;
1045 }
1046
1047 /*
1048 * This is the configuration table for all of the PCI serial boards
1049 * which we support. It is directly indexed by the pci_board_num_t enum
1050 * value, which is encoded in the pci_device_id PCI probe table's
1051 * driver_data member.
1052 *
1053 * The makeup of these names are:
1054 * pbn_bn{_bt}_n_baud{_offsetinhex}
1055 *
1056 * bn = PCI BAR number
1057 * bt = Index using PCI BARs
1058 * n = number of serial ports
1059 * baud = baud rate
1060 * offsetinhex = offset for each sequential port (in hex)
1061 *
1062 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1063 *
1064 * Please note: in theory if n = 1, _bt infix should make no difference.
1065 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1066 */
1067 enum pci_board_num_t {
1068 pbn_default = 0,
1069
1070 pbn_b0_1_115200,
1071 pbn_b0_2_115200,
1072 pbn_b0_4_115200,
1073 pbn_b0_5_115200,
1074 pbn_b0_8_115200,
1075
1076 pbn_b0_1_921600,
1077 pbn_b0_2_921600,
1078 pbn_b0_4_921600,
1079
1080 pbn_b0_2_1130000,
1081
1082 pbn_b0_4_1152000,
1083
1084 pbn_b0_2_1843200,
1085 pbn_b0_4_1843200,
1086
1087 pbn_b0_2_1843200_200,
1088 pbn_b0_4_1843200_200,
1089 pbn_b0_8_1843200_200,
1090
1091 pbn_b0_bt_1_115200,
1092 pbn_b0_bt_2_115200,
1093 pbn_b0_bt_8_115200,
1094
1095 pbn_b0_bt_1_460800,
1096 pbn_b0_bt_2_460800,
1097 pbn_b0_bt_4_460800,
1098
1099 pbn_b0_bt_1_921600,
1100 pbn_b0_bt_2_921600,
1101 pbn_b0_bt_4_921600,
1102 pbn_b0_bt_8_921600,
1103
1104 pbn_b1_1_115200,
1105 pbn_b1_2_115200,
1106 pbn_b1_4_115200,
1107 pbn_b1_8_115200,
1108
1109 pbn_b1_1_921600,
1110 pbn_b1_2_921600,
1111 pbn_b1_4_921600,
1112 pbn_b1_8_921600,
1113
1114 pbn_b1_2_1250000,
1115
1116 pbn_b1_bt_1_115200,
1117 pbn_b1_bt_2_921600,
1118
1119 pbn_b1_1_1382400,
1120 pbn_b1_2_1382400,
1121 pbn_b1_4_1382400,
1122 pbn_b1_8_1382400,
1123
1124 pbn_b2_1_115200,
1125 pbn_b2_2_115200,
1126 pbn_b2_4_115200,
1127 pbn_b2_8_115200,
1128
1129 pbn_b2_1_460800,
1130 pbn_b2_4_460800,
1131 pbn_b2_8_460800,
1132 pbn_b2_16_460800,
1133
1134 pbn_b2_1_921600,
1135 pbn_b2_4_921600,
1136 pbn_b2_8_921600,
1137
1138 pbn_b2_bt_1_115200,
1139 pbn_b2_bt_2_115200,
1140 pbn_b2_bt_4_115200,
1141
1142 pbn_b2_bt_2_921600,
1143 pbn_b2_bt_4_921600,
1144
1145 pbn_b3_2_115200,
1146 pbn_b3_4_115200,
1147 pbn_b3_8_115200,
1148
1149 /*
1150 * Board-specific versions.
1151 */
1152 pbn_panacom,
1153 pbn_panacom2,
1154 pbn_panacom4,
1155 pbn_exsys_4055,
1156 pbn_plx_romulus,
1157 pbn_oxsemi,
1158 pbn_intel_i960,
1159 pbn_sgi_ioc3,
1160 pbn_computone_4,
1161 pbn_computone_6,
1162 pbn_computone_8,
1163 pbn_sbsxrsio,
1164 pbn_exar_XR17C152,
1165 pbn_exar_XR17C154,
1166 pbn_exar_XR17C158,
1167 pbn_pasemi_1682M,
1168 };
1169
1170 /*
1171 * uart_offset - the space between channels
1172 * reg_shift - describes how the UART registers are mapped
1173 * to PCI memory by the card.
1174 * For example IER register on SBS, Inc. PMC-OctPro is located at
1175 * offset 0x10 from the UART base, while UART_IER is defined as 1
1176 * in include/linux/serial_reg.h,
1177 * see first lines of serial_in() and serial_out() in 8250.c
1178 */
1179
1180 static struct pciserial_board pci_boards[] __devinitdata = {
1181 [pbn_default] = {
1182 .flags = FL_BASE0,
1183 .num_ports = 1,
1184 .base_baud = 115200,
1185 .uart_offset = 8,
1186 },
1187 [pbn_b0_1_115200] = {
1188 .flags = FL_BASE0,
1189 .num_ports = 1,
1190 .base_baud = 115200,
1191 .uart_offset = 8,
1192 },
1193 [pbn_b0_2_115200] = {
1194 .flags = FL_BASE0,
1195 .num_ports = 2,
1196 .base_baud = 115200,
1197 .uart_offset = 8,
1198 },
1199 [pbn_b0_4_115200] = {
1200 .flags = FL_BASE0,
1201 .num_ports = 4,
1202 .base_baud = 115200,
1203 .uart_offset = 8,
1204 },
1205 [pbn_b0_5_115200] = {
1206 .flags = FL_BASE0,
1207 .num_ports = 5,
1208 .base_baud = 115200,
1209 .uart_offset = 8,
1210 },
1211 [pbn_b0_8_115200] = {
1212 .flags = FL_BASE0,
1213 .num_ports = 8,
1214 .base_baud = 115200,
1215 .uart_offset = 8,
1216 },
1217 [pbn_b0_1_921600] = {
1218 .flags = FL_BASE0,
1219 .num_ports = 1,
1220 .base_baud = 921600,
1221 .uart_offset = 8,
1222 },
1223 [pbn_b0_2_921600] = {
1224 .flags = FL_BASE0,
1225 .num_ports = 2,
1226 .base_baud = 921600,
1227 .uart_offset = 8,
1228 },
1229 [pbn_b0_4_921600] = {
1230 .flags = FL_BASE0,
1231 .num_ports = 4,
1232 .base_baud = 921600,
1233 .uart_offset = 8,
1234 },
1235
1236 [pbn_b0_2_1130000] = {
1237 .flags = FL_BASE0,
1238 .num_ports = 2,
1239 .base_baud = 1130000,
1240 .uart_offset = 8,
1241 },
1242
1243 [pbn_b0_4_1152000] = {
1244 .flags = FL_BASE0,
1245 .num_ports = 4,
1246 .base_baud = 1152000,
1247 .uart_offset = 8,
1248 },
1249
1250 [pbn_b0_2_1843200] = {
1251 .flags = FL_BASE0,
1252 .num_ports = 2,
1253 .base_baud = 1843200,
1254 .uart_offset = 8,
1255 },
1256 [pbn_b0_4_1843200] = {
1257 .flags = FL_BASE0,
1258 .num_ports = 4,
1259 .base_baud = 1843200,
1260 .uart_offset = 8,
1261 },
1262
1263 [pbn_b0_2_1843200_200] = {
1264 .flags = FL_BASE0,
1265 .num_ports = 2,
1266 .base_baud = 1843200,
1267 .uart_offset = 0x200,
1268 },
1269 [pbn_b0_4_1843200_200] = {
1270 .flags = FL_BASE0,
1271 .num_ports = 4,
1272 .base_baud = 1843200,
1273 .uart_offset = 0x200,
1274 },
1275 [pbn_b0_8_1843200_200] = {
1276 .flags = FL_BASE0,
1277 .num_ports = 8,
1278 .base_baud = 1843200,
1279 .uart_offset = 0x200,
1280 },
1281
1282 [pbn_b0_bt_1_115200] = {
1283 .flags = FL_BASE0|FL_BASE_BARS,
1284 .num_ports = 1,
1285 .base_baud = 115200,
1286 .uart_offset = 8,
1287 },
1288 [pbn_b0_bt_2_115200] = {
1289 .flags = FL_BASE0|FL_BASE_BARS,
1290 .num_ports = 2,
1291 .base_baud = 115200,
1292 .uart_offset = 8,
1293 },
1294 [pbn_b0_bt_8_115200] = {
1295 .flags = FL_BASE0|FL_BASE_BARS,
1296 .num_ports = 8,
1297 .base_baud = 115200,
1298 .uart_offset = 8,
1299 },
1300
1301 [pbn_b0_bt_1_460800] = {
1302 .flags = FL_BASE0|FL_BASE_BARS,
1303 .num_ports = 1,
1304 .base_baud = 460800,
1305 .uart_offset = 8,
1306 },
1307 [pbn_b0_bt_2_460800] = {
1308 .flags = FL_BASE0|FL_BASE_BARS,
1309 .num_ports = 2,
1310 .base_baud = 460800,
1311 .uart_offset = 8,
1312 },
1313 [pbn_b0_bt_4_460800] = {
1314 .flags = FL_BASE0|FL_BASE_BARS,
1315 .num_ports = 4,
1316 .base_baud = 460800,
1317 .uart_offset = 8,
1318 },
1319
1320 [pbn_b0_bt_1_921600] = {
1321 .flags = FL_BASE0|FL_BASE_BARS,
1322 .num_ports = 1,
1323 .base_baud = 921600,
1324 .uart_offset = 8,
1325 },
1326 [pbn_b0_bt_2_921600] = {
1327 .flags = FL_BASE0|FL_BASE_BARS,
1328 .num_ports = 2,
1329 .base_baud = 921600,
1330 .uart_offset = 8,
1331 },
1332 [pbn_b0_bt_4_921600] = {
1333 .flags = FL_BASE0|FL_BASE_BARS,
1334 .num_ports = 4,
1335 .base_baud = 921600,
1336 .uart_offset = 8,
1337 },
1338 [pbn_b0_bt_8_921600] = {
1339 .flags = FL_BASE0|FL_BASE_BARS,
1340 .num_ports = 8,
1341 .base_baud = 921600,
1342 .uart_offset = 8,
1343 },
1344
1345 [pbn_b1_1_115200] = {
1346 .flags = FL_BASE1,
1347 .num_ports = 1,
1348 .base_baud = 115200,
1349 .uart_offset = 8,
1350 },
1351 [pbn_b1_2_115200] = {
1352 .flags = FL_BASE1,
1353 .num_ports = 2,
1354 .base_baud = 115200,
1355 .uart_offset = 8,
1356 },
1357 [pbn_b1_4_115200] = {
1358 .flags = FL_BASE1,
1359 .num_ports = 4,
1360 .base_baud = 115200,
1361 .uart_offset = 8,
1362 },
1363 [pbn_b1_8_115200] = {
1364 .flags = FL_BASE1,
1365 .num_ports = 8,
1366 .base_baud = 115200,
1367 .uart_offset = 8,
1368 },
1369
1370 [pbn_b1_1_921600] = {
1371 .flags = FL_BASE1,
1372 .num_ports = 1,
1373 .base_baud = 921600,
1374 .uart_offset = 8,
1375 },
1376 [pbn_b1_2_921600] = {
1377 .flags = FL_BASE1,
1378 .num_ports = 2,
1379 .base_baud = 921600,
1380 .uart_offset = 8,
1381 },
1382 [pbn_b1_4_921600] = {
1383 .flags = FL_BASE1,
1384 .num_ports = 4,
1385 .base_baud = 921600,
1386 .uart_offset = 8,
1387 },
1388 [pbn_b1_8_921600] = {
1389 .flags = FL_BASE1,
1390 .num_ports = 8,
1391 .base_baud = 921600,
1392 .uart_offset = 8,
1393 },
1394 [pbn_b1_2_1250000] = {
1395 .flags = FL_BASE1,
1396 .num_ports = 2,
1397 .base_baud = 1250000,
1398 .uart_offset = 8,
1399 },
1400
1401 [pbn_b1_bt_1_115200] = {
1402 .flags = FL_BASE1|FL_BASE_BARS,
1403 .num_ports = 1,
1404 .base_baud = 115200,
1405 .uart_offset = 8,
1406 },
1407
1408 [pbn_b1_bt_2_921600] = {
1409 .flags = FL_BASE1|FL_BASE_BARS,
1410 .num_ports = 2,
1411 .base_baud = 921600,
1412 .uart_offset = 8,
1413 },
1414
1415 [pbn_b1_1_1382400] = {
1416 .flags = FL_BASE1,
1417 .num_ports = 1,
1418 .base_baud = 1382400,
1419 .uart_offset = 8,
1420 },
1421 [pbn_b1_2_1382400] = {
1422 .flags = FL_BASE1,
1423 .num_ports = 2,
1424 .base_baud = 1382400,
1425 .uart_offset = 8,
1426 },
1427 [pbn_b1_4_1382400] = {
1428 .flags = FL_BASE1,
1429 .num_ports = 4,
1430 .base_baud = 1382400,
1431 .uart_offset = 8,
1432 },
1433 [pbn_b1_8_1382400] = {
1434 .flags = FL_BASE1,
1435 .num_ports = 8,
1436 .base_baud = 1382400,
1437 .uart_offset = 8,
1438 },
1439
1440 [pbn_b2_1_115200] = {
1441 .flags = FL_BASE2,
1442 .num_ports = 1,
1443 .base_baud = 115200,
1444 .uart_offset = 8,
1445 },
1446 [pbn_b2_2_115200] = {
1447 .flags = FL_BASE2,
1448 .num_ports = 2,
1449 .base_baud = 115200,
1450 .uart_offset = 8,
1451 },
1452 [pbn_b2_4_115200] = {
1453 .flags = FL_BASE2,
1454 .num_ports = 4,
1455 .base_baud = 115200,
1456 .uart_offset = 8,
1457 },
1458 [pbn_b2_8_115200] = {
1459 .flags = FL_BASE2,
1460 .num_ports = 8,
1461 .base_baud = 115200,
1462 .uart_offset = 8,
1463 },
1464
1465 [pbn_b2_1_460800] = {
1466 .flags = FL_BASE2,
1467 .num_ports = 1,
1468 .base_baud = 460800,
1469 .uart_offset = 8,
1470 },
1471 [pbn_b2_4_460800] = {
1472 .flags = FL_BASE2,
1473 .num_ports = 4,
1474 .base_baud = 460800,
1475 .uart_offset = 8,
1476 },
1477 [pbn_b2_8_460800] = {
1478 .flags = FL_BASE2,
1479 .num_ports = 8,
1480 .base_baud = 460800,
1481 .uart_offset = 8,
1482 },
1483 [pbn_b2_16_460800] = {
1484 .flags = FL_BASE2,
1485 .num_ports = 16,
1486 .base_baud = 460800,
1487 .uart_offset = 8,
1488 },
1489
1490 [pbn_b2_1_921600] = {
1491 .flags = FL_BASE2,
1492 .num_ports = 1,
1493 .base_baud = 921600,
1494 .uart_offset = 8,
1495 },
1496 [pbn_b2_4_921600] = {
1497 .flags = FL_BASE2,
1498 .num_ports = 4,
1499 .base_baud = 921600,
1500 .uart_offset = 8,
1501 },
1502 [pbn_b2_8_921600] = {
1503 .flags = FL_BASE2,
1504 .num_ports = 8,
1505 .base_baud = 921600,
1506 .uart_offset = 8,
1507 },
1508
1509 [pbn_b2_bt_1_115200] = {
1510 .flags = FL_BASE2|FL_BASE_BARS,
1511 .num_ports = 1,
1512 .base_baud = 115200,
1513 .uart_offset = 8,
1514 },
1515 [pbn_b2_bt_2_115200] = {
1516 .flags = FL_BASE2|FL_BASE_BARS,
1517 .num_ports = 2,
1518 .base_baud = 115200,
1519 .uart_offset = 8,
1520 },
1521 [pbn_b2_bt_4_115200] = {
1522 .flags = FL_BASE2|FL_BASE_BARS,
1523 .num_ports = 4,
1524 .base_baud = 115200,
1525 .uart_offset = 8,
1526 },
1527
1528 [pbn_b2_bt_2_921600] = {
1529 .flags = FL_BASE2|FL_BASE_BARS,
1530 .num_ports = 2,
1531 .base_baud = 921600,
1532 .uart_offset = 8,
1533 },
1534 [pbn_b2_bt_4_921600] = {
1535 .flags = FL_BASE2|FL_BASE_BARS,
1536 .num_ports = 4,
1537 .base_baud = 921600,
1538 .uart_offset = 8,
1539 },
1540
1541 [pbn_b3_2_115200] = {
1542 .flags = FL_BASE3,
1543 .num_ports = 2,
1544 .base_baud = 115200,
1545 .uart_offset = 8,
1546 },
1547 [pbn_b3_4_115200] = {
1548 .flags = FL_BASE3,
1549 .num_ports = 4,
1550 .base_baud = 115200,
1551 .uart_offset = 8,
1552 },
1553 [pbn_b3_8_115200] = {
1554 .flags = FL_BASE3,
1555 .num_ports = 8,
1556 .base_baud = 115200,
1557 .uart_offset = 8,
1558 },
1559
1560 /*
1561 * Entries following this are board-specific.
1562 */
1563
1564 /*
1565 * Panacom - IOMEM
1566 */
1567 [pbn_panacom] = {
1568 .flags = FL_BASE2,
1569 .num_ports = 2,
1570 .base_baud = 921600,
1571 .uart_offset = 0x400,
1572 .reg_shift = 7,
1573 },
1574 [pbn_panacom2] = {
1575 .flags = FL_BASE2|FL_BASE_BARS,
1576 .num_ports = 2,
1577 .base_baud = 921600,
1578 .uart_offset = 0x400,
1579 .reg_shift = 7,
1580 },
1581 [pbn_panacom4] = {
1582 .flags = FL_BASE2|FL_BASE_BARS,
1583 .num_ports = 4,
1584 .base_baud = 921600,
1585 .uart_offset = 0x400,
1586 .reg_shift = 7,
1587 },
1588
1589 [pbn_exsys_4055] = {
1590 .flags = FL_BASE2,
1591 .num_ports = 4,
1592 .base_baud = 115200,
1593 .uart_offset = 8,
1594 },
1595
1596 /* I think this entry is broken - the first_offset looks wrong --rmk */
1597 [pbn_plx_romulus] = {
1598 .flags = FL_BASE2,
1599 .num_ports = 4,
1600 .base_baud = 921600,
1601 .uart_offset = 8 << 2,
1602 .reg_shift = 2,
1603 .first_offset = 0x03,
1604 },
1605
1606 /*
1607 * This board uses the size of PCI Base region 0 to
1608 * signal now many ports are available
1609 */
1610 [pbn_oxsemi] = {
1611 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1612 .num_ports = 32,
1613 .base_baud = 115200,
1614 .uart_offset = 8,
1615 },
1616
1617 /*
1618 * EKF addition for i960 Boards form EKF with serial port.
1619 * Max 256 ports.
1620 */
1621 [pbn_intel_i960] = {
1622 .flags = FL_BASE0,
1623 .num_ports = 32,
1624 .base_baud = 921600,
1625 .uart_offset = 8 << 2,
1626 .reg_shift = 2,
1627 .first_offset = 0x10000,
1628 },
1629 [pbn_sgi_ioc3] = {
1630 .flags = FL_BASE0|FL_NOIRQ,
1631 .num_ports = 1,
1632 .base_baud = 458333,
1633 .uart_offset = 8,
1634 .reg_shift = 0,
1635 .first_offset = 0x20178,
1636 },
1637
1638 /*
1639 * Computone - uses IOMEM.
1640 */
1641 [pbn_computone_4] = {
1642 .flags = FL_BASE0,
1643 .num_ports = 4,
1644 .base_baud = 921600,
1645 .uart_offset = 0x40,
1646 .reg_shift = 2,
1647 .first_offset = 0x200,
1648 },
1649 [pbn_computone_6] = {
1650 .flags = FL_BASE0,
1651 .num_ports = 6,
1652 .base_baud = 921600,
1653 .uart_offset = 0x40,
1654 .reg_shift = 2,
1655 .first_offset = 0x200,
1656 },
1657 [pbn_computone_8] = {
1658 .flags = FL_BASE0,
1659 .num_ports = 8,
1660 .base_baud = 921600,
1661 .uart_offset = 0x40,
1662 .reg_shift = 2,
1663 .first_offset = 0x200,
1664 },
1665 [pbn_sbsxrsio] = {
1666 .flags = FL_BASE0,
1667 .num_ports = 8,
1668 .base_baud = 460800,
1669 .uart_offset = 256,
1670 .reg_shift = 4,
1671 },
1672 /*
1673 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1674 * Only basic 16550A support.
1675 * XR17C15[24] are not tested, but they should work.
1676 */
1677 [pbn_exar_XR17C152] = {
1678 .flags = FL_BASE0,
1679 .num_ports = 2,
1680 .base_baud = 921600,
1681 .uart_offset = 0x200,
1682 },
1683 [pbn_exar_XR17C154] = {
1684 .flags = FL_BASE0,
1685 .num_ports = 4,
1686 .base_baud = 921600,
1687 .uart_offset = 0x200,
1688 },
1689 [pbn_exar_XR17C158] = {
1690 .flags = FL_BASE0,
1691 .num_ports = 8,
1692 .base_baud = 921600,
1693 .uart_offset = 0x200,
1694 },
1695 /*
1696 * PA Semi PWRficient PA6T-1682M on-chip UART
1697 */
1698 [pbn_pasemi_1682M] = {
1699 .flags = FL_BASE0,
1700 .num_ports = 1,
1701 .base_baud = 8333333,
1702 },
1703 };
1704
1705 static const struct pci_device_id softmodem_blacklist[] = {
1706 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
1707 };
1708
1709 /*
1710 * Given a complete unknown PCI device, try to use some heuristics to
1711 * guess what the configuration might be, based on the pitiful PCI
1712 * serial specs. Returns 0 on success, 1 on failure.
1713 */
1714 static int __devinit
1715 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1716 {
1717 const struct pci_device_id *blacklist;
1718 int num_iomem, num_port, first_port = -1, i;
1719
1720 /*
1721 * If it is not a communications device or the programming
1722 * interface is greater than 6, give up.
1723 *
1724 * (Should we try to make guesses for multiport serial devices
1725 * later?)
1726 */
1727 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1728 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1729 (dev->class & 0xff) > 6)
1730 return -ENODEV;
1731
1732 /*
1733 * Do not access blacklisted devices that are known not to
1734 * feature serial ports.
1735 */
1736 for (blacklist = softmodem_blacklist;
1737 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1738 blacklist++) {
1739 if (dev->vendor == blacklist->vendor &&
1740 dev->device == blacklist->device)
1741 return -ENODEV;
1742 }
1743
1744 num_iomem = num_port = 0;
1745 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1746 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1747 num_port++;
1748 if (first_port == -1)
1749 first_port = i;
1750 }
1751 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1752 num_iomem++;
1753 }
1754
1755 /*
1756 * If there is 1 or 0 iomem regions, and exactly one port,
1757 * use it. We guess the number of ports based on the IO
1758 * region size.
1759 */
1760 if (num_iomem <= 1 && num_port == 1) {
1761 board->flags = first_port;
1762 board->num_ports = pci_resource_len(dev, first_port) / 8;
1763 return 0;
1764 }
1765
1766 /*
1767 * Now guess if we've got a board which indexes by BARs.
1768 * Each IO BAR should be 8 bytes, and they should follow
1769 * consecutively.
1770 */
1771 first_port = -1;
1772 num_port = 0;
1773 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1774 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1775 pci_resource_len(dev, i) == 8 &&
1776 (first_port == -1 || (first_port + num_port) == i)) {
1777 num_port++;
1778 if (first_port == -1)
1779 first_port = i;
1780 }
1781 }
1782
1783 if (num_port > 1) {
1784 board->flags = first_port | FL_BASE_BARS;
1785 board->num_ports = num_port;
1786 return 0;
1787 }
1788
1789 return -ENODEV;
1790 }
1791
1792 static inline int
1793 serial_pci_matches(struct pciserial_board *board,
1794 struct pciserial_board *guessed)
1795 {
1796 return
1797 board->num_ports == guessed->num_ports &&
1798 board->base_baud == guessed->base_baud &&
1799 board->uart_offset == guessed->uart_offset &&
1800 board->reg_shift == guessed->reg_shift &&
1801 board->first_offset == guessed->first_offset;
1802 }
1803
1804 struct serial_private *
1805 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1806 {
1807 struct uart_port serial_port;
1808 struct serial_private *priv;
1809 struct pci_serial_quirk *quirk;
1810 int rc, nr_ports, i;
1811
1812 nr_ports = board->num_ports;
1813
1814 /*
1815 * Find an init and setup quirks.
1816 */
1817 quirk = find_quirk(dev);
1818
1819 /*
1820 * Run the new-style initialization function.
1821 * The initialization function returns:
1822 * <0 - error
1823 * 0 - use board->num_ports
1824 * >0 - number of ports
1825 */
1826 if (quirk->init) {
1827 rc = quirk->init(dev);
1828 if (rc < 0) {
1829 priv = ERR_PTR(rc);
1830 goto err_out;
1831 }
1832 if (rc)
1833 nr_ports = rc;
1834 }
1835
1836 priv = kzalloc(sizeof(struct serial_private) +
1837 sizeof(unsigned int) * nr_ports,
1838 GFP_KERNEL);
1839 if (!priv) {
1840 priv = ERR_PTR(-ENOMEM);
1841 goto err_deinit;
1842 }
1843
1844 priv->dev = dev;
1845 priv->quirk = quirk;
1846
1847 memset(&serial_port, 0, sizeof(struct uart_port));
1848 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1849 serial_port.uartclk = board->base_baud * 16;
1850 serial_port.irq = get_pci_irq(dev, board);
1851 serial_port.dev = &dev->dev;
1852
1853 for (i = 0; i < nr_ports; i++) {
1854 if (quirk->setup(priv, board, &serial_port, i))
1855 break;
1856
1857 #ifdef SERIAL_DEBUG_PCI
1858 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1859 serial_port.iobase, serial_port.irq, serial_port.iotype);
1860 #endif
1861
1862 priv->line[i] = serial8250_register_port(&serial_port);
1863 if (priv->line[i] < 0) {
1864 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1865 break;
1866 }
1867 }
1868 priv->nr = i;
1869 return priv;
1870
1871 err_deinit:
1872 if (quirk->exit)
1873 quirk->exit(dev);
1874 err_out:
1875 return priv;
1876 }
1877 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1878
1879 void pciserial_remove_ports(struct serial_private *priv)
1880 {
1881 struct pci_serial_quirk *quirk;
1882 int i;
1883
1884 for (i = 0; i < priv->nr; i++)
1885 serial8250_unregister_port(priv->line[i]);
1886
1887 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1888 if (priv->remapped_bar[i])
1889 iounmap(priv->remapped_bar[i]);
1890 priv->remapped_bar[i] = NULL;
1891 }
1892
1893 /*
1894 * Find the exit quirks.
1895 */
1896 quirk = find_quirk(priv->dev);
1897 if (quirk->exit)
1898 quirk->exit(priv->dev);
1899
1900 kfree(priv);
1901 }
1902 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1903
1904 void pciserial_suspend_ports(struct serial_private *priv)
1905 {
1906 int i;
1907
1908 for (i = 0; i < priv->nr; i++)
1909 if (priv->line[i] >= 0)
1910 serial8250_suspend_port(priv->line[i]);
1911 }
1912 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1913
1914 void pciserial_resume_ports(struct serial_private *priv)
1915 {
1916 int i;
1917
1918 /*
1919 * Ensure that the board is correctly configured.
1920 */
1921 if (priv->quirk->init)
1922 priv->quirk->init(priv->dev);
1923
1924 for (i = 0; i < priv->nr; i++)
1925 if (priv->line[i] >= 0)
1926 serial8250_resume_port(priv->line[i]);
1927 }
1928 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1929
1930 /*
1931 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1932 * to the arrangement of serial ports on a PCI card.
1933 */
1934 static int __devinit
1935 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1936 {
1937 struct serial_private *priv;
1938 struct pciserial_board *board, tmp;
1939 int rc;
1940
1941 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1942 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1943 ent->driver_data);
1944 return -EINVAL;
1945 }
1946
1947 board = &pci_boards[ent->driver_data];
1948
1949 rc = pci_enable_device(dev);
1950 if (rc)
1951 return rc;
1952
1953 if (ent->driver_data == pbn_default) {
1954 /*
1955 * Use a copy of the pci_board entry for this;
1956 * avoid changing entries in the table.
1957 */
1958 memcpy(&tmp, board, sizeof(struct pciserial_board));
1959 board = &tmp;
1960
1961 /*
1962 * We matched one of our class entries. Try to
1963 * determine the parameters of this board.
1964 */
1965 rc = serial_pci_guess_board(dev, board);
1966 if (rc)
1967 goto disable;
1968 } else {
1969 /*
1970 * We matched an explicit entry. If we are able to
1971 * detect this boards settings with our heuristic,
1972 * then we no longer need this entry.
1973 */
1974 memcpy(&tmp, &pci_boards[pbn_default],
1975 sizeof(struct pciserial_board));
1976 rc = serial_pci_guess_board(dev, &tmp);
1977 if (rc == 0 && serial_pci_matches(board, &tmp))
1978 moan_device("Redundant entry in serial pci_table.",
1979 dev);
1980 }
1981
1982 priv = pciserial_init_ports(dev, board);
1983 if (!IS_ERR(priv)) {
1984 pci_set_drvdata(dev, priv);
1985 return 0;
1986 }
1987
1988 rc = PTR_ERR(priv);
1989
1990 disable:
1991 pci_disable_device(dev);
1992 return rc;
1993 }
1994
1995 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1996 {
1997 struct serial_private *priv = pci_get_drvdata(dev);
1998
1999 pci_set_drvdata(dev, NULL);
2000
2001 pciserial_remove_ports(priv);
2002
2003 pci_disable_device(dev);
2004 }
2005
2006 #ifdef CONFIG_PM
2007 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2008 {
2009 struct serial_private *priv = pci_get_drvdata(dev);
2010
2011 if (priv)
2012 pciserial_suspend_ports(priv);
2013
2014 pci_save_state(dev);
2015 pci_set_power_state(dev, pci_choose_state(dev, state));
2016 return 0;
2017 }
2018
2019 static int pciserial_resume_one(struct pci_dev *dev)
2020 {
2021 int err;
2022 struct serial_private *priv = pci_get_drvdata(dev);
2023
2024 pci_set_power_state(dev, PCI_D0);
2025 pci_restore_state(dev);
2026
2027 if (priv) {
2028 /*
2029 * The device may have been disabled. Re-enable it.
2030 */
2031 err = pci_enable_device(dev);
2032 if (err)
2033 return err;
2034
2035 pciserial_resume_ports(priv);
2036 }
2037 return 0;
2038 }
2039 #endif
2040
2041 static struct pci_device_id serial_pci_tbl[] = {
2042 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2043 PCI_SUBVENDOR_ID_CONNECT_TECH,
2044 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2045 pbn_b1_8_1382400 },
2046 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2047 PCI_SUBVENDOR_ID_CONNECT_TECH,
2048 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2049 pbn_b1_4_1382400 },
2050 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2051 PCI_SUBVENDOR_ID_CONNECT_TECH,
2052 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2053 pbn_b1_2_1382400 },
2054 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2055 PCI_SUBVENDOR_ID_CONNECT_TECH,
2056 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2057 pbn_b1_8_1382400 },
2058 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2059 PCI_SUBVENDOR_ID_CONNECT_TECH,
2060 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2061 pbn_b1_4_1382400 },
2062 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2063 PCI_SUBVENDOR_ID_CONNECT_TECH,
2064 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2065 pbn_b1_2_1382400 },
2066 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2067 PCI_SUBVENDOR_ID_CONNECT_TECH,
2068 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2069 pbn_b1_8_921600 },
2070 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2071 PCI_SUBVENDOR_ID_CONNECT_TECH,
2072 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2073 pbn_b1_8_921600 },
2074 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2075 PCI_SUBVENDOR_ID_CONNECT_TECH,
2076 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2077 pbn_b1_4_921600 },
2078 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2079 PCI_SUBVENDOR_ID_CONNECT_TECH,
2080 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2081 pbn_b1_4_921600 },
2082 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2083 PCI_SUBVENDOR_ID_CONNECT_TECH,
2084 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2085 pbn_b1_2_921600 },
2086 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2087 PCI_SUBVENDOR_ID_CONNECT_TECH,
2088 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2089 pbn_b1_8_921600 },
2090 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2091 PCI_SUBVENDOR_ID_CONNECT_TECH,
2092 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2093 pbn_b1_8_921600 },
2094 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2095 PCI_SUBVENDOR_ID_CONNECT_TECH,
2096 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2097 pbn_b1_4_921600 },
2098 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2099 PCI_SUBVENDOR_ID_CONNECT_TECH,
2100 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2101 pbn_b1_2_1250000 },
2102 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2103 PCI_SUBVENDOR_ID_CONNECT_TECH,
2104 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2105 pbn_b0_2_1843200 },
2106 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2107 PCI_SUBVENDOR_ID_CONNECT_TECH,
2108 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2109 pbn_b0_4_1843200 },
2110 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2111 PCI_VENDOR_ID_AFAVLAB,
2112 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2113 pbn_b0_4_1152000 },
2114 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2115 PCI_SUBVENDOR_ID_CONNECT_TECH,
2116 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2117 pbn_b0_2_1843200_200 },
2118 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2119 PCI_SUBVENDOR_ID_CONNECT_TECH,
2120 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2121 pbn_b0_4_1843200_200 },
2122 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2123 PCI_SUBVENDOR_ID_CONNECT_TECH,
2124 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2125 pbn_b0_8_1843200_200 },
2126 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2127 PCI_SUBVENDOR_ID_CONNECT_TECH,
2128 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2129 pbn_b0_2_1843200_200 },
2130 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2131 PCI_SUBVENDOR_ID_CONNECT_TECH,
2132 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2133 pbn_b0_4_1843200_200 },
2134 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2135 PCI_SUBVENDOR_ID_CONNECT_TECH,
2136 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2137 pbn_b0_8_1843200_200 },
2138 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2139 PCI_SUBVENDOR_ID_CONNECT_TECH,
2140 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2141 pbn_b0_2_1843200_200 },
2142 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2143 PCI_SUBVENDOR_ID_CONNECT_TECH,
2144 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2145 pbn_b0_4_1843200_200 },
2146 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2147 PCI_SUBVENDOR_ID_CONNECT_TECH,
2148 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2149 pbn_b0_8_1843200_200 },
2150 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2151 PCI_SUBVENDOR_ID_CONNECT_TECH,
2152 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2153 pbn_b0_2_1843200_200 },
2154 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2155 PCI_SUBVENDOR_ID_CONNECT_TECH,
2156 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2157 pbn_b0_4_1843200_200 },
2158 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2159 PCI_SUBVENDOR_ID_CONNECT_TECH,
2160 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2161 pbn_b0_8_1843200_200 },
2162
2163 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2165 pbn_b2_bt_1_115200 },
2166 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2168 pbn_b2_bt_2_115200 },
2169 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2171 pbn_b2_bt_4_115200 },
2172 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2174 pbn_b2_bt_2_115200 },
2175 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2177 pbn_b2_bt_4_115200 },
2178 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2180 pbn_b2_8_115200 },
2181 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2183 pbn_b2_8_115200 },
2184
2185 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2187 pbn_b2_bt_2_115200 },
2188 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2190 pbn_b2_bt_2_921600 },
2191 /*
2192 * VScom SPCOM800, from sl@s.pl
2193 */
2194 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2196 pbn_b2_8_921600 },
2197 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2199 pbn_b2_4_921600 },
2200 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2201 PCI_SUBVENDOR_ID_KEYSPAN,
2202 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2203 pbn_panacom },
2204 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2206 pbn_panacom4 },
2207 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2209 pbn_panacom2 },
2210 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2211 PCI_VENDOR_ID_ESDGMBH,
2212 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2213 pbn_b2_4_115200 },
2214 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2215 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2216 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2217 pbn_b2_4_460800 },
2218 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2219 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2220 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2221 pbn_b2_8_460800 },
2222 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2223 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2224 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2225 pbn_b2_16_460800 },
2226 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2227 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2228 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2229 pbn_b2_16_460800 },
2230 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2231 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2232 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2233 pbn_b2_4_460800 },
2234 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2235 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2236 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2237 pbn_b2_8_460800 },
2238 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2239 PCI_SUBVENDOR_ID_EXSYS,
2240 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2241 pbn_exsys_4055 },
2242 /*
2243 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2244 * (Exoray@isys.ca)
2245 */
2246 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2247 0x10b5, 0x106a, 0, 0,
2248 pbn_plx_romulus },
2249 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2251 pbn_b1_4_115200 },
2252 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2254 pbn_b1_2_115200 },
2255 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2257 pbn_b1_8_115200 },
2258 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2260 pbn_b1_8_115200 },
2261 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2262 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2263 0, 0,
2264 pbn_b0_4_921600 },
2265 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2266 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2267 0, 0,
2268 pbn_b0_4_1152000 },
2269
2270 /*
2271 * The below card is a little controversial since it is the
2272 * subject of a PCI vendor/device ID clash. (See
2273 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2274 * For now just used the hex ID 0x950a.
2275 */
2276 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2278 pbn_b0_2_1130000 },
2279 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2281 pbn_b0_4_115200 },
2282 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2284 pbn_b0_bt_2_921600 },
2285
2286 /*
2287 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2288 * from skokodyn@yahoo.com
2289 */
2290 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2291 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2292 pbn_sbsxrsio },
2293 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2294 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2295 pbn_sbsxrsio },
2296 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2297 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2298 pbn_sbsxrsio },
2299 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2300 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2301 pbn_sbsxrsio },
2302
2303 /*
2304 * Digitan DS560-558, from jimd@esoft.com
2305 */
2306 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2308 pbn_b1_1_115200 },
2309
2310 /*
2311 * Titan Electronic cards
2312 * The 400L and 800L have a custom setup quirk.
2313 */
2314 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2316 pbn_b0_1_921600 },
2317 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2319 pbn_b0_2_921600 },
2320 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2322 pbn_b0_4_921600 },
2323 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2325 pbn_b0_4_921600 },
2326 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2328 pbn_b1_1_921600 },
2329 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2331 pbn_b1_bt_2_921600 },
2332 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2334 pbn_b0_bt_4_921600 },
2335 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2337 pbn_b0_bt_8_921600 },
2338
2339 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2341 pbn_b2_1_460800 },
2342 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2344 pbn_b2_1_460800 },
2345 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2347 pbn_b2_1_460800 },
2348 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2350 pbn_b2_bt_2_921600 },
2351 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2353 pbn_b2_bt_2_921600 },
2354 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2356 pbn_b2_bt_2_921600 },
2357 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2359 pbn_b2_bt_4_921600 },
2360 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2362 pbn_b2_bt_4_921600 },
2363 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2365 pbn_b2_bt_4_921600 },
2366 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2368 pbn_b0_1_921600 },
2369 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2371 pbn_b0_1_921600 },
2372 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2374 pbn_b0_1_921600 },
2375 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2377 pbn_b0_bt_2_921600 },
2378 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2380 pbn_b0_bt_2_921600 },
2381 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2383 pbn_b0_bt_2_921600 },
2384 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2386 pbn_b0_bt_4_921600 },
2387 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2389 pbn_b0_bt_4_921600 },
2390 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2392 pbn_b0_bt_4_921600 },
2393 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2395 pbn_b0_bt_8_921600 },
2396 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2398 pbn_b0_bt_8_921600 },
2399 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2401 pbn_b0_bt_8_921600 },
2402
2403 /*
2404 * Computone devices submitted by Doug McNash dmcnash@computone.com
2405 */
2406 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2407 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2408 0, 0, pbn_computone_4 },
2409 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2410 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2411 0, 0, pbn_computone_8 },
2412 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2413 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2414 0, 0, pbn_computone_6 },
2415
2416 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2418 pbn_oxsemi },
2419 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2420 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2421 pbn_b0_bt_1_921600 },
2422
2423 /*
2424 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2425 */
2426 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2428 pbn_b0_bt_8_115200 },
2429 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2431 pbn_b0_bt_8_115200 },
2432
2433 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2435 pbn_b0_bt_2_115200 },
2436 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2438 pbn_b0_bt_2_115200 },
2439 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2441 pbn_b0_bt_2_115200 },
2442 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2444 pbn_b0_bt_4_460800 },
2445 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2447 pbn_b0_bt_4_460800 },
2448 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2450 pbn_b0_bt_2_460800 },
2451 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2453 pbn_b0_bt_2_460800 },
2454 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2456 pbn_b0_bt_2_460800 },
2457 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2459 pbn_b0_bt_1_115200 },
2460 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2462 pbn_b0_bt_1_460800 },
2463
2464 /*
2465 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2466 * Cards are identified by their subsystem vendor IDs, which
2467 * (in hex) match the model number.
2468 *
2469 * Note that JC140x are RS422/485 cards which require ox950
2470 * ACR = 0x10, and as such are not currently fully supported.
2471 */
2472 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2473 0x1204, 0x0004, 0, 0,
2474 pbn_b0_4_921600 },
2475 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2476 0x1208, 0x0004, 0, 0,
2477 pbn_b0_4_921600 },
2478 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2479 0x1402, 0x0002, 0, 0,
2480 pbn_b0_2_921600 }, */
2481 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2482 0x1404, 0x0004, 0, 0,
2483 pbn_b0_4_921600 }, */
2484 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2485 0x1208, 0x0004, 0, 0,
2486 pbn_b0_4_921600 },
2487
2488 /*
2489 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2490 */
2491 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2493 pbn_b1_1_1382400 },
2494
2495 /*
2496 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2497 */
2498 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2500 pbn_b1_1_1382400 },
2501
2502 /*
2503 * RAStel 2 port modem, gerg@moreton.com.au
2504 */
2505 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2507 pbn_b2_bt_2_115200 },
2508
2509 /*
2510 * EKF addition for i960 Boards form EKF with serial port
2511 */
2512 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2513 0xE4BF, PCI_ANY_ID, 0, 0,
2514 pbn_intel_i960 },
2515
2516 /*
2517 * Xircom Cardbus/Ethernet combos
2518 */
2519 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2521 pbn_b0_1_115200 },
2522 /*
2523 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2524 */
2525 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2527 pbn_b0_1_115200 },
2528
2529 /*
2530 * Untested PCI modems, sent in from various folks...
2531 */
2532
2533 /*
2534 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2535 */
2536 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2537 0x1048, 0x1500, 0, 0,
2538 pbn_b1_1_115200 },
2539
2540 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2541 0xFF00, 0, 0, 0,
2542 pbn_sgi_ioc3 },
2543
2544 /*
2545 * HP Diva card
2546 */
2547 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2548 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2549 pbn_b1_1_115200 },
2550 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2552 pbn_b0_5_115200 },
2553 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2555 pbn_b2_1_115200 },
2556
2557 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2559 pbn_b3_2_115200 },
2560 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2562 pbn_b3_4_115200 },
2563 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2565 pbn_b3_8_115200 },
2566
2567 /*
2568 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2569 */
2570 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2571 PCI_ANY_ID, PCI_ANY_ID,
2572 0,
2573 0, pbn_exar_XR17C152 },
2574 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2575 PCI_ANY_ID, PCI_ANY_ID,
2576 0,
2577 0, pbn_exar_XR17C154 },
2578 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2579 PCI_ANY_ID, PCI_ANY_ID,
2580 0,
2581 0, pbn_exar_XR17C158 },
2582
2583 /*
2584 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2585 */
2586 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2588 pbn_b0_1_115200 },
2589 /*
2590 * ITE
2591 */
2592 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2593 PCI_ANY_ID, PCI_ANY_ID,
2594 0, 0,
2595 pbn_b1_bt_1_115200 },
2596
2597 /*
2598 * IntaShield IS-200
2599 */
2600 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2602 pbn_b2_2_115200 },
2603
2604 /*
2605 * Perle PCI-RAS cards
2606 */
2607 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2608 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2609 0, 0, pbn_b2_4_921600 },
2610 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2611 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2612 0, 0, pbn_b2_8_921600 },
2613
2614 /*
2615 * Mainpine series cards: Fairly standard layout but fools
2616 * parts of the autodetect in some cases and uses otherwise
2617 * unmatched communications subclasses in the PCI Express case
2618 */
2619
2620 { /* RockForceDUO */
2621 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2622 PCI_VENDOR_ID_MAINPINE, 0x0200,
2623 0, 0, pbn_b0_2_115200 },
2624 { /* RockForceQUATRO */
2625 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2626 PCI_VENDOR_ID_MAINPINE, 0x0300,
2627 0, 0, pbn_b0_4_115200 },
2628 { /* RockForceDUO+ */
2629 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2630 PCI_VENDOR_ID_MAINPINE, 0x0400,
2631 0, 0, pbn_b0_2_115200 },
2632 { /* RockForceQUATRO+ */
2633 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2634 PCI_VENDOR_ID_MAINPINE, 0x0500,
2635 0, 0, pbn_b0_4_115200 },
2636 { /* RockForce+ */
2637 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2638 PCI_VENDOR_ID_MAINPINE, 0x0600,
2639 0, 0, pbn_b0_2_115200 },
2640 { /* RockForce+ */
2641 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2642 PCI_VENDOR_ID_MAINPINE, 0x0700,
2643 0, 0, pbn_b0_4_115200 },
2644 { /* RockForceOCTO+ */
2645 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2646 PCI_VENDOR_ID_MAINPINE, 0x0800,
2647 0, 0, pbn_b0_8_115200 },
2648 { /* RockForceDUO+ */
2649 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2650 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2651 0, 0, pbn_b0_2_115200 },
2652 { /* RockForceQUARTRO+ */
2653 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2654 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2655 0, 0, pbn_b0_4_115200 },
2656 { /* RockForceOCTO+ */
2657 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2658 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2659 0, 0, pbn_b0_8_115200 },
2660 { /* RockForceD1 */
2661 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2662 PCI_VENDOR_ID_MAINPINE, 0x2000,
2663 0, 0, pbn_b0_1_115200 },
2664 { /* RockForceF1 */
2665 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2666 PCI_VENDOR_ID_MAINPINE, 0x2100,
2667 0, 0, pbn_b0_1_115200 },
2668 { /* RockForceD2 */
2669 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2670 PCI_VENDOR_ID_MAINPINE, 0x2200,
2671 0, 0, pbn_b0_2_115200 },
2672 { /* RockForceF2 */
2673 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2674 PCI_VENDOR_ID_MAINPINE, 0x2300,
2675 0, 0, pbn_b0_2_115200 },
2676 { /* RockForceD4 */
2677 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2678 PCI_VENDOR_ID_MAINPINE, 0x2400,
2679 0, 0, pbn_b0_4_115200 },
2680 { /* RockForceF4 */
2681 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2682 PCI_VENDOR_ID_MAINPINE, 0x2500,
2683 0, 0, pbn_b0_4_115200 },
2684 { /* RockForceD8 */
2685 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2686 PCI_VENDOR_ID_MAINPINE, 0x2600,
2687 0, 0, pbn_b0_8_115200 },
2688 { /* RockForceF8 */
2689 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2690 PCI_VENDOR_ID_MAINPINE, 0x2700,
2691 0, 0, pbn_b0_8_115200 },
2692 { /* IQ Express D1 */
2693 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2694 PCI_VENDOR_ID_MAINPINE, 0x3000,
2695 0, 0, pbn_b0_1_115200 },
2696 { /* IQ Express F1 */
2697 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2698 PCI_VENDOR_ID_MAINPINE, 0x3100,
2699 0, 0, pbn_b0_1_115200 },
2700 { /* IQ Express D2 */
2701 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2702 PCI_VENDOR_ID_MAINPINE, 0x3200,
2703 0, 0, pbn_b0_2_115200 },
2704 { /* IQ Express F2 */
2705 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2706 PCI_VENDOR_ID_MAINPINE, 0x3300,
2707 0, 0, pbn_b0_2_115200 },
2708 { /* IQ Express D4 */
2709 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2710 PCI_VENDOR_ID_MAINPINE, 0x3400,
2711 0, 0, pbn_b0_4_115200 },
2712 { /* IQ Express F4 */
2713 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2714 PCI_VENDOR_ID_MAINPINE, 0x3500,
2715 0, 0, pbn_b0_4_115200 },
2716 { /* IQ Express D8 */
2717 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2718 PCI_VENDOR_ID_MAINPINE, 0x3C00,
2719 0, 0, pbn_b0_8_115200 },
2720 { /* IQ Express F8 */
2721 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2722 PCI_VENDOR_ID_MAINPINE, 0x3D00,
2723 0, 0, pbn_b0_8_115200 },
2724
2725
2726 /*
2727 * PA Semi PA6T-1682M on-chip UART
2728 */
2729 { PCI_VENDOR_ID_PASEMI, 0xa004,
2730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2731 pbn_pasemi_1682M },
2732
2733 /*
2734 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2735 */
2736 { PCI_VENDOR_ID_ADDIDATA,
2737 PCI_DEVICE_ID_ADDIDATA_APCI7500,
2738 PCI_ANY_ID,
2739 PCI_ANY_ID,
2740 0,
2741 0,
2742 pbn_b0_4_115200 },
2743
2744 { PCI_VENDOR_ID_ADDIDATA,
2745 PCI_DEVICE_ID_ADDIDATA_APCI7420,
2746 PCI_ANY_ID,
2747 PCI_ANY_ID,
2748 0,
2749 0,
2750 pbn_b0_2_115200 },
2751
2752 { PCI_VENDOR_ID_ADDIDATA,
2753 PCI_DEVICE_ID_ADDIDATA_APCI7300,
2754 PCI_ANY_ID,
2755 PCI_ANY_ID,
2756 0,
2757 0,
2758 pbn_b0_1_115200 },
2759
2760 { PCI_VENDOR_ID_ADDIDATA_OLD,
2761 PCI_DEVICE_ID_ADDIDATA_APCI7800,
2762 PCI_ANY_ID,
2763 PCI_ANY_ID,
2764 0,
2765 0,
2766 pbn_b1_8_115200 },
2767
2768 { PCI_VENDOR_ID_ADDIDATA,
2769 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
2770 PCI_ANY_ID,
2771 PCI_ANY_ID,
2772 0,
2773 0,
2774 pbn_b0_4_115200 },
2775
2776 { PCI_VENDOR_ID_ADDIDATA,
2777 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
2778 PCI_ANY_ID,
2779 PCI_ANY_ID,
2780 0,
2781 0,
2782 pbn_b0_2_115200 },
2783
2784 { PCI_VENDOR_ID_ADDIDATA,
2785 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
2786 PCI_ANY_ID,
2787 PCI_ANY_ID,
2788 0,
2789 0,
2790 pbn_b0_1_115200 },
2791
2792 { PCI_VENDOR_ID_ADDIDATA,
2793 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
2794 PCI_ANY_ID,
2795 PCI_ANY_ID,
2796 0,
2797 0,
2798 pbn_b0_4_115200 },
2799
2800 { PCI_VENDOR_ID_ADDIDATA,
2801 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
2802 PCI_ANY_ID,
2803 PCI_ANY_ID,
2804 0,
2805 0,
2806 pbn_b0_2_115200 },
2807
2808 { PCI_VENDOR_ID_ADDIDATA,
2809 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
2810 PCI_ANY_ID,
2811 PCI_ANY_ID,
2812 0,
2813 0,
2814 pbn_b0_1_115200 },
2815
2816 { PCI_VENDOR_ID_ADDIDATA,
2817 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
2818 PCI_ANY_ID,
2819 PCI_ANY_ID,
2820 0,
2821 0,
2822 pbn_b0_8_115200 },
2823
2824 /*
2825 * These entries match devices with class COMMUNICATION_SERIAL,
2826 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2827 */
2828 { PCI_ANY_ID, PCI_ANY_ID,
2829 PCI_ANY_ID, PCI_ANY_ID,
2830 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2831 0xffff00, pbn_default },
2832 { PCI_ANY_ID, PCI_ANY_ID,
2833 PCI_ANY_ID, PCI_ANY_ID,
2834 PCI_CLASS_COMMUNICATION_MODEM << 8,
2835 0xffff00, pbn_default },
2836 { PCI_ANY_ID, PCI_ANY_ID,
2837 PCI_ANY_ID, PCI_ANY_ID,
2838 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2839 0xffff00, pbn_default },
2840 { 0, }
2841 };
2842
2843 static struct pci_driver serial_pci_driver = {
2844 .name = "serial",
2845 .probe = pciserial_init_one,
2846 .remove = __devexit_p(pciserial_remove_one),
2847 #ifdef CONFIG_PM
2848 .suspend = pciserial_suspend_one,
2849 .resume = pciserial_resume_one,
2850 #endif
2851 .id_table = serial_pci_tbl,
2852 };
2853
2854 static int __init serial8250_pci_init(void)
2855 {
2856 return pci_register_driver(&serial_pci_driver);
2857 }
2858
2859 static void __exit serial8250_pci_exit(void)
2860 {
2861 pci_unregister_driver(&serial_pci_driver);
2862 }
2863
2864 module_init(serial8250_pci_init);
2865 module_exit(serial8250_pci_exit);
2866
2867 MODULE_LICENSE("GPL");
2868 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2869 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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