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1 /*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
26 *
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
33 */
34 #include <linux/config.h>
35
36 #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #define SUPPORT_SYSRQ
38 #endif
39
40 #include <linux/module.h>
41 #include <linux/ioport.h>
42 #include <linux/init.h>
43 #include <linux/console.h>
44 #include <linux/sysrq.h>
45 #include <linux/device.h>
46 #include <linux/tty.h>
47 #include <linux/tty_flip.h>
48 #include <linux/serial_core.h>
49 #include <linux/serial.h>
50
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <asm/hardware.h>
54 #include <asm/hardware/amba.h>
55 #include <asm/hardware/amba_serial.h>
56
57 #define UART_NR 2
58
59 #define SERIAL_AMBA_MAJOR 204
60 #define SERIAL_AMBA_MINOR 16
61 #define SERIAL_AMBA_NR UART_NR
62
63 #define AMBA_ISR_PASS_LIMIT 256
64
65 /*
66 * Access macros for the AMBA UARTs
67 */
68 #define UART_GET_INT_STATUS(p) readb((p)->membase + UART010_IIR)
69 #define UART_PUT_ICR(p, c) writel((c), (p)->membase + UART010_ICR)
70 #define UART_GET_FR(p) readb((p)->membase + UART01x_FR)
71 #define UART_GET_CHAR(p) readb((p)->membase + UART01x_DR)
72 #define UART_PUT_CHAR(p, c) writel((c), (p)->membase + UART01x_DR)
73 #define UART_GET_RSR(p) readb((p)->membase + UART01x_RSR)
74 #define UART_GET_CR(p) readb((p)->membase + UART010_CR)
75 #define UART_PUT_CR(p,c) writel((c), (p)->membase + UART010_CR)
76 #define UART_GET_LCRL(p) readb((p)->membase + UART010_LCRL)
77 #define UART_PUT_LCRL(p,c) writel((c), (p)->membase + UART010_LCRL)
78 #define UART_GET_LCRM(p) readb((p)->membase + UART010_LCRM)
79 #define UART_PUT_LCRM(p,c) writel((c), (p)->membase + UART010_LCRM)
80 #define UART_GET_LCRH(p) readb((p)->membase + UART010_LCRH)
81 #define UART_PUT_LCRH(p,c) writel((c), (p)->membase + UART010_LCRH)
82 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
83 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
84 #define UART_TX_EMPTY(p) ((UART_GET_FR(p) & UART01x_FR_TMSK) == 0)
85
86 #define UART_DUMMY_RSR_RX /*256*/0
87 #define UART_PORT_SIZE 64
88
89 /*
90 * On the Integrator platform, the port RTS and DTR are provided by
91 * bits in the following SC_CTRLS register bits:
92 * RTS DTR
93 * UART0 7 6
94 * UART1 5 4
95 */
96 #define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
97 #define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
98
99 /*
100 * We wrap our port structure around the generic uart_port.
101 */
102 struct uart_amba_port {
103 struct uart_port port;
104 unsigned int dtr_mask;
105 unsigned int rts_mask;
106 unsigned int old_status;
107 };
108
109 static void pl010_stop_tx(struct uart_port *port)
110 {
111 unsigned int cr;
112
113 cr = UART_GET_CR(port);
114 cr &= ~UART010_CR_TIE;
115 UART_PUT_CR(port, cr);
116 }
117
118 static void pl010_start_tx(struct uart_port *port)
119 {
120 unsigned int cr;
121
122 cr = UART_GET_CR(port);
123 cr |= UART010_CR_TIE;
124 UART_PUT_CR(port, cr);
125 }
126
127 static void pl010_stop_rx(struct uart_port *port)
128 {
129 unsigned int cr;
130
131 cr = UART_GET_CR(port);
132 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
133 UART_PUT_CR(port, cr);
134 }
135
136 static void pl010_enable_ms(struct uart_port *port)
137 {
138 unsigned int cr;
139
140 cr = UART_GET_CR(port);
141 cr |= UART010_CR_MSIE;
142 UART_PUT_CR(port, cr);
143 }
144
145 static void
146 #ifdef SUPPORT_SYSRQ
147 pl010_rx_chars(struct uart_port *port, struct pt_regs *regs)
148 #else
149 pl010_rx_chars(struct uart_port *port)
150 #endif
151 {
152 struct tty_struct *tty = port->info->tty;
153 unsigned int status, ch, flag, rsr, max_count = 256;
154
155 status = UART_GET_FR(port);
156 while (UART_RX_DATA(status) && max_count--) {
157 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
158 if (tty->low_latency)
159 tty_flip_buffer_push(tty);
160 /*
161 * If this failed then we will throw away the
162 * bytes but must do so to clear interrupts.
163 */
164 }
165
166 ch = UART_GET_CHAR(port);
167 flag = TTY_NORMAL;
168
169 port->icount.rx++;
170
171 /*
172 * Note that the error handling code is
173 * out of the main execution path
174 */
175 rsr = UART_GET_RSR(port) | UART_DUMMY_RSR_RX;
176 if (unlikely(rsr & UART01x_RSR_ANY)) {
177 if (rsr & UART01x_RSR_BE) {
178 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
179 port->icount.brk++;
180 if (uart_handle_break(port))
181 goto ignore_char;
182 } else if (rsr & UART01x_RSR_PE)
183 port->icount.parity++;
184 else if (rsr & UART01x_RSR_FE)
185 port->icount.frame++;
186 if (rsr & UART01x_RSR_OE)
187 port->icount.overrun++;
188
189 rsr &= port->read_status_mask;
190
191 if (rsr & UART01x_RSR_BE)
192 flag = TTY_BREAK;
193 else if (rsr & UART01x_RSR_PE)
194 flag = TTY_PARITY;
195 else if (rsr & UART01x_RSR_FE)
196 flag = TTY_FRAME;
197 }
198
199 if (uart_handle_sysrq_char(port, ch, regs))
200 goto ignore_char;
201
202 uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag);
203
204 ignore_char:
205 status = UART_GET_FR(port);
206 }
207 tty_flip_buffer_push(tty);
208 return;
209 }
210
211 static void pl010_tx_chars(struct uart_port *port)
212 {
213 struct circ_buf *xmit = &port->info->xmit;
214 int count;
215
216 if (port->x_char) {
217 UART_PUT_CHAR(port, port->x_char);
218 port->icount.tx++;
219 port->x_char = 0;
220 return;
221 }
222 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
223 pl010_stop_tx(port);
224 return;
225 }
226
227 count = port->fifosize >> 1;
228 do {
229 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
230 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
231 port->icount.tx++;
232 if (uart_circ_empty(xmit))
233 break;
234 } while (--count > 0);
235
236 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
237 uart_write_wakeup(port);
238
239 if (uart_circ_empty(xmit))
240 pl010_stop_tx(port);
241 }
242
243 static void pl010_modem_status(struct uart_port *port)
244 {
245 struct uart_amba_port *uap = (struct uart_amba_port *)port;
246 unsigned int status, delta;
247
248 UART_PUT_ICR(&uap->port, 0);
249
250 status = UART_GET_FR(&uap->port) & UART01x_FR_MODEM_ANY;
251
252 delta = status ^ uap->old_status;
253 uap->old_status = status;
254
255 if (!delta)
256 return;
257
258 if (delta & UART01x_FR_DCD)
259 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
260
261 if (delta & UART01x_FR_DSR)
262 uap->port.icount.dsr++;
263
264 if (delta & UART01x_FR_CTS)
265 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
266
267 wake_up_interruptible(&uap->port.info->delta_msr_wait);
268 }
269
270 static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
271 {
272 struct uart_port *port = dev_id;
273 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
274 int handled = 0;
275
276 spin_lock(&port->lock);
277
278 status = UART_GET_INT_STATUS(port);
279 if (status) {
280 do {
281 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
282 #ifdef SUPPORT_SYSRQ
283 pl010_rx_chars(port, regs);
284 #else
285 pl010_rx_chars(port);
286 #endif
287 if (status & UART010_IIR_MIS)
288 pl010_modem_status(port);
289 if (status & UART010_IIR_TIS)
290 pl010_tx_chars(port);
291
292 if (pass_counter-- == 0)
293 break;
294
295 status = UART_GET_INT_STATUS(port);
296 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
297 UART010_IIR_TIS));
298 handled = 1;
299 }
300
301 spin_unlock(&port->lock);
302
303 return IRQ_RETVAL(handled);
304 }
305
306 static unsigned int pl010_tx_empty(struct uart_port *port)
307 {
308 return UART_GET_FR(port) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
309 }
310
311 static unsigned int pl010_get_mctrl(struct uart_port *port)
312 {
313 unsigned int result = 0;
314 unsigned int status;
315
316 status = UART_GET_FR(port);
317 if (status & UART01x_FR_DCD)
318 result |= TIOCM_CAR;
319 if (status & UART01x_FR_DSR)
320 result |= TIOCM_DSR;
321 if (status & UART01x_FR_CTS)
322 result |= TIOCM_CTS;
323
324 return result;
325 }
326
327 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
328 {
329 struct uart_amba_port *uap = (struct uart_amba_port *)port;
330 unsigned int ctrls = 0, ctrlc = 0;
331
332 if (mctrl & TIOCM_RTS)
333 ctrlc |= uap->rts_mask;
334 else
335 ctrls |= uap->rts_mask;
336
337 if (mctrl & TIOCM_DTR)
338 ctrlc |= uap->dtr_mask;
339 else
340 ctrls |= uap->dtr_mask;
341
342 __raw_writel(ctrls, SC_CTRLS);
343 __raw_writel(ctrlc, SC_CTRLC);
344 }
345
346 static void pl010_break_ctl(struct uart_port *port, int break_state)
347 {
348 unsigned long flags;
349 unsigned int lcr_h;
350
351 spin_lock_irqsave(&port->lock, flags);
352 lcr_h = UART_GET_LCRH(port);
353 if (break_state == -1)
354 lcr_h |= UART01x_LCRH_BRK;
355 else
356 lcr_h &= ~UART01x_LCRH_BRK;
357 UART_PUT_LCRH(port, lcr_h);
358 spin_unlock_irqrestore(&port->lock, flags);
359 }
360
361 static int pl010_startup(struct uart_port *port)
362 {
363 struct uart_amba_port *uap = (struct uart_amba_port *)port;
364 int retval;
365
366 /*
367 * Allocate the IRQ
368 */
369 retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", port);
370 if (retval)
371 return retval;
372
373 /*
374 * initialise the old status of the modem signals
375 */
376 uap->old_status = UART_GET_FR(port) & UART01x_FR_MODEM_ANY;
377
378 /*
379 * Finally, enable interrupts
380 */
381 UART_PUT_CR(port, UART01x_CR_UARTEN | UART010_CR_RIE |
382 UART010_CR_RTIE);
383
384 return 0;
385 }
386
387 static void pl010_shutdown(struct uart_port *port)
388 {
389 /*
390 * Free the interrupt
391 */
392 free_irq(port->irq, port);
393
394 /*
395 * disable all interrupts, disable the port
396 */
397 UART_PUT_CR(port, 0);
398
399 /* disable break condition and fifos */
400 UART_PUT_LCRH(port, UART_GET_LCRH(port) &
401 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN));
402 }
403
404 static void
405 pl010_set_termios(struct uart_port *port, struct termios *termios,
406 struct termios *old)
407 {
408 unsigned int lcr_h, old_cr;
409 unsigned long flags;
410 unsigned int baud, quot;
411
412 /*
413 * Ask the core to calculate the divisor for us.
414 */
415 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
416 quot = uart_get_divisor(port, baud);
417
418 switch (termios->c_cflag & CSIZE) {
419 case CS5:
420 lcr_h = UART01x_LCRH_WLEN_5;
421 break;
422 case CS6:
423 lcr_h = UART01x_LCRH_WLEN_6;
424 break;
425 case CS7:
426 lcr_h = UART01x_LCRH_WLEN_7;
427 break;
428 default: // CS8
429 lcr_h = UART01x_LCRH_WLEN_8;
430 break;
431 }
432 if (termios->c_cflag & CSTOPB)
433 lcr_h |= UART01x_LCRH_STP2;
434 if (termios->c_cflag & PARENB) {
435 lcr_h |= UART01x_LCRH_PEN;
436 if (!(termios->c_cflag & PARODD))
437 lcr_h |= UART01x_LCRH_EPS;
438 }
439 if (port->fifosize > 1)
440 lcr_h |= UART01x_LCRH_FEN;
441
442 spin_lock_irqsave(&port->lock, flags);
443
444 /*
445 * Update the per-port timeout.
446 */
447 uart_update_timeout(port, termios->c_cflag, baud);
448
449 port->read_status_mask = UART01x_RSR_OE;
450 if (termios->c_iflag & INPCK)
451 port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
452 if (termios->c_iflag & (BRKINT | PARMRK))
453 port->read_status_mask |= UART01x_RSR_BE;
454
455 /*
456 * Characters to ignore
457 */
458 port->ignore_status_mask = 0;
459 if (termios->c_iflag & IGNPAR)
460 port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
461 if (termios->c_iflag & IGNBRK) {
462 port->ignore_status_mask |= UART01x_RSR_BE;
463 /*
464 * If we're ignoring parity and break indicators,
465 * ignore overruns too (for real raw support).
466 */
467 if (termios->c_iflag & IGNPAR)
468 port->ignore_status_mask |= UART01x_RSR_OE;
469 }
470
471 /*
472 * Ignore all characters if CREAD is not set.
473 */
474 if ((termios->c_cflag & CREAD) == 0)
475 port->ignore_status_mask |= UART_DUMMY_RSR_RX;
476
477 /* first, disable everything */
478 old_cr = UART_GET_CR(port) & ~UART010_CR_MSIE;
479
480 if (UART_ENABLE_MS(port, termios->c_cflag))
481 old_cr |= UART010_CR_MSIE;
482
483 UART_PUT_CR(port, 0);
484
485 /* Set baud rate */
486 quot -= 1;
487 UART_PUT_LCRM(port, ((quot & 0xf00) >> 8));
488 UART_PUT_LCRL(port, (quot & 0xff));
489
490 /*
491 * ----------v----------v----------v----------v-----
492 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
493 * ----------^----------^----------^----------^-----
494 */
495 UART_PUT_LCRH(port, lcr_h);
496 UART_PUT_CR(port, old_cr);
497
498 spin_unlock_irqrestore(&port->lock, flags);
499 }
500
501 static const char *pl010_type(struct uart_port *port)
502 {
503 return port->type == PORT_AMBA ? "AMBA" : NULL;
504 }
505
506 /*
507 * Release the memory region(s) being used by 'port'
508 */
509 static void pl010_release_port(struct uart_port *port)
510 {
511 release_mem_region(port->mapbase, UART_PORT_SIZE);
512 }
513
514 /*
515 * Request the memory region(s) being used by 'port'
516 */
517 static int pl010_request_port(struct uart_port *port)
518 {
519 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
520 != NULL ? 0 : -EBUSY;
521 }
522
523 /*
524 * Configure/autoconfigure the port.
525 */
526 static void pl010_config_port(struct uart_port *port, int flags)
527 {
528 if (flags & UART_CONFIG_TYPE) {
529 port->type = PORT_AMBA;
530 pl010_request_port(port);
531 }
532 }
533
534 /*
535 * verify the new serial_struct (for TIOCSSERIAL).
536 */
537 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
538 {
539 int ret = 0;
540 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
541 ret = -EINVAL;
542 if (ser->irq < 0 || ser->irq >= NR_IRQS)
543 ret = -EINVAL;
544 if (ser->baud_base < 9600)
545 ret = -EINVAL;
546 return ret;
547 }
548
549 static struct uart_ops amba_pl010_pops = {
550 .tx_empty = pl010_tx_empty,
551 .set_mctrl = pl010_set_mctrl,
552 .get_mctrl = pl010_get_mctrl,
553 .stop_tx = pl010_stop_tx,
554 .start_tx = pl010_start_tx,
555 .stop_rx = pl010_stop_rx,
556 .enable_ms = pl010_enable_ms,
557 .break_ctl = pl010_break_ctl,
558 .startup = pl010_startup,
559 .shutdown = pl010_shutdown,
560 .set_termios = pl010_set_termios,
561 .type = pl010_type,
562 .release_port = pl010_release_port,
563 .request_port = pl010_request_port,
564 .config_port = pl010_config_port,
565 .verify_port = pl010_verify_port,
566 };
567
568 static struct uart_amba_port amba_ports[UART_NR] = {
569 {
570 .port = {
571 .membase = (void *)IO_ADDRESS(INTEGRATOR_UART0_BASE),
572 .mapbase = INTEGRATOR_UART0_BASE,
573 .iotype = SERIAL_IO_MEM,
574 .irq = IRQ_UARTINT0,
575 .uartclk = 14745600,
576 .fifosize = 16,
577 .ops = &amba_pl010_pops,
578 .flags = ASYNC_BOOT_AUTOCONF,
579 .line = 0,
580 },
581 .dtr_mask = 1 << 5,
582 .rts_mask = 1 << 4,
583 },
584 {
585 .port = {
586 .membase = (void *)IO_ADDRESS(INTEGRATOR_UART1_BASE),
587 .mapbase = INTEGRATOR_UART1_BASE,
588 .iotype = SERIAL_IO_MEM,
589 .irq = IRQ_UARTINT1,
590 .uartclk = 14745600,
591 .fifosize = 16,
592 .ops = &amba_pl010_pops,
593 .flags = ASYNC_BOOT_AUTOCONF,
594 .line = 1,
595 },
596 .dtr_mask = 1 << 7,
597 .rts_mask = 1 << 6,
598 }
599 };
600
601 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
602
603 static void
604 pl010_console_write(struct console *co, const char *s, unsigned int count)
605 {
606 struct uart_port *port = &amba_ports[co->index].port;
607 unsigned int status, old_cr;
608 int i;
609
610 /*
611 * First save the CR then disable the interrupts
612 */
613 old_cr = UART_GET_CR(port);
614 UART_PUT_CR(port, UART01x_CR_UARTEN);
615
616 /*
617 * Now, do each character
618 */
619 for (i = 0; i < count; i++) {
620 do {
621 status = UART_GET_FR(port);
622 } while (!UART_TX_READY(status));
623 UART_PUT_CHAR(port, s[i]);
624 if (s[i] == '\n') {
625 do {
626 status = UART_GET_FR(port);
627 } while (!UART_TX_READY(status));
628 UART_PUT_CHAR(port, '\r');
629 }
630 }
631
632 /*
633 * Finally, wait for transmitter to become empty
634 * and restore the TCR
635 */
636 do {
637 status = UART_GET_FR(port);
638 } while (status & UART01x_FR_BUSY);
639 UART_PUT_CR(port, old_cr);
640 }
641
642 static void __init
643 pl010_console_get_options(struct uart_port *port, int *baud,
644 int *parity, int *bits)
645 {
646 if (UART_GET_CR(port) & UART01x_CR_UARTEN) {
647 unsigned int lcr_h, quot;
648 lcr_h = UART_GET_LCRH(port);
649
650 *parity = 'n';
651 if (lcr_h & UART01x_LCRH_PEN) {
652 if (lcr_h & UART01x_LCRH_EPS)
653 *parity = 'e';
654 else
655 *parity = 'o';
656 }
657
658 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
659 *bits = 7;
660 else
661 *bits = 8;
662
663 quot = UART_GET_LCRL(port) | UART_GET_LCRM(port) << 8;
664 *baud = port->uartclk / (16 * (quot + 1));
665 }
666 }
667
668 static int __init pl010_console_setup(struct console *co, char *options)
669 {
670 struct uart_port *port;
671 int baud = 38400;
672 int bits = 8;
673 int parity = 'n';
674 int flow = 'n';
675
676 /*
677 * Check whether an invalid uart number has been specified, and
678 * if so, search for the first available port that does have
679 * console support.
680 */
681 if (co->index >= UART_NR)
682 co->index = 0;
683 port = &amba_ports[co->index].port;
684
685 if (options)
686 uart_parse_options(options, &baud, &parity, &bits, &flow);
687 else
688 pl010_console_get_options(port, &baud, &parity, &bits);
689
690 return uart_set_options(port, co, baud, parity, bits, flow);
691 }
692
693 static struct uart_driver amba_reg;
694 static struct console amba_console = {
695 .name = "ttyAM",
696 .write = pl010_console_write,
697 .device = uart_console_device,
698 .setup = pl010_console_setup,
699 .flags = CON_PRINTBUFFER,
700 .index = -1,
701 .data = &amba_reg,
702 };
703
704 static int __init amba_console_init(void)
705 {
706 /*
707 * All port initializations are done statically
708 */
709 register_console(&amba_console);
710 return 0;
711 }
712 console_initcall(amba_console_init);
713
714 static int __init amba_late_console_init(void)
715 {
716 if (!(amba_console.flags & CON_ENABLED))
717 register_console(&amba_console);
718 return 0;
719 }
720 late_initcall(amba_late_console_init);
721
722 #define AMBA_CONSOLE &amba_console
723 #else
724 #define AMBA_CONSOLE NULL
725 #endif
726
727 static struct uart_driver amba_reg = {
728 .owner = THIS_MODULE,
729 .driver_name = "ttyAM",
730 .dev_name = "ttyAM",
731 .major = SERIAL_AMBA_MAJOR,
732 .minor = SERIAL_AMBA_MINOR,
733 .nr = UART_NR,
734 .cons = AMBA_CONSOLE,
735 };
736
737 static int pl010_probe(struct amba_device *dev, void *id)
738 {
739 int i;
740
741 for (i = 0; i < UART_NR; i++) {
742 if (amba_ports[i].port.mapbase != dev->res.start)
743 continue;
744
745 amba_ports[i].port.dev = &dev->dev;
746 uart_add_one_port(&amba_reg, &amba_ports[i].port);
747 amba_set_drvdata(dev, &amba_ports[i]);
748 break;
749 }
750
751 return 0;
752 }
753
754 static int pl010_remove(struct amba_device *dev)
755 {
756 struct uart_amba_port *uap = amba_get_drvdata(dev);
757
758 if (uap)
759 uart_remove_one_port(&amba_reg, &uap->port);
760
761 amba_set_drvdata(dev, NULL);
762
763 return 0;
764 }
765
766 static int pl010_suspend(struct amba_device *dev, pm_message_t state)
767 {
768 struct uart_amba_port *uap = amba_get_drvdata(dev);
769
770 if (uap)
771 uart_suspend_port(&amba_reg, &uap->port);
772
773 return 0;
774 }
775
776 static int pl010_resume(struct amba_device *dev)
777 {
778 struct uart_amba_port *uap = amba_get_drvdata(dev);
779
780 if (uap)
781 uart_resume_port(&amba_reg, &uap->port);
782
783 return 0;
784 }
785
786 static struct amba_id pl010_ids[] __initdata = {
787 {
788 .id = 0x00041010,
789 .mask = 0x000fffff,
790 },
791 { 0, 0 },
792 };
793
794 static struct amba_driver pl010_driver = {
795 .drv = {
796 .name = "uart-pl010",
797 },
798 .id_table = pl010_ids,
799 .probe = pl010_probe,
800 .remove = pl010_remove,
801 .suspend = pl010_suspend,
802 .resume = pl010_resume,
803 };
804
805 static int __init pl010_init(void)
806 {
807 int ret;
808
809 printk(KERN_INFO "Serial: AMBA driver $Revision: 1.41 $\n");
810
811 ret = uart_register_driver(&amba_reg);
812 if (ret == 0) {
813 ret = amba_driver_register(&pl010_driver);
814 if (ret)
815 uart_unregister_driver(&amba_reg);
816 }
817 return ret;
818 }
819
820 static void __exit pl010_exit(void)
821 {
822 amba_driver_unregister(&pl010_driver);
823 uart_unregister_driver(&amba_reg);
824 }
825
826 module_init(pl010_init);
827 module_exit(pl010_exit);
828
829 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
830 MODULE_DESCRIPTION("ARM AMBA serial port driver $Revision: 1.41 $");
831 MODULE_LICENSE("GPL");