]>
git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/serial/amba-pl011.c
2 * linux/drivers/char/amba.c
4 * Driver for AMBA serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * This is a generic driver for ARM AMBA-type serial ports. They
26 * have a lot of 16550-like features, but are not register compatible.
27 * Note that although they do have CTS, DCD and DSR inputs, they do
28 * not have an RI input, nor do they have DTR or RTS outputs. If
29 * required, these have to be supplied via some other means (eg, GPIO)
30 * and hooked into this driver.
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
53 #include <asm/sizes.h>
57 #define SERIAL_AMBA_MAJOR 204
58 #define SERIAL_AMBA_MINOR 64
59 #define SERIAL_AMBA_NR UART_NR
61 #define AMBA_ISR_PASS_LIMIT 256
63 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
64 #define UART_DUMMY_DR_RX (1 << 16)
67 * We wrap our port structure around the generic uart_port.
69 struct uart_amba_port
{
70 struct uart_port port
;
72 unsigned int im
; /* interrupt mask */
73 unsigned int old_status
;
74 unsigned int ifls
; /* vendor-specific */
75 unsigned int lcrh_tx
; /* vendor-specific */
76 unsigned int lcrh_rx
; /* vendor-specific */
77 bool oversampling
; /* vendor-specific */
81 /* There is by now at least one vendor with differing details, so handle it */
84 unsigned int fifosize
;
90 static struct vendor_data vendor_arm
= {
91 .ifls
= UART011_IFLS_RX4_8
|UART011_IFLS_TX4_8
,
93 .lcrh_tx
= UART011_LCRH
,
94 .lcrh_rx
= UART011_LCRH
,
95 .oversampling
= false,
98 static struct vendor_data vendor_st
= {
99 .ifls
= UART011_IFLS_RX_HALF
|UART011_IFLS_TX_HALF
,
101 .lcrh_tx
= ST_UART011_LCRH_TX
,
102 .lcrh_rx
= ST_UART011_LCRH_RX
,
103 .oversampling
= true,
106 static void pl011_stop_tx(struct uart_port
*port
)
108 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
110 uap
->im
&= ~UART011_TXIM
;
111 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
114 static void pl011_start_tx(struct uart_port
*port
)
116 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
118 uap
->im
|= UART011_TXIM
;
119 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
122 static void pl011_stop_rx(struct uart_port
*port
)
124 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
126 uap
->im
&= ~(UART011_RXIM
|UART011_RTIM
|UART011_FEIM
|
127 UART011_PEIM
|UART011_BEIM
|UART011_OEIM
);
128 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
131 static void pl011_enable_ms(struct uart_port
*port
)
133 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
135 uap
->im
|= UART011_RIMIM
|UART011_CTSMIM
|UART011_DCDMIM
|UART011_DSRMIM
;
136 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
139 static void pl011_rx_chars(struct uart_amba_port
*uap
)
141 struct tty_struct
*tty
= uap
->port
.state
->port
.tty
;
142 unsigned int status
, ch
, flag
, max_count
= 256;
144 status
= readw(uap
->port
.membase
+ UART01x_FR
);
145 while ((status
& UART01x_FR_RXFE
) == 0 && max_count
--) {
146 ch
= readw(uap
->port
.membase
+ UART01x_DR
) | UART_DUMMY_DR_RX
;
148 uap
->port
.icount
.rx
++;
151 * Note that the error handling code is
152 * out of the main execution path
154 if (unlikely(ch
& UART_DR_ERROR
)) {
155 if (ch
& UART011_DR_BE
) {
156 ch
&= ~(UART011_DR_FE
| UART011_DR_PE
);
157 uap
->port
.icount
.brk
++;
158 if (uart_handle_break(&uap
->port
))
160 } else if (ch
& UART011_DR_PE
)
161 uap
->port
.icount
.parity
++;
162 else if (ch
& UART011_DR_FE
)
163 uap
->port
.icount
.frame
++;
164 if (ch
& UART011_DR_OE
)
165 uap
->port
.icount
.overrun
++;
167 ch
&= uap
->port
.read_status_mask
;
169 if (ch
& UART011_DR_BE
)
171 else if (ch
& UART011_DR_PE
)
173 else if (ch
& UART011_DR_FE
)
177 if (uart_handle_sysrq_char(&uap
->port
, ch
& 255))
180 uart_insert_char(&uap
->port
, ch
, UART011_DR_OE
, ch
, flag
);
183 status
= readw(uap
->port
.membase
+ UART01x_FR
);
185 spin_unlock(&uap
->port
.lock
);
186 tty_flip_buffer_push(tty
);
187 spin_lock(&uap
->port
.lock
);
190 static void pl011_tx_chars(struct uart_amba_port
*uap
)
192 struct circ_buf
*xmit
= &uap
->port
.state
->xmit
;
195 if (uap
->port
.x_char
) {
196 writew(uap
->port
.x_char
, uap
->port
.membase
+ UART01x_DR
);
197 uap
->port
.icount
.tx
++;
198 uap
->port
.x_char
= 0;
201 if (uart_circ_empty(xmit
) || uart_tx_stopped(&uap
->port
)) {
202 pl011_stop_tx(&uap
->port
);
206 count
= uap
->port
.fifosize
>> 1;
208 writew(xmit
->buf
[xmit
->tail
], uap
->port
.membase
+ UART01x_DR
);
209 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
210 uap
->port
.icount
.tx
++;
211 if (uart_circ_empty(xmit
))
213 } while (--count
> 0);
215 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
216 uart_write_wakeup(&uap
->port
);
218 if (uart_circ_empty(xmit
))
219 pl011_stop_tx(&uap
->port
);
222 static void pl011_modem_status(struct uart_amba_port
*uap
)
224 unsigned int status
, delta
;
226 status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
228 delta
= status
^ uap
->old_status
;
229 uap
->old_status
= status
;
234 if (delta
& UART01x_FR_DCD
)
235 uart_handle_dcd_change(&uap
->port
, status
& UART01x_FR_DCD
);
237 if (delta
& UART01x_FR_DSR
)
238 uap
->port
.icount
.dsr
++;
240 if (delta
& UART01x_FR_CTS
)
241 uart_handle_cts_change(&uap
->port
, status
& UART01x_FR_CTS
);
243 wake_up_interruptible(&uap
->port
.state
->port
.delta_msr_wait
);
246 static irqreturn_t
pl011_int(int irq
, void *dev_id
)
248 struct uart_amba_port
*uap
= dev_id
;
249 unsigned int status
, pass_counter
= AMBA_ISR_PASS_LIMIT
;
252 spin_lock(&uap
->port
.lock
);
254 status
= readw(uap
->port
.membase
+ UART011_MIS
);
257 writew(status
& ~(UART011_TXIS
|UART011_RTIS
|
259 uap
->port
.membase
+ UART011_ICR
);
261 if (status
& (UART011_RTIS
|UART011_RXIS
))
263 if (status
& (UART011_DSRMIS
|UART011_DCDMIS
|
264 UART011_CTSMIS
|UART011_RIMIS
))
265 pl011_modem_status(uap
);
266 if (status
& UART011_TXIS
)
269 if (pass_counter
-- == 0)
272 status
= readw(uap
->port
.membase
+ UART011_MIS
);
273 } while (status
!= 0);
277 spin_unlock(&uap
->port
.lock
);
279 return IRQ_RETVAL(handled
);
282 static unsigned int pl01x_tx_empty(struct uart_port
*port
)
284 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
285 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
286 return status
& (UART01x_FR_BUSY
|UART01x_FR_TXFF
) ? 0 : TIOCSER_TEMT
;
289 static unsigned int pl01x_get_mctrl(struct uart_port
*port
)
291 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
292 unsigned int result
= 0;
293 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
295 #define TIOCMBIT(uartbit, tiocmbit) \
296 if (status & uartbit) \
299 TIOCMBIT(UART01x_FR_DCD
, TIOCM_CAR
);
300 TIOCMBIT(UART01x_FR_DSR
, TIOCM_DSR
);
301 TIOCMBIT(UART01x_FR_CTS
, TIOCM_CTS
);
302 TIOCMBIT(UART011_FR_RI
, TIOCM_RNG
);
307 static void pl011_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
309 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
312 cr
= readw(uap
->port
.membase
+ UART011_CR
);
314 #define TIOCMBIT(tiocmbit, uartbit) \
315 if (mctrl & tiocmbit) \
320 TIOCMBIT(TIOCM_RTS
, UART011_CR_RTS
);
321 TIOCMBIT(TIOCM_DTR
, UART011_CR_DTR
);
322 TIOCMBIT(TIOCM_OUT1
, UART011_CR_OUT1
);
323 TIOCMBIT(TIOCM_OUT2
, UART011_CR_OUT2
);
324 TIOCMBIT(TIOCM_LOOP
, UART011_CR_LBE
);
327 /* We need to disable auto-RTS if we want to turn RTS off */
328 TIOCMBIT(TIOCM_RTS
, UART011_CR_RTSEN
);
332 writew(cr
, uap
->port
.membase
+ UART011_CR
);
335 static void pl011_break_ctl(struct uart_port
*port
, int break_state
)
337 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
341 spin_lock_irqsave(&uap
->port
.lock
, flags
);
342 lcr_h
= readw(uap
->port
.membase
+ uap
->lcrh_tx
);
343 if (break_state
== -1)
344 lcr_h
|= UART01x_LCRH_BRK
;
346 lcr_h
&= ~UART01x_LCRH_BRK
;
347 writew(lcr_h
, uap
->port
.membase
+ uap
->lcrh_tx
);
348 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
351 #ifdef CONFIG_CONSOLE_POLL
352 static int pl010_get_poll_char(struct uart_port
*port
)
354 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
357 status
= readw(uap
->port
.membase
+ UART01x_FR
);
358 if (status
& UART01x_FR_RXFE
)
361 return readw(uap
->port
.membase
+ UART01x_DR
);
364 static void pl010_put_poll_char(struct uart_port
*port
,
367 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
369 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_TXFF
)
372 writew(ch
, uap
->port
.membase
+ UART01x_DR
);
375 #endif /* CONFIG_CONSOLE_POLL */
377 static int pl011_startup(struct uart_port
*port
)
379 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
384 * Try to enable the clock producer.
386 retval
= clk_enable(uap
->clk
);
390 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
395 retval
= request_irq(uap
->port
.irq
, pl011_int
, 0, "uart-pl011", uap
);
399 writew(uap
->ifls
, uap
->port
.membase
+ UART011_IFLS
);
402 * Provoke TX FIFO interrupt into asserting.
404 cr
= UART01x_CR_UARTEN
| UART011_CR_TXE
| UART011_CR_LBE
;
405 writew(cr
, uap
->port
.membase
+ UART011_CR
);
406 writew(0, uap
->port
.membase
+ UART011_FBRD
);
407 writew(1, uap
->port
.membase
+ UART011_IBRD
);
408 writew(0, uap
->port
.membase
+ uap
->lcrh_rx
);
409 if (uap
->lcrh_tx
!= uap
->lcrh_rx
) {
412 * Wait 10 PCLKs before writing LCRH_TX register,
413 * to get this delay write read only register 10 times
415 for (i
= 0; i
< 10; ++i
)
416 writew(0xff, uap
->port
.membase
+ UART011_MIS
);
417 writew(0, uap
->port
.membase
+ uap
->lcrh_tx
);
419 writew(0, uap
->port
.membase
+ UART01x_DR
);
420 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_BUSY
)
423 cr
= UART01x_CR_UARTEN
| UART011_CR_RXE
| UART011_CR_TXE
;
424 writew(cr
, uap
->port
.membase
+ UART011_CR
);
427 * initialise the old status of the modem signals
429 uap
->old_status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
432 * Finally, enable interrupts
434 spin_lock_irq(&uap
->port
.lock
);
435 uap
->im
= UART011_RXIM
| UART011_RTIM
;
436 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
437 spin_unlock_irq(&uap
->port
.lock
);
442 clk_disable(uap
->clk
);
447 static void pl011_shutdown_channel(struct uart_amba_port
*uap
,
452 val
= readw(uap
->port
.membase
+ lcrh
);
453 val
&= ~(UART01x_LCRH_BRK
| UART01x_LCRH_FEN
);
454 writew(val
, uap
->port
.membase
+ lcrh
);
457 static void pl011_shutdown(struct uart_port
*port
)
459 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
462 * disable all interrupts
464 spin_lock_irq(&uap
->port
.lock
);
466 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
467 writew(0xffff, uap
->port
.membase
+ UART011_ICR
);
468 spin_unlock_irq(&uap
->port
.lock
);
473 free_irq(uap
->port
.irq
, uap
);
478 uap
->autorts
= false;
479 writew(UART01x_CR_UARTEN
| UART011_CR_TXE
, uap
->port
.membase
+ UART011_CR
);
482 * disable break condition and fifos
484 pl011_shutdown_channel(uap
, uap
->lcrh_rx
);
485 if (uap
->lcrh_rx
!= uap
->lcrh_tx
)
486 pl011_shutdown_channel(uap
, uap
->lcrh_tx
);
489 * Shut down the clock producer
491 clk_disable(uap
->clk
);
495 pl011_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
496 struct ktermios
*old
)
498 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
499 unsigned int lcr_h
, old_cr
;
501 unsigned int baud
, quot
;
504 * Ask the core to calculate the divisor for us.
506 baud
= uart_get_baud_rate(port
, termios
, old
, 0,
507 port
->uartclk
/(uap
->oversampling
? 8 : 16));
509 if (baud
> port
->uartclk
/16)
510 quot
= DIV_ROUND_CLOSEST(port
->uartclk
* 8, baud
);
512 quot
= DIV_ROUND_CLOSEST(port
->uartclk
* 4, baud
);
514 switch (termios
->c_cflag
& CSIZE
) {
516 lcr_h
= UART01x_LCRH_WLEN_5
;
519 lcr_h
= UART01x_LCRH_WLEN_6
;
522 lcr_h
= UART01x_LCRH_WLEN_7
;
525 lcr_h
= UART01x_LCRH_WLEN_8
;
528 if (termios
->c_cflag
& CSTOPB
)
529 lcr_h
|= UART01x_LCRH_STP2
;
530 if (termios
->c_cflag
& PARENB
) {
531 lcr_h
|= UART01x_LCRH_PEN
;
532 if (!(termios
->c_cflag
& PARODD
))
533 lcr_h
|= UART01x_LCRH_EPS
;
535 if (port
->fifosize
> 1)
536 lcr_h
|= UART01x_LCRH_FEN
;
538 spin_lock_irqsave(&port
->lock
, flags
);
541 * Update the per-port timeout.
543 uart_update_timeout(port
, termios
->c_cflag
, baud
);
545 port
->read_status_mask
= UART011_DR_OE
| 255;
546 if (termios
->c_iflag
& INPCK
)
547 port
->read_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
548 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
549 port
->read_status_mask
|= UART011_DR_BE
;
552 * Characters to ignore
554 port
->ignore_status_mask
= 0;
555 if (termios
->c_iflag
& IGNPAR
)
556 port
->ignore_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
557 if (termios
->c_iflag
& IGNBRK
) {
558 port
->ignore_status_mask
|= UART011_DR_BE
;
560 * If we're ignoring parity and break indicators,
561 * ignore overruns too (for real raw support).
563 if (termios
->c_iflag
& IGNPAR
)
564 port
->ignore_status_mask
|= UART011_DR_OE
;
568 * Ignore all characters if CREAD is not set.
570 if ((termios
->c_cflag
& CREAD
) == 0)
571 port
->ignore_status_mask
|= UART_DUMMY_DR_RX
;
573 if (UART_ENABLE_MS(port
, termios
->c_cflag
))
574 pl011_enable_ms(port
);
576 /* first, disable everything */
577 old_cr
= readw(port
->membase
+ UART011_CR
);
578 writew(0, port
->membase
+ UART011_CR
);
580 if (termios
->c_cflag
& CRTSCTS
) {
581 if (old_cr
& UART011_CR_RTS
)
582 old_cr
|= UART011_CR_RTSEN
;
584 old_cr
|= UART011_CR_CTSEN
;
587 old_cr
&= ~(UART011_CR_CTSEN
| UART011_CR_RTSEN
);
588 uap
->autorts
= false;
591 if (uap
->oversampling
) {
592 if (baud
> port
->uartclk
/16)
593 old_cr
|= ST_UART011_CR_OVSFACT
;
595 old_cr
&= ~ST_UART011_CR_OVSFACT
;
599 writew(quot
& 0x3f, port
->membase
+ UART011_FBRD
);
600 writew(quot
>> 6, port
->membase
+ UART011_IBRD
);
603 * ----------v----------v----------v----------v-----
604 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
605 * ----------^----------^----------^----------^-----
607 writew(lcr_h
, port
->membase
+ uap
->lcrh_rx
);
608 if (uap
->lcrh_rx
!= uap
->lcrh_tx
) {
611 * Wait 10 PCLKs before writing LCRH_TX register,
612 * to get this delay write read only register 10 times
614 for (i
= 0; i
< 10; ++i
)
615 writew(0xff, uap
->port
.membase
+ UART011_MIS
);
616 writew(lcr_h
, port
->membase
+ uap
->lcrh_tx
);
618 writew(old_cr
, port
->membase
+ UART011_CR
);
620 spin_unlock_irqrestore(&port
->lock
, flags
);
623 static const char *pl011_type(struct uart_port
*port
)
625 return port
->type
== PORT_AMBA
? "AMBA/PL011" : NULL
;
629 * Release the memory region(s) being used by 'port'
631 static void pl010_release_port(struct uart_port
*port
)
633 release_mem_region(port
->mapbase
, SZ_4K
);
637 * Request the memory region(s) being used by 'port'
639 static int pl010_request_port(struct uart_port
*port
)
641 return request_mem_region(port
->mapbase
, SZ_4K
, "uart-pl011")
642 != NULL
? 0 : -EBUSY
;
646 * Configure/autoconfigure the port.
648 static void pl010_config_port(struct uart_port
*port
, int flags
)
650 if (flags
& UART_CONFIG_TYPE
) {
651 port
->type
= PORT_AMBA
;
652 pl010_request_port(port
);
657 * verify the new serial_struct (for TIOCSSERIAL).
659 static int pl010_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
662 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_AMBA
)
664 if (ser
->irq
< 0 || ser
->irq
>= nr_irqs
)
666 if (ser
->baud_base
< 9600)
671 static struct uart_ops amba_pl011_pops
= {
672 .tx_empty
= pl01x_tx_empty
,
673 .set_mctrl
= pl011_set_mctrl
,
674 .get_mctrl
= pl01x_get_mctrl
,
675 .stop_tx
= pl011_stop_tx
,
676 .start_tx
= pl011_start_tx
,
677 .stop_rx
= pl011_stop_rx
,
678 .enable_ms
= pl011_enable_ms
,
679 .break_ctl
= pl011_break_ctl
,
680 .startup
= pl011_startup
,
681 .shutdown
= pl011_shutdown
,
682 .set_termios
= pl011_set_termios
,
684 .release_port
= pl010_release_port
,
685 .request_port
= pl010_request_port
,
686 .config_port
= pl010_config_port
,
687 .verify_port
= pl010_verify_port
,
688 #ifdef CONFIG_CONSOLE_POLL
689 .poll_get_char
= pl010_get_poll_char
,
690 .poll_put_char
= pl010_put_poll_char
,
694 static struct uart_amba_port
*amba_ports
[UART_NR
];
696 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
698 static void pl011_console_putchar(struct uart_port
*port
, int ch
)
700 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
702 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_TXFF
)
704 writew(ch
, uap
->port
.membase
+ UART01x_DR
);
708 pl011_console_write(struct console
*co
, const char *s
, unsigned int count
)
710 struct uart_amba_port
*uap
= amba_ports
[co
->index
];
711 unsigned int status
, old_cr
, new_cr
;
713 clk_enable(uap
->clk
);
716 * First save the CR then disable the interrupts
718 old_cr
= readw(uap
->port
.membase
+ UART011_CR
);
719 new_cr
= old_cr
& ~UART011_CR_CTSEN
;
720 new_cr
|= UART01x_CR_UARTEN
| UART011_CR_TXE
;
721 writew(new_cr
, uap
->port
.membase
+ UART011_CR
);
723 uart_console_write(&uap
->port
, s
, count
, pl011_console_putchar
);
726 * Finally, wait for transmitter to become empty
727 * and restore the TCR
730 status
= readw(uap
->port
.membase
+ UART01x_FR
);
731 } while (status
& UART01x_FR_BUSY
);
732 writew(old_cr
, uap
->port
.membase
+ UART011_CR
);
734 clk_disable(uap
->clk
);
738 pl011_console_get_options(struct uart_amba_port
*uap
, int *baud
,
739 int *parity
, int *bits
)
741 if (readw(uap
->port
.membase
+ UART011_CR
) & UART01x_CR_UARTEN
) {
742 unsigned int lcr_h
, ibrd
, fbrd
;
744 lcr_h
= readw(uap
->port
.membase
+ uap
->lcrh_tx
);
747 if (lcr_h
& UART01x_LCRH_PEN
) {
748 if (lcr_h
& UART01x_LCRH_EPS
)
754 if ((lcr_h
& 0x60) == UART01x_LCRH_WLEN_7
)
759 ibrd
= readw(uap
->port
.membase
+ UART011_IBRD
);
760 fbrd
= readw(uap
->port
.membase
+ UART011_FBRD
);
762 *baud
= uap
->port
.uartclk
* 4 / (64 * ibrd
+ fbrd
);
764 if (uap
->oversampling
) {
765 if (readw(uap
->port
.membase
+ UART011_CR
)
766 & ST_UART011_CR_OVSFACT
)
772 static int __init
pl011_console_setup(struct console
*co
, char *options
)
774 struct uart_amba_port
*uap
;
781 * Check whether an invalid uart number has been specified, and
782 * if so, search for the first available port that does have
785 if (co
->index
>= UART_NR
)
787 uap
= amba_ports
[co
->index
];
791 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
794 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
796 pl011_console_get_options(uap
, &baud
, &parity
, &bits
);
798 return uart_set_options(&uap
->port
, co
, baud
, parity
, bits
, flow
);
801 static struct uart_driver amba_reg
;
802 static struct console amba_console
= {
804 .write
= pl011_console_write
,
805 .device
= uart_console_device
,
806 .setup
= pl011_console_setup
,
807 .flags
= CON_PRINTBUFFER
,
812 #define AMBA_CONSOLE (&amba_console)
814 #define AMBA_CONSOLE NULL
817 static struct uart_driver amba_reg
= {
818 .owner
= THIS_MODULE
,
819 .driver_name
= "ttyAMA",
820 .dev_name
= "ttyAMA",
821 .major
= SERIAL_AMBA_MAJOR
,
822 .minor
= SERIAL_AMBA_MINOR
,
824 .cons
= AMBA_CONSOLE
,
827 static int pl011_probe(struct amba_device
*dev
, struct amba_id
*id
)
829 struct uart_amba_port
*uap
;
830 struct vendor_data
*vendor
= id
->data
;
834 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
835 if (amba_ports
[i
] == NULL
)
838 if (i
== ARRAY_SIZE(amba_ports
)) {
843 uap
= kzalloc(sizeof(struct uart_amba_port
), GFP_KERNEL
);
849 base
= ioremap(dev
->res
.start
, resource_size(&dev
->res
));
855 uap
->clk
= clk_get(&dev
->dev
, NULL
);
856 if (IS_ERR(uap
->clk
)) {
857 ret
= PTR_ERR(uap
->clk
);
861 uap
->ifls
= vendor
->ifls
;
862 uap
->lcrh_rx
= vendor
->lcrh_rx
;
863 uap
->lcrh_tx
= vendor
->lcrh_tx
;
864 uap
->oversampling
= vendor
->oversampling
;
865 uap
->port
.dev
= &dev
->dev
;
866 uap
->port
.mapbase
= dev
->res
.start
;
867 uap
->port
.membase
= base
;
868 uap
->port
.iotype
= UPIO_MEM
;
869 uap
->port
.irq
= dev
->irq
[0];
870 uap
->port
.fifosize
= vendor
->fifosize
;
871 uap
->port
.ops
= &amba_pl011_pops
;
872 uap
->port
.flags
= UPF_BOOT_AUTOCONF
;
877 amba_set_drvdata(dev
, uap
);
878 ret
= uart_add_one_port(&amba_reg
, &uap
->port
);
880 amba_set_drvdata(dev
, NULL
);
881 amba_ports
[i
] = NULL
;
892 static int pl011_remove(struct amba_device
*dev
)
894 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
897 amba_set_drvdata(dev
, NULL
);
899 uart_remove_one_port(&amba_reg
, &uap
->port
);
901 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
902 if (amba_ports
[i
] == uap
)
903 amba_ports
[i
] = NULL
;
905 iounmap(uap
->port
.membase
);
912 static int pl011_suspend(struct amba_device
*dev
, pm_message_t state
)
914 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
919 return uart_suspend_port(&amba_reg
, &uap
->port
);
922 static int pl011_resume(struct amba_device
*dev
)
924 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
929 return uart_resume_port(&amba_reg
, &uap
->port
);
933 static struct amba_id pl011_ids
[] = {
947 static struct amba_driver pl011_driver
= {
949 .name
= "uart-pl011",
951 .id_table
= pl011_ids
,
952 .probe
= pl011_probe
,
953 .remove
= pl011_remove
,
955 .suspend
= pl011_suspend
,
956 .resume
= pl011_resume
,
960 static int __init
pl011_init(void)
963 printk(KERN_INFO
"Serial: AMBA PL011 UART driver\n");
965 ret
= uart_register_driver(&amba_reg
);
967 ret
= amba_driver_register(&pl011_driver
);
969 uart_unregister_driver(&amba_reg
);
974 static void __exit
pl011_exit(void)
976 amba_driver_unregister(&pl011_driver
);
977 uart_unregister_driver(&amba_reg
);
981 * While this can be a module, if builtin it's most likely the console
982 * So let's leave module_exit but move module_init to an earlier place
984 arch_initcall(pl011_init
);
985 module_exit(pl011_exit
);
987 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
988 MODULE_DESCRIPTION("ARM AMBA serial port driver");
989 MODULE_LICENSE("GPL");