]>
git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/serial/amba-pl011.c
2 * linux/drivers/char/amba.c
4 * Driver for AMBA serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
35 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
39 #include <linux/module.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/console.h>
43 #include <linux/sysrq.h>
44 #include <linux/device.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial_core.h>
48 #include <linux/serial.h>
49 #include <linux/amba/bus.h>
50 #include <linux/amba/serial.h>
51 #include <linux/clk.h>
54 #include <asm/sizes.h>
58 #define SERIAL_AMBA_MAJOR 204
59 #define SERIAL_AMBA_MINOR 64
60 #define SERIAL_AMBA_NR UART_NR
62 #define AMBA_ISR_PASS_LIMIT 256
64 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
65 #define UART_DUMMY_DR_RX (1 << 16)
68 * We wrap our port structure around the generic uart_port.
70 struct uart_amba_port
{
71 struct uart_port port
;
73 unsigned int im
; /* interrupt mask */
74 unsigned int old_status
;
77 static void pl011_stop_tx(struct uart_port
*port
)
79 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
81 uap
->im
&= ~UART011_TXIM
;
82 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
85 static void pl011_start_tx(struct uart_port
*port
)
87 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
89 uap
->im
|= UART011_TXIM
;
90 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
93 static void pl011_stop_rx(struct uart_port
*port
)
95 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
97 uap
->im
&= ~(UART011_RXIM
|UART011_RTIM
|UART011_FEIM
|
98 UART011_PEIM
|UART011_BEIM
|UART011_OEIM
);
99 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
102 static void pl011_enable_ms(struct uart_port
*port
)
104 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
106 uap
->im
|= UART011_RIMIM
|UART011_CTSMIM
|UART011_DCDMIM
|UART011_DSRMIM
;
107 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
110 static void pl011_rx_chars(struct uart_amba_port
*uap
)
112 struct tty_struct
*tty
= uap
->port
.info
->tty
;
113 unsigned int status
, ch
, flag
, max_count
= 256;
115 status
= readw(uap
->port
.membase
+ UART01x_FR
);
116 while ((status
& UART01x_FR_RXFE
) == 0 && max_count
--) {
117 ch
= readw(uap
->port
.membase
+ UART01x_DR
) | UART_DUMMY_DR_RX
;
119 uap
->port
.icount
.rx
++;
122 * Note that the error handling code is
123 * out of the main execution path
125 if (unlikely(ch
& UART_DR_ERROR
)) {
126 if (ch
& UART011_DR_BE
) {
127 ch
&= ~(UART011_DR_FE
| UART011_DR_PE
);
128 uap
->port
.icount
.brk
++;
129 if (uart_handle_break(&uap
->port
))
131 } else if (ch
& UART011_DR_PE
)
132 uap
->port
.icount
.parity
++;
133 else if (ch
& UART011_DR_FE
)
134 uap
->port
.icount
.frame
++;
135 if (ch
& UART011_DR_OE
)
136 uap
->port
.icount
.overrun
++;
138 ch
&= uap
->port
.read_status_mask
;
140 if (ch
& UART011_DR_BE
)
142 else if (ch
& UART011_DR_PE
)
144 else if (ch
& UART011_DR_FE
)
148 if (uart_handle_sysrq_char(&uap
->port
, ch
& 255))
151 uart_insert_char(&uap
->port
, ch
, UART011_DR_OE
, ch
, flag
);
154 status
= readw(uap
->port
.membase
+ UART01x_FR
);
156 tty_flip_buffer_push(tty
);
160 static void pl011_tx_chars(struct uart_amba_port
*uap
)
162 struct circ_buf
*xmit
= &uap
->port
.info
->xmit
;
165 if (uap
->port
.x_char
) {
166 writew(uap
->port
.x_char
, uap
->port
.membase
+ UART01x_DR
);
167 uap
->port
.icount
.tx
++;
168 uap
->port
.x_char
= 0;
171 if (uart_circ_empty(xmit
) || uart_tx_stopped(&uap
->port
)) {
172 pl011_stop_tx(&uap
->port
);
176 count
= uap
->port
.fifosize
>> 1;
178 writew(xmit
->buf
[xmit
->tail
], uap
->port
.membase
+ UART01x_DR
);
179 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
180 uap
->port
.icount
.tx
++;
181 if (uart_circ_empty(xmit
))
183 } while (--count
> 0);
185 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
186 uart_write_wakeup(&uap
->port
);
188 if (uart_circ_empty(xmit
))
189 pl011_stop_tx(&uap
->port
);
192 static void pl011_modem_status(struct uart_amba_port
*uap
)
194 unsigned int status
, delta
;
196 status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
198 delta
= status
^ uap
->old_status
;
199 uap
->old_status
= status
;
204 if (delta
& UART01x_FR_DCD
)
205 uart_handle_dcd_change(&uap
->port
, status
& UART01x_FR_DCD
);
207 if (delta
& UART01x_FR_DSR
)
208 uap
->port
.icount
.dsr
++;
210 if (delta
& UART01x_FR_CTS
)
211 uart_handle_cts_change(&uap
->port
, status
& UART01x_FR_CTS
);
213 wake_up_interruptible(&uap
->port
.info
->delta_msr_wait
);
216 static irqreturn_t
pl011_int(int irq
, void *dev_id
)
218 struct uart_amba_port
*uap
= dev_id
;
219 unsigned int status
, pass_counter
= AMBA_ISR_PASS_LIMIT
;
222 spin_lock(&uap
->port
.lock
);
224 status
= readw(uap
->port
.membase
+ UART011_MIS
);
227 writew(status
& ~(UART011_TXIS
|UART011_RTIS
|
229 uap
->port
.membase
+ UART011_ICR
);
231 if (status
& (UART011_RTIS
|UART011_RXIS
))
233 if (status
& (UART011_DSRMIS
|UART011_DCDMIS
|
234 UART011_CTSMIS
|UART011_RIMIS
))
235 pl011_modem_status(uap
);
236 if (status
& UART011_TXIS
)
239 if (pass_counter
-- == 0)
242 status
= readw(uap
->port
.membase
+ UART011_MIS
);
243 } while (status
!= 0);
247 spin_unlock(&uap
->port
.lock
);
249 return IRQ_RETVAL(handled
);
252 static unsigned int pl01x_tx_empty(struct uart_port
*port
)
254 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
255 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
256 return status
& (UART01x_FR_BUSY
|UART01x_FR_TXFF
) ? 0 : TIOCSER_TEMT
;
259 static unsigned int pl01x_get_mctrl(struct uart_port
*port
)
261 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
262 unsigned int result
= 0;
263 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
265 #define BIT(uartbit, tiocmbit) \
266 if (status & uartbit) \
269 BIT(UART01x_FR_DCD
, TIOCM_CAR
);
270 BIT(UART01x_FR_DSR
, TIOCM_DSR
);
271 BIT(UART01x_FR_CTS
, TIOCM_CTS
);
272 BIT(UART011_FR_RI
, TIOCM_RNG
);
277 static void pl011_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
279 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
282 cr
= readw(uap
->port
.membase
+ UART011_CR
);
284 #define BIT(tiocmbit, uartbit) \
285 if (mctrl & tiocmbit) \
290 BIT(TIOCM_RTS
, UART011_CR_RTS
);
291 BIT(TIOCM_DTR
, UART011_CR_DTR
);
292 BIT(TIOCM_OUT1
, UART011_CR_OUT1
);
293 BIT(TIOCM_OUT2
, UART011_CR_OUT2
);
294 BIT(TIOCM_LOOP
, UART011_CR_LBE
);
297 writew(cr
, uap
->port
.membase
+ UART011_CR
);
300 static void pl011_break_ctl(struct uart_port
*port
, int break_state
)
302 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
306 spin_lock_irqsave(&uap
->port
.lock
, flags
);
307 lcr_h
= readw(uap
->port
.membase
+ UART011_LCRH
);
308 if (break_state
== -1)
309 lcr_h
|= UART01x_LCRH_BRK
;
311 lcr_h
&= ~UART01x_LCRH_BRK
;
312 writew(lcr_h
, uap
->port
.membase
+ UART011_LCRH
);
313 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
316 static int pl011_startup(struct uart_port
*port
)
318 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
323 * Try to enable the clock producer.
325 retval
= clk_enable(uap
->clk
);
329 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
334 retval
= request_irq(uap
->port
.irq
, pl011_int
, 0, "uart-pl011", uap
);
338 writew(UART011_IFLS_RX4_8
|UART011_IFLS_TX4_8
,
339 uap
->port
.membase
+ UART011_IFLS
);
342 * Provoke TX FIFO interrupt into asserting.
344 cr
= UART01x_CR_UARTEN
| UART011_CR_TXE
| UART011_CR_LBE
;
345 writew(cr
, uap
->port
.membase
+ UART011_CR
);
346 writew(0, uap
->port
.membase
+ UART011_FBRD
);
347 writew(1, uap
->port
.membase
+ UART011_IBRD
);
348 writew(0, uap
->port
.membase
+ UART011_LCRH
);
349 writew(0, uap
->port
.membase
+ UART01x_DR
);
350 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_BUSY
)
353 cr
= UART01x_CR_UARTEN
| UART011_CR_RXE
| UART011_CR_TXE
;
354 writew(cr
, uap
->port
.membase
+ UART011_CR
);
357 * initialise the old status of the modem signals
359 uap
->old_status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
362 * Finally, enable interrupts
364 spin_lock_irq(&uap
->port
.lock
);
365 uap
->im
= UART011_RXIM
| UART011_RTIM
;
366 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
367 spin_unlock_irq(&uap
->port
.lock
);
372 clk_disable(uap
->clk
);
377 static void pl011_shutdown(struct uart_port
*port
)
379 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
383 * disable all interrupts
385 spin_lock_irq(&uap
->port
.lock
);
387 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
388 writew(0xffff, uap
->port
.membase
+ UART011_ICR
);
389 spin_unlock_irq(&uap
->port
.lock
);
394 free_irq(uap
->port
.irq
, uap
);
399 writew(UART01x_CR_UARTEN
| UART011_CR_TXE
, uap
->port
.membase
+ UART011_CR
);
402 * disable break condition and fifos
404 val
= readw(uap
->port
.membase
+ UART011_LCRH
);
405 val
&= ~(UART01x_LCRH_BRK
| UART01x_LCRH_FEN
);
406 writew(val
, uap
->port
.membase
+ UART011_LCRH
);
409 * Shut down the clock producer
411 clk_disable(uap
->clk
);
415 pl011_set_termios(struct uart_port
*port
, struct termios
*termios
,
418 unsigned int lcr_h
, old_cr
;
420 unsigned int baud
, quot
;
423 * Ask the core to calculate the divisor for us.
425 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/16);
426 quot
= port
->uartclk
* 4 / baud
;
428 switch (termios
->c_cflag
& CSIZE
) {
430 lcr_h
= UART01x_LCRH_WLEN_5
;
433 lcr_h
= UART01x_LCRH_WLEN_6
;
436 lcr_h
= UART01x_LCRH_WLEN_7
;
439 lcr_h
= UART01x_LCRH_WLEN_8
;
442 if (termios
->c_cflag
& CSTOPB
)
443 lcr_h
|= UART01x_LCRH_STP2
;
444 if (termios
->c_cflag
& PARENB
) {
445 lcr_h
|= UART01x_LCRH_PEN
;
446 if (!(termios
->c_cflag
& PARODD
))
447 lcr_h
|= UART01x_LCRH_EPS
;
449 if (port
->fifosize
> 1)
450 lcr_h
|= UART01x_LCRH_FEN
;
452 spin_lock_irqsave(&port
->lock
, flags
);
455 * Update the per-port timeout.
457 uart_update_timeout(port
, termios
->c_cflag
, baud
);
459 port
->read_status_mask
= UART011_DR_OE
| 255;
460 if (termios
->c_iflag
& INPCK
)
461 port
->read_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
462 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
463 port
->read_status_mask
|= UART011_DR_BE
;
466 * Characters to ignore
468 port
->ignore_status_mask
= 0;
469 if (termios
->c_iflag
& IGNPAR
)
470 port
->ignore_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
471 if (termios
->c_iflag
& IGNBRK
) {
472 port
->ignore_status_mask
|= UART011_DR_BE
;
474 * If we're ignoring parity and break indicators,
475 * ignore overruns too (for real raw support).
477 if (termios
->c_iflag
& IGNPAR
)
478 port
->ignore_status_mask
|= UART011_DR_OE
;
482 * Ignore all characters if CREAD is not set.
484 if ((termios
->c_cflag
& CREAD
) == 0)
485 port
->ignore_status_mask
|= UART_DUMMY_DR_RX
;
487 if (UART_ENABLE_MS(port
, termios
->c_cflag
))
488 pl011_enable_ms(port
);
490 /* first, disable everything */
491 old_cr
= readw(port
->membase
+ UART011_CR
);
492 writew(0, port
->membase
+ UART011_CR
);
495 writew(quot
& 0x3f, port
->membase
+ UART011_FBRD
);
496 writew(quot
>> 6, port
->membase
+ UART011_IBRD
);
499 * ----------v----------v----------v----------v-----
500 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
501 * ----------^----------^----------^----------^-----
503 writew(lcr_h
, port
->membase
+ UART011_LCRH
);
504 writew(old_cr
, port
->membase
+ UART011_CR
);
506 spin_unlock_irqrestore(&port
->lock
, flags
);
509 static const char *pl011_type(struct uart_port
*port
)
511 return port
->type
== PORT_AMBA
? "AMBA/PL011" : NULL
;
515 * Release the memory region(s) being used by 'port'
517 static void pl010_release_port(struct uart_port
*port
)
519 release_mem_region(port
->mapbase
, SZ_4K
);
523 * Request the memory region(s) being used by 'port'
525 static int pl010_request_port(struct uart_port
*port
)
527 return request_mem_region(port
->mapbase
, SZ_4K
, "uart-pl011")
528 != NULL
? 0 : -EBUSY
;
532 * Configure/autoconfigure the port.
534 static void pl010_config_port(struct uart_port
*port
, int flags
)
536 if (flags
& UART_CONFIG_TYPE
) {
537 port
->type
= PORT_AMBA
;
538 pl010_request_port(port
);
543 * verify the new serial_struct (for TIOCSSERIAL).
545 static int pl010_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
548 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_AMBA
)
550 if (ser
->irq
< 0 || ser
->irq
>= NR_IRQS
)
552 if (ser
->baud_base
< 9600)
557 static struct uart_ops amba_pl011_pops
= {
558 .tx_empty
= pl01x_tx_empty
,
559 .set_mctrl
= pl011_set_mctrl
,
560 .get_mctrl
= pl01x_get_mctrl
,
561 .stop_tx
= pl011_stop_tx
,
562 .start_tx
= pl011_start_tx
,
563 .stop_rx
= pl011_stop_rx
,
564 .enable_ms
= pl011_enable_ms
,
565 .break_ctl
= pl011_break_ctl
,
566 .startup
= pl011_startup
,
567 .shutdown
= pl011_shutdown
,
568 .set_termios
= pl011_set_termios
,
570 .release_port
= pl010_release_port
,
571 .request_port
= pl010_request_port
,
572 .config_port
= pl010_config_port
,
573 .verify_port
= pl010_verify_port
,
576 static struct uart_amba_port
*amba_ports
[UART_NR
];
578 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
580 static void pl011_console_putchar(struct uart_port
*port
, int ch
)
582 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
584 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_TXFF
)
586 writew(ch
, uap
->port
.membase
+ UART01x_DR
);
590 pl011_console_write(struct console
*co
, const char *s
, unsigned int count
)
592 struct uart_amba_port
*uap
= amba_ports
[co
->index
];
593 unsigned int status
, old_cr
, new_cr
;
595 clk_enable(uap
->clk
);
598 * First save the CR then disable the interrupts
600 old_cr
= readw(uap
->port
.membase
+ UART011_CR
);
601 new_cr
= old_cr
& ~UART011_CR_CTSEN
;
602 new_cr
|= UART01x_CR_UARTEN
| UART011_CR_TXE
;
603 writew(new_cr
, uap
->port
.membase
+ UART011_CR
);
605 uart_console_write(&uap
->port
, s
, count
, pl011_console_putchar
);
608 * Finally, wait for transmitter to become empty
609 * and restore the TCR
612 status
= readw(uap
->port
.membase
+ UART01x_FR
);
613 } while (status
& UART01x_FR_BUSY
);
614 writew(old_cr
, uap
->port
.membase
+ UART011_CR
);
616 clk_disable(uap
->clk
);
620 pl011_console_get_options(struct uart_amba_port
*uap
, int *baud
,
621 int *parity
, int *bits
)
623 if (readw(uap
->port
.membase
+ UART011_CR
) & UART01x_CR_UARTEN
) {
624 unsigned int lcr_h
, ibrd
, fbrd
;
626 lcr_h
= readw(uap
->port
.membase
+ UART011_LCRH
);
629 if (lcr_h
& UART01x_LCRH_PEN
) {
630 if (lcr_h
& UART01x_LCRH_EPS
)
636 if ((lcr_h
& 0x60) == UART01x_LCRH_WLEN_7
)
641 ibrd
= readw(uap
->port
.membase
+ UART011_IBRD
);
642 fbrd
= readw(uap
->port
.membase
+ UART011_FBRD
);
644 *baud
= uap
->port
.uartclk
* 4 / (64 * ibrd
+ fbrd
);
648 static int __init
pl011_console_setup(struct console
*co
, char *options
)
650 struct uart_amba_port
*uap
;
657 * Check whether an invalid uart number has been specified, and
658 * if so, search for the first available port that does have
661 if (co
->index
>= UART_NR
)
663 uap
= amba_ports
[co
->index
];
665 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
668 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
670 pl011_console_get_options(uap
, &baud
, &parity
, &bits
);
672 return uart_set_options(&uap
->port
, co
, baud
, parity
, bits
, flow
);
675 static struct uart_driver amba_reg
;
676 static struct console amba_console
= {
678 .write
= pl011_console_write
,
679 .device
= uart_console_device
,
680 .setup
= pl011_console_setup
,
681 .flags
= CON_PRINTBUFFER
,
686 #define AMBA_CONSOLE (&amba_console)
688 #define AMBA_CONSOLE NULL
691 static struct uart_driver amba_reg
= {
692 .owner
= THIS_MODULE
,
693 .driver_name
= "ttyAMA",
694 .dev_name
= "ttyAMA",
695 .major
= SERIAL_AMBA_MAJOR
,
696 .minor
= SERIAL_AMBA_MINOR
,
698 .cons
= AMBA_CONSOLE
,
701 static int pl011_probe(struct amba_device
*dev
, void *id
)
703 struct uart_amba_port
*uap
;
707 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
708 if (amba_ports
[i
] == NULL
)
711 if (i
== ARRAY_SIZE(amba_ports
)) {
716 uap
= kmalloc(sizeof(struct uart_amba_port
), GFP_KERNEL
);
722 base
= ioremap(dev
->res
.start
, PAGE_SIZE
);
728 memset(uap
, 0, sizeof(struct uart_amba_port
));
729 uap
->clk
= clk_get(&dev
->dev
, "UARTCLK");
730 if (IS_ERR(uap
->clk
)) {
731 ret
= PTR_ERR(uap
->clk
);
735 uap
->port
.dev
= &dev
->dev
;
736 uap
->port
.mapbase
= dev
->res
.start
;
737 uap
->port
.membase
= base
;
738 uap
->port
.iotype
= UPIO_MEM
;
739 uap
->port
.irq
= dev
->irq
[0];
740 uap
->port
.fifosize
= 16;
741 uap
->port
.ops
= &amba_pl011_pops
;
742 uap
->port
.flags
= UPF_BOOT_AUTOCONF
;
747 amba_set_drvdata(dev
, uap
);
748 ret
= uart_add_one_port(&amba_reg
, &uap
->port
);
750 amba_set_drvdata(dev
, NULL
);
751 amba_ports
[i
] = NULL
;
762 static int pl011_remove(struct amba_device
*dev
)
764 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
767 amba_set_drvdata(dev
, NULL
);
769 uart_remove_one_port(&amba_reg
, &uap
->port
);
771 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
772 if (amba_ports
[i
] == uap
)
773 amba_ports
[i
] = NULL
;
775 iounmap(uap
->port
.membase
);
781 static struct amba_id pl011_ids
[] __initdata
= {
789 static struct amba_driver pl011_driver
= {
791 .name
= "uart-pl011",
793 .id_table
= pl011_ids
,
794 .probe
= pl011_probe
,
795 .remove
= pl011_remove
,
798 static int __init
pl011_init(void)
801 printk(KERN_INFO
"Serial: AMBA PL011 UART driver\n");
803 ret
= uart_register_driver(&amba_reg
);
805 ret
= amba_driver_register(&pl011_driver
);
807 uart_unregister_driver(&amba_reg
);
812 static void __exit
pl011_exit(void)
814 amba_driver_unregister(&pl011_driver
);
815 uart_unregister_driver(&amba_reg
);
818 module_init(pl011_init
);
819 module_exit(pl011_exit
);
821 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
822 MODULE_DESCRIPTION("ARM AMBA serial port driver");
823 MODULE_LICENSE("GPL");