]>
git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/serial/amba-pl011.c
2 * linux/drivers/char/amba.c
4 * Driver for AMBA serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
34 #include <linux/config.h>
36 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
40 #include <linux/module.h>
41 #include <linux/ioport.h>
42 #include <linux/init.h>
43 #include <linux/console.h>
44 #include <linux/sysrq.h>
45 #include <linux/device.h>
46 #include <linux/tty.h>
47 #include <linux/tty_flip.h>
48 #include <linux/serial_core.h>
49 #include <linux/serial.h>
50 #include <linux/amba/bus.h>
51 #include <linux/amba/serial.h>
52 #include <linux/clk.h>
55 #include <asm/sizes.h>
59 #define SERIAL_AMBA_MAJOR 204
60 #define SERIAL_AMBA_MINOR 64
61 #define SERIAL_AMBA_NR UART_NR
63 #define AMBA_ISR_PASS_LIMIT 256
65 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
66 #define UART_DUMMY_DR_RX (1 << 16)
69 * We wrap our port structure around the generic uart_port.
71 struct uart_amba_port
{
72 struct uart_port port
;
74 unsigned int im
; /* interrupt mask */
75 unsigned int old_status
;
78 static void pl011_stop_tx(struct uart_port
*port
)
80 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
82 uap
->im
&= ~UART011_TXIM
;
83 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
86 static void pl011_start_tx(struct uart_port
*port
)
88 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
90 uap
->im
|= UART011_TXIM
;
91 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
94 static void pl011_stop_rx(struct uart_port
*port
)
96 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
98 uap
->im
&= ~(UART011_RXIM
|UART011_RTIM
|UART011_FEIM
|
99 UART011_PEIM
|UART011_BEIM
|UART011_OEIM
);
100 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
103 static void pl011_enable_ms(struct uart_port
*port
)
105 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
107 uap
->im
|= UART011_RIMIM
|UART011_CTSMIM
|UART011_DCDMIM
|UART011_DSRMIM
;
108 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
113 pl011_rx_chars(struct uart_amba_port
*uap
, struct pt_regs
*regs
)
115 pl011_rx_chars(struct uart_amba_port
*uap
)
118 struct tty_struct
*tty
= uap
->port
.info
->tty
;
119 unsigned int status
, ch
, flag
, max_count
= 256;
121 status
= readw(uap
->port
.membase
+ UART01x_FR
);
122 while ((status
& UART01x_FR_RXFE
) == 0 && max_count
--) {
123 if (tty
->flip
.count
>= TTY_FLIPBUF_SIZE
) {
124 if (tty
->low_latency
)
125 tty_flip_buffer_push(tty
);
127 * If this failed then we will throw away the
128 * bytes but must do so to clear interrupts
132 ch
= readw(uap
->port
.membase
+ UART01x_DR
) | UART_DUMMY_DR_RX
;
134 uap
->port
.icount
.rx
++;
137 * Note that the error handling code is
138 * out of the main execution path
140 if (unlikely(ch
& UART_DR_ERROR
)) {
141 if (ch
& UART011_DR_BE
) {
142 ch
&= ~(UART011_DR_FE
| UART011_DR_PE
);
143 uap
->port
.icount
.brk
++;
144 if (uart_handle_break(&uap
->port
))
146 } else if (ch
& UART011_DR_PE
)
147 uap
->port
.icount
.parity
++;
148 else if (ch
& UART011_DR_FE
)
149 uap
->port
.icount
.frame
++;
150 if (ch
& UART011_DR_OE
)
151 uap
->port
.icount
.overrun
++;
153 ch
&= uap
->port
.read_status_mask
;
155 if (ch
& UART011_DR_BE
)
157 else if (ch
& UART011_DR_PE
)
159 else if (ch
& UART011_DR_FE
)
163 if (uart_handle_sysrq_char(&uap
->port
, ch
& 255, regs
))
166 uart_insert_char(&uap
->port
, ch
, UART011_DR_OE
, ch
, flag
);
169 status
= readw(uap
->port
.membase
+ UART01x_FR
);
171 tty_flip_buffer_push(tty
);
175 static void pl011_tx_chars(struct uart_amba_port
*uap
)
177 struct circ_buf
*xmit
= &uap
->port
.info
->xmit
;
180 if (uap
->port
.x_char
) {
181 writew(uap
->port
.x_char
, uap
->port
.membase
+ UART01x_DR
);
182 uap
->port
.icount
.tx
++;
183 uap
->port
.x_char
= 0;
186 if (uart_circ_empty(xmit
) || uart_tx_stopped(&uap
->port
)) {
187 pl011_stop_tx(&uap
->port
);
191 count
= uap
->port
.fifosize
>> 1;
193 writew(xmit
->buf
[xmit
->tail
], uap
->port
.membase
+ UART01x_DR
);
194 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
195 uap
->port
.icount
.tx
++;
196 if (uart_circ_empty(xmit
))
198 } while (--count
> 0);
200 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
201 uart_write_wakeup(&uap
->port
);
203 if (uart_circ_empty(xmit
))
204 pl011_stop_tx(&uap
->port
);
207 static void pl011_modem_status(struct uart_amba_port
*uap
)
209 unsigned int status
, delta
;
211 status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
213 delta
= status
^ uap
->old_status
;
214 uap
->old_status
= status
;
219 if (delta
& UART01x_FR_DCD
)
220 uart_handle_dcd_change(&uap
->port
, status
& UART01x_FR_DCD
);
222 if (delta
& UART01x_FR_DSR
)
223 uap
->port
.icount
.dsr
++;
225 if (delta
& UART01x_FR_CTS
)
226 uart_handle_cts_change(&uap
->port
, status
& UART01x_FR_CTS
);
228 wake_up_interruptible(&uap
->port
.info
->delta_msr_wait
);
231 static irqreturn_t
pl011_int(int irq
, void *dev_id
, struct pt_regs
*regs
)
233 struct uart_amba_port
*uap
= dev_id
;
234 unsigned int status
, pass_counter
= AMBA_ISR_PASS_LIMIT
;
237 spin_lock(&uap
->port
.lock
);
239 status
= readw(uap
->port
.membase
+ UART011_MIS
);
242 writew(status
& ~(UART011_TXIS
|UART011_RTIS
|
244 uap
->port
.membase
+ UART011_ICR
);
246 if (status
& (UART011_RTIS
|UART011_RXIS
))
248 pl011_rx_chars(uap
, regs
);
252 if (status
& (UART011_DSRMIS
|UART011_DCDMIS
|
253 UART011_CTSMIS
|UART011_RIMIS
))
254 pl011_modem_status(uap
);
255 if (status
& UART011_TXIS
)
258 if (pass_counter
-- == 0)
261 status
= readw(uap
->port
.membase
+ UART011_MIS
);
262 } while (status
!= 0);
266 spin_unlock(&uap
->port
.lock
);
268 return IRQ_RETVAL(handled
);
271 static unsigned int pl01x_tx_empty(struct uart_port
*port
)
273 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
274 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
275 return status
& (UART01x_FR_BUSY
|UART01x_FR_TXFF
) ? 0 : TIOCSER_TEMT
;
278 static unsigned int pl01x_get_mctrl(struct uart_port
*port
)
280 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
281 unsigned int result
= 0;
282 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
284 #define BIT(uartbit, tiocmbit) \
285 if (status & uartbit) \
288 BIT(UART01x_FR_DCD
, TIOCM_CAR
);
289 BIT(UART01x_FR_DSR
, TIOCM_DSR
);
290 BIT(UART01x_FR_CTS
, TIOCM_CTS
);
291 BIT(UART011_FR_RI
, TIOCM_RNG
);
296 static void pl011_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
298 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
301 cr
= readw(uap
->port
.membase
+ UART011_CR
);
303 #define BIT(tiocmbit, uartbit) \
304 if (mctrl & tiocmbit) \
309 BIT(TIOCM_RTS
, UART011_CR_RTS
);
310 BIT(TIOCM_DTR
, UART011_CR_DTR
);
311 BIT(TIOCM_OUT1
, UART011_CR_OUT1
);
312 BIT(TIOCM_OUT2
, UART011_CR_OUT2
);
313 BIT(TIOCM_LOOP
, UART011_CR_LBE
);
316 writew(cr
, uap
->port
.membase
+ UART011_CR
);
319 static void pl011_break_ctl(struct uart_port
*port
, int break_state
)
321 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
325 spin_lock_irqsave(&uap
->port
.lock
, flags
);
326 lcr_h
= readw(uap
->port
.membase
+ UART011_LCRH
);
327 if (break_state
== -1)
328 lcr_h
|= UART01x_LCRH_BRK
;
330 lcr_h
&= ~UART01x_LCRH_BRK
;
331 writew(lcr_h
, uap
->port
.membase
+ UART011_LCRH
);
332 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
335 static int pl011_startup(struct uart_port
*port
)
337 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
342 * Try to enable the clock producer.
344 retval
= clk_enable(uap
->clk
);
348 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
353 retval
= request_irq(uap
->port
.irq
, pl011_int
, 0, "uart-pl011", uap
);
357 writew(UART011_IFLS_RX4_8
|UART011_IFLS_TX4_8
,
358 uap
->port
.membase
+ UART011_IFLS
);
361 * Provoke TX FIFO interrupt into asserting.
363 cr
= UART01x_CR_UARTEN
| UART011_CR_TXE
| UART011_CR_LBE
;
364 writew(cr
, uap
->port
.membase
+ UART011_CR
);
365 writew(0, uap
->port
.membase
+ UART011_FBRD
);
366 writew(1, uap
->port
.membase
+ UART011_IBRD
);
367 writew(0, uap
->port
.membase
+ UART011_LCRH
);
368 writew(0, uap
->port
.membase
+ UART01x_DR
);
369 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_BUSY
)
372 cr
= UART01x_CR_UARTEN
| UART011_CR_RXE
| UART011_CR_TXE
;
373 writew(cr
, uap
->port
.membase
+ UART011_CR
);
376 * initialise the old status of the modem signals
378 uap
->old_status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
381 * Finally, enable interrupts
383 spin_lock_irq(&uap
->port
.lock
);
384 uap
->im
= UART011_RXIM
| UART011_RTIM
;
385 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
386 spin_unlock_irq(&uap
->port
.lock
);
391 clk_disable(uap
->clk
);
396 static void pl011_shutdown(struct uart_port
*port
)
398 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
402 * disable all interrupts
404 spin_lock_irq(&uap
->port
.lock
);
406 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
407 writew(0xffff, uap
->port
.membase
+ UART011_ICR
);
408 spin_unlock_irq(&uap
->port
.lock
);
413 free_irq(uap
->port
.irq
, uap
);
418 writew(UART01x_CR_UARTEN
| UART011_CR_TXE
, uap
->port
.membase
+ UART011_CR
);
421 * disable break condition and fifos
423 val
= readw(uap
->port
.membase
+ UART011_LCRH
);
424 val
&= ~(UART01x_LCRH_BRK
| UART01x_LCRH_FEN
);
425 writew(val
, uap
->port
.membase
+ UART011_LCRH
);
428 * Shut down the clock producer
430 clk_disable(uap
->clk
);
434 pl011_set_termios(struct uart_port
*port
, struct termios
*termios
,
437 unsigned int lcr_h
, old_cr
;
439 unsigned int baud
, quot
;
442 * Ask the core to calculate the divisor for us.
444 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/16);
445 quot
= port
->uartclk
* 4 / baud
;
447 switch (termios
->c_cflag
& CSIZE
) {
449 lcr_h
= UART01x_LCRH_WLEN_5
;
452 lcr_h
= UART01x_LCRH_WLEN_6
;
455 lcr_h
= UART01x_LCRH_WLEN_7
;
458 lcr_h
= UART01x_LCRH_WLEN_8
;
461 if (termios
->c_cflag
& CSTOPB
)
462 lcr_h
|= UART01x_LCRH_STP2
;
463 if (termios
->c_cflag
& PARENB
) {
464 lcr_h
|= UART01x_LCRH_PEN
;
465 if (!(termios
->c_cflag
& PARODD
))
466 lcr_h
|= UART01x_LCRH_EPS
;
468 if (port
->fifosize
> 1)
469 lcr_h
|= UART01x_LCRH_FEN
;
471 spin_lock_irqsave(&port
->lock
, flags
);
474 * Update the per-port timeout.
476 uart_update_timeout(port
, termios
->c_cflag
, baud
);
478 port
->read_status_mask
= UART011_DR_OE
| 255;
479 if (termios
->c_iflag
& INPCK
)
480 port
->read_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
481 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
482 port
->read_status_mask
|= UART011_DR_BE
;
485 * Characters to ignore
487 port
->ignore_status_mask
= 0;
488 if (termios
->c_iflag
& IGNPAR
)
489 port
->ignore_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
490 if (termios
->c_iflag
& IGNBRK
) {
491 port
->ignore_status_mask
|= UART011_DR_BE
;
493 * If we're ignoring parity and break indicators,
494 * ignore overruns too (for real raw support).
496 if (termios
->c_iflag
& IGNPAR
)
497 port
->ignore_status_mask
|= UART011_DR_OE
;
501 * Ignore all characters if CREAD is not set.
503 if ((termios
->c_cflag
& CREAD
) == 0)
504 port
->ignore_status_mask
|= UART_DUMMY_DR_RX
;
506 if (UART_ENABLE_MS(port
, termios
->c_cflag
))
507 pl011_enable_ms(port
);
509 /* first, disable everything */
510 old_cr
= readw(port
->membase
+ UART011_CR
);
511 writew(0, port
->membase
+ UART011_CR
);
514 writew(quot
& 0x3f, port
->membase
+ UART011_FBRD
);
515 writew(quot
>> 6, port
->membase
+ UART011_IBRD
);
518 * ----------v----------v----------v----------v-----
519 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
520 * ----------^----------^----------^----------^-----
522 writew(lcr_h
, port
->membase
+ UART011_LCRH
);
523 writew(old_cr
, port
->membase
+ UART011_CR
);
525 spin_unlock_irqrestore(&port
->lock
, flags
);
528 static const char *pl011_type(struct uart_port
*port
)
530 return port
->type
== PORT_AMBA
? "AMBA/PL011" : NULL
;
534 * Release the memory region(s) being used by 'port'
536 static void pl010_release_port(struct uart_port
*port
)
538 release_mem_region(port
->mapbase
, SZ_4K
);
542 * Request the memory region(s) being used by 'port'
544 static int pl010_request_port(struct uart_port
*port
)
546 return request_mem_region(port
->mapbase
, SZ_4K
, "uart-pl011")
547 != NULL
? 0 : -EBUSY
;
551 * Configure/autoconfigure the port.
553 static void pl010_config_port(struct uart_port
*port
, int flags
)
555 if (flags
& UART_CONFIG_TYPE
) {
556 port
->type
= PORT_AMBA
;
557 pl010_request_port(port
);
562 * verify the new serial_struct (for TIOCSSERIAL).
564 static int pl010_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
567 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_AMBA
)
569 if (ser
->irq
< 0 || ser
->irq
>= NR_IRQS
)
571 if (ser
->baud_base
< 9600)
576 static struct uart_ops amba_pl011_pops
= {
577 .tx_empty
= pl01x_tx_empty
,
578 .set_mctrl
= pl011_set_mctrl
,
579 .get_mctrl
= pl01x_get_mctrl
,
580 .stop_tx
= pl011_stop_tx
,
581 .start_tx
= pl011_start_tx
,
582 .stop_rx
= pl011_stop_rx
,
583 .enable_ms
= pl011_enable_ms
,
584 .break_ctl
= pl011_break_ctl
,
585 .startup
= pl011_startup
,
586 .shutdown
= pl011_shutdown
,
587 .set_termios
= pl011_set_termios
,
589 .release_port
= pl010_release_port
,
590 .request_port
= pl010_request_port
,
591 .config_port
= pl010_config_port
,
592 .verify_port
= pl010_verify_port
,
595 static struct uart_amba_port
*amba_ports
[UART_NR
];
597 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
600 pl011_console_write_char(struct uart_amba_port
*uap
, char ch
)
605 status
= readw(uap
->port
.membase
+ UART01x_FR
);
606 } while (status
& UART01x_FR_TXFF
);
607 writew(ch
, uap
->port
.membase
+ UART01x_DR
);
611 pl011_console_write(struct console
*co
, const char *s
, unsigned int count
)
613 struct uart_amba_port
*uap
= amba_ports
[co
->index
];
614 unsigned int status
, old_cr
, new_cr
;
617 clk_enable(uap
->clk
);
620 * First save the CR then disable the interrupts
622 old_cr
= readw(uap
->port
.membase
+ UART011_CR
);
623 new_cr
= old_cr
& ~UART011_CR_CTSEN
;
624 new_cr
|= UART01x_CR_UARTEN
| UART011_CR_TXE
;
625 writew(new_cr
, uap
->port
.membase
+ UART011_CR
);
628 * Now, do each character
630 for (i
= 0; i
< count
; i
++) {
631 pl011_console_write_char(uap
, s
[i
]);
633 pl011_console_write_char(uap
, '\r');
637 * Finally, wait for transmitter to become empty
638 * and restore the TCR
641 status
= readw(uap
->port
.membase
+ UART01x_FR
);
642 } while (status
& UART01x_FR_BUSY
);
643 writew(old_cr
, uap
->port
.membase
+ UART011_CR
);
645 clk_disable(uap
->clk
);
649 pl011_console_get_options(struct uart_amba_port
*uap
, int *baud
,
650 int *parity
, int *bits
)
652 if (readw(uap
->port
.membase
+ UART011_CR
) & UART01x_CR_UARTEN
) {
653 unsigned int lcr_h
, ibrd
, fbrd
;
655 lcr_h
= readw(uap
->port
.membase
+ UART011_LCRH
);
658 if (lcr_h
& UART01x_LCRH_PEN
) {
659 if (lcr_h
& UART01x_LCRH_EPS
)
665 if ((lcr_h
& 0x60) == UART01x_LCRH_WLEN_7
)
670 ibrd
= readw(uap
->port
.membase
+ UART011_IBRD
);
671 fbrd
= readw(uap
->port
.membase
+ UART011_FBRD
);
673 *baud
= uap
->port
.uartclk
* 4 / (64 * ibrd
+ fbrd
);
677 static int __init
pl011_console_setup(struct console
*co
, char *options
)
679 struct uart_amba_port
*uap
;
686 * Check whether an invalid uart number has been specified, and
687 * if so, search for the first available port that does have
690 if (co
->index
>= UART_NR
)
692 uap
= amba_ports
[co
->index
];
694 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
697 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
699 pl011_console_get_options(uap
, &baud
, &parity
, &bits
);
701 return uart_set_options(&uap
->port
, co
, baud
, parity
, bits
, flow
);
704 static struct uart_driver amba_reg
;
705 static struct console amba_console
= {
707 .write
= pl011_console_write
,
708 .device
= uart_console_device
,
709 .setup
= pl011_console_setup
,
710 .flags
= CON_PRINTBUFFER
,
715 #define AMBA_CONSOLE (&amba_console)
717 #define AMBA_CONSOLE NULL
720 static struct uart_driver amba_reg
= {
721 .owner
= THIS_MODULE
,
722 .driver_name
= "ttyAMA",
723 .dev_name
= "ttyAMA",
724 .major
= SERIAL_AMBA_MAJOR
,
725 .minor
= SERIAL_AMBA_MINOR
,
727 .cons
= AMBA_CONSOLE
,
730 static int pl011_probe(struct amba_device
*dev
, void *id
)
732 struct uart_amba_port
*uap
;
736 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
737 if (amba_ports
[i
] == NULL
)
740 if (i
== ARRAY_SIZE(amba_ports
)) {
745 uap
= kmalloc(sizeof(struct uart_amba_port
), GFP_KERNEL
);
751 base
= ioremap(dev
->res
.start
, PAGE_SIZE
);
757 memset(uap
, 0, sizeof(struct uart_amba_port
));
758 uap
->clk
= clk_get(&dev
->dev
, "UARTCLK");
759 if (IS_ERR(uap
->clk
)) {
760 ret
= PTR_ERR(uap
->clk
);
764 uap
->port
.dev
= &dev
->dev
;
765 uap
->port
.mapbase
= dev
->res
.start
;
766 uap
->port
.membase
= base
;
767 uap
->port
.iotype
= UPIO_MEM
;
768 uap
->port
.irq
= dev
->irq
[0];
769 uap
->port
.fifosize
= 16;
770 uap
->port
.ops
= &amba_pl011_pops
;
771 uap
->port
.flags
= UPF_BOOT_AUTOCONF
;
776 amba_set_drvdata(dev
, uap
);
777 ret
= uart_add_one_port(&amba_reg
, &uap
->port
);
779 amba_set_drvdata(dev
, NULL
);
780 amba_ports
[i
] = NULL
;
791 static int pl011_remove(struct amba_device
*dev
)
793 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
796 amba_set_drvdata(dev
, NULL
);
798 uart_remove_one_port(&amba_reg
, &uap
->port
);
800 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
801 if (amba_ports
[i
] == uap
)
802 amba_ports
[i
] = NULL
;
804 iounmap(uap
->port
.membase
);
810 static struct amba_id pl011_ids
[] __initdata
= {
818 static struct amba_driver pl011_driver
= {
820 .name
= "uart-pl011",
822 .id_table
= pl011_ids
,
823 .probe
= pl011_probe
,
824 .remove
= pl011_remove
,
827 static int __init
pl011_init(void)
830 printk(KERN_INFO
"Serial: AMBA PL011 UART driver\n");
832 ret
= uart_register_driver(&amba_reg
);
834 ret
= amba_driver_register(&pl011_driver
);
836 uart_unregister_driver(&amba_reg
);
841 static void __exit
pl011_exit(void)
843 amba_driver_unregister(&pl011_driver
);
844 uart_unregister_driver(&amba_reg
);
847 module_init(pl011_init
);
848 module_exit(pl011_exit
);
850 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
851 MODULE_DESCRIPTION("ARM AMBA serial port driver");
852 MODULE_LICENSE("GPL");