]>
git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/serial/amba-pl011.c
2 * linux/drivers/char/amba.c
4 * Driver for AMBA serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
34 #include <linux/config.h>
36 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
40 #include <linux/module.h>
41 #include <linux/ioport.h>
42 #include <linux/init.h>
43 #include <linux/console.h>
44 #include <linux/sysrq.h>
45 #include <linux/device.h>
46 #include <linux/tty.h>
47 #include <linux/tty_flip.h>
48 #include <linux/serial_core.h>
49 #include <linux/serial.h>
50 #include <linux/amba/bus.h>
51 #include <linux/amba/serial.h>
52 #include <linux/clk.h>
55 #include <asm/sizes.h>
59 #define SERIAL_AMBA_MAJOR 204
60 #define SERIAL_AMBA_MINOR 64
61 #define SERIAL_AMBA_NR UART_NR
63 #define AMBA_ISR_PASS_LIMIT 256
65 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
66 #define UART_DUMMY_DR_RX (1 << 16)
69 * We wrap our port structure around the generic uart_port.
71 struct uart_amba_port
{
72 struct uart_port port
;
74 unsigned int im
; /* interrupt mask */
75 unsigned int old_status
;
78 static void pl011_stop_tx(struct uart_port
*port
)
80 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
82 uap
->im
&= ~UART011_TXIM
;
83 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
86 static void pl011_start_tx(struct uart_port
*port
)
88 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
90 uap
->im
|= UART011_TXIM
;
91 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
94 static void pl011_stop_rx(struct uart_port
*port
)
96 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
98 uap
->im
&= ~(UART011_RXIM
|UART011_RTIM
|UART011_FEIM
|
99 UART011_PEIM
|UART011_BEIM
|UART011_OEIM
);
100 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
103 static void pl011_enable_ms(struct uart_port
*port
)
105 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
107 uap
->im
|= UART011_RIMIM
|UART011_CTSMIM
|UART011_DCDMIM
|UART011_DSRMIM
;
108 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
113 pl011_rx_chars(struct uart_amba_port
*uap
, struct pt_regs
*regs
)
115 pl011_rx_chars(struct uart_amba_port
*uap
)
118 struct tty_struct
*tty
= uap
->port
.info
->tty
;
119 unsigned int status
, ch
, flag
, max_count
= 256;
121 status
= readw(uap
->port
.membase
+ UART01x_FR
);
122 while ((status
& UART01x_FR_RXFE
) == 0 && max_count
--) {
123 ch
= readw(uap
->port
.membase
+ UART01x_DR
) | UART_DUMMY_DR_RX
;
125 uap
->port
.icount
.rx
++;
128 * Note that the error handling code is
129 * out of the main execution path
131 if (unlikely(ch
& UART_DR_ERROR
)) {
132 if (ch
& UART011_DR_BE
) {
133 ch
&= ~(UART011_DR_FE
| UART011_DR_PE
);
134 uap
->port
.icount
.brk
++;
135 if (uart_handle_break(&uap
->port
))
137 } else if (ch
& UART011_DR_PE
)
138 uap
->port
.icount
.parity
++;
139 else if (ch
& UART011_DR_FE
)
140 uap
->port
.icount
.frame
++;
141 if (ch
& UART011_DR_OE
)
142 uap
->port
.icount
.overrun
++;
144 ch
&= uap
->port
.read_status_mask
;
146 if (ch
& UART011_DR_BE
)
148 else if (ch
& UART011_DR_PE
)
150 else if (ch
& UART011_DR_FE
)
154 if (uart_handle_sysrq_char(&uap
->port
, ch
& 255, regs
))
157 uart_insert_char(&uap
->port
, ch
, UART011_DR_OE
, ch
, flag
);
160 status
= readw(uap
->port
.membase
+ UART01x_FR
);
162 tty_flip_buffer_push(tty
);
166 static void pl011_tx_chars(struct uart_amba_port
*uap
)
168 struct circ_buf
*xmit
= &uap
->port
.info
->xmit
;
171 if (uap
->port
.x_char
) {
172 writew(uap
->port
.x_char
, uap
->port
.membase
+ UART01x_DR
);
173 uap
->port
.icount
.tx
++;
174 uap
->port
.x_char
= 0;
177 if (uart_circ_empty(xmit
) || uart_tx_stopped(&uap
->port
)) {
178 pl011_stop_tx(&uap
->port
);
182 count
= uap
->port
.fifosize
>> 1;
184 writew(xmit
->buf
[xmit
->tail
], uap
->port
.membase
+ UART01x_DR
);
185 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
186 uap
->port
.icount
.tx
++;
187 if (uart_circ_empty(xmit
))
189 } while (--count
> 0);
191 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
192 uart_write_wakeup(&uap
->port
);
194 if (uart_circ_empty(xmit
))
195 pl011_stop_tx(&uap
->port
);
198 static void pl011_modem_status(struct uart_amba_port
*uap
)
200 unsigned int status
, delta
;
202 status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
204 delta
= status
^ uap
->old_status
;
205 uap
->old_status
= status
;
210 if (delta
& UART01x_FR_DCD
)
211 uart_handle_dcd_change(&uap
->port
, status
& UART01x_FR_DCD
);
213 if (delta
& UART01x_FR_DSR
)
214 uap
->port
.icount
.dsr
++;
216 if (delta
& UART01x_FR_CTS
)
217 uart_handle_cts_change(&uap
->port
, status
& UART01x_FR_CTS
);
219 wake_up_interruptible(&uap
->port
.info
->delta_msr_wait
);
222 static irqreturn_t
pl011_int(int irq
, void *dev_id
, struct pt_regs
*regs
)
224 struct uart_amba_port
*uap
= dev_id
;
225 unsigned int status
, pass_counter
= AMBA_ISR_PASS_LIMIT
;
228 spin_lock(&uap
->port
.lock
);
230 status
= readw(uap
->port
.membase
+ UART011_MIS
);
233 writew(status
& ~(UART011_TXIS
|UART011_RTIS
|
235 uap
->port
.membase
+ UART011_ICR
);
237 if (status
& (UART011_RTIS
|UART011_RXIS
))
239 pl011_rx_chars(uap
, regs
);
243 if (status
& (UART011_DSRMIS
|UART011_DCDMIS
|
244 UART011_CTSMIS
|UART011_RIMIS
))
245 pl011_modem_status(uap
);
246 if (status
& UART011_TXIS
)
249 if (pass_counter
-- == 0)
252 status
= readw(uap
->port
.membase
+ UART011_MIS
);
253 } while (status
!= 0);
257 spin_unlock(&uap
->port
.lock
);
259 return IRQ_RETVAL(handled
);
262 static unsigned int pl01x_tx_empty(struct uart_port
*port
)
264 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
265 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
266 return status
& (UART01x_FR_BUSY
|UART01x_FR_TXFF
) ? 0 : TIOCSER_TEMT
;
269 static unsigned int pl01x_get_mctrl(struct uart_port
*port
)
271 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
272 unsigned int result
= 0;
273 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
275 #define BIT(uartbit, tiocmbit) \
276 if (status & uartbit) \
279 BIT(UART01x_FR_DCD
, TIOCM_CAR
);
280 BIT(UART01x_FR_DSR
, TIOCM_DSR
);
281 BIT(UART01x_FR_CTS
, TIOCM_CTS
);
282 BIT(UART011_FR_RI
, TIOCM_RNG
);
287 static void pl011_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
289 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
292 cr
= readw(uap
->port
.membase
+ UART011_CR
);
294 #define BIT(tiocmbit, uartbit) \
295 if (mctrl & tiocmbit) \
300 BIT(TIOCM_RTS
, UART011_CR_RTS
);
301 BIT(TIOCM_DTR
, UART011_CR_DTR
);
302 BIT(TIOCM_OUT1
, UART011_CR_OUT1
);
303 BIT(TIOCM_OUT2
, UART011_CR_OUT2
);
304 BIT(TIOCM_LOOP
, UART011_CR_LBE
);
307 writew(cr
, uap
->port
.membase
+ UART011_CR
);
310 static void pl011_break_ctl(struct uart_port
*port
, int break_state
)
312 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
316 spin_lock_irqsave(&uap
->port
.lock
, flags
);
317 lcr_h
= readw(uap
->port
.membase
+ UART011_LCRH
);
318 if (break_state
== -1)
319 lcr_h
|= UART01x_LCRH_BRK
;
321 lcr_h
&= ~UART01x_LCRH_BRK
;
322 writew(lcr_h
, uap
->port
.membase
+ UART011_LCRH
);
323 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
326 static int pl011_startup(struct uart_port
*port
)
328 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
333 * Try to enable the clock producer.
335 retval
= clk_enable(uap
->clk
);
339 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
344 retval
= request_irq(uap
->port
.irq
, pl011_int
, 0, "uart-pl011", uap
);
348 writew(UART011_IFLS_RX4_8
|UART011_IFLS_TX4_8
,
349 uap
->port
.membase
+ UART011_IFLS
);
352 * Provoke TX FIFO interrupt into asserting.
354 cr
= UART01x_CR_UARTEN
| UART011_CR_TXE
| UART011_CR_LBE
;
355 writew(cr
, uap
->port
.membase
+ UART011_CR
);
356 writew(0, uap
->port
.membase
+ UART011_FBRD
);
357 writew(1, uap
->port
.membase
+ UART011_IBRD
);
358 writew(0, uap
->port
.membase
+ UART011_LCRH
);
359 writew(0, uap
->port
.membase
+ UART01x_DR
);
360 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_BUSY
)
363 cr
= UART01x_CR_UARTEN
| UART011_CR_RXE
| UART011_CR_TXE
;
364 writew(cr
, uap
->port
.membase
+ UART011_CR
);
367 * initialise the old status of the modem signals
369 uap
->old_status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
372 * Finally, enable interrupts
374 spin_lock_irq(&uap
->port
.lock
);
375 uap
->im
= UART011_RXIM
| UART011_RTIM
;
376 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
377 spin_unlock_irq(&uap
->port
.lock
);
382 clk_disable(uap
->clk
);
387 static void pl011_shutdown(struct uart_port
*port
)
389 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
393 * disable all interrupts
395 spin_lock_irq(&uap
->port
.lock
);
397 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
398 writew(0xffff, uap
->port
.membase
+ UART011_ICR
);
399 spin_unlock_irq(&uap
->port
.lock
);
404 free_irq(uap
->port
.irq
, uap
);
409 writew(UART01x_CR_UARTEN
| UART011_CR_TXE
, uap
->port
.membase
+ UART011_CR
);
412 * disable break condition and fifos
414 val
= readw(uap
->port
.membase
+ UART011_LCRH
);
415 val
&= ~(UART01x_LCRH_BRK
| UART01x_LCRH_FEN
);
416 writew(val
, uap
->port
.membase
+ UART011_LCRH
);
419 * Shut down the clock producer
421 clk_disable(uap
->clk
);
425 pl011_set_termios(struct uart_port
*port
, struct termios
*termios
,
428 unsigned int lcr_h
, old_cr
;
430 unsigned int baud
, quot
;
433 * Ask the core to calculate the divisor for us.
435 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/16);
436 quot
= port
->uartclk
* 4 / baud
;
438 switch (termios
->c_cflag
& CSIZE
) {
440 lcr_h
= UART01x_LCRH_WLEN_5
;
443 lcr_h
= UART01x_LCRH_WLEN_6
;
446 lcr_h
= UART01x_LCRH_WLEN_7
;
449 lcr_h
= UART01x_LCRH_WLEN_8
;
452 if (termios
->c_cflag
& CSTOPB
)
453 lcr_h
|= UART01x_LCRH_STP2
;
454 if (termios
->c_cflag
& PARENB
) {
455 lcr_h
|= UART01x_LCRH_PEN
;
456 if (!(termios
->c_cflag
& PARODD
))
457 lcr_h
|= UART01x_LCRH_EPS
;
459 if (port
->fifosize
> 1)
460 lcr_h
|= UART01x_LCRH_FEN
;
462 spin_lock_irqsave(&port
->lock
, flags
);
465 * Update the per-port timeout.
467 uart_update_timeout(port
, termios
->c_cflag
, baud
);
469 port
->read_status_mask
= UART011_DR_OE
| 255;
470 if (termios
->c_iflag
& INPCK
)
471 port
->read_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
472 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
473 port
->read_status_mask
|= UART011_DR_BE
;
476 * Characters to ignore
478 port
->ignore_status_mask
= 0;
479 if (termios
->c_iflag
& IGNPAR
)
480 port
->ignore_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
481 if (termios
->c_iflag
& IGNBRK
) {
482 port
->ignore_status_mask
|= UART011_DR_BE
;
484 * If we're ignoring parity and break indicators,
485 * ignore overruns too (for real raw support).
487 if (termios
->c_iflag
& IGNPAR
)
488 port
->ignore_status_mask
|= UART011_DR_OE
;
492 * Ignore all characters if CREAD is not set.
494 if ((termios
->c_cflag
& CREAD
) == 0)
495 port
->ignore_status_mask
|= UART_DUMMY_DR_RX
;
497 if (UART_ENABLE_MS(port
, termios
->c_cflag
))
498 pl011_enable_ms(port
);
500 /* first, disable everything */
501 old_cr
= readw(port
->membase
+ UART011_CR
);
502 writew(0, port
->membase
+ UART011_CR
);
505 writew(quot
& 0x3f, port
->membase
+ UART011_FBRD
);
506 writew(quot
>> 6, port
->membase
+ UART011_IBRD
);
509 * ----------v----------v----------v----------v-----
510 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
511 * ----------^----------^----------^----------^-----
513 writew(lcr_h
, port
->membase
+ UART011_LCRH
);
514 writew(old_cr
, port
->membase
+ UART011_CR
);
516 spin_unlock_irqrestore(&port
->lock
, flags
);
519 static const char *pl011_type(struct uart_port
*port
)
521 return port
->type
== PORT_AMBA
? "AMBA/PL011" : NULL
;
525 * Release the memory region(s) being used by 'port'
527 static void pl010_release_port(struct uart_port
*port
)
529 release_mem_region(port
->mapbase
, SZ_4K
);
533 * Request the memory region(s) being used by 'port'
535 static int pl010_request_port(struct uart_port
*port
)
537 return request_mem_region(port
->mapbase
, SZ_4K
, "uart-pl011")
538 != NULL
? 0 : -EBUSY
;
542 * Configure/autoconfigure the port.
544 static void pl010_config_port(struct uart_port
*port
, int flags
)
546 if (flags
& UART_CONFIG_TYPE
) {
547 port
->type
= PORT_AMBA
;
548 pl010_request_port(port
);
553 * verify the new serial_struct (for TIOCSSERIAL).
555 static int pl010_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
558 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_AMBA
)
560 if (ser
->irq
< 0 || ser
->irq
>= NR_IRQS
)
562 if (ser
->baud_base
< 9600)
567 static struct uart_ops amba_pl011_pops
= {
568 .tx_empty
= pl01x_tx_empty
,
569 .set_mctrl
= pl011_set_mctrl
,
570 .get_mctrl
= pl01x_get_mctrl
,
571 .stop_tx
= pl011_stop_tx
,
572 .start_tx
= pl011_start_tx
,
573 .stop_rx
= pl011_stop_rx
,
574 .enable_ms
= pl011_enable_ms
,
575 .break_ctl
= pl011_break_ctl
,
576 .startup
= pl011_startup
,
577 .shutdown
= pl011_shutdown
,
578 .set_termios
= pl011_set_termios
,
580 .release_port
= pl010_release_port
,
581 .request_port
= pl010_request_port
,
582 .config_port
= pl010_config_port
,
583 .verify_port
= pl010_verify_port
,
586 static struct uart_amba_port
*amba_ports
[UART_NR
];
588 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
590 static void pl011_console_putchar(struct uart_port
*port
, int ch
)
592 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
594 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_TXFF
)
596 writew(ch
, uap
->port
.membase
+ UART01x_DR
);
600 pl011_console_write(struct console
*co
, const char *s
, unsigned int count
)
602 struct uart_amba_port
*uap
= amba_ports
[co
->index
];
603 unsigned int status
, old_cr
, new_cr
;
605 clk_enable(uap
->clk
);
608 * First save the CR then disable the interrupts
610 old_cr
= readw(uap
->port
.membase
+ UART011_CR
);
611 new_cr
= old_cr
& ~UART011_CR_CTSEN
;
612 new_cr
|= UART01x_CR_UARTEN
| UART011_CR_TXE
;
613 writew(new_cr
, uap
->port
.membase
+ UART011_CR
);
615 uart_console_write(&uap
->port
, s
, count
, pl011_console_putchar
);
618 * Finally, wait for transmitter to become empty
619 * and restore the TCR
622 status
= readw(uap
->port
.membase
+ UART01x_FR
);
623 } while (status
& UART01x_FR_BUSY
);
624 writew(old_cr
, uap
->port
.membase
+ UART011_CR
);
626 clk_disable(uap
->clk
);
630 pl011_console_get_options(struct uart_amba_port
*uap
, int *baud
,
631 int *parity
, int *bits
)
633 if (readw(uap
->port
.membase
+ UART011_CR
) & UART01x_CR_UARTEN
) {
634 unsigned int lcr_h
, ibrd
, fbrd
;
636 lcr_h
= readw(uap
->port
.membase
+ UART011_LCRH
);
639 if (lcr_h
& UART01x_LCRH_PEN
) {
640 if (lcr_h
& UART01x_LCRH_EPS
)
646 if ((lcr_h
& 0x60) == UART01x_LCRH_WLEN_7
)
651 ibrd
= readw(uap
->port
.membase
+ UART011_IBRD
);
652 fbrd
= readw(uap
->port
.membase
+ UART011_FBRD
);
654 *baud
= uap
->port
.uartclk
* 4 / (64 * ibrd
+ fbrd
);
658 static int __init
pl011_console_setup(struct console
*co
, char *options
)
660 struct uart_amba_port
*uap
;
667 * Check whether an invalid uart number has been specified, and
668 * if so, search for the first available port that does have
671 if (co
->index
>= UART_NR
)
673 uap
= amba_ports
[co
->index
];
675 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
678 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
680 pl011_console_get_options(uap
, &baud
, &parity
, &bits
);
682 return uart_set_options(&uap
->port
, co
, baud
, parity
, bits
, flow
);
685 static struct uart_driver amba_reg
;
686 static struct console amba_console
= {
688 .write
= pl011_console_write
,
689 .device
= uart_console_device
,
690 .setup
= pl011_console_setup
,
691 .flags
= CON_PRINTBUFFER
,
696 #define AMBA_CONSOLE (&amba_console)
698 #define AMBA_CONSOLE NULL
701 static struct uart_driver amba_reg
= {
702 .owner
= THIS_MODULE
,
703 .driver_name
= "ttyAMA",
704 .dev_name
= "ttyAMA",
705 .major
= SERIAL_AMBA_MAJOR
,
706 .minor
= SERIAL_AMBA_MINOR
,
708 .cons
= AMBA_CONSOLE
,
711 static int pl011_probe(struct amba_device
*dev
, void *id
)
713 struct uart_amba_port
*uap
;
717 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
718 if (amba_ports
[i
] == NULL
)
721 if (i
== ARRAY_SIZE(amba_ports
)) {
726 uap
= kmalloc(sizeof(struct uart_amba_port
), GFP_KERNEL
);
732 base
= ioremap(dev
->res
.start
, PAGE_SIZE
);
738 memset(uap
, 0, sizeof(struct uart_amba_port
));
739 uap
->clk
= clk_get(&dev
->dev
, "UARTCLK");
740 if (IS_ERR(uap
->clk
)) {
741 ret
= PTR_ERR(uap
->clk
);
745 uap
->port
.dev
= &dev
->dev
;
746 uap
->port
.mapbase
= dev
->res
.start
;
747 uap
->port
.membase
= base
;
748 uap
->port
.iotype
= UPIO_MEM
;
749 uap
->port
.irq
= dev
->irq
[0];
750 uap
->port
.fifosize
= 16;
751 uap
->port
.ops
= &amba_pl011_pops
;
752 uap
->port
.flags
= UPF_BOOT_AUTOCONF
;
757 amba_set_drvdata(dev
, uap
);
758 ret
= uart_add_one_port(&amba_reg
, &uap
->port
);
760 amba_set_drvdata(dev
, NULL
);
761 amba_ports
[i
] = NULL
;
772 static int pl011_remove(struct amba_device
*dev
)
774 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
777 amba_set_drvdata(dev
, NULL
);
779 uart_remove_one_port(&amba_reg
, &uap
->port
);
781 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
782 if (amba_ports
[i
] == uap
)
783 amba_ports
[i
] = NULL
;
785 iounmap(uap
->port
.membase
);
791 static struct amba_id pl011_ids
[] __initdata
= {
799 static struct amba_driver pl011_driver
= {
801 .name
= "uart-pl011",
803 .id_table
= pl011_ids
,
804 .probe
= pl011_probe
,
805 .remove
= pl011_remove
,
808 static int __init
pl011_init(void)
811 printk(KERN_INFO
"Serial: AMBA PL011 UART driver\n");
813 ret
= uart_register_driver(&amba_reg
);
815 ret
= amba_driver_register(&pl011_driver
);
817 uart_unregister_driver(&amba_reg
);
822 static void __exit
pl011_exit(void)
824 amba_driver_unregister(&pl011_driver
);
825 uart_unregister_driver(&amba_reg
);
828 module_init(pl011_init
);
829 module_exit(pl011_exit
);
831 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
832 MODULE_DESCRIPTION("ARM AMBA serial port driver");
833 MODULE_LICENSE("GPL");