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imx: serial: use tty_encode_baud_rate to set true rate
[mirror_ubuntu-artful-kernel.git] / drivers / serial / imx.c
1 /*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * Copyright (C) 2009 emlix GmbH
12 * Author: Fabian Godehardt (added IrDA support for iMX)
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 * [29-Mar-2005] Mike Lee
29 * Added hardware handshake
30 */
31
32 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #define SUPPORT_SYSRQ
34 #endif
35
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/platform_device.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/clk.h>
47 #include <linux/delay.h>
48 #include <linux/rational.h>
49
50 #include <asm/io.h>
51 #include <asm/irq.h>
52 #include <mach/hardware.h>
53 #include <mach/imx-uart.h>
54
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
71 #define ONEMS 0xb0 /* One Millisecond register */
72 #define UTS 0xb4 /* UART Test Register */
73 #endif
74 #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
75 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
76 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
77 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
78 #define BIPR4 0xbc /* Incremental Preset Register 4 */
79 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
80 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
81 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
82 #define BMPR4 0xcc /* BRM Modulator Register 4 */
83 #define UTS 0xd0 /* UART Test Register */
84 #endif
85
86 /* UART Control Register Bit Fields.*/
87 #define URXD_CHARRDY (1<<15)
88 #define URXD_ERR (1<<14)
89 #define URXD_OVRRUN (1<<13)
90 #define URXD_FRMERR (1<<12)
91 #define URXD_BRK (1<<11)
92 #define URXD_PRERR (1<<10)
93 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
94 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
95 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
96 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
97 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
98 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
99 #define UCR1_IREN (1<<7) /* Infrared interface enable */
100 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
101 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
102 #define UCR1_SNDBRK (1<<4) /* Send break */
103 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
104 #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
105 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
106 #endif
107 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
108 #define UCR1_UARTCLKEN (0) /* not present on mx2/mx3 */
109 #endif
110 #define UCR1_DOZE (1<<1) /* Doze */
111 #define UCR1_UARTEN (1<<0) /* UART enabled */
112 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
113 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
114 #define UCR2_CTSC (1<<13) /* CTS pin control */
115 #define UCR2_CTS (1<<12) /* Clear to send */
116 #define UCR2_ESCEN (1<<11) /* Escape enable */
117 #define UCR2_PREN (1<<8) /* Parity enable */
118 #define UCR2_PROE (1<<7) /* Parity odd/even */
119 #define UCR2_STPB (1<<6) /* Stop */
120 #define UCR2_WS (1<<5) /* Word size */
121 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
122 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
123 #define UCR2_RXEN (1<<1) /* Receiver enabled */
124 #define UCR2_SRST (1<<0) /* SW reset */
125 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
126 #define UCR3_PARERREN (1<<12) /* Parity enable */
127 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
128 #define UCR3_DSR (1<<10) /* Data set ready */
129 #define UCR3_DCD (1<<9) /* Data carrier detect */
130 #define UCR3_RI (1<<8) /* Ring indicator */
131 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
132 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
133 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
134 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
135 #ifdef CONFIG_ARCH_IMX
136 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
137 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
138 #endif
139 #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
140 #define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
141 #endif
142 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
143 #define UCR3_BPEN (1<<0) /* Preset registers enable */
144 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
145 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
146 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
147 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
148 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
149 #define UCR4_IRSC (1<<5) /* IR special case */
150 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
151 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
152 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
153 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
154 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
155 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
156 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
157 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
158 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
159 #define USR1_RTSS (1<<14) /* RTS pin status */
160 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
161 #define USR1_RTSD (1<<12) /* RTS delta */
162 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
163 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
164 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
165 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
166 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
167 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
168 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
169 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
170 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
171 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
172 #define USR2_IDLE (1<<12) /* Idle condition */
173 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
174 #define USR2_WAKE (1<<7) /* Wake */
175 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
176 #define USR2_TXDC (1<<3) /* Transmitter complete */
177 #define USR2_BRCD (1<<2) /* Break condition */
178 #define USR2_ORE (1<<1) /* Overrun error */
179 #define USR2_RDR (1<<0) /* Recv data ready */
180 #define UTS_FRCPERR (1<<13) /* Force parity error */
181 #define UTS_LOOP (1<<12) /* Loop tx and rx */
182 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
183 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
184 #define UTS_TXFULL (1<<4) /* TxFIFO full */
185 #define UTS_RXFULL (1<<3) /* RxFIFO full */
186 #define UTS_SOFTRST (1<<0) /* Software reset */
187
188 /* We've been assigned a range on the "Low-density serial ports" major */
189 #ifdef CONFIG_ARCH_IMX
190 #define SERIAL_IMX_MAJOR 204
191 #define MINOR_START 41
192 #define DEV_NAME "ttySMX"
193 #define MAX_INTERNAL_IRQ IMX_IRQS
194 #endif
195
196 #ifdef CONFIG_ARCH_MXC
197 #define SERIAL_IMX_MAJOR 207
198 #define MINOR_START 16
199 #define DEV_NAME "ttymxc"
200 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
201 #endif
202
203 /*
204 * This determines how often we check the modem status signals
205 * for any change. They generally aren't connected to an IRQ
206 * so we have to poll them. We also check immediately before
207 * filling the TX fifo incase CTS has been dropped.
208 */
209 #define MCTRL_TIMEOUT (250*HZ/1000)
210
211 #define DRIVER_NAME "IMX-uart"
212
213 #define UART_NR 8
214
215 struct imx_port {
216 struct uart_port port;
217 struct timer_list timer;
218 unsigned int old_status;
219 int txirq,rxirq,rtsirq;
220 unsigned int have_rtscts:1;
221 unsigned int use_irda:1;
222 unsigned int irda_inv_rx:1;
223 unsigned int irda_inv_tx:1;
224 unsigned short trcv_delay; /* transceiver delay */
225 struct clk *clk;
226 };
227
228 #ifdef CONFIG_IRDA
229 #define USE_IRDA(sport) ((sport)->use_irda)
230 #else
231 #define USE_IRDA(sport) (0)
232 #endif
233
234 /*
235 * Handle any change of modem status signal since we were last called.
236 */
237 static void imx_mctrl_check(struct imx_port *sport)
238 {
239 unsigned int status, changed;
240
241 status = sport->port.ops->get_mctrl(&sport->port);
242 changed = status ^ sport->old_status;
243
244 if (changed == 0)
245 return;
246
247 sport->old_status = status;
248
249 if (changed & TIOCM_RI)
250 sport->port.icount.rng++;
251 if (changed & TIOCM_DSR)
252 sport->port.icount.dsr++;
253 if (changed & TIOCM_CAR)
254 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
255 if (changed & TIOCM_CTS)
256 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
257
258 wake_up_interruptible(&sport->port.info->delta_msr_wait);
259 }
260
261 /*
262 * This is our per-port timeout handler, for checking the
263 * modem status signals.
264 */
265 static void imx_timeout(unsigned long data)
266 {
267 struct imx_port *sport = (struct imx_port *)data;
268 unsigned long flags;
269
270 if (sport->port.info) {
271 spin_lock_irqsave(&sport->port.lock, flags);
272 imx_mctrl_check(sport);
273 spin_unlock_irqrestore(&sport->port.lock, flags);
274
275 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
276 }
277 }
278
279 /*
280 * interrupts disabled on entry
281 */
282 static void imx_stop_tx(struct uart_port *port)
283 {
284 struct imx_port *sport = (struct imx_port *)port;
285 unsigned long temp;
286
287 if (USE_IRDA(sport)) {
288 /* half duplex - wait for end of transmission */
289 int n = 256;
290 while ((--n > 0) &&
291 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
292 udelay(5);
293 barrier();
294 }
295 /*
296 * irda transceiver - wait a bit more to avoid
297 * cutoff, hardware dependent
298 */
299 udelay(sport->trcv_delay);
300
301 /*
302 * half duplex - reactivate receive mode,
303 * flush receive pipe echo crap
304 */
305 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
306 temp = readl(sport->port.membase + UCR1);
307 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
308 writel(temp, sport->port.membase + UCR1);
309
310 temp = readl(sport->port.membase + UCR4);
311 temp &= ~(UCR4_TCEN);
312 writel(temp, sport->port.membase + UCR4);
313
314 while (readl(sport->port.membase + URXD0) &
315 URXD_CHARRDY)
316 barrier();
317
318 temp = readl(sport->port.membase + UCR1);
319 temp |= UCR1_RRDYEN;
320 writel(temp, sport->port.membase + UCR1);
321
322 temp = readl(sport->port.membase + UCR4);
323 temp |= UCR4_DREN;
324 writel(temp, sport->port.membase + UCR4);
325 }
326 return;
327 }
328
329 temp = readl(sport->port.membase + UCR1);
330 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
331 }
332
333 /*
334 * interrupts disabled on entry
335 */
336 static void imx_stop_rx(struct uart_port *port)
337 {
338 struct imx_port *sport = (struct imx_port *)port;
339 unsigned long temp;
340
341 temp = readl(sport->port.membase + UCR2);
342 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
343 }
344
345 /*
346 * Set the modem control timer to fire immediately.
347 */
348 static void imx_enable_ms(struct uart_port *port)
349 {
350 struct imx_port *sport = (struct imx_port *)port;
351
352 mod_timer(&sport->timer, jiffies);
353 }
354
355 static inline void imx_transmit_buffer(struct imx_port *sport)
356 {
357 struct circ_buf *xmit = &sport->port.info->xmit;
358
359 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
360 /* send xmit->buf[xmit->tail]
361 * out the port here */
362 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
363 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
364 sport->port.icount.tx++;
365 if (uart_circ_empty(xmit))
366 break;
367 }
368
369 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
370 uart_write_wakeup(&sport->port);
371
372 if (uart_circ_empty(xmit))
373 imx_stop_tx(&sport->port);
374 }
375
376 /*
377 * interrupts disabled on entry
378 */
379 static void imx_start_tx(struct uart_port *port)
380 {
381 struct imx_port *sport = (struct imx_port *)port;
382 unsigned long temp;
383
384 if (USE_IRDA(sport)) {
385 /* half duplex in IrDA mode; have to disable receive mode */
386 temp = readl(sport->port.membase + UCR4);
387 temp &= ~(UCR4_DREN);
388 writel(temp, sport->port.membase + UCR4);
389
390 temp = readl(sport->port.membase + UCR1);
391 temp &= ~(UCR1_RRDYEN);
392 writel(temp, sport->port.membase + UCR1);
393 }
394
395 temp = readl(sport->port.membase + UCR1);
396 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
397
398 if (USE_IRDA(sport)) {
399 temp = readl(sport->port.membase + UCR1);
400 temp |= UCR1_TRDYEN;
401 writel(temp, sport->port.membase + UCR1);
402
403 temp = readl(sport->port.membase + UCR4);
404 temp |= UCR4_TCEN;
405 writel(temp, sport->port.membase + UCR4);
406 }
407
408 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
409 imx_transmit_buffer(sport);
410 }
411
412 static irqreturn_t imx_rtsint(int irq, void *dev_id)
413 {
414 struct imx_port *sport = dev_id;
415 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
416 unsigned long flags;
417
418 spin_lock_irqsave(&sport->port.lock, flags);
419
420 writel(USR1_RTSD, sport->port.membase + USR1);
421 uart_handle_cts_change(&sport->port, !!val);
422 wake_up_interruptible(&sport->port.info->delta_msr_wait);
423
424 spin_unlock_irqrestore(&sport->port.lock, flags);
425 return IRQ_HANDLED;
426 }
427
428 static irqreturn_t imx_txint(int irq, void *dev_id)
429 {
430 struct imx_port *sport = dev_id;
431 struct circ_buf *xmit = &sport->port.info->xmit;
432 unsigned long flags;
433
434 spin_lock_irqsave(&sport->port.lock,flags);
435 if (sport->port.x_char)
436 {
437 /* Send next char */
438 writel(sport->port.x_char, sport->port.membase + URTX0);
439 goto out;
440 }
441
442 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
443 imx_stop_tx(&sport->port);
444 goto out;
445 }
446
447 imx_transmit_buffer(sport);
448
449 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
450 uart_write_wakeup(&sport->port);
451
452 out:
453 spin_unlock_irqrestore(&sport->port.lock,flags);
454 return IRQ_HANDLED;
455 }
456
457 static irqreturn_t imx_rxint(int irq, void *dev_id)
458 {
459 struct imx_port *sport = dev_id;
460 unsigned int rx,flg,ignored = 0;
461 struct tty_struct *tty = sport->port.info->port.tty;
462 unsigned long flags, temp;
463
464 spin_lock_irqsave(&sport->port.lock,flags);
465
466 while (readl(sport->port.membase + USR2) & USR2_RDR) {
467 flg = TTY_NORMAL;
468 sport->port.icount.rx++;
469
470 rx = readl(sport->port.membase + URXD0);
471
472 temp = readl(sport->port.membase + USR2);
473 if (temp & USR2_BRCD) {
474 writel(temp | USR2_BRCD, sport->port.membase + USR2);
475 if (uart_handle_break(&sport->port))
476 continue;
477 }
478
479 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
480 continue;
481
482 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
483 if (rx & URXD_PRERR)
484 sport->port.icount.parity++;
485 else if (rx & URXD_FRMERR)
486 sport->port.icount.frame++;
487 if (rx & URXD_OVRRUN)
488 sport->port.icount.overrun++;
489
490 if (rx & sport->port.ignore_status_mask) {
491 if (++ignored > 100)
492 goto out;
493 continue;
494 }
495
496 rx &= sport->port.read_status_mask;
497
498 if (rx & URXD_PRERR)
499 flg = TTY_PARITY;
500 else if (rx & URXD_FRMERR)
501 flg = TTY_FRAME;
502 if (rx & URXD_OVRRUN)
503 flg = TTY_OVERRUN;
504
505 #ifdef SUPPORT_SYSRQ
506 sport->port.sysrq = 0;
507 #endif
508 }
509
510 tty_insert_flip_char(tty, rx, flg);
511 }
512
513 out:
514 spin_unlock_irqrestore(&sport->port.lock,flags);
515 tty_flip_buffer_push(tty);
516 return IRQ_HANDLED;
517 }
518
519 static irqreturn_t imx_int(int irq, void *dev_id)
520 {
521 struct imx_port *sport = dev_id;
522 unsigned int sts;
523
524 sts = readl(sport->port.membase + USR1);
525
526 if (sts & USR1_RRDY)
527 imx_rxint(irq, dev_id);
528
529 if (sts & USR1_TRDY &&
530 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
531 imx_txint(irq, dev_id);
532
533 if (sts & USR1_RTSD)
534 imx_rtsint(irq, dev_id);
535
536 return IRQ_HANDLED;
537 }
538
539 /*
540 * Return TIOCSER_TEMT when transmitter is not busy.
541 */
542 static unsigned int imx_tx_empty(struct uart_port *port)
543 {
544 struct imx_port *sport = (struct imx_port *)port;
545
546 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
547 }
548
549 /*
550 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
551 */
552 static unsigned int imx_get_mctrl(struct uart_port *port)
553 {
554 struct imx_port *sport = (struct imx_port *)port;
555 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
556
557 if (readl(sport->port.membase + USR1) & USR1_RTSS)
558 tmp |= TIOCM_CTS;
559
560 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
561 tmp |= TIOCM_RTS;
562
563 return tmp;
564 }
565
566 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
567 {
568 struct imx_port *sport = (struct imx_port *)port;
569 unsigned long temp;
570
571 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
572
573 if (mctrl & TIOCM_RTS)
574 temp |= UCR2_CTS;
575
576 writel(temp, sport->port.membase + UCR2);
577 }
578
579 /*
580 * Interrupts always disabled.
581 */
582 static void imx_break_ctl(struct uart_port *port, int break_state)
583 {
584 struct imx_port *sport = (struct imx_port *)port;
585 unsigned long flags, temp;
586
587 spin_lock_irqsave(&sport->port.lock, flags);
588
589 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
590
591 if ( break_state != 0 )
592 temp |= UCR1_SNDBRK;
593
594 writel(temp, sport->port.membase + UCR1);
595
596 spin_unlock_irqrestore(&sport->port.lock, flags);
597 }
598
599 #define TXTL 2 /* reset default */
600 #define RXTL 1 /* reset default */
601
602 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
603 {
604 unsigned int val;
605 unsigned int ufcr_rfdiv;
606
607 /* set receiver / transmitter trigger level.
608 * RFDIV is set such way to satisfy requested uartclk value
609 */
610 val = TXTL << 10 | RXTL;
611 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
612 / sport->port.uartclk;
613
614 if(!ufcr_rfdiv)
615 ufcr_rfdiv = 1;
616
617 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
618
619 writel(val, sport->port.membase + UFCR);
620
621 return 0;
622 }
623
624 static int imx_startup(struct uart_port *port)
625 {
626 struct imx_port *sport = (struct imx_port *)port;
627 int retval;
628 unsigned long flags, temp;
629
630 imx_setup_ufcr(sport, 0);
631
632 /* disable the DREN bit (Data Ready interrupt enable) before
633 * requesting IRQs
634 */
635 temp = readl(sport->port.membase + UCR4);
636
637 if (USE_IRDA(sport))
638 temp |= UCR4_IRSC;
639
640 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
641
642 if (USE_IRDA(sport)) {
643 /* reset fifo's and state machines */
644 int i = 100;
645 temp = readl(sport->port.membase + UCR2);
646 temp &= ~UCR2_SRST;
647 writel(temp, sport->port.membase + UCR2);
648 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
649 (--i > 0)) {
650 udelay(1);
651 }
652 }
653
654 /*
655 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
656 * chips only have one interrupt.
657 */
658 if (sport->txirq > 0) {
659 retval = request_irq(sport->rxirq, imx_rxint, 0,
660 DRIVER_NAME, sport);
661 if (retval)
662 goto error_out1;
663
664 retval = request_irq(sport->txirq, imx_txint, 0,
665 DRIVER_NAME, sport);
666 if (retval)
667 goto error_out2;
668
669 /* do not use RTS IRQ on IrDA */
670 if (!USE_IRDA(sport)) {
671 retval = request_irq(sport->rtsirq, imx_rtsint,
672 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
673 IRQF_TRIGGER_FALLING |
674 IRQF_TRIGGER_RISING,
675 DRIVER_NAME, sport);
676 if (retval)
677 goto error_out3;
678 }
679 } else {
680 retval = request_irq(sport->port.irq, imx_int, 0,
681 DRIVER_NAME, sport);
682 if (retval) {
683 free_irq(sport->port.irq, sport);
684 goto error_out1;
685 }
686 }
687
688 /*
689 * Finally, clear and enable interrupts
690 */
691 writel(USR1_RTSD, sport->port.membase + USR1);
692
693 temp = readl(sport->port.membase + UCR1);
694 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
695
696 if (USE_IRDA(sport)) {
697 temp |= UCR1_IREN;
698 temp &= ~(UCR1_RTSDEN);
699 }
700
701 writel(temp, sport->port.membase + UCR1);
702
703 temp = readl(sport->port.membase + UCR2);
704 temp |= (UCR2_RXEN | UCR2_TXEN);
705 writel(temp, sport->port.membase + UCR2);
706
707 if (USE_IRDA(sport)) {
708 /* clear RX-FIFO */
709 int i = 64;
710 while ((--i > 0) &&
711 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
712 barrier();
713 }
714 }
715
716 #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
717 temp = readl(sport->port.membase + UCR3);
718 temp |= UCR3_RXDMUXSEL;
719 writel(temp, sport->port.membase + UCR3);
720 #endif
721
722 if (USE_IRDA(sport)) {
723 temp = readl(sport->port.membase + UCR4);
724 if (sport->irda_inv_rx)
725 temp |= UCR4_INVR;
726 else
727 temp &= ~(UCR4_INVR);
728 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
729
730 temp = readl(sport->port.membase + UCR3);
731 if (sport->irda_inv_tx)
732 temp |= UCR3_INVT;
733 else
734 temp &= ~(UCR3_INVT);
735 writel(temp, sport->port.membase + UCR3);
736 }
737
738 /*
739 * Enable modem status interrupts
740 */
741 spin_lock_irqsave(&sport->port.lock,flags);
742 imx_enable_ms(&sport->port);
743 spin_unlock_irqrestore(&sport->port.lock,flags);
744
745 if (USE_IRDA(sport)) {
746 struct imxuart_platform_data *pdata;
747 pdata = sport->port.dev->platform_data;
748 sport->irda_inv_rx = pdata->irda_inv_rx;
749 sport->irda_inv_tx = pdata->irda_inv_tx;
750 sport->trcv_delay = pdata->transceiver_delay;
751 if (pdata->irda_enable)
752 pdata->irda_enable(1);
753 }
754
755 return 0;
756
757 error_out3:
758 if (sport->txirq)
759 free_irq(sport->txirq, sport);
760 error_out2:
761 if (sport->rxirq)
762 free_irq(sport->rxirq, sport);
763 error_out1:
764 return retval;
765 }
766
767 static void imx_shutdown(struct uart_port *port)
768 {
769 struct imx_port *sport = (struct imx_port *)port;
770 unsigned long temp;
771
772 temp = readl(sport->port.membase + UCR2);
773 temp &= ~(UCR2_TXEN);
774 writel(temp, sport->port.membase + UCR2);
775
776 if (USE_IRDA(sport)) {
777 struct imxuart_platform_data *pdata;
778 pdata = sport->port.dev->platform_data;
779 if (pdata->irda_enable)
780 pdata->irda_enable(0);
781 }
782
783 /*
784 * Stop our timer.
785 */
786 del_timer_sync(&sport->timer);
787
788 /*
789 * Free the interrupts
790 */
791 if (sport->txirq > 0) {
792 if (!USE_IRDA(sport))
793 free_irq(sport->rtsirq, sport);
794 free_irq(sport->txirq, sport);
795 free_irq(sport->rxirq, sport);
796 } else
797 free_irq(sport->port.irq, sport);
798
799 /*
800 * Disable all interrupts, port and break condition.
801 */
802
803 temp = readl(sport->port.membase + UCR1);
804 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
805 if (USE_IRDA(sport))
806 temp &= ~(UCR1_IREN);
807
808 writel(temp, sport->port.membase + UCR1);
809 }
810
811 static void
812 imx_set_termios(struct uart_port *port, struct ktermios *termios,
813 struct ktermios *old)
814 {
815 struct imx_port *sport = (struct imx_port *)port;
816 unsigned long flags;
817 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
818 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
819 unsigned int div, ufcr;
820 unsigned long num, denom;
821 uint64_t tdiv64;
822
823 /*
824 * If we don't support modem control lines, don't allow
825 * these to be set.
826 */
827 if (0) {
828 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
829 termios->c_cflag |= CLOCAL;
830 }
831
832 /*
833 * We only support CS7 and CS8.
834 */
835 while ((termios->c_cflag & CSIZE) != CS7 &&
836 (termios->c_cflag & CSIZE) != CS8) {
837 termios->c_cflag &= ~CSIZE;
838 termios->c_cflag |= old_csize;
839 old_csize = CS8;
840 }
841
842 if ((termios->c_cflag & CSIZE) == CS8)
843 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
844 else
845 ucr2 = UCR2_SRST | UCR2_IRTS;
846
847 if (termios->c_cflag & CRTSCTS) {
848 if( sport->have_rtscts ) {
849 ucr2 &= ~UCR2_IRTS;
850 ucr2 |= UCR2_CTSC;
851 } else {
852 termios->c_cflag &= ~CRTSCTS;
853 }
854 }
855
856 if (termios->c_cflag & CSTOPB)
857 ucr2 |= UCR2_STPB;
858 if (termios->c_cflag & PARENB) {
859 ucr2 |= UCR2_PREN;
860 if (termios->c_cflag & PARODD)
861 ucr2 |= UCR2_PROE;
862 }
863
864 /*
865 * Ask the core to calculate the divisor for us.
866 */
867 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
868 quot = uart_get_divisor(port, baud);
869
870 spin_lock_irqsave(&sport->port.lock, flags);
871
872 sport->port.read_status_mask = 0;
873 if (termios->c_iflag & INPCK)
874 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
875 if (termios->c_iflag & (BRKINT | PARMRK))
876 sport->port.read_status_mask |= URXD_BRK;
877
878 /*
879 * Characters to ignore
880 */
881 sport->port.ignore_status_mask = 0;
882 if (termios->c_iflag & IGNPAR)
883 sport->port.ignore_status_mask |= URXD_PRERR;
884 if (termios->c_iflag & IGNBRK) {
885 sport->port.ignore_status_mask |= URXD_BRK;
886 /*
887 * If we're ignoring parity and break indicators,
888 * ignore overruns too (for real raw support).
889 */
890 if (termios->c_iflag & IGNPAR)
891 sport->port.ignore_status_mask |= URXD_OVRRUN;
892 }
893
894 del_timer_sync(&sport->timer);
895
896 /*
897 * Update the per-port timeout.
898 */
899 uart_update_timeout(port, termios->c_cflag, baud);
900
901 /*
902 * disable interrupts and drain transmitter
903 */
904 old_ucr1 = readl(sport->port.membase + UCR1);
905 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
906 sport->port.membase + UCR1);
907
908 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
909 barrier();
910
911 /* then, disable everything */
912 old_txrxen = readl(sport->port.membase + UCR2);
913 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
914 sport->port.membase + UCR2);
915 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
916
917 if (USE_IRDA(sport)) {
918 /*
919 * use maximum available submodule frequency to
920 * avoid missing short pulses due to low sampling rate
921 */
922 div = 1;
923 } else {
924 div = sport->port.uartclk / (baud * 16);
925 if (div > 7)
926 div = 7;
927 if (!div)
928 div = 1;
929 }
930
931 rational_best_approximation(16 * div * baud, sport->port.uartclk,
932 1 << 16, 1 << 16, &num, &denom);
933
934 tdiv64 = sport->port.uartclk;
935 tdiv64 *= num;
936 do_div(tdiv64, denom * 16 * div);
937 tty_encode_baud_rate(sport->port.info->port.tty,
938 (speed_t)tdiv64, (speed_t)tdiv64);
939
940 num -= 1;
941 denom -= 1;
942
943 ufcr = readl(sport->port.membase + UFCR);
944 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
945 writel(ufcr, sport->port.membase + UFCR);
946
947 writel(num, sport->port.membase + UBIR);
948 writel(denom, sport->port.membase + UBMR);
949
950 #ifdef ONEMS
951 writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
952 #endif
953
954 writel(old_ucr1, sport->port.membase + UCR1);
955
956 /* set the parity, stop bits and data size */
957 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
958
959 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
960 imx_enable_ms(&sport->port);
961
962 spin_unlock_irqrestore(&sport->port.lock, flags);
963 }
964
965 static const char *imx_type(struct uart_port *port)
966 {
967 struct imx_port *sport = (struct imx_port *)port;
968
969 return sport->port.type == PORT_IMX ? "IMX" : NULL;
970 }
971
972 /*
973 * Release the memory region(s) being used by 'port'.
974 */
975 static void imx_release_port(struct uart_port *port)
976 {
977 struct platform_device *pdev = to_platform_device(port->dev);
978 struct resource *mmres;
979
980 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
981 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
982 }
983
984 /*
985 * Request the memory region(s) being used by 'port'.
986 */
987 static int imx_request_port(struct uart_port *port)
988 {
989 struct platform_device *pdev = to_platform_device(port->dev);
990 struct resource *mmres;
991 void *ret;
992
993 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994 if (!mmres)
995 return -ENODEV;
996
997 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
998 "imx-uart");
999
1000 return ret ? 0 : -EBUSY;
1001 }
1002
1003 /*
1004 * Configure/autoconfigure the port.
1005 */
1006 static void imx_config_port(struct uart_port *port, int flags)
1007 {
1008 struct imx_port *sport = (struct imx_port *)port;
1009
1010 if (flags & UART_CONFIG_TYPE &&
1011 imx_request_port(&sport->port) == 0)
1012 sport->port.type = PORT_IMX;
1013 }
1014
1015 /*
1016 * Verify the new serial_struct (for TIOCSSERIAL).
1017 * The only change we allow are to the flags and type, and
1018 * even then only between PORT_IMX and PORT_UNKNOWN
1019 */
1020 static int
1021 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1022 {
1023 struct imx_port *sport = (struct imx_port *)port;
1024 int ret = 0;
1025
1026 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1027 ret = -EINVAL;
1028 if (sport->port.irq != ser->irq)
1029 ret = -EINVAL;
1030 if (ser->io_type != UPIO_MEM)
1031 ret = -EINVAL;
1032 if (sport->port.uartclk / 16 != ser->baud_base)
1033 ret = -EINVAL;
1034 if ((void *)sport->port.mapbase != ser->iomem_base)
1035 ret = -EINVAL;
1036 if (sport->port.iobase != ser->port)
1037 ret = -EINVAL;
1038 if (ser->hub6 != 0)
1039 ret = -EINVAL;
1040 return ret;
1041 }
1042
1043 static struct uart_ops imx_pops = {
1044 .tx_empty = imx_tx_empty,
1045 .set_mctrl = imx_set_mctrl,
1046 .get_mctrl = imx_get_mctrl,
1047 .stop_tx = imx_stop_tx,
1048 .start_tx = imx_start_tx,
1049 .stop_rx = imx_stop_rx,
1050 .enable_ms = imx_enable_ms,
1051 .break_ctl = imx_break_ctl,
1052 .startup = imx_startup,
1053 .shutdown = imx_shutdown,
1054 .set_termios = imx_set_termios,
1055 .type = imx_type,
1056 .release_port = imx_release_port,
1057 .request_port = imx_request_port,
1058 .config_port = imx_config_port,
1059 .verify_port = imx_verify_port,
1060 };
1061
1062 static struct imx_port *imx_ports[UART_NR];
1063
1064 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1065 static void imx_console_putchar(struct uart_port *port, int ch)
1066 {
1067 struct imx_port *sport = (struct imx_port *)port;
1068
1069 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
1070 barrier();
1071
1072 writel(ch, sport->port.membase + URTX0);
1073 }
1074
1075 /*
1076 * Interrupts are disabled on entering
1077 */
1078 static void
1079 imx_console_write(struct console *co, const char *s, unsigned int count)
1080 {
1081 struct imx_port *sport = imx_ports[co->index];
1082 unsigned int old_ucr1, old_ucr2;
1083
1084 /*
1085 * First, save UCR1/2 and then disable interrupts
1086 */
1087 old_ucr1 = readl(sport->port.membase + UCR1);
1088 old_ucr2 = readl(sport->port.membase + UCR2);
1089
1090 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
1091 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1092 sport->port.membase + UCR1);
1093
1094 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1095
1096 uart_console_write(&sport->port, s, count, imx_console_putchar);
1097
1098 /*
1099 * Finally, wait for transmitter to become empty
1100 * and restore UCR1/2
1101 */
1102 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1103
1104 writel(old_ucr1, sport->port.membase + UCR1);
1105 writel(old_ucr2, sport->port.membase + UCR2);
1106 }
1107
1108 /*
1109 * If the port was already initialised (eg, by a boot loader),
1110 * try to determine the current setup.
1111 */
1112 static void __init
1113 imx_console_get_options(struct imx_port *sport, int *baud,
1114 int *parity, int *bits)
1115 {
1116
1117 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
1118 /* ok, the port was enabled */
1119 unsigned int ucr2, ubir,ubmr, uartclk;
1120 unsigned int baud_raw;
1121 unsigned int ucfr_rfdiv;
1122
1123 ucr2 = readl(sport->port.membase + UCR2);
1124
1125 *parity = 'n';
1126 if (ucr2 & UCR2_PREN) {
1127 if (ucr2 & UCR2_PROE)
1128 *parity = 'o';
1129 else
1130 *parity = 'e';
1131 }
1132
1133 if (ucr2 & UCR2_WS)
1134 *bits = 8;
1135 else
1136 *bits = 7;
1137
1138 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1139 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1140
1141 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1142 if (ucfr_rfdiv == 6)
1143 ucfr_rfdiv = 7;
1144 else
1145 ucfr_rfdiv = 6 - ucfr_rfdiv;
1146
1147 uartclk = clk_get_rate(sport->clk);
1148 uartclk /= ucfr_rfdiv;
1149
1150 { /*
1151 * The next code provides exact computation of
1152 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1153 * without need of float support or long long division,
1154 * which would be required to prevent 32bit arithmetic overflow
1155 */
1156 unsigned int mul = ubir + 1;
1157 unsigned int div = 16 * (ubmr + 1);
1158 unsigned int rem = uartclk % div;
1159
1160 baud_raw = (uartclk / div) * mul;
1161 baud_raw += (rem * mul + div / 2) / div;
1162 *baud = (baud_raw + 50) / 100 * 100;
1163 }
1164
1165 if(*baud != baud_raw)
1166 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1167 baud_raw, *baud);
1168 }
1169 }
1170
1171 static int __init
1172 imx_console_setup(struct console *co, char *options)
1173 {
1174 struct imx_port *sport;
1175 int baud = 9600;
1176 int bits = 8;
1177 int parity = 'n';
1178 int flow = 'n';
1179
1180 /*
1181 * Check whether an invalid uart number has been specified, and
1182 * if so, search for the first available port that does have
1183 * console support.
1184 */
1185 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1186 co->index = 0;
1187 sport = imx_ports[co->index];
1188 if(sport == NULL)
1189 return -ENODEV;
1190
1191 if (options)
1192 uart_parse_options(options, &baud, &parity, &bits, &flow);
1193 else
1194 imx_console_get_options(sport, &baud, &parity, &bits);
1195
1196 imx_setup_ufcr(sport, 0);
1197
1198 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1199 }
1200
1201 static struct uart_driver imx_reg;
1202 static struct console imx_console = {
1203 .name = DEV_NAME,
1204 .write = imx_console_write,
1205 .device = uart_console_device,
1206 .setup = imx_console_setup,
1207 .flags = CON_PRINTBUFFER,
1208 .index = -1,
1209 .data = &imx_reg,
1210 };
1211
1212 #define IMX_CONSOLE &imx_console
1213 #else
1214 #define IMX_CONSOLE NULL
1215 #endif
1216
1217 static struct uart_driver imx_reg = {
1218 .owner = THIS_MODULE,
1219 .driver_name = DRIVER_NAME,
1220 .dev_name = DEV_NAME,
1221 .major = SERIAL_IMX_MAJOR,
1222 .minor = MINOR_START,
1223 .nr = ARRAY_SIZE(imx_ports),
1224 .cons = IMX_CONSOLE,
1225 };
1226
1227 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1228 {
1229 struct imx_port *sport = platform_get_drvdata(dev);
1230
1231 if (sport)
1232 uart_suspend_port(&imx_reg, &sport->port);
1233
1234 return 0;
1235 }
1236
1237 static int serial_imx_resume(struct platform_device *dev)
1238 {
1239 struct imx_port *sport = platform_get_drvdata(dev);
1240
1241 if (sport)
1242 uart_resume_port(&imx_reg, &sport->port);
1243
1244 return 0;
1245 }
1246
1247 static int serial_imx_probe(struct platform_device *pdev)
1248 {
1249 struct imx_port *sport;
1250 struct imxuart_platform_data *pdata;
1251 void __iomem *base;
1252 int ret = 0;
1253 struct resource *res;
1254
1255 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1256 if (!sport)
1257 return -ENOMEM;
1258
1259 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260 if (!res) {
1261 ret = -ENODEV;
1262 goto free;
1263 }
1264
1265 base = ioremap(res->start, PAGE_SIZE);
1266 if (!base) {
1267 ret = -ENOMEM;
1268 goto free;
1269 }
1270
1271 sport->port.dev = &pdev->dev;
1272 sport->port.mapbase = res->start;
1273 sport->port.membase = base;
1274 sport->port.type = PORT_IMX,
1275 sport->port.iotype = UPIO_MEM;
1276 sport->port.irq = platform_get_irq(pdev, 0);
1277 sport->rxirq = platform_get_irq(pdev, 0);
1278 sport->txirq = platform_get_irq(pdev, 1);
1279 sport->rtsirq = platform_get_irq(pdev, 2);
1280 sport->port.fifosize = 32;
1281 sport->port.ops = &imx_pops;
1282 sport->port.flags = UPF_BOOT_AUTOCONF;
1283 sport->port.line = pdev->id;
1284 init_timer(&sport->timer);
1285 sport->timer.function = imx_timeout;
1286 sport->timer.data = (unsigned long)sport;
1287
1288 sport->clk = clk_get(&pdev->dev, "uart");
1289 if (IS_ERR(sport->clk)) {
1290 ret = PTR_ERR(sport->clk);
1291 goto unmap;
1292 }
1293 clk_enable(sport->clk);
1294
1295 sport->port.uartclk = clk_get_rate(sport->clk);
1296
1297 imx_ports[pdev->id] = sport;
1298
1299 pdata = pdev->dev.platform_data;
1300 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1301 sport->have_rtscts = 1;
1302
1303 #ifdef CONFIG_IRDA
1304 if (pdata && (pdata->flags & IMXUART_IRDA))
1305 sport->use_irda = 1;
1306 #endif
1307
1308 if (pdata->init) {
1309 ret = pdata->init(pdev);
1310 if (ret)
1311 goto clkput;
1312 }
1313
1314 ret = uart_add_one_port(&imx_reg, &sport->port);
1315 if (ret)
1316 goto deinit;
1317 platform_set_drvdata(pdev, &sport->port);
1318
1319 return 0;
1320 deinit:
1321 if (pdata->exit)
1322 pdata->exit(pdev);
1323 clkput:
1324 clk_put(sport->clk);
1325 clk_disable(sport->clk);
1326 unmap:
1327 iounmap(sport->port.membase);
1328 free:
1329 kfree(sport);
1330
1331 return ret;
1332 }
1333
1334 static int serial_imx_remove(struct platform_device *pdev)
1335 {
1336 struct imxuart_platform_data *pdata;
1337 struct imx_port *sport = platform_get_drvdata(pdev);
1338
1339 pdata = pdev->dev.platform_data;
1340
1341 platform_set_drvdata(pdev, NULL);
1342
1343 if (sport) {
1344 uart_remove_one_port(&imx_reg, &sport->port);
1345 clk_put(sport->clk);
1346 }
1347
1348 clk_disable(sport->clk);
1349
1350 if (pdata->exit)
1351 pdata->exit(pdev);
1352
1353 iounmap(sport->port.membase);
1354 kfree(sport);
1355
1356 return 0;
1357 }
1358
1359 static struct platform_driver serial_imx_driver = {
1360 .probe = serial_imx_probe,
1361 .remove = serial_imx_remove,
1362
1363 .suspend = serial_imx_suspend,
1364 .resume = serial_imx_resume,
1365 .driver = {
1366 .name = "imx-uart",
1367 .owner = THIS_MODULE,
1368 },
1369 };
1370
1371 static int __init imx_serial_init(void)
1372 {
1373 int ret;
1374
1375 printk(KERN_INFO "Serial: IMX driver\n");
1376
1377 ret = uart_register_driver(&imx_reg);
1378 if (ret)
1379 return ret;
1380
1381 ret = platform_driver_register(&serial_imx_driver);
1382 if (ret != 0)
1383 uart_unregister_driver(&imx_reg);
1384
1385 return 0;
1386 }
1387
1388 static void __exit imx_serial_exit(void)
1389 {
1390 platform_driver_unregister(&serial_imx_driver);
1391 uart_unregister_driver(&imx_reg);
1392 }
1393
1394 module_init(imx_serial_init);
1395 module_exit(imx_serial_exit);
1396
1397 MODULE_AUTHOR("Sascha Hauer");
1398 MODULE_DESCRIPTION("IMX generic serial port driver");
1399 MODULE_LICENSE("GPL");
1400 MODULE_ALIAS("platform:imx-uart");
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