]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/serial/ip22zilog.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[mirror_ubuntu-bionic-kernel.git] / drivers / serial / ip22zilog.c
1 /*
2 * Driver for Zilog serial chips found on SGI workstations and
3 * servers. This driver could actually be made more generic.
4 *
5 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
6 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
7 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over
8 * directly from there but much has been rewritten. Credits therefore go out
9 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
10 * for their work there.
11 *
12 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
14 */
15 #include <linux/config.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/errno.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/major.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/circ_buf.h>
29 #include <linux/serial.h>
30 #include <linux/sysrq.h>
31 #include <linux/console.h>
32 #include <linux/spinlock.h>
33 #include <linux/init.h>
34
35 #include <asm/io.h>
36 #include <asm/irq.h>
37 #include <asm/sgialib.h>
38 #include <asm/sgi/ioc.h>
39 #include <asm/sgi/hpc3.h>
40 #include <asm/sgi/ip22.h>
41
42 #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43 #define SUPPORT_SYSRQ
44 #endif
45
46 #include <linux/serial_core.h>
47
48 #include "ip22zilog.h"
49
50 void ip22_do_break(void);
51
52 /*
53 * On IP22 we need to delay after register accesses but we do not need to
54 * flush writes.
55 */
56 #define ZSDELAY() udelay(5)
57 #define ZSDELAY_LONG() udelay(20)
58 #define ZS_WSYNC(channel) do { } while (0)
59
60 #define NUM_IP22ZILOG 1
61 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
62
63 #define ZS_CLOCK 3672000 /* Zilog input clock rate. */
64 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
65
66 /*
67 * We wrap our port structure around the generic uart_port.
68 */
69 struct uart_ip22zilog_port {
70 struct uart_port port;
71
72 /* IRQ servicing chain. */
73 struct uart_ip22zilog_port *next;
74
75 /* Current values of Zilog write registers. */
76 unsigned char curregs[NUM_ZSREGS];
77
78 unsigned int flags;
79 #define IP22ZILOG_FLAG_IS_CONS 0x00000004
80 #define IP22ZILOG_FLAG_IS_KGDB 0x00000008
81 #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
82 #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
83 #define IP22ZILOG_FLAG_REGS_HELD 0x00000040
84 #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
85 #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
86
87 unsigned int cflag;
88
89 /* L1-A keyboard break state. */
90 int kbd_id;
91 int l1_down;
92
93 unsigned char parity_mask;
94 unsigned char prev_status;
95 };
96
97 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
98 #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
99 #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
100 (UART_ZILOG(PORT)->curregs[REGNUM])
101 #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
102 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
103 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
104 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
105 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
106 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
107 #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
108 #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
109 #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
110
111 /* Reading and writing Zilog8530 registers. The delays are to make this
112 * driver work on the IP22 which needs a settling delay after each chip
113 * register access, other machines handle this in hardware via auxiliary
114 * flip-flops which implement the settle time we do in software.
115 *
116 * The port lock must be held and local IRQs must be disabled
117 * when {read,write}_zsreg is invoked.
118 */
119 static unsigned char read_zsreg(struct zilog_channel *channel,
120 unsigned char reg)
121 {
122 unsigned char retval;
123
124 writeb(reg, &channel->control);
125 ZSDELAY();
126 retval = readb(&channel->control);
127 ZSDELAY();
128
129 return retval;
130 }
131
132 static void write_zsreg(struct zilog_channel *channel,
133 unsigned char reg, unsigned char value)
134 {
135 writeb(reg, &channel->control);
136 ZSDELAY();
137 writeb(value, &channel->control);
138 ZSDELAY();
139 }
140
141 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
142 {
143 int i;
144
145 for (i = 0; i < 32; i++) {
146 unsigned char regval;
147
148 regval = readb(&channel->control);
149 ZSDELAY();
150 if (regval & Rx_CH_AV)
151 break;
152
153 regval = read_zsreg(channel, R1);
154 readb(&channel->data);
155 ZSDELAY();
156
157 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
158 writeb(ERR_RES, &channel->control);
159 ZSDELAY();
160 ZS_WSYNC(channel);
161 }
162 }
163 }
164
165 /* This function must only be called when the TX is not busy. The UART
166 * port lock must be held and local interrupts disabled.
167 */
168 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
169 {
170 int i;
171
172 /* Let pending transmits finish. */
173 for (i = 0; i < 1000; i++) {
174 unsigned char stat = read_zsreg(channel, R1);
175 if (stat & ALL_SNT)
176 break;
177 udelay(100);
178 }
179
180 writeb(ERR_RES, &channel->control);
181 ZSDELAY();
182 ZS_WSYNC(channel);
183
184 ip22zilog_clear_fifo(channel);
185
186 /* Disable all interrupts. */
187 write_zsreg(channel, R1,
188 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
189
190 /* Set parity, sync config, stop bits, and clock divisor. */
191 write_zsreg(channel, R4, regs[R4]);
192
193 /* Set misc. TX/RX control bits. */
194 write_zsreg(channel, R10, regs[R10]);
195
196 /* Set TX/RX controls sans the enable bits. */
197 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
198 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
199
200 /* Synchronous mode config. */
201 write_zsreg(channel, R6, regs[R6]);
202 write_zsreg(channel, R7, regs[R7]);
203
204 /* Don't mess with the interrupt vector (R2, unused by us) and
205 * master interrupt control (R9). We make sure this is setup
206 * properly at probe time then never touch it again.
207 */
208
209 /* Disable baud generator. */
210 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
211
212 /* Clock mode control. */
213 write_zsreg(channel, R11, regs[R11]);
214
215 /* Lower and upper byte of baud rate generator divisor. */
216 write_zsreg(channel, R12, regs[R12]);
217 write_zsreg(channel, R13, regs[R13]);
218
219 /* Now rewrite R14, with BRENAB (if set). */
220 write_zsreg(channel, R14, regs[R14]);
221
222 /* External status interrupt control. */
223 write_zsreg(channel, R15, regs[R15]);
224
225 /* Reset external status interrupts. */
226 write_zsreg(channel, R0, RES_EXT_INT);
227 write_zsreg(channel, R0, RES_EXT_INT);
228
229 /* Rewrite R3/R5, this time without enables masked. */
230 write_zsreg(channel, R3, regs[R3]);
231 write_zsreg(channel, R5, regs[R5]);
232
233 /* Rewrite R1, this time without IRQ enabled masked. */
234 write_zsreg(channel, R1, regs[R1]);
235 }
236
237 /* Reprogram the Zilog channel HW registers with the copies found in the
238 * software state struct. If the transmitter is busy, we defer this update
239 * until the next TX complete interrupt. Else, we do it right now.
240 *
241 * The UART port lock must be held and local interrupts disabled.
242 */
243 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
244 struct zilog_channel *channel)
245 {
246 if (!ZS_REGS_HELD(up)) {
247 if (ZS_TX_ACTIVE(up)) {
248 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
249 } else {
250 __load_zsregs(channel, up->curregs);
251 }
252 }
253 }
254
255 static void ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
256 struct zilog_channel *channel,
257 struct pt_regs *regs)
258 {
259 struct tty_struct *tty = up->port.info->tty; /* XXX info==NULL? */
260
261 while (1) {
262 unsigned char ch, r1, flag;
263
264 r1 = read_zsreg(channel, R1);
265 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
266 writeb(ERR_RES, &channel->control);
267 ZSDELAY();
268 ZS_WSYNC(channel);
269 }
270
271 ch = readb(&channel->control);
272 ZSDELAY();
273
274 /* This funny hack depends upon BRK_ABRT not interfering
275 * with the other bits we care about in R1.
276 */
277 if (ch & BRK_ABRT)
278 r1 |= BRK_ABRT;
279
280 ch = readb(&channel->data);
281 ZSDELAY();
282
283 ch &= up->parity_mask;
284
285 if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) {
286 /* Wait for BREAK to deassert to avoid potentially
287 * confusing the PROM.
288 */
289 while (1) {
290 ch = readb(&channel->control);
291 ZSDELAY();
292 if (!(ch & BRK_ABRT))
293 break;
294 }
295 ip22_do_break();
296 return;
297 }
298
299 /* A real serial line, record the character and status. */
300 flag = TTY_NORMAL;
301 up->port.icount.rx++;
302 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
303 if (r1 & BRK_ABRT) {
304 r1 &= ~(PAR_ERR | CRC_ERR);
305 up->port.icount.brk++;
306 if (uart_handle_break(&up->port))
307 goto next_char;
308 }
309 else if (r1 & PAR_ERR)
310 up->port.icount.parity++;
311 else if (r1 & CRC_ERR)
312 up->port.icount.frame++;
313 if (r1 & Rx_OVR)
314 up->port.icount.overrun++;
315 r1 &= up->port.read_status_mask;
316 if (r1 & BRK_ABRT)
317 flag = TTY_BREAK;
318 else if (r1 & PAR_ERR)
319 flag = TTY_PARITY;
320 else if (r1 & CRC_ERR)
321 flag = TTY_FRAME;
322 }
323 if (uart_handle_sysrq_char(&up->port, ch, regs))
324 goto next_char;
325
326 if (up->port.ignore_status_mask == 0xff ||
327 (r1 & up->port.ignore_status_mask) == 0)
328 tty_insert_flip_char(tty, ch, flag);
329
330 if (r1 & Rx_OVR)
331 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
332 next_char:
333 ch = readb(&channel->control);
334 ZSDELAY();
335 if (!(ch & Rx_CH_AV))
336 break;
337 }
338
339 tty_flip_buffer_push(tty);
340 }
341
342 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
343 struct zilog_channel *channel,
344 struct pt_regs *regs)
345 {
346 unsigned char status;
347
348 status = readb(&channel->control);
349 ZSDELAY();
350
351 writeb(RES_EXT_INT, &channel->control);
352 ZSDELAY();
353 ZS_WSYNC(channel);
354
355 if (ZS_WANTS_MODEM_STATUS(up)) {
356 if (status & SYNC)
357 up->port.icount.dsr++;
358
359 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
360 * But it does not tell us which bit has changed, we have to keep
361 * track of this ourselves.
362 */
363 if ((status & DCD) ^ up->prev_status)
364 uart_handle_dcd_change(&up->port,
365 (status & DCD));
366 if ((status & CTS) ^ up->prev_status)
367 uart_handle_cts_change(&up->port,
368 (status & CTS));
369
370 wake_up_interruptible(&up->port.info->delta_msr_wait);
371 }
372
373 up->prev_status = status;
374 }
375
376 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
377 struct zilog_channel *channel)
378 {
379 struct circ_buf *xmit;
380
381 if (ZS_IS_CONS(up)) {
382 unsigned char status = readb(&channel->control);
383 ZSDELAY();
384
385 /* TX still busy? Just wait for the next TX done interrupt.
386 *
387 * It can occur because of how we do serial console writes. It would
388 * be nice to transmit console writes just like we normally would for
389 * a TTY line. (ie. buffered and TX interrupt driven). That is not
390 * easy because console writes cannot sleep. One solution might be
391 * to poll on enough port->xmit space becomming free. -DaveM
392 */
393 if (!(status & Tx_BUF_EMP))
394 return;
395 }
396
397 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
398
399 if (ZS_REGS_HELD(up)) {
400 __load_zsregs(channel, up->curregs);
401 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
402 }
403
404 if (ZS_TX_STOPPED(up)) {
405 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
406 goto ack_tx_int;
407 }
408
409 if (up->port.x_char) {
410 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
411 writeb(up->port.x_char, &channel->data);
412 ZSDELAY();
413 ZS_WSYNC(channel);
414
415 up->port.icount.tx++;
416 up->port.x_char = 0;
417 return;
418 }
419
420 if (up->port.info == NULL)
421 goto ack_tx_int;
422 xmit = &up->port.info->xmit;
423 if (uart_circ_empty(xmit)) {
424 uart_write_wakeup(&up->port);
425 goto ack_tx_int;
426 }
427 if (uart_tx_stopped(&up->port))
428 goto ack_tx_int;
429
430 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
431 writeb(xmit->buf[xmit->tail], &channel->data);
432 ZSDELAY();
433 ZS_WSYNC(channel);
434
435 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
436 up->port.icount.tx++;
437
438 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
439 uart_write_wakeup(&up->port);
440
441 return;
442
443 ack_tx_int:
444 writeb(RES_Tx_P, &channel->control);
445 ZSDELAY();
446 ZS_WSYNC(channel);
447 }
448
449 static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
450 {
451 struct uart_ip22zilog_port *up = dev_id;
452
453 while (up) {
454 struct zilog_channel *channel
455 = ZILOG_CHANNEL_FROM_PORT(&up->port);
456 unsigned char r3;
457
458 spin_lock(&up->port.lock);
459 r3 = read_zsreg(channel, R3);
460
461 /* Channel A */
462 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
463 writeb(RES_H_IUS, &channel->control);
464 ZSDELAY();
465 ZS_WSYNC(channel);
466
467 if (r3 & CHARxIP)
468 ip22zilog_receive_chars(up, channel, regs);
469 if (r3 & CHAEXT)
470 ip22zilog_status_handle(up, channel, regs);
471 if (r3 & CHATxIP)
472 ip22zilog_transmit_chars(up, channel);
473 }
474 spin_unlock(&up->port.lock);
475
476 /* Channel B */
477 up = up->next;
478 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
479
480 spin_lock(&up->port.lock);
481 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
482 writeb(RES_H_IUS, &channel->control);
483 ZSDELAY();
484 ZS_WSYNC(channel);
485
486 if (r3 & CHBRxIP)
487 ip22zilog_receive_chars(up, channel, regs);
488 if (r3 & CHBEXT)
489 ip22zilog_status_handle(up, channel, regs);
490 if (r3 & CHBTxIP)
491 ip22zilog_transmit_chars(up, channel);
492 }
493 spin_unlock(&up->port.lock);
494
495 up = up->next;
496 }
497
498 return IRQ_HANDLED;
499 }
500
501 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
502 * port lock, it is acquired here.
503 */
504 static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
505 {
506 struct zilog_channel *channel;
507 unsigned char status;
508
509 channel = ZILOG_CHANNEL_FROM_PORT(port);
510 status = readb(&channel->control);
511 ZSDELAY();
512
513 return status;
514 }
515
516 /* The port lock is not held. */
517 static unsigned int ip22zilog_tx_empty(struct uart_port *port)
518 {
519 unsigned long flags;
520 unsigned char status;
521 unsigned int ret;
522
523 spin_lock_irqsave(&port->lock, flags);
524
525 status = ip22zilog_read_channel_status(port);
526
527 spin_unlock_irqrestore(&port->lock, flags);
528
529 if (status & Tx_BUF_EMP)
530 ret = TIOCSER_TEMT;
531 else
532 ret = 0;
533
534 return ret;
535 }
536
537 /* The port lock is held and interrupts are disabled. */
538 static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
539 {
540 unsigned char status;
541 unsigned int ret;
542
543 status = ip22zilog_read_channel_status(port);
544
545 ret = 0;
546 if (status & DCD)
547 ret |= TIOCM_CAR;
548 if (status & SYNC)
549 ret |= TIOCM_DSR;
550 if (status & CTS)
551 ret |= TIOCM_CTS;
552
553 return ret;
554 }
555
556 /* The port lock is held and interrupts are disabled. */
557 static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
558 {
559 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
560 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
561 unsigned char set_bits, clear_bits;
562
563 set_bits = clear_bits = 0;
564
565 if (mctrl & TIOCM_RTS)
566 set_bits |= RTS;
567 else
568 clear_bits |= RTS;
569 if (mctrl & TIOCM_DTR)
570 set_bits |= DTR;
571 else
572 clear_bits |= DTR;
573
574 /* NOTE: Not subject to 'transmitter active' rule. */
575 up->curregs[R5] |= set_bits;
576 up->curregs[R5] &= ~clear_bits;
577 write_zsreg(channel, R5, up->curregs[R5]);
578 }
579
580 /* The port lock is held and interrupts are disabled. */
581 static void ip22zilog_stop_tx(struct uart_port *port)
582 {
583 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
584
585 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
586 }
587
588 /* The port lock is held and interrupts are disabled. */
589 static void ip22zilog_start_tx(struct uart_port *port)
590 {
591 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
592 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
593 unsigned char status;
594
595 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
596 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
597
598 status = readb(&channel->control);
599 ZSDELAY();
600
601 /* TX busy? Just wait for the TX done interrupt. */
602 if (!(status & Tx_BUF_EMP))
603 return;
604
605 /* Send the first character to jump-start the TX done
606 * IRQ sending engine.
607 */
608 if (port->x_char) {
609 writeb(port->x_char, &channel->data);
610 ZSDELAY();
611 ZS_WSYNC(channel);
612
613 port->icount.tx++;
614 port->x_char = 0;
615 } else {
616 struct circ_buf *xmit = &port->info->xmit;
617
618 writeb(xmit->buf[xmit->tail], &channel->data);
619 ZSDELAY();
620 ZS_WSYNC(channel);
621
622 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
623 port->icount.tx++;
624
625 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
626 uart_write_wakeup(&up->port);
627 }
628 }
629
630 /* The port lock is held and interrupts are disabled. */
631 static void ip22zilog_stop_rx(struct uart_port *port)
632 {
633 struct uart_ip22zilog_port *up = UART_ZILOG(port);
634 struct zilog_channel *channel;
635
636 if (ZS_IS_CONS(up))
637 return;
638
639 channel = ZILOG_CHANNEL_FROM_PORT(port);
640
641 /* Disable all RX interrupts. */
642 up->curregs[R1] &= ~RxINT_MASK;
643 ip22zilog_maybe_update_regs(up, channel);
644 }
645
646 /* The port lock is held. */
647 static void ip22zilog_enable_ms(struct uart_port *port)
648 {
649 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
650 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
651 unsigned char new_reg;
652
653 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
654 if (new_reg != up->curregs[R15]) {
655 up->curregs[R15] = new_reg;
656
657 /* NOTE: Not subject to 'transmitter active' rule. */
658 write_zsreg(channel, R15, up->curregs[R15]);
659 }
660 }
661
662 /* The port lock is not held. */
663 static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
664 {
665 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
666 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
667 unsigned char set_bits, clear_bits, new_reg;
668 unsigned long flags;
669
670 set_bits = clear_bits = 0;
671
672 if (break_state)
673 set_bits |= SND_BRK;
674 else
675 clear_bits |= SND_BRK;
676
677 spin_lock_irqsave(&port->lock, flags);
678
679 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
680 if (new_reg != up->curregs[R5]) {
681 up->curregs[R5] = new_reg;
682
683 /* NOTE: Not subject to 'transmitter active' rule. */
684 write_zsreg(channel, R5, up->curregs[R5]);
685 }
686
687 spin_unlock_irqrestore(&port->lock, flags);
688 }
689
690 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
691 {
692 struct zilog_channel *channel;
693
694 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
695 up->prev_status = readb(&channel->control);
696
697 /* Enable receiver and transmitter. */
698 up->curregs[R3] |= RxENAB;
699 up->curregs[R5] |= TxENAB;
700
701 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
702 ip22zilog_maybe_update_regs(up, channel);
703 }
704
705 static int ip22zilog_startup(struct uart_port *port)
706 {
707 struct uart_ip22zilog_port *up = UART_ZILOG(port);
708 unsigned long flags;
709
710 if (ZS_IS_CONS(up))
711 return 0;
712
713 spin_lock_irqsave(&port->lock, flags);
714 __ip22zilog_startup(up);
715 spin_unlock_irqrestore(&port->lock, flags);
716 return 0;
717 }
718
719 /*
720 * The test for ZS_IS_CONS is explained by the following e-mail:
721 *****
722 * From: Russell King <rmk@arm.linux.org.uk>
723 * Date: Sun, 8 Dec 2002 10:18:38 +0000
724 *
725 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
726 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
727 * > and I noticed that something is not right with reference
728 * > counting in this case. It seems that when the console
729 * > is open by kernel initially, this is not accounted
730 * > as an open, and uart_startup is not called.
731 *
732 * That is correct. We are unable to call uart_startup when the serial
733 * console is initialised because it may need to allocate memory (as
734 * request_irq does) and the memory allocators may not have been
735 * initialised.
736 *
737 * 1. initialise the port into a state where it can send characters in the
738 * console write method.
739 *
740 * 2. don't do the actual hardware shutdown in your shutdown() method (but
741 * do the normal software shutdown - ie, free irqs etc)
742 *****
743 */
744 static void ip22zilog_shutdown(struct uart_port *port)
745 {
746 struct uart_ip22zilog_port *up = UART_ZILOG(port);
747 struct zilog_channel *channel;
748 unsigned long flags;
749
750 if (ZS_IS_CONS(up))
751 return;
752
753 spin_lock_irqsave(&port->lock, flags);
754
755 channel = ZILOG_CHANNEL_FROM_PORT(port);
756
757 /* Disable receiver and transmitter. */
758 up->curregs[R3] &= ~RxENAB;
759 up->curregs[R5] &= ~TxENAB;
760
761 /* Disable all interrupts and BRK assertion. */
762 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
763 up->curregs[R5] &= ~SND_BRK;
764 ip22zilog_maybe_update_regs(up, channel);
765
766 spin_unlock_irqrestore(&port->lock, flags);
767 }
768
769 /* Shared by TTY driver and serial console setup. The port lock is held
770 * and local interrupts are disabled.
771 */
772 static void
773 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
774 unsigned int iflag, int brg)
775 {
776
777 up->curregs[R10] = NRZ;
778 up->curregs[R11] = TCBR | RCBR;
779
780 /* Program BAUD and clock source. */
781 up->curregs[R4] &= ~XCLK_MASK;
782 up->curregs[R4] |= X16CLK;
783 up->curregs[R12] = brg & 0xff;
784 up->curregs[R13] = (brg >> 8) & 0xff;
785 up->curregs[R14] = BRENAB;
786
787 /* Character size, stop bits, and parity. */
788 up->curregs[3] &= ~RxN_MASK;
789 up->curregs[5] &= ~TxN_MASK;
790 switch (cflag & CSIZE) {
791 case CS5:
792 up->curregs[3] |= Rx5;
793 up->curregs[5] |= Tx5;
794 up->parity_mask = 0x1f;
795 break;
796 case CS6:
797 up->curregs[3] |= Rx6;
798 up->curregs[5] |= Tx6;
799 up->parity_mask = 0x3f;
800 break;
801 case CS7:
802 up->curregs[3] |= Rx7;
803 up->curregs[5] |= Tx7;
804 up->parity_mask = 0x7f;
805 break;
806 case CS8:
807 default:
808 up->curregs[3] |= Rx8;
809 up->curregs[5] |= Tx8;
810 up->parity_mask = 0xff;
811 break;
812 };
813 up->curregs[4] &= ~0x0c;
814 if (cflag & CSTOPB)
815 up->curregs[4] |= SB2;
816 else
817 up->curregs[4] |= SB1;
818 if (cflag & PARENB)
819 up->curregs[4] |= PAR_ENAB;
820 else
821 up->curregs[4] &= ~PAR_ENAB;
822 if (!(cflag & PARODD))
823 up->curregs[4] |= PAR_EVEN;
824 else
825 up->curregs[4] &= ~PAR_EVEN;
826
827 up->port.read_status_mask = Rx_OVR;
828 if (iflag & INPCK)
829 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
830 if (iflag & (BRKINT | PARMRK))
831 up->port.read_status_mask |= BRK_ABRT;
832
833 up->port.ignore_status_mask = 0;
834 if (iflag & IGNPAR)
835 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
836 if (iflag & IGNBRK) {
837 up->port.ignore_status_mask |= BRK_ABRT;
838 if (iflag & IGNPAR)
839 up->port.ignore_status_mask |= Rx_OVR;
840 }
841
842 if ((cflag & CREAD) == 0)
843 up->port.ignore_status_mask = 0xff;
844 }
845
846 /* The port lock is not held. */
847 static void
848 ip22zilog_set_termios(struct uart_port *port, struct termios *termios,
849 struct termios *old)
850 {
851 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
852 unsigned long flags;
853 int baud, brg;
854
855 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
856
857 spin_lock_irqsave(&up->port.lock, flags);
858
859 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
860
861 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
862
863 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
864 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
865 else
866 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
867
868 up->cflag = termios->c_cflag;
869
870 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
871
872 spin_unlock_irqrestore(&up->port.lock, flags);
873 }
874
875 static const char *ip22zilog_type(struct uart_port *port)
876 {
877 return "IP22-Zilog";
878 }
879
880 /* We do not request/release mappings of the registers here, this
881 * happens at early serial probe time.
882 */
883 static void ip22zilog_release_port(struct uart_port *port)
884 {
885 }
886
887 static int ip22zilog_request_port(struct uart_port *port)
888 {
889 return 0;
890 }
891
892 /* These do not need to do anything interesting either. */
893 static void ip22zilog_config_port(struct uart_port *port, int flags)
894 {
895 }
896
897 /* We do not support letting the user mess with the divisor, IRQ, etc. */
898 static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
899 {
900 return -EINVAL;
901 }
902
903 static struct uart_ops ip22zilog_pops = {
904 .tx_empty = ip22zilog_tx_empty,
905 .set_mctrl = ip22zilog_set_mctrl,
906 .get_mctrl = ip22zilog_get_mctrl,
907 .stop_tx = ip22zilog_stop_tx,
908 .start_tx = ip22zilog_start_tx,
909 .stop_rx = ip22zilog_stop_rx,
910 .enable_ms = ip22zilog_enable_ms,
911 .break_ctl = ip22zilog_break_ctl,
912 .startup = ip22zilog_startup,
913 .shutdown = ip22zilog_shutdown,
914 .set_termios = ip22zilog_set_termios,
915 .type = ip22zilog_type,
916 .release_port = ip22zilog_release_port,
917 .request_port = ip22zilog_request_port,
918 .config_port = ip22zilog_config_port,
919 .verify_port = ip22zilog_verify_port,
920 };
921
922 static struct uart_ip22zilog_port *ip22zilog_port_table;
923 static struct zilog_layout **ip22zilog_chip_regs;
924
925 static struct uart_ip22zilog_port *ip22zilog_irq_chain;
926 static int zilog_irq = -1;
927
928 static void * __init alloc_one_table(unsigned long size)
929 {
930 void *ret;
931
932 ret = kmalloc(size, GFP_KERNEL);
933 if (ret != NULL)
934 memset(ret, 0, size);
935
936 return ret;
937 }
938
939 static void __init ip22zilog_alloc_tables(void)
940 {
941 ip22zilog_port_table = (struct uart_ip22zilog_port *)
942 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
943 ip22zilog_chip_regs = (struct zilog_layout **)
944 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
945
946 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
947 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
948 }
949 }
950
951 /* Get the address of the registers for IP22-Zilog instance CHIP. */
952 static struct zilog_layout * __init get_zs(int chip)
953 {
954 unsigned long base;
955
956 if (chip < 0 || chip >= NUM_IP22ZILOG) {
957 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
958 }
959
960 /* Not probe-able, hard code it. */
961 base = (unsigned long) &sgioc->uart;
962
963 zilog_irq = SGI_SERIAL_IRQ;
964 request_mem_region(base, 8, "IP22-Zilog");
965
966 return (struct zilog_layout *) base;
967 }
968
969 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
970
971 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
972 static void ip22zilog_put_char(struct zilog_channel *channel, unsigned char ch)
973 {
974 int loops = ZS_PUT_CHAR_MAX_DELAY;
975
976 /* This is a timed polling loop so do not switch the explicit
977 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
978 */
979 do {
980 unsigned char val = readb(&channel->control);
981 if (val & Tx_BUF_EMP) {
982 ZSDELAY();
983 break;
984 }
985 udelay(5);
986 } while (--loops);
987
988 writeb(ch, &channel->data);
989 ZSDELAY();
990 ZS_WSYNC(channel);
991 }
992
993 static void
994 ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
995 {
996 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
997 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
998 unsigned long flags;
999 int i;
1000
1001 spin_lock_irqsave(&up->port.lock, flags);
1002 for (i = 0; i < count; i++, s++) {
1003 ip22zilog_put_char(channel, *s);
1004 if (*s == 10)
1005 ip22zilog_put_char(channel, 13);
1006 }
1007 udelay(2);
1008 spin_unlock_irqrestore(&up->port.lock, flags);
1009 }
1010
1011 void
1012 ip22serial_console_termios(struct console *con, char *options)
1013 {
1014 int baud = 9600, bits = 8, cflag;
1015 int parity = 'n';
1016 int flow = 'n';
1017
1018 if (options)
1019 uart_parse_options(options, &baud, &parity, &bits, &flow);
1020
1021 cflag = CREAD | HUPCL | CLOCAL;
1022
1023 switch (baud) {
1024 case 150: cflag |= B150; break;
1025 case 300: cflag |= B300; break;
1026 case 600: cflag |= B600; break;
1027 case 1200: cflag |= B1200; break;
1028 case 2400: cflag |= B2400; break;
1029 case 4800: cflag |= B4800; break;
1030 case 9600: cflag |= B9600; break;
1031 case 19200: cflag |= B19200; break;
1032 case 38400: cflag |= B38400; break;
1033 default: baud = 9600; cflag |= B9600; break;
1034 }
1035
1036 con->cflag = cflag | CS8; /* 8N1 */
1037 }
1038
1039 static int __init ip22zilog_console_setup(struct console *con, char *options)
1040 {
1041 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1042 unsigned long flags;
1043 int baud, brg;
1044
1045 printk("Console: ttyS%d (IP22-Zilog)\n", con->index);
1046
1047 /* Get firmware console settings. */
1048 ip22serial_console_termios(con, options);
1049
1050 /* Firmware console speed is limited to 150-->38400 baud so
1051 * this hackish cflag thing is OK.
1052 */
1053 switch (con->cflag & CBAUD) {
1054 case B150: baud = 150; break;
1055 case B300: baud = 300; break;
1056 case B600: baud = 600; break;
1057 case B1200: baud = 1200; break;
1058 case B2400: baud = 2400; break;
1059 case B4800: baud = 4800; break;
1060 default: case B9600: baud = 9600; break;
1061 case B19200: baud = 19200; break;
1062 case B38400: baud = 38400; break;
1063 };
1064
1065 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1066
1067 spin_lock_irqsave(&up->port.lock, flags);
1068
1069 up->curregs[R15] = BRKIE;
1070 ip22zilog_convert_to_zs(up, con->cflag, 0, brg);
1071
1072 __ip22zilog_startup(up);
1073
1074 spin_unlock_irqrestore(&up->port.lock, flags);
1075
1076 return 0;
1077 }
1078
1079 static struct uart_driver ip22zilog_reg;
1080
1081 static struct console ip22zilog_console = {
1082 .name = "ttyS",
1083 .write = ip22zilog_console_write,
1084 .device = uart_console_device,
1085 .setup = ip22zilog_console_setup,
1086 .flags = CON_PRINTBUFFER,
1087 .index = -1,
1088 .data = &ip22zilog_reg,
1089 };
1090 #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1091
1092 static struct uart_driver ip22zilog_reg = {
1093 .owner = THIS_MODULE,
1094 .driver_name = "serial",
1095 .devfs_name = "tts/",
1096 .dev_name = "ttyS",
1097 .major = TTY_MAJOR,
1098 .minor = 64,
1099 .nr = NUM_CHANNELS,
1100 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1101 .cons = &ip22zilog_console,
1102 #endif
1103 };
1104
1105 static void __init ip22zilog_prepare(void)
1106 {
1107 struct uart_ip22zilog_port *up;
1108 struct zilog_layout *rp;
1109 int channel, chip;
1110
1111 /*
1112 * Temporary fix.
1113 */
1114 for (channel = 0; channel < NUM_CHANNELS; channel++)
1115 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1116
1117 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1118 up = &ip22zilog_port_table[0];
1119 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1120 up[channel].next = &up[channel - 1];
1121 up[channel].next = NULL;
1122
1123 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1124 if (!ip22zilog_chip_regs[chip]) {
1125 ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1126
1127 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1128 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1129
1130 /* In theory mapbase is the physical address ... */
1131 up[(chip * 2) + 0].port.mapbase =
1132 (unsigned long) ioremap((unsigned long) &rp->channelB, 8);
1133 up[(chip * 2) + 1].port.mapbase =
1134 (unsigned long) ioremap((unsigned long) &rp->channelA, 8);
1135 }
1136
1137 /* Channel A */
1138 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1139 up[(chip * 2) + 0].port.irq = zilog_irq;
1140 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1141 up[(chip * 2) + 0].port.fifosize = 1;
1142 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1143 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1144 up[(chip * 2) + 0].port.flags = 0;
1145 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1146 up[(chip * 2) + 0].flags = 0;
1147
1148 /* Channel B */
1149 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1150 up[(chip * 2) + 1].port.irq = zilog_irq;
1151 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1152 up[(chip * 2) + 1].port.fifosize = 1;
1153 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1154 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1155 up[(chip * 2) + 1].port.flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1156 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1157 up[(chip * 2) + 1].flags = 0;
1158 }
1159 }
1160
1161 static void __init ip22zilog_init_hw(void)
1162 {
1163 int i;
1164
1165 for (i = 0; i < NUM_CHANNELS; i++) {
1166 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1167 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1168 unsigned long flags;
1169 int baud, brg;
1170
1171 spin_lock_irqsave(&up->port.lock, flags);
1172
1173 if (ZS_IS_CHANNEL_A(up)) {
1174 write_zsreg(channel, R9, FHWRES);
1175 ZSDELAY_LONG();
1176 (void) read_zsreg(channel, R0);
1177 }
1178
1179 /* Normal serial TTY. */
1180 up->parity_mask = 0xff;
1181 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1182 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1183 up->curregs[R3] = RxENAB | Rx8;
1184 up->curregs[R5] = TxENAB | Tx8;
1185 up->curregs[R9] = NV | MIE;
1186 up->curregs[R10] = NRZ;
1187 up->curregs[R11] = TCBR | RCBR;
1188 baud = 9600;
1189 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1190 up->curregs[R12] = (brg & 0xff);
1191 up->curregs[R13] = (brg >> 8) & 0xff;
1192 up->curregs[R14] = BRENAB;
1193 __load_zsregs(channel, up->curregs);
1194 /* set master interrupt enable */
1195 write_zsreg(channel, R9, up->curregs[R9]);
1196
1197 spin_unlock_irqrestore(&up->port.lock, flags);
1198 }
1199 }
1200
1201 static int __init ip22zilog_ports_init(void)
1202 {
1203 int ret;
1204
1205 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1206
1207 ip22zilog_prepare();
1208
1209 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1210 "IP22-Zilog", ip22zilog_irq_chain)) {
1211 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1212 }
1213
1214 ip22zilog_init_hw();
1215
1216 ret = uart_register_driver(&ip22zilog_reg);
1217 if (ret == 0) {
1218 int i;
1219
1220 for (i = 0; i < NUM_CHANNELS; i++) {
1221 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1222
1223 uart_add_one_port(&ip22zilog_reg, &up->port);
1224 }
1225 }
1226
1227 return ret;
1228 }
1229
1230 static int __init ip22zilog_init(void)
1231 {
1232 /* IP22 Zilog setup is hard coded, no probing to do. */
1233 ip22zilog_alloc_tables();
1234 ip22zilog_ports_init();
1235
1236 return 0;
1237 }
1238
1239 static void __exit ip22zilog_exit(void)
1240 {
1241 int i;
1242
1243 for (i = 0; i < NUM_CHANNELS; i++) {
1244 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1245
1246 uart_remove_one_port(&ip22zilog_reg, &up->port);
1247 }
1248
1249 uart_unregister_driver(&ip22zilog_reg);
1250 }
1251
1252 module_init(ip22zilog_init);
1253 module_exit(ip22zilog_exit);
1254
1255 /* David wrote it but I'm to blame for the bugs ... */
1256 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1257 MODULE_DESCRIPTION("SGI Zilog serial port driver");
1258 MODULE_LICENSE("GPL");
ubuntu-bionic-kernel mirror