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Merge branch 'for-rmk-realview' of git://linux-arm.org/linux-2.6 into devel
[mirror_ubuntu-eoan-kernel.git] / drivers / serial / sh-sci.c
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50
51 #ifdef CONFIG_SUPERH
52 #include <asm/clock.h>
53 #include <asm/sh_bios.h>
54 #include <asm/kgdb.h>
55 #endif
56
57 #include "sh-sci.h"
58
59 struct sci_port {
60 struct uart_port port;
61
62 /* Port type */
63 unsigned int type;
64
65 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
66 unsigned int irqs[SCIx_NR_IRQS];
67
68 /* Port pin configuration */
69 void (*init_pins)(struct uart_port *port,
70 unsigned int cflag);
71
72 /* Port enable callback */
73 void (*enable)(struct uart_port *port);
74
75 /* Port disable callback */
76 void (*disable)(struct uart_port *port);
77
78 /* Break timer */
79 struct timer_list break_timer;
80 int break_flag;
81
82 #ifdef CONFIG_HAVE_CLK
83 /* Port clock */
84 struct clk *clk;
85 #endif
86 };
87
88 #ifdef CONFIG_SH_KGDB
89 static struct sci_port *kgdb_sci_port;
90 #endif
91
92 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
93 static struct sci_port *serial_console_port;
94 #endif
95
96 /* Function prototypes */
97 static void sci_stop_tx(struct uart_port *port);
98
99 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
100
101 static struct sci_port sci_ports[SCI_NPORTS];
102 static struct uart_driver sci_uart_driver;
103
104 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
105 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
106 static inline void handle_error(struct uart_port *port)
107 {
108 /* Clear error flags */
109 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
110 }
111
112 static int get_char(struct uart_port *port)
113 {
114 unsigned long flags;
115 unsigned short status;
116 int c;
117
118 spin_lock_irqsave(&port->lock, flags);
119 do {
120 status = sci_in(port, SCxSR);
121 if (status & SCxSR_ERRORS(port)) {
122 handle_error(port);
123 continue;
124 }
125 } while (!(status & SCxSR_RDxF(port)));
126 c = sci_in(port, SCxRDR);
127 sci_in(port, SCxSR); /* Dummy read */
128 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
129 spin_unlock_irqrestore(&port->lock, flags);
130
131 return c;
132 }
133 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
134
135 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
136 static void put_char(struct uart_port *port, char c)
137 {
138 unsigned long flags;
139 unsigned short status;
140
141 spin_lock_irqsave(&port->lock, flags);
142
143 do {
144 status = sci_in(port, SCxSR);
145 } while (!(status & SCxSR_TDxE(port)));
146
147 sci_in(port, SCxSR); /* Dummy read */
148 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
149 sci_out(port, SCxTDR, c);
150
151 spin_unlock_irqrestore(&port->lock, flags);
152 }
153 #endif
154
155 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
156 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
157 {
158 struct uart_port *port = &sci_port->port;
159 const unsigned char *p = buffer;
160 int i;
161
162 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
163 int checksum;
164 int usegdb=0;
165
166 #ifdef CONFIG_SH_STANDARD_BIOS
167 /* This call only does a trap the first time it is
168 * called, and so is safe to do here unconditionally
169 */
170 usegdb |= sh_bios_in_gdb_mode();
171 #endif
172 #ifdef CONFIG_SH_KGDB
173 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
174 #endif
175
176 if (usegdb) {
177 /* $<packet info>#<checksum>. */
178 do {
179 unsigned char c;
180 put_char(port, '$');
181 put_char(port, 'O'); /* 'O'utput to console */
182 checksum = 'O';
183
184 for (i=0; i<count; i++) { /* Don't use run length encoding */
185 int h, l;
186
187 c = *p++;
188 h = hex_asc_hi(c);
189 l = hex_asc_lo(c);
190 put_char(port, h);
191 put_char(port, l);
192 checksum += h + l;
193 }
194 put_char(port, '#');
195 put_char(port, hex_asc_hi(checksum));
196 put_char(port, hex_asc_lo(checksum));
197 } while (get_char(port) != '+');
198 } else
199 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
200 for (i=0; i<count; i++) {
201 if (*p == 10)
202 put_char(port, '\r');
203 put_char(port, *p++);
204 }
205 }
206 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
207
208 #ifdef CONFIG_SH_KGDB
209 static int kgdb_sci_getchar(void)
210 {
211 int c;
212
213 /* Keep trying to read a character, this could be neater */
214 while ((c = get_char(&kgdb_sci_port->port)) < 0)
215 cpu_relax();
216
217 return c;
218 }
219
220 static inline void kgdb_sci_putchar(int c)
221 {
222 put_char(&kgdb_sci_port->port, c);
223 }
224 #endif /* CONFIG_SH_KGDB */
225
226 #if defined(__H8300S__)
227 enum { sci_disable, sci_enable };
228
229 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
230 {
231 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
232 int ch = (port->mapbase - SMR0) >> 3;
233 unsigned char mask = 1 << (ch+1);
234
235 if (ctrl == sci_disable) {
236 *mstpcrl |= mask;
237 } else {
238 *mstpcrl &= ~mask;
239 }
240 }
241
242 static inline void h8300_sci_enable(struct uart_port *port)
243 {
244 h8300_sci_config(port, sci_enable);
245 }
246
247 static inline void h8300_sci_disable(struct uart_port *port)
248 {
249 h8300_sci_config(port, sci_disable);
250 }
251 #endif
252
253 #if defined(__H8300H__) || defined(__H8300S__)
254 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
255 {
256 int ch = (port->mapbase - SMR0) >> 3;
257
258 /* set DDR regs */
259 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
260 h8300_sci_pins[ch].rx,
261 H8300_GPIO_INPUT);
262 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
263 h8300_sci_pins[ch].tx,
264 H8300_GPIO_OUTPUT);
265
266 /* tx mark output*/
267 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
268 }
269 #else
270 #define sci_init_pins_sci NULL
271 #endif
272
273 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
274 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
275 {
276 unsigned int fcr_val = 0;
277
278 if (cflag & CRTSCTS)
279 fcr_val |= SCFCR_MCE;
280
281 sci_out(port, SCFCR, fcr_val);
282 }
283 #else
284 #define sci_init_pins_irda NULL
285 #endif
286
287 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
288 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
289 {
290 unsigned int fcr_val = 0;
291
292 set_sh771x_scif_pfc(port);
293 if (cflag & CRTSCTS) {
294 fcr_val |= SCFCR_MCE;
295 }
296 sci_out(port, SCFCR, fcr_val);
297 }
298 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
299 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
300 {
301 unsigned int fcr_val = 0;
302 unsigned short data;
303
304 if (cflag & CRTSCTS) {
305 /* enable RTS/CTS */
306 if (port->mapbase == 0xa4430000) { /* SCIF0 */
307 /* Clear PTCR bit 9-2; enable all scif pins but sck */
308 data = ctrl_inw(PORT_PTCR);
309 ctrl_outw((data & 0xfc03), PORT_PTCR);
310 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
311 /* Clear PVCR bit 9-2 */
312 data = ctrl_inw(PORT_PVCR);
313 ctrl_outw((data & 0xfc03), PORT_PVCR);
314 }
315 fcr_val |= SCFCR_MCE;
316 } else {
317 if (port->mapbase == 0xa4430000) { /* SCIF0 */
318 /* Clear PTCR bit 5-2; enable only tx and rx */
319 data = ctrl_inw(PORT_PTCR);
320 ctrl_outw((data & 0xffc3), PORT_PTCR);
321 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
322 /* Clear PVCR bit 5-2 */
323 data = ctrl_inw(PORT_PVCR);
324 ctrl_outw((data & 0xffc3), PORT_PVCR);
325 }
326 }
327 sci_out(port, SCFCR, fcr_val);
328 }
329 #elif defined(CONFIG_CPU_SH3)
330 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
331 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
332 {
333 unsigned int fcr_val = 0;
334 unsigned short data;
335
336 /* We need to set SCPCR to enable RTS/CTS */
337 data = ctrl_inw(SCPCR);
338 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
339 ctrl_outw(data & 0x0fcf, SCPCR);
340
341 if (cflag & CRTSCTS)
342 fcr_val |= SCFCR_MCE;
343 else {
344 /* We need to set SCPCR to enable RTS/CTS */
345 data = ctrl_inw(SCPCR);
346 /* Clear out SCP7MD1,0, SCP4MD1,0,
347 Set SCP6MD1,0 = {01} (output) */
348 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
349
350 data = ctrl_inb(SCPDR);
351 /* Set /RTS2 (bit6) = 0 */
352 ctrl_outb(data & 0xbf, SCPDR);
353 }
354
355 sci_out(port, SCFCR, fcr_val);
356 }
357 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
358 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
359 {
360 unsigned int fcr_val = 0;
361 unsigned short data;
362
363 if (port->mapbase == 0xffe00000) {
364 data = ctrl_inw(PSCR);
365 data &= ~0x03cf;
366 if (cflag & CRTSCTS)
367 fcr_val |= SCFCR_MCE;
368 else
369 data |= 0x0340;
370
371 ctrl_outw(data, PSCR);
372 }
373 /* SCIF1 and SCIF2 should be setup by board code */
374
375 sci_out(port, SCFCR, fcr_val);
376 }
377 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
378 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
379 {
380 /* Nothing to do here.. */
381 sci_out(port, SCFCR, 0);
382 }
383 #else
384 /* For SH7750 */
385 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
386 {
387 unsigned int fcr_val = 0;
388
389 if (cflag & CRTSCTS) {
390 fcr_val |= SCFCR_MCE;
391 } else {
392 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
393 /* Nothing */
394 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
395 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
396 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
397 defined(CONFIG_CPU_SUBTYPE_SHX3)
398 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
399 #else
400 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
401 #endif
402 }
403 sci_out(port, SCFCR, fcr_val);
404 }
405 #endif
406
407 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
408 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
409 defined(CONFIG_CPU_SUBTYPE_SH7785)
410 static inline int scif_txroom(struct uart_port *port)
411 {
412 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
413 }
414
415 static inline int scif_rxroom(struct uart_port *port)
416 {
417 return sci_in(port, SCRFDR) & 0xff;
418 }
419 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
420 static inline int scif_txroom(struct uart_port *port)
421 {
422 if((port->mapbase == 0xffe00000) || (port->mapbase == 0xffe08000)) /* SCIF0/1*/
423 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
424 else /* SCIF2 */
425 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
426 }
427
428 static inline int scif_rxroom(struct uart_port *port)
429 {
430 if((port->mapbase == 0xffe00000) || (port->mapbase == 0xffe08000)) /* SCIF0/1*/
431 return sci_in(port, SCRFDR) & 0xff;
432 else /* SCIF2 */
433 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
434 }
435 #else
436 static inline int scif_txroom(struct uart_port *port)
437 {
438 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
439 }
440
441 static inline int scif_rxroom(struct uart_port *port)
442 {
443 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
444 }
445 #endif
446
447 static inline int sci_txroom(struct uart_port *port)
448 {
449 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
450 }
451
452 static inline int sci_rxroom(struct uart_port *port)
453 {
454 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
455 }
456
457 /* ********************************************************************** *
458 * the interrupt related routines *
459 * ********************************************************************** */
460
461 static void sci_transmit_chars(struct uart_port *port)
462 {
463 struct circ_buf *xmit = &port->info->xmit;
464 unsigned int stopped = uart_tx_stopped(port);
465 unsigned short status;
466 unsigned short ctrl;
467 int count;
468
469 status = sci_in(port, SCxSR);
470 if (!(status & SCxSR_TDxE(port))) {
471 ctrl = sci_in(port, SCSCR);
472 if (uart_circ_empty(xmit)) {
473 ctrl &= ~SCI_CTRL_FLAGS_TIE;
474 } else {
475 ctrl |= SCI_CTRL_FLAGS_TIE;
476 }
477 sci_out(port, SCSCR, ctrl);
478 return;
479 }
480
481 if (port->type == PORT_SCI)
482 count = sci_txroom(port);
483 else
484 count = scif_txroom(port);
485
486 do {
487 unsigned char c;
488
489 if (port->x_char) {
490 c = port->x_char;
491 port->x_char = 0;
492 } else if (!uart_circ_empty(xmit) && !stopped) {
493 c = xmit->buf[xmit->tail];
494 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
495 } else {
496 break;
497 }
498
499 sci_out(port, SCxTDR, c);
500
501 port->icount.tx++;
502 } while (--count > 0);
503
504 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
505
506 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
507 uart_write_wakeup(port);
508 if (uart_circ_empty(xmit)) {
509 sci_stop_tx(port);
510 } else {
511 ctrl = sci_in(port, SCSCR);
512
513 if (port->type != PORT_SCI) {
514 sci_in(port, SCxSR); /* Dummy read */
515 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
516 }
517
518 ctrl |= SCI_CTRL_FLAGS_TIE;
519 sci_out(port, SCSCR, ctrl);
520 }
521 }
522
523 /* On SH3, SCIF may read end-of-break as a space->mark char */
524 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
525
526 static inline void sci_receive_chars(struct uart_port *port)
527 {
528 struct sci_port *sci_port = (struct sci_port *)port;
529 struct tty_struct *tty = port->info->port.tty;
530 int i, count, copied = 0;
531 unsigned short status;
532 unsigned char flag;
533
534 status = sci_in(port, SCxSR);
535 if (!(status & SCxSR_RDxF(port)))
536 return;
537
538 while (1) {
539 if (port->type == PORT_SCI)
540 count = sci_rxroom(port);
541 else
542 count = scif_rxroom(port);
543
544 /* Don't copy more bytes than there is room for in the buffer */
545 count = tty_buffer_request_room(tty, count);
546
547 /* If for any reason we can't copy more data, we're done! */
548 if (count == 0)
549 break;
550
551 if (port->type == PORT_SCI) {
552 char c = sci_in(port, SCxRDR);
553 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
554 count = 0;
555 else {
556 tty_insert_flip_char(tty, c, TTY_NORMAL);
557 }
558 } else {
559 for (i=0; i<count; i++) {
560 char c = sci_in(port, SCxRDR);
561 status = sci_in(port, SCxSR);
562 #if defined(CONFIG_CPU_SH3)
563 /* Skip "chars" during break */
564 if (sci_port->break_flag) {
565 if ((c == 0) &&
566 (status & SCxSR_FER(port))) {
567 count--; i--;
568 continue;
569 }
570
571 /* Nonzero => end-of-break */
572 pr_debug("scif: debounce<%02x>\n", c);
573 sci_port->break_flag = 0;
574
575 if (STEPFN(c)) {
576 count--; i--;
577 continue;
578 }
579 }
580 #endif /* CONFIG_CPU_SH3 */
581 if (uart_handle_sysrq_char(port, c)) {
582 count--; i--;
583 continue;
584 }
585
586 /* Store data and status */
587 if (status&SCxSR_FER(port)) {
588 flag = TTY_FRAME;
589 pr_debug("sci: frame error\n");
590 } else if (status&SCxSR_PER(port)) {
591 flag = TTY_PARITY;
592 pr_debug("sci: parity error\n");
593 } else
594 flag = TTY_NORMAL;
595 tty_insert_flip_char(tty, c, flag);
596 }
597 }
598
599 sci_in(port, SCxSR); /* dummy read */
600 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
601
602 copied += count;
603 port->icount.rx += count;
604 }
605
606 if (copied) {
607 /* Tell the rest of the system the news. New characters! */
608 tty_flip_buffer_push(tty);
609 } else {
610 sci_in(port, SCxSR); /* dummy read */
611 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
612 }
613 }
614
615 #define SCI_BREAK_JIFFIES (HZ/20)
616 /* The sci generates interrupts during the break,
617 * 1 per millisecond or so during the break period, for 9600 baud.
618 * So dont bother disabling interrupts.
619 * But dont want more than 1 break event.
620 * Use a kernel timer to periodically poll the rx line until
621 * the break is finished.
622 */
623 static void sci_schedule_break_timer(struct sci_port *port)
624 {
625 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
626 add_timer(&port->break_timer);
627 }
628 /* Ensure that two consecutive samples find the break over. */
629 static void sci_break_timer(unsigned long data)
630 {
631 struct sci_port *port = (struct sci_port *)data;
632
633 if (sci_rxd_in(&port->port) == 0) {
634 port->break_flag = 1;
635 sci_schedule_break_timer(port);
636 } else if (port->break_flag == 1) {
637 /* break is over. */
638 port->break_flag = 2;
639 sci_schedule_break_timer(port);
640 } else
641 port->break_flag = 0;
642 }
643
644 static inline int sci_handle_errors(struct uart_port *port)
645 {
646 int copied = 0;
647 unsigned short status = sci_in(port, SCxSR);
648 struct tty_struct *tty = port->info->port.tty;
649
650 if (status & SCxSR_ORER(port)) {
651 /* overrun error */
652 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
653 copied++;
654 pr_debug("sci: overrun error\n");
655 }
656
657 if (status & SCxSR_FER(port)) {
658 if (sci_rxd_in(port) == 0) {
659 /* Notify of BREAK */
660 struct sci_port *sci_port = (struct sci_port *)port;
661
662 if (!sci_port->break_flag) {
663 sci_port->break_flag = 1;
664 sci_schedule_break_timer(sci_port);
665
666 /* Do sysrq handling. */
667 if (uart_handle_break(port))
668 return 0;
669 pr_debug("sci: BREAK detected\n");
670 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
671 copied++;
672 }
673 } else {
674 /* frame error */
675 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
676 copied++;
677 pr_debug("sci: frame error\n");
678 }
679 }
680
681 if (status & SCxSR_PER(port)) {
682 /* parity error */
683 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
684 copied++;
685 pr_debug("sci: parity error\n");
686 }
687
688 if (copied)
689 tty_flip_buffer_push(tty);
690
691 return copied;
692 }
693
694 static inline int sci_handle_breaks(struct uart_port *port)
695 {
696 int copied = 0;
697 unsigned short status = sci_in(port, SCxSR);
698 struct tty_struct *tty = port->info->port.tty;
699 struct sci_port *s = &sci_ports[port->line];
700
701 if (uart_handle_break(port))
702 return 0;
703
704 if (!s->break_flag && status & SCxSR_BRK(port)) {
705 #if defined(CONFIG_CPU_SH3)
706 /* Debounce break */
707 s->break_flag = 1;
708 #endif
709 /* Notify of BREAK */
710 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
711 copied++;
712 pr_debug("sci: BREAK detected\n");
713 }
714
715 #if defined(SCIF_ORER)
716 /* XXX: Handle SCIF overrun error */
717 if (port->type != PORT_SCI && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
718 sci_out(port, SCLSR, 0);
719 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
720 copied++;
721 pr_debug("sci: overrun error\n");
722 }
723 }
724 #endif
725
726 if (copied)
727 tty_flip_buffer_push(tty);
728
729 return copied;
730 }
731
732 static irqreturn_t sci_rx_interrupt(int irq, void *port)
733 {
734 /* I think sci_receive_chars has to be called irrespective
735 * of whether the I_IXOFF is set, otherwise, how is the interrupt
736 * to be disabled?
737 */
738 sci_receive_chars(port);
739
740 return IRQ_HANDLED;
741 }
742
743 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
744 {
745 struct uart_port *port = ptr;
746
747 spin_lock_irq(&port->lock);
748 sci_transmit_chars(port);
749 spin_unlock_irq(&port->lock);
750
751 return IRQ_HANDLED;
752 }
753
754 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
755 {
756 struct uart_port *port = ptr;
757
758 /* Handle errors */
759 if (port->type == PORT_SCI) {
760 if (sci_handle_errors(port)) {
761 /* discard character in rx buffer */
762 sci_in(port, SCxSR);
763 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
764 }
765 } else {
766 #if defined(SCIF_ORER)
767 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
768 struct tty_struct *tty = port->info->port.tty;
769
770 sci_out(port, SCLSR, 0);
771 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
772 tty_flip_buffer_push(tty);
773 pr_debug("scif: overrun error\n");
774 }
775 #endif
776 sci_rx_interrupt(irq, ptr);
777 }
778
779 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
780
781 /* Kick the transmission */
782 sci_tx_interrupt(irq, ptr);
783
784 return IRQ_HANDLED;
785 }
786
787 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
788 {
789 struct uart_port *port = ptr;
790
791 /* Handle BREAKs */
792 sci_handle_breaks(port);
793 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
794
795 return IRQ_HANDLED;
796 }
797
798 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
799 {
800 unsigned short ssr_status, scr_status;
801 struct uart_port *port = ptr;
802 irqreturn_t ret = IRQ_NONE;
803
804 ssr_status = sci_in(port,SCxSR);
805 scr_status = sci_in(port,SCSCR);
806
807 /* Tx Interrupt */
808 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
809 ret = sci_tx_interrupt(irq, ptr);
810 /* Rx Interrupt */
811 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
812 ret = sci_rx_interrupt(irq, ptr);
813 /* Error Interrupt */
814 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
815 ret = sci_er_interrupt(irq, ptr);
816 /* Break Interrupt */
817 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
818 ret = sci_br_interrupt(irq, ptr);
819
820 return ret;
821 }
822
823 #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
824 /*
825 * Here we define a transistion notifier so that we can update all of our
826 * ports' baud rate when the peripheral clock changes.
827 */
828 static int sci_notifier(struct notifier_block *self,
829 unsigned long phase, void *p)
830 {
831 struct cpufreq_freqs *freqs = p;
832 int i;
833
834 if ((phase == CPUFREQ_POSTCHANGE) ||
835 (phase == CPUFREQ_RESUMECHANGE)){
836 for (i = 0; i < SCI_NPORTS; i++) {
837 struct uart_port *port = &sci_ports[i].port;
838 struct clk *clk;
839
840 /*
841 * Update the uartclk per-port if frequency has
842 * changed, since it will no longer necessarily be
843 * consistent with the old frequency.
844 *
845 * Really we want to be able to do something like
846 * uart_change_speed() or something along those lines
847 * here to implicitly reset the per-port baud rate..
848 *
849 * Clean this up later..
850 */
851 clk = clk_get(NULL, "module_clk");
852 port->uartclk = clk_get_rate(clk);
853 clk_put(clk);
854 }
855
856 printk(KERN_INFO "%s: got a postchange notification "
857 "for cpu %d (old %d, new %d)\n",
858 __func__, freqs->cpu, freqs->old, freqs->new);
859 }
860
861 return NOTIFY_OK;
862 }
863
864 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
865 #endif /* CONFIG_CPU_FREQ && CONFIG_HAVE_CLK */
866
867 static int sci_request_irq(struct sci_port *port)
868 {
869 int i;
870 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
871 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
872 sci_br_interrupt,
873 };
874 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
875 "SCI Transmit Data Empty", "SCI Break" };
876
877 if (port->irqs[0] == port->irqs[1]) {
878 if (!port->irqs[0]) {
879 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
880 return -ENODEV;
881 }
882
883 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
884 IRQF_DISABLED, "sci", port)) {
885 printk(KERN_ERR "sci: Cannot allocate irq.\n");
886 return -ENODEV;
887 }
888 } else {
889 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
890 if (!port->irqs[i])
891 continue;
892 if (request_irq(port->irqs[i], handlers[i],
893 IRQF_DISABLED, desc[i], port)) {
894 printk(KERN_ERR "sci: Cannot allocate irq.\n");
895 return -ENODEV;
896 }
897 }
898 }
899
900 return 0;
901 }
902
903 static void sci_free_irq(struct sci_port *port)
904 {
905 int i;
906
907 if (port->irqs[0] == port->irqs[1]) {
908 if (!port->irqs[0])
909 printk("sci: sci_free_irq error\n");
910 else
911 free_irq(port->irqs[0], port);
912 } else {
913 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
914 if (!port->irqs[i])
915 continue;
916
917 free_irq(port->irqs[i], port);
918 }
919 }
920 }
921
922 static unsigned int sci_tx_empty(struct uart_port *port)
923 {
924 /* Can't detect */
925 return TIOCSER_TEMT;
926 }
927
928 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
929 {
930 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
931 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
932 /* If you have signals for DTR and DCD, please implement here. */
933 }
934
935 static unsigned int sci_get_mctrl(struct uart_port *port)
936 {
937 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
938 and CTS/RTS */
939
940 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
941 }
942
943 static void sci_start_tx(struct uart_port *port)
944 {
945 unsigned short ctrl;
946
947 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
948 ctrl = sci_in(port, SCSCR);
949 ctrl |= SCI_CTRL_FLAGS_TIE;
950 sci_out(port, SCSCR, ctrl);
951 }
952
953 static void sci_stop_tx(struct uart_port *port)
954 {
955 unsigned short ctrl;
956
957 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
958 ctrl = sci_in(port, SCSCR);
959 ctrl &= ~SCI_CTRL_FLAGS_TIE;
960 sci_out(port, SCSCR, ctrl);
961 }
962
963 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
964 {
965 unsigned short ctrl;
966
967 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
968 ctrl = sci_in(port, SCSCR);
969 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
970 sci_out(port, SCSCR, ctrl);
971 }
972
973 static void sci_stop_rx(struct uart_port *port)
974 {
975 unsigned short ctrl;
976
977 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
978 ctrl = sci_in(port, SCSCR);
979 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
980 sci_out(port, SCSCR, ctrl);
981 }
982
983 static void sci_enable_ms(struct uart_port *port)
984 {
985 /* Nothing here yet .. */
986 }
987
988 static void sci_break_ctl(struct uart_port *port, int break_state)
989 {
990 /* Nothing here yet .. */
991 }
992
993 static int sci_startup(struct uart_port *port)
994 {
995 struct sci_port *s = &sci_ports[port->line];
996
997 if (s->enable)
998 s->enable(port);
999
1000 #ifdef CONFIG_HAVE_CLK
1001 s->clk = clk_get(NULL, "module_clk");
1002 #endif
1003
1004 sci_request_irq(s);
1005 sci_start_tx(port);
1006 sci_start_rx(port, 1);
1007
1008 return 0;
1009 }
1010
1011 static void sci_shutdown(struct uart_port *port)
1012 {
1013 struct sci_port *s = &sci_ports[port->line];
1014
1015 sci_stop_rx(port);
1016 sci_stop_tx(port);
1017 sci_free_irq(s);
1018
1019 if (s->disable)
1020 s->disable(port);
1021
1022 #ifdef CONFIG_HAVE_CLK
1023 clk_put(s->clk);
1024 s->clk = NULL;
1025 #endif
1026 }
1027
1028 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1029 struct ktermios *old)
1030 {
1031 struct sci_port *s = &sci_ports[port->line];
1032 unsigned int status, baud, smr_val;
1033 int t = -1;
1034
1035 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1036 if (likely(baud))
1037 t = SCBRR_VALUE(baud, port->uartclk);
1038
1039 do {
1040 status = sci_in(port, SCxSR);
1041 } while (!(status & SCxSR_TEND(port)));
1042
1043 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1044
1045 if (port->type != PORT_SCI)
1046 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1047
1048 smr_val = sci_in(port, SCSMR) & 3;
1049 if ((termios->c_cflag & CSIZE) == CS7)
1050 smr_val |= 0x40;
1051 if (termios->c_cflag & PARENB)
1052 smr_val |= 0x20;
1053 if (termios->c_cflag & PARODD)
1054 smr_val |= 0x30;
1055 if (termios->c_cflag & CSTOPB)
1056 smr_val |= 0x08;
1057
1058 uart_update_timeout(port, termios->c_cflag, baud);
1059
1060 sci_out(port, SCSMR, smr_val);
1061
1062 if (t > 0) {
1063 if(t >= 256) {
1064 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1065 t >>= 2;
1066 } else {
1067 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1068 }
1069 sci_out(port, SCBRR, t);
1070 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1071 }
1072
1073 if (likely(s->init_pins))
1074 s->init_pins(port, termios->c_cflag);
1075
1076 sci_out(port, SCSCR, SCSCR_INIT(port));
1077
1078 if ((termios->c_cflag & CREAD) != 0)
1079 sci_start_rx(port,0);
1080 }
1081
1082 static const char *sci_type(struct uart_port *port)
1083 {
1084 switch (port->type) {
1085 case PORT_SCI: return "sci";
1086 case PORT_SCIF: return "scif";
1087 case PORT_IRDA: return "irda";
1088 case PORT_SCIFA: return "scifa";
1089 }
1090
1091 return NULL;
1092 }
1093
1094 static void sci_release_port(struct uart_port *port)
1095 {
1096 /* Nothing here yet .. */
1097 }
1098
1099 static int sci_request_port(struct uart_port *port)
1100 {
1101 /* Nothing here yet .. */
1102 return 0;
1103 }
1104
1105 static void sci_config_port(struct uart_port *port, int flags)
1106 {
1107 struct sci_port *s = &sci_ports[port->line];
1108
1109 port->type = s->type;
1110
1111 switch (port->type) {
1112 case PORT_SCI:
1113 s->init_pins = sci_init_pins_sci;
1114 break;
1115 case PORT_SCIF:
1116 case PORT_SCIFA:
1117 s->init_pins = sci_init_pins_scif;
1118 break;
1119 case PORT_IRDA:
1120 s->init_pins = sci_init_pins_irda;
1121 break;
1122 }
1123
1124 if (port->flags & UPF_IOREMAP && !port->membase) {
1125 #if defined(CONFIG_SUPERH64)
1126 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1127 port->membase = (void __iomem *)port->mapbase;
1128 #else
1129 port->membase = ioremap_nocache(port->mapbase, 0x40);
1130 #endif
1131
1132 printk(KERN_ERR "sci: can't remap port#%d\n", port->line);
1133 }
1134 }
1135
1136 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1137 {
1138 struct sci_port *s = &sci_ports[port->line];
1139
1140 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1141 return -EINVAL;
1142 if (ser->baud_base < 2400)
1143 /* No paper tape reader for Mitch.. */
1144 return -EINVAL;
1145
1146 return 0;
1147 }
1148
1149 static struct uart_ops sci_uart_ops = {
1150 .tx_empty = sci_tx_empty,
1151 .set_mctrl = sci_set_mctrl,
1152 .get_mctrl = sci_get_mctrl,
1153 .start_tx = sci_start_tx,
1154 .stop_tx = sci_stop_tx,
1155 .stop_rx = sci_stop_rx,
1156 .enable_ms = sci_enable_ms,
1157 .break_ctl = sci_break_ctl,
1158 .startup = sci_startup,
1159 .shutdown = sci_shutdown,
1160 .set_termios = sci_set_termios,
1161 .type = sci_type,
1162 .release_port = sci_release_port,
1163 .request_port = sci_request_port,
1164 .config_port = sci_config_port,
1165 .verify_port = sci_verify_port,
1166 };
1167
1168 static void __init sci_init_ports(void)
1169 {
1170 static int first = 1;
1171 int i;
1172
1173 if (!first)
1174 return;
1175
1176 first = 0;
1177
1178 for (i = 0; i < SCI_NPORTS; i++) {
1179 sci_ports[i].port.ops = &sci_uart_ops;
1180 sci_ports[i].port.iotype = UPIO_MEM;
1181 sci_ports[i].port.line = i;
1182 sci_ports[i].port.fifosize = 1;
1183
1184 #if defined(__H8300H__) || defined(__H8300S__)
1185 #ifdef __H8300S__
1186 sci_ports[i].enable = h8300_sci_enable;
1187 sci_ports[i].disable = h8300_sci_disable;
1188 #endif
1189 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1190 #elif defined(CONFIG_HAVE_CLK)
1191 /*
1192 * XXX: We should use a proper SCI/SCIF clock
1193 */
1194 {
1195 struct clk *clk = clk_get(NULL, "module_clk");
1196 sci_ports[i].port.uartclk = clk_get_rate(clk);
1197 clk_put(clk);
1198 }
1199 #else
1200 #error "Need a valid uartclk"
1201 #endif
1202
1203 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1204 sci_ports[i].break_timer.function = sci_break_timer;
1205
1206 init_timer(&sci_ports[i].break_timer);
1207 }
1208 }
1209
1210 int __init early_sci_setup(struct uart_port *port)
1211 {
1212 if (unlikely(port->line > SCI_NPORTS))
1213 return -ENODEV;
1214
1215 sci_init_ports();
1216
1217 sci_ports[port->line].port.membase = port->membase;
1218 sci_ports[port->line].port.mapbase = port->mapbase;
1219 sci_ports[port->line].port.type = port->type;
1220
1221 return 0;
1222 }
1223
1224 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1225 /*
1226 * Print a string to the serial port trying not to disturb
1227 * any possible real use of the port...
1228 */
1229 static void serial_console_write(struct console *co, const char *s,
1230 unsigned count)
1231 {
1232 put_string(serial_console_port, s, count);
1233 }
1234
1235 static int __init serial_console_setup(struct console *co, char *options)
1236 {
1237 struct uart_port *port;
1238 int baud = 115200;
1239 int bits = 8;
1240 int parity = 'n';
1241 int flow = 'n';
1242 int ret;
1243
1244 /*
1245 * Check whether an invalid uart number has been specified, and
1246 * if so, search for the first available port that does have
1247 * console support.
1248 */
1249 if (co->index >= SCI_NPORTS)
1250 co->index = 0;
1251
1252 serial_console_port = &sci_ports[co->index];
1253 port = &serial_console_port->port;
1254
1255 /*
1256 * Also need to check port->type, we don't actually have any
1257 * UPIO_PORT ports, but uart_report_port() handily misreports
1258 * it anyways if we don't have a port available by the time this is
1259 * called.
1260 */
1261 if (!port->type)
1262 return -ENODEV;
1263 if (!port->membase || !port->mapbase)
1264 return -ENODEV;
1265
1266 port->type = serial_console_port->type;
1267
1268 #ifdef CONFIG_HAVE_CLK
1269 if (!serial_console_port->clk)
1270 serial_console_port->clk = clk_get(NULL, "module_clk");
1271 #endif
1272
1273 if (port->flags & UPF_IOREMAP)
1274 sci_config_port(port, 0);
1275
1276 if (serial_console_port->enable)
1277 serial_console_port->enable(port);
1278
1279 if (options)
1280 uart_parse_options(options, &baud, &parity, &bits, &flow);
1281
1282 ret = uart_set_options(port, co, baud, parity, bits, flow);
1283 #if defined(__H8300H__) || defined(__H8300S__)
1284 /* disable rx interrupt */
1285 if (ret == 0)
1286 sci_stop_rx(port);
1287 #endif
1288 return ret;
1289 }
1290
1291 static struct console serial_console = {
1292 .name = "ttySC",
1293 .device = uart_console_device,
1294 .write = serial_console_write,
1295 .setup = serial_console_setup,
1296 .flags = CON_PRINTBUFFER,
1297 .index = -1,
1298 .data = &sci_uart_driver,
1299 };
1300
1301 static int __init sci_console_init(void)
1302 {
1303 sci_init_ports();
1304 register_console(&serial_console);
1305 return 0;
1306 }
1307 console_initcall(sci_console_init);
1308 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1309
1310 #ifdef CONFIG_SH_KGDB_CONSOLE
1311 /*
1312 * FIXME: Most of this can go away.. at the moment, we rely on
1313 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1314 * most of that can easily be done here instead.
1315 *
1316 * For the time being, just accept the values that were parsed earlier..
1317 */
1318 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1319 int *parity, int *bits)
1320 {
1321 *baud = kgdb_baud;
1322 *parity = tolower(kgdb_parity);
1323 *bits = kgdb_bits - '0';
1324 }
1325
1326 /*
1327 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1328 * care of the early-on initialization for kgdb, regardless of whether we
1329 * actually use kgdb as a console or not.
1330 *
1331 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1332 */
1333 int __init kgdb_console_setup(struct console *co, char *options)
1334 {
1335 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1336 int baud = 38400;
1337 int bits = 8;
1338 int parity = 'n';
1339 int flow = 'n';
1340
1341 if (co->index != kgdb_portnum)
1342 co->index = kgdb_portnum;
1343
1344 kgdb_sci_port = &sci_ports[co->index];
1345 port = &kgdb_sci_port->port;
1346
1347 /*
1348 * Also need to check port->type, we don't actually have any
1349 * UPIO_PORT ports, but uart_report_port() handily misreports
1350 * it anyways if we don't have a port available by the time this is
1351 * called.
1352 */
1353 if (!port->type)
1354 return -ENODEV;
1355 if (!port->membase || !port->mapbase)
1356 return -ENODEV;
1357
1358 if (options)
1359 uart_parse_options(options, &baud, &parity, &bits, &flow);
1360 else
1361 kgdb_console_get_options(port, &baud, &parity, &bits);
1362
1363 kgdb_getchar = kgdb_sci_getchar;
1364 kgdb_putchar = kgdb_sci_putchar;
1365
1366 return uart_set_options(port, co, baud, parity, bits, flow);
1367 }
1368
1369 static struct console kgdb_console = {
1370 .name = "ttySC",
1371 .device = uart_console_device,
1372 .write = kgdb_console_write,
1373 .setup = kgdb_console_setup,
1374 .flags = CON_PRINTBUFFER,
1375 .index = -1,
1376 .data = &sci_uart_driver,
1377 };
1378
1379 /* Register the KGDB console so we get messages (d'oh!) */
1380 static int __init kgdb_console_init(void)
1381 {
1382 sci_init_ports();
1383 register_console(&kgdb_console);
1384 return 0;
1385 }
1386 console_initcall(kgdb_console_init);
1387 #endif /* CONFIG_SH_KGDB_CONSOLE */
1388
1389 #if defined(CONFIG_SH_KGDB_CONSOLE)
1390 #define SCI_CONSOLE &kgdb_console
1391 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1392 #define SCI_CONSOLE &serial_console
1393 #else
1394 #define SCI_CONSOLE 0
1395 #endif
1396
1397 static char banner[] __initdata =
1398 KERN_INFO "SuperH SCI(F) driver initialized\n";
1399
1400 static struct uart_driver sci_uart_driver = {
1401 .owner = THIS_MODULE,
1402 .driver_name = "sci",
1403 .dev_name = "ttySC",
1404 .major = SCI_MAJOR,
1405 .minor = SCI_MINOR_START,
1406 .nr = SCI_NPORTS,
1407 .cons = SCI_CONSOLE,
1408 };
1409
1410 /*
1411 * Register a set of serial devices attached to a platform device. The
1412 * list is terminated with a zero flags entry, which means we expect
1413 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1414 * remapping (such as sh64) should also set UPF_IOREMAP.
1415 */
1416 static int __devinit sci_probe(struct platform_device *dev)
1417 {
1418 struct plat_sci_port *p = dev->dev.platform_data;
1419 int i, ret = -EINVAL;
1420
1421 for (i = 0; p && p->flags != 0; p++, i++) {
1422 struct sci_port *sciport = &sci_ports[i];
1423
1424 /* Sanity check */
1425 if (unlikely(i == SCI_NPORTS)) {
1426 dev_notice(&dev->dev, "Attempting to register port "
1427 "%d when only %d are available.\n",
1428 i+1, SCI_NPORTS);
1429 dev_notice(&dev->dev, "Consider bumping "
1430 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1431 break;
1432 }
1433
1434 sciport->port.mapbase = p->mapbase;
1435
1436 if (p->mapbase && !p->membase) {
1437 if (p->flags & UPF_IOREMAP) {
1438 p->membase = ioremap_nocache(p->mapbase, 0x40);
1439 if (IS_ERR(p->membase)) {
1440 ret = PTR_ERR(p->membase);
1441 goto err_unreg;
1442 }
1443 } else {
1444 /*
1445 * For the simple (and majority of) cases
1446 * where we don't need to do any remapping,
1447 * just cast the cookie directly.
1448 */
1449 p->membase = (void __iomem *)p->mapbase;
1450 }
1451 }
1452
1453 sciport->port.membase = p->membase;
1454
1455 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1456 sciport->port.flags = p->flags;
1457 sciport->port.dev = &dev->dev;
1458
1459 sciport->type = sciport->port.type = p->type;
1460
1461 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1462
1463 uart_add_one_port(&sci_uart_driver, &sciport->port);
1464 }
1465
1466 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1467 kgdb_sci_port = &sci_ports[kgdb_portnum];
1468 kgdb_getchar = kgdb_sci_getchar;
1469 kgdb_putchar = kgdb_sci_putchar;
1470 #endif
1471
1472 #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
1473 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1474 dev_info(&dev->dev, "CPU frequency notifier registered\n");
1475 #endif
1476
1477 #ifdef CONFIG_SH_STANDARD_BIOS
1478 sh_bios_gdb_detach();
1479 #endif
1480
1481 return 0;
1482
1483 err_unreg:
1484 for (i = i - 1; i >= 0; i--)
1485 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1486
1487 return ret;
1488 }
1489
1490 static int __devexit sci_remove(struct platform_device *dev)
1491 {
1492 int i;
1493
1494 for (i = 0; i < SCI_NPORTS; i++)
1495 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1496
1497 return 0;
1498 }
1499
1500 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1501 {
1502 int i;
1503
1504 for (i = 0; i < SCI_NPORTS; i++) {
1505 struct sci_port *p = &sci_ports[i];
1506
1507 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1508 uart_suspend_port(&sci_uart_driver, &p->port);
1509 }
1510
1511 return 0;
1512 }
1513
1514 static int sci_resume(struct platform_device *dev)
1515 {
1516 int i;
1517
1518 for (i = 0; i < SCI_NPORTS; i++) {
1519 struct sci_port *p = &sci_ports[i];
1520
1521 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1522 uart_resume_port(&sci_uart_driver, &p->port);
1523 }
1524
1525 return 0;
1526 }
1527
1528 static struct platform_driver sci_driver = {
1529 .probe = sci_probe,
1530 .remove = __devexit_p(sci_remove),
1531 .suspend = sci_suspend,
1532 .resume = sci_resume,
1533 .driver = {
1534 .name = "sh-sci",
1535 .owner = THIS_MODULE,
1536 },
1537 };
1538
1539 static int __init sci_init(void)
1540 {
1541 int ret;
1542
1543 printk(banner);
1544
1545 sci_init_ports();
1546
1547 ret = uart_register_driver(&sci_uart_driver);
1548 if (likely(ret == 0)) {
1549 ret = platform_driver_register(&sci_driver);
1550 if (unlikely(ret))
1551 uart_unregister_driver(&sci_uart_driver);
1552 }
1553
1554 return ret;
1555 }
1556
1557 static void __exit sci_exit(void)
1558 {
1559 platform_driver_unregister(&sci_driver);
1560 uart_unregister_driver(&sci_uart_driver);
1561 }
1562
1563 module_init(sci_init);
1564 module_exit(sci_exit);
1565
1566 MODULE_LICENSE("GPL");
1567 MODULE_ALIAS("platform:sh-sci");
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