]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/serial/sh-sci.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[mirror_ubuntu-artful-kernel.git] / drivers / serial / sh-sci.c
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
37 #include <linux/mm.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42
43 #ifdef CONFIG_CPU_FREQ
44 #include <linux/notifier.h>
45 #include <linux/cpufreq.h>
46 #endif
47
48 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
49 #include <linux/ctype.h>
50 #include <asm/clock.h>
51 #include <asm/sh_bios.h>
52 #include <asm/kgdb.h>
53 #endif
54
55 #include <asm/sci.h>
56 #include "sh-sci.h"
57
58 struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
66
67 /* Port pin configuration */
68 void (*init_pins)(struct uart_port *port,
69 unsigned int cflag);
70
71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
73
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
76
77 /* Break timer */
78 struct timer_list break_timer;
79 int break_flag;
80
81 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
82 /* Port clock */
83 struct clk *clk;
84 #endif
85 };
86
87 #ifdef CONFIG_SH_KGDB
88 static struct sci_port *kgdb_sci_port;
89 #endif
90
91 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
92 static struct sci_port *serial_console_port;
93 #endif
94
95 /* Function prototypes */
96 static void sci_stop_tx(struct uart_port *port);
97
98 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
99
100 static struct sci_port sci_ports[SCI_NPORTS];
101 static struct uart_driver sci_uart_driver;
102
103 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
104 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
105 static inline void handle_error(struct uart_port *port)
106 {
107 /* Clear error flags */
108 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
109 }
110
111 static int get_char(struct uart_port *port)
112 {
113 unsigned long flags;
114 unsigned short status;
115 int c;
116
117 spin_lock_irqsave(&port->lock, flags);
118 do {
119 status = sci_in(port, SCxSR);
120 if (status & SCxSR_ERRORS(port)) {
121 handle_error(port);
122 continue;
123 }
124 } while (!(status & SCxSR_RDxF(port)));
125 c = sci_in(port, SCxRDR);
126 sci_in(port, SCxSR); /* Dummy read */
127 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
128 spin_unlock_irqrestore(&port->lock, flags);
129
130 return c;
131 }
132 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
133
134 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
135 static void put_char(struct uart_port *port, char c)
136 {
137 unsigned long flags;
138 unsigned short status;
139
140 spin_lock_irqsave(&port->lock, flags);
141
142 do {
143 status = sci_in(port, SCxSR);
144 } while (!(status & SCxSR_TDxE(port)));
145
146 sci_out(port, SCxTDR, c);
147 sci_in(port, SCxSR); /* Dummy read */
148 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
149
150 spin_unlock_irqrestore(&port->lock, flags);
151 }
152 #endif
153
154 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
155 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
156 {
157 struct uart_port *port = &sci_port->port;
158 const unsigned char *p = buffer;
159 int i;
160
161 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
162 int checksum;
163 int usegdb=0;
164
165 #ifdef CONFIG_SH_STANDARD_BIOS
166 /* This call only does a trap the first time it is
167 * called, and so is safe to do here unconditionally
168 */
169 usegdb |= sh_bios_in_gdb_mode();
170 #endif
171 #ifdef CONFIG_SH_KGDB
172 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
173 #endif
174
175 if (usegdb) {
176 /* $<packet info>#<checksum>. */
177 do {
178 unsigned char c;
179 put_char(port, '$');
180 put_char(port, 'O'); /* 'O'utput to console */
181 checksum = 'O';
182
183 for (i=0; i<count; i++) { /* Don't use run length encoding */
184 int h, l;
185
186 c = *p++;
187 h = highhex(c);
188 l = lowhex(c);
189 put_char(port, h);
190 put_char(port, l);
191 checksum += h + l;
192 }
193 put_char(port, '#');
194 put_char(port, highhex(checksum));
195 put_char(port, lowhex(checksum));
196 } while (get_char(port) != '+');
197 } else
198 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
199 for (i=0; i<count; i++) {
200 if (*p == 10)
201 put_char(port, '\r');
202 put_char(port, *p++);
203 }
204 }
205 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
206
207 #ifdef CONFIG_SH_KGDB
208 static int kgdb_sci_getchar(void)
209 {
210 int c;
211
212 /* Keep trying to read a character, this could be neater */
213 while ((c = get_char(&kgdb_sci_port->port)) < 0)
214 cpu_relax();
215
216 return c;
217 }
218
219 static inline void kgdb_sci_putchar(int c)
220 {
221 put_char(&kgdb_sci_port->port, c);
222 }
223 #endif /* CONFIG_SH_KGDB */
224
225 #if defined(__H8300S__)
226 enum { sci_disable, sci_enable };
227
228 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
229 {
230 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
231 int ch = (port->mapbase - SMR0) >> 3;
232 unsigned char mask = 1 << (ch+1);
233
234 if (ctrl == sci_disable) {
235 *mstpcrl |= mask;
236 } else {
237 *mstpcrl &= ~mask;
238 }
239 }
240
241 static inline void h8300_sci_enable(struct uart_port *port)
242 {
243 h8300_sci_config(port, sci_enable);
244 }
245
246 static inline void h8300_sci_disable(struct uart_port *port)
247 {
248 h8300_sci_config(port, sci_disable);
249 }
250 #endif
251
252 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
253 defined(__H8300H__) || defined(__H8300S__)
254 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
255 {
256 int ch = (port->mapbase - SMR0) >> 3;
257
258 /* set DDR regs */
259 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
260 h8300_sci_pins[ch].rx,
261 H8300_GPIO_INPUT);
262 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
263 h8300_sci_pins[ch].tx,
264 H8300_GPIO_OUTPUT);
265
266 /* tx mark output*/
267 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
268 }
269 #else
270 #define sci_init_pins_sci NULL
271 #endif
272
273 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
274 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
275 {
276 unsigned int fcr_val = 0;
277
278 if (cflag & CRTSCTS)
279 fcr_val |= SCFCR_MCE;
280
281 sci_out(port, SCFCR, fcr_val);
282 }
283 #else
284 #define sci_init_pins_irda NULL
285 #endif
286
287 #ifdef SCI_ONLY
288 #define sci_init_pins_scif NULL
289 #endif
290
291 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
292 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
293 /* SH7300 doesn't use RTS/CTS */
294 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
295 {
296 sci_out(port, SCFCR, 0);
297 }
298 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
299 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
300 {
301 unsigned int fcr_val = 0;
302
303 set_sh771x_scif_pfc(port);
304 if (cflag & CRTSCTS) {
305 fcr_val |= SCFCR_MCE;
306 }
307 sci_out(port, SCFCR, fcr_val);
308 }
309 #elif defined(CONFIG_CPU_SH3)
310 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
311 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
312 {
313 unsigned int fcr_val = 0;
314 unsigned short data;
315
316 /* We need to set SCPCR to enable RTS/CTS */
317 data = ctrl_inw(SCPCR);
318 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
319 ctrl_outw(data & 0x0fcf, SCPCR);
320
321 if (cflag & CRTSCTS)
322 fcr_val |= SCFCR_MCE;
323 else {
324 /* We need to set SCPCR to enable RTS/CTS */
325 data = ctrl_inw(SCPCR);
326 /* Clear out SCP7MD1,0, SCP4MD1,0,
327 Set SCP6MD1,0 = {01} (output) */
328 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
329
330 data = ctrl_inb(SCPDR);
331 /* Set /RTS2 (bit6) = 0 */
332 ctrl_outb(data & 0xbf, SCPDR);
333 }
334
335 sci_out(port, SCFCR, fcr_val);
336 }
337 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
338 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
339 {
340 unsigned int fcr_val = 0;
341
342 if (cflag & CRTSCTS) {
343 fcr_val |= SCFCR_MCE;
344
345 ctrl_outw(0x0000, PORT_PSCR);
346 } else {
347 unsigned short data;
348
349 data = ctrl_inw(PORT_PSCR);
350 data &= 0x033f;
351 data |= 0x0400;
352 ctrl_outw(data, PORT_PSCR);
353
354 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
355 }
356
357 sci_out(port, SCFCR, fcr_val);
358 }
359 #else
360 /* For SH7750 */
361 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
362 {
363 unsigned int fcr_val = 0;
364
365 if (cflag & CRTSCTS) {
366 fcr_val |= SCFCR_MCE;
367 } else {
368 #ifdef CONFIG_CPU_SUBTYPE_SH7343
369 /* Nothing */
370 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
371 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
372 defined(CONFIG_CPU_SUBTYPE_SHX3)
373 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
374 #else
375 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
376 #endif
377 }
378 sci_out(port, SCFCR, fcr_val);
379 }
380 #endif
381
382 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
383 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
384 defined(CONFIG_CPU_SUBTYPE_SH7785)
385 static inline int scif_txroom(struct uart_port *port)
386 {
387 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
388 }
389
390 static inline int scif_rxroom(struct uart_port *port)
391 {
392 return sci_in(port, SCRFDR) & 0x7f;
393 }
394 #else
395 static inline int scif_txroom(struct uart_port *port)
396 {
397 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
398 }
399
400 static inline int scif_rxroom(struct uart_port *port)
401 {
402 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
403 }
404 #endif
405 #endif /* SCIF_ONLY || SCI_AND_SCIF */
406
407 static inline int sci_txroom(struct uart_port *port)
408 {
409 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
410 }
411
412 static inline int sci_rxroom(struct uart_port *port)
413 {
414 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
415 }
416
417 /* ********************************************************************** *
418 * the interrupt related routines *
419 * ********************************************************************** */
420
421 static void sci_transmit_chars(struct uart_port *port)
422 {
423 struct circ_buf *xmit = &port->info->xmit;
424 unsigned int stopped = uart_tx_stopped(port);
425 unsigned short status;
426 unsigned short ctrl;
427 int count;
428
429 status = sci_in(port, SCxSR);
430 if (!(status & SCxSR_TDxE(port))) {
431 ctrl = sci_in(port, SCSCR);
432 if (uart_circ_empty(xmit)) {
433 ctrl &= ~SCI_CTRL_FLAGS_TIE;
434 } else {
435 ctrl |= SCI_CTRL_FLAGS_TIE;
436 }
437 sci_out(port, SCSCR, ctrl);
438 return;
439 }
440
441 #ifndef SCI_ONLY
442 if (port->type == PORT_SCIF)
443 count = scif_txroom(port);
444 else
445 #endif
446 count = sci_txroom(port);
447
448 do {
449 unsigned char c;
450
451 if (port->x_char) {
452 c = port->x_char;
453 port->x_char = 0;
454 } else if (!uart_circ_empty(xmit) && !stopped) {
455 c = xmit->buf[xmit->tail];
456 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
457 } else {
458 break;
459 }
460
461 sci_out(port, SCxTDR, c);
462
463 port->icount.tx++;
464 } while (--count > 0);
465
466 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
467
468 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
469 uart_write_wakeup(port);
470 if (uart_circ_empty(xmit)) {
471 sci_stop_tx(port);
472 } else {
473 ctrl = sci_in(port, SCSCR);
474
475 #if !defined(SCI_ONLY)
476 if (port->type == PORT_SCIF) {
477 sci_in(port, SCxSR); /* Dummy read */
478 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
479 }
480 #endif
481
482 ctrl |= SCI_CTRL_FLAGS_TIE;
483 sci_out(port, SCSCR, ctrl);
484 }
485 }
486
487 /* On SH3, SCIF may read end-of-break as a space->mark char */
488 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
489
490 static inline void sci_receive_chars(struct uart_port *port)
491 {
492 struct sci_port *sci_port = (struct sci_port *)port;
493 struct tty_struct *tty = port->info->tty;
494 int i, count, copied = 0;
495 unsigned short status;
496 unsigned char flag;
497
498 status = sci_in(port, SCxSR);
499 if (!(status & SCxSR_RDxF(port)))
500 return;
501
502 while (1) {
503 #if !defined(SCI_ONLY)
504 if (port->type == PORT_SCIF)
505 count = scif_rxroom(port);
506 else
507 #endif
508 count = sci_rxroom(port);
509
510 /* Don't copy more bytes than there is room for in the buffer */
511 count = tty_buffer_request_room(tty, count);
512
513 /* If for any reason we can't copy more data, we're done! */
514 if (count == 0)
515 break;
516
517 if (port->type == PORT_SCI) {
518 char c = sci_in(port, SCxRDR);
519 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
520 count = 0;
521 else {
522 tty_insert_flip_char(tty, c, TTY_NORMAL);
523 }
524 } else {
525 for (i=0; i<count; i++) {
526 char c = sci_in(port, SCxRDR);
527 status = sci_in(port, SCxSR);
528 #if defined(CONFIG_CPU_SH3)
529 /* Skip "chars" during break */
530 if (sci_port->break_flag) {
531 if ((c == 0) &&
532 (status & SCxSR_FER(port))) {
533 count--; i--;
534 continue;
535 }
536
537 /* Nonzero => end-of-break */
538 pr_debug("scif: debounce<%02x>\n", c);
539 sci_port->break_flag = 0;
540
541 if (STEPFN(c)) {
542 count--; i--;
543 continue;
544 }
545 }
546 #endif /* CONFIG_CPU_SH3 */
547 if (uart_handle_sysrq_char(port, c)) {
548 count--; i--;
549 continue;
550 }
551
552 /* Store data and status */
553 if (status&SCxSR_FER(port)) {
554 flag = TTY_FRAME;
555 pr_debug("sci: frame error\n");
556 } else if (status&SCxSR_PER(port)) {
557 flag = TTY_PARITY;
558 pr_debug("sci: parity error\n");
559 } else
560 flag = TTY_NORMAL;
561 tty_insert_flip_char(tty, c, flag);
562 }
563 }
564
565 sci_in(port, SCxSR); /* dummy read */
566 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
567
568 copied += count;
569 port->icount.rx += count;
570 }
571
572 if (copied) {
573 /* Tell the rest of the system the news. New characters! */
574 tty_flip_buffer_push(tty);
575 } else {
576 sci_in(port, SCxSR); /* dummy read */
577 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
578 }
579 }
580
581 #define SCI_BREAK_JIFFIES (HZ/20)
582 /* The sci generates interrupts during the break,
583 * 1 per millisecond or so during the break period, for 9600 baud.
584 * So dont bother disabling interrupts.
585 * But dont want more than 1 break event.
586 * Use a kernel timer to periodically poll the rx line until
587 * the break is finished.
588 */
589 static void sci_schedule_break_timer(struct sci_port *port)
590 {
591 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
592 add_timer(&port->break_timer);
593 }
594 /* Ensure that two consecutive samples find the break over. */
595 static void sci_break_timer(unsigned long data)
596 {
597 struct sci_port *port = (struct sci_port *)data;
598
599 if (sci_rxd_in(&port->port) == 0) {
600 port->break_flag = 1;
601 sci_schedule_break_timer(port);
602 } else if (port->break_flag == 1) {
603 /* break is over. */
604 port->break_flag = 2;
605 sci_schedule_break_timer(port);
606 } else
607 port->break_flag = 0;
608 }
609
610 static inline int sci_handle_errors(struct uart_port *port)
611 {
612 int copied = 0;
613 unsigned short status = sci_in(port, SCxSR);
614 struct tty_struct *tty = port->info->tty;
615
616 if (status & SCxSR_ORER(port)) {
617 /* overrun error */
618 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
619 copied++;
620 pr_debug("sci: overrun error\n");
621 }
622
623 if (status & SCxSR_FER(port)) {
624 if (sci_rxd_in(port) == 0) {
625 /* Notify of BREAK */
626 struct sci_port *sci_port = (struct sci_port *)port;
627
628 if (!sci_port->break_flag) {
629 sci_port->break_flag = 1;
630 sci_schedule_break_timer(sci_port);
631
632 /* Do sysrq handling. */
633 if (uart_handle_break(port))
634 return 0;
635 pr_debug("sci: BREAK detected\n");
636 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
637 copied++;
638 }
639 } else {
640 /* frame error */
641 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
642 copied++;
643 pr_debug("sci: frame error\n");
644 }
645 }
646
647 if (status & SCxSR_PER(port)) {
648 /* parity error */
649 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
650 copied++;
651 pr_debug("sci: parity error\n");
652 }
653
654 if (copied)
655 tty_flip_buffer_push(tty);
656
657 return copied;
658 }
659
660 static inline int sci_handle_breaks(struct uart_port *port)
661 {
662 int copied = 0;
663 unsigned short status = sci_in(port, SCxSR);
664 struct tty_struct *tty = port->info->tty;
665 struct sci_port *s = &sci_ports[port->line];
666
667 if (uart_handle_break(port))
668 return 0;
669
670 if (!s->break_flag && status & SCxSR_BRK(port)) {
671 #if defined(CONFIG_CPU_SH3)
672 /* Debounce break */
673 s->break_flag = 1;
674 #endif
675 /* Notify of BREAK */
676 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
677 copied++;
678 pr_debug("sci: BREAK detected\n");
679 }
680
681 #if defined(SCIF_ORER)
682 /* XXX: Handle SCIF overrun error */
683 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
684 sci_out(port, SCLSR, 0);
685 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
686 copied++;
687 pr_debug("sci: overrun error\n");
688 }
689 }
690 #endif
691
692 if (copied)
693 tty_flip_buffer_push(tty);
694
695 return copied;
696 }
697
698 static irqreturn_t sci_rx_interrupt(int irq, void *port)
699 {
700 /* I think sci_receive_chars has to be called irrespective
701 * of whether the I_IXOFF is set, otherwise, how is the interrupt
702 * to be disabled?
703 */
704 sci_receive_chars(port);
705
706 return IRQ_HANDLED;
707 }
708
709 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
710 {
711 struct uart_port *port = ptr;
712
713 spin_lock_irq(&port->lock);
714 sci_transmit_chars(port);
715 spin_unlock_irq(&port->lock);
716
717 return IRQ_HANDLED;
718 }
719
720 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
721 {
722 struct uart_port *port = ptr;
723
724 /* Handle errors */
725 if (port->type == PORT_SCI) {
726 if (sci_handle_errors(port)) {
727 /* discard character in rx buffer */
728 sci_in(port, SCxSR);
729 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
730 }
731 } else {
732 #if defined(SCIF_ORER)
733 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
734 struct tty_struct *tty = port->info->tty;
735
736 sci_out(port, SCLSR, 0);
737 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
738 tty_flip_buffer_push(tty);
739 pr_debug("scif: overrun error\n");
740 }
741 #endif
742 sci_rx_interrupt(irq, ptr);
743 }
744
745 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
746
747 /* Kick the transmission */
748 sci_tx_interrupt(irq, ptr);
749
750 return IRQ_HANDLED;
751 }
752
753 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
754 {
755 struct uart_port *port = ptr;
756
757 /* Handle BREAKs */
758 sci_handle_breaks(port);
759 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
760
761 return IRQ_HANDLED;
762 }
763
764 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
765 {
766 unsigned short ssr_status, scr_status;
767 struct uart_port *port = ptr;
768
769 ssr_status = sci_in(port,SCxSR);
770 scr_status = sci_in(port,SCSCR);
771
772 /* Tx Interrupt */
773 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
774 sci_tx_interrupt(irq, ptr);
775 /* Rx Interrupt */
776 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
777 sci_rx_interrupt(irq, ptr);
778 /* Error Interrupt */
779 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
780 sci_er_interrupt(irq, ptr);
781 /* Break Interrupt */
782 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
783 sci_br_interrupt(irq, ptr);
784
785 return IRQ_HANDLED;
786 }
787
788 #ifdef CONFIG_CPU_FREQ
789 /*
790 * Here we define a transistion notifier so that we can update all of our
791 * ports' baud rate when the peripheral clock changes.
792 */
793 static int sci_notifier(struct notifier_block *self,
794 unsigned long phase, void *p)
795 {
796 struct cpufreq_freqs *freqs = p;
797 int i;
798
799 if ((phase == CPUFREQ_POSTCHANGE) ||
800 (phase == CPUFREQ_RESUMECHANGE)){
801 for (i = 0; i < SCI_NPORTS; i++) {
802 struct uart_port *port = &sci_ports[i].port;
803 struct clk *clk;
804
805 /*
806 * Update the uartclk per-port if frequency has
807 * changed, since it will no longer necessarily be
808 * consistent with the old frequency.
809 *
810 * Really we want to be able to do something like
811 * uart_change_speed() or something along those lines
812 * here to implicitly reset the per-port baud rate..
813 *
814 * Clean this up later..
815 */
816 clk = clk_get(NULL, "module_clk");
817 port->uartclk = clk_get_rate(clk) * 16;
818 clk_put(clk);
819 }
820
821 printk(KERN_INFO "%s: got a postchange notification "
822 "for cpu %d (old %d, new %d)\n",
823 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
824 }
825
826 return NOTIFY_OK;
827 }
828
829 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
830 #endif /* CONFIG_CPU_FREQ */
831
832 static int sci_request_irq(struct sci_port *port)
833 {
834 int i;
835 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
836 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
837 sci_br_interrupt,
838 };
839 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
840 "SCI Transmit Data Empty", "SCI Break" };
841
842 if (port->irqs[0] == port->irqs[1]) {
843 if (!port->irqs[0]) {
844 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
845 return -ENODEV;
846 }
847
848 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
849 IRQF_DISABLED, "sci", port)) {
850 printk(KERN_ERR "sci: Cannot allocate irq.\n");
851 return -ENODEV;
852 }
853 } else {
854 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
855 if (!port->irqs[i])
856 continue;
857 if (request_irq(port->irqs[i], handlers[i],
858 IRQF_DISABLED, desc[i], port)) {
859 printk(KERN_ERR "sci: Cannot allocate irq.\n");
860 return -ENODEV;
861 }
862 }
863 }
864
865 return 0;
866 }
867
868 static void sci_free_irq(struct sci_port *port)
869 {
870 int i;
871
872 if (port->irqs[0] == port->irqs[1]) {
873 if (!port->irqs[0])
874 printk("sci: sci_free_irq error\n");
875 else
876 free_irq(port->irqs[0], port);
877 } else {
878 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
879 if (!port->irqs[i])
880 continue;
881
882 free_irq(port->irqs[i], port);
883 }
884 }
885 }
886
887 static unsigned int sci_tx_empty(struct uart_port *port)
888 {
889 /* Can't detect */
890 return TIOCSER_TEMT;
891 }
892
893 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
894 {
895 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
896 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
897 /* If you have signals for DTR and DCD, please implement here. */
898 }
899
900 static unsigned int sci_get_mctrl(struct uart_port *port)
901 {
902 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
903 and CTS/RTS */
904
905 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
906 }
907
908 static void sci_start_tx(struct uart_port *port)
909 {
910 unsigned short ctrl;
911
912 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
913 ctrl = sci_in(port, SCSCR);
914 ctrl |= SCI_CTRL_FLAGS_TIE;
915 sci_out(port, SCSCR, ctrl);
916 }
917
918 static void sci_stop_tx(struct uart_port *port)
919 {
920 unsigned short ctrl;
921
922 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
923 ctrl = sci_in(port, SCSCR);
924 ctrl &= ~SCI_CTRL_FLAGS_TIE;
925 sci_out(port, SCSCR, ctrl);
926 }
927
928 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
929 {
930 unsigned short ctrl;
931
932 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
933 ctrl = sci_in(port, SCSCR);
934 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
935 sci_out(port, SCSCR, ctrl);
936 }
937
938 static void sci_stop_rx(struct uart_port *port)
939 {
940 unsigned short ctrl;
941
942 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
943 ctrl = sci_in(port, SCSCR);
944 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
945 sci_out(port, SCSCR, ctrl);
946 }
947
948 static void sci_enable_ms(struct uart_port *port)
949 {
950 /* Nothing here yet .. */
951 }
952
953 static void sci_break_ctl(struct uart_port *port, int break_state)
954 {
955 /* Nothing here yet .. */
956 }
957
958 static int sci_startup(struct uart_port *port)
959 {
960 struct sci_port *s = &sci_ports[port->line];
961
962 if (s->enable)
963 s->enable(port);
964
965 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
966 s->clk = clk_get(NULL, "module_clk");
967 #endif
968
969 sci_request_irq(s);
970 sci_start_tx(port);
971 sci_start_rx(port, 1);
972
973 return 0;
974 }
975
976 static void sci_shutdown(struct uart_port *port)
977 {
978 struct sci_port *s = &sci_ports[port->line];
979
980 sci_stop_rx(port);
981 sci_stop_tx(port);
982 sci_free_irq(s);
983
984 if (s->disable)
985 s->disable(port);
986
987 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
988 clk_put(s->clk);
989 s->clk = NULL;
990 #endif
991 }
992
993 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
994 struct ktermios *old)
995 {
996 struct sci_port *s = &sci_ports[port->line];
997 unsigned int status, baud, smr_val;
998 int t;
999
1000 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1001
1002 switch (baud) {
1003 case 0:
1004 t = -1;
1005 break;
1006 default:
1007 {
1008 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1009 t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
1010 #else
1011 t = SCBRR_VALUE(baud);
1012 #endif
1013 break;
1014 }
1015 }
1016
1017 do {
1018 status = sci_in(port, SCxSR);
1019 } while (!(status & SCxSR_TEND(port)));
1020
1021 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1022
1023 #if !defined(SCI_ONLY)
1024 if (port->type == PORT_SCIF)
1025 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1026 #endif
1027
1028 smr_val = sci_in(port, SCSMR) & 3;
1029 if ((termios->c_cflag & CSIZE) == CS7)
1030 smr_val |= 0x40;
1031 if (termios->c_cflag & PARENB)
1032 smr_val |= 0x20;
1033 if (termios->c_cflag & PARODD)
1034 smr_val |= 0x30;
1035 if (termios->c_cflag & CSTOPB)
1036 smr_val |= 0x08;
1037
1038 uart_update_timeout(port, termios->c_cflag, baud);
1039
1040 sci_out(port, SCSMR, smr_val);
1041
1042 if (t > 0) {
1043 if(t >= 256) {
1044 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1045 t >>= 2;
1046 } else {
1047 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1048 }
1049 sci_out(port, SCBRR, t);
1050 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1051 }
1052
1053 if (likely(s->init_pins))
1054 s->init_pins(port, termios->c_cflag);
1055
1056 sci_out(port, SCSCR, SCSCR_INIT(port));
1057
1058 if ((termios->c_cflag & CREAD) != 0)
1059 sci_start_rx(port,0);
1060 }
1061
1062 static const char *sci_type(struct uart_port *port)
1063 {
1064 switch (port->type) {
1065 case PORT_SCI: return "sci";
1066 case PORT_SCIF: return "scif";
1067 case PORT_IRDA: return "irda";
1068 }
1069
1070 return 0;
1071 }
1072
1073 static void sci_release_port(struct uart_port *port)
1074 {
1075 /* Nothing here yet .. */
1076 }
1077
1078 static int sci_request_port(struct uart_port *port)
1079 {
1080 /* Nothing here yet .. */
1081 return 0;
1082 }
1083
1084 static void sci_config_port(struct uart_port *port, int flags)
1085 {
1086 struct sci_port *s = &sci_ports[port->line];
1087
1088 port->type = s->type;
1089
1090 switch (port->type) {
1091 case PORT_SCI:
1092 s->init_pins = sci_init_pins_sci;
1093 break;
1094 case PORT_SCIF:
1095 s->init_pins = sci_init_pins_scif;
1096 break;
1097 case PORT_IRDA:
1098 s->init_pins = sci_init_pins_irda;
1099 break;
1100 }
1101
1102 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1103 if (port->mapbase == 0)
1104 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1105
1106 port->membase = (void __iomem *)port->mapbase;
1107 #endif
1108 }
1109
1110 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1111 {
1112 struct sci_port *s = &sci_ports[port->line];
1113
1114 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1115 return -EINVAL;
1116 if (ser->baud_base < 2400)
1117 /* No paper tape reader for Mitch.. */
1118 return -EINVAL;
1119
1120 return 0;
1121 }
1122
1123 static struct uart_ops sci_uart_ops = {
1124 .tx_empty = sci_tx_empty,
1125 .set_mctrl = sci_set_mctrl,
1126 .get_mctrl = sci_get_mctrl,
1127 .start_tx = sci_start_tx,
1128 .stop_tx = sci_stop_tx,
1129 .stop_rx = sci_stop_rx,
1130 .enable_ms = sci_enable_ms,
1131 .break_ctl = sci_break_ctl,
1132 .startup = sci_startup,
1133 .shutdown = sci_shutdown,
1134 .set_termios = sci_set_termios,
1135 .type = sci_type,
1136 .release_port = sci_release_port,
1137 .request_port = sci_request_port,
1138 .config_port = sci_config_port,
1139 .verify_port = sci_verify_port,
1140 };
1141
1142 static void __init sci_init_ports(void)
1143 {
1144 static int first = 1;
1145 int i;
1146
1147 if (!first)
1148 return;
1149
1150 first = 0;
1151
1152 for (i = 0; i < SCI_NPORTS; i++) {
1153 sci_ports[i].port.ops = &sci_uart_ops;
1154 sci_ports[i].port.iotype = UPIO_MEM;
1155 sci_ports[i].port.line = i;
1156 sci_ports[i].port.fifosize = 1;
1157
1158 #if defined(__H8300H__) || defined(__H8300S__)
1159 #ifdef __H8300S__
1160 sci_ports[i].enable = h8300_sci_enable;
1161 sci_ports[i].disable = h8300_sci_disable;
1162 #endif
1163 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1164 #elif defined(CONFIG_SUPERH64)
1165 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1166 #else
1167 /*
1168 * XXX: We should use a proper SCI/SCIF clock
1169 */
1170 {
1171 struct clk *clk = clk_get(NULL, "module_clk");
1172 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1173 clk_put(clk);
1174 }
1175 #endif
1176
1177 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1178 sci_ports[i].break_timer.function = sci_break_timer;
1179
1180 init_timer(&sci_ports[i].break_timer);
1181 }
1182 }
1183
1184 int __init early_sci_setup(struct uart_port *port)
1185 {
1186 if (unlikely(port->line > SCI_NPORTS))
1187 return -ENODEV;
1188
1189 sci_init_ports();
1190
1191 sci_ports[port->line].port.membase = port->membase;
1192 sci_ports[port->line].port.mapbase = port->mapbase;
1193 sci_ports[port->line].port.type = port->type;
1194
1195 return 0;
1196 }
1197
1198 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1199 /*
1200 * Print a string to the serial port trying not to disturb
1201 * any possible real use of the port...
1202 */
1203 static void serial_console_write(struct console *co, const char *s,
1204 unsigned count)
1205 {
1206 put_string(serial_console_port, s, count);
1207 }
1208
1209 static int __init serial_console_setup(struct console *co, char *options)
1210 {
1211 struct uart_port *port;
1212 int baud = 115200;
1213 int bits = 8;
1214 int parity = 'n';
1215 int flow = 'n';
1216 int ret;
1217
1218 /*
1219 * Check whether an invalid uart number has been specified, and
1220 * if so, search for the first available port that does have
1221 * console support.
1222 */
1223 if (co->index >= SCI_NPORTS)
1224 co->index = 0;
1225
1226 serial_console_port = &sci_ports[co->index];
1227 port = &serial_console_port->port;
1228
1229 /*
1230 * Also need to check port->type, we don't actually have any
1231 * UPIO_PORT ports, but uart_report_port() handily misreports
1232 * it anyways if we don't have a port available by the time this is
1233 * called.
1234 */
1235 if (!port->type)
1236 return -ENODEV;
1237 if (!port->membase || !port->mapbase)
1238 return -ENODEV;
1239
1240 port->type = serial_console_port->type;
1241
1242 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1243 if (!serial_console_port->clk)
1244 serial_console_port->clk = clk_get(NULL, "module_clk");
1245 #endif
1246
1247 if (port->flags & UPF_IOREMAP)
1248 sci_config_port(port, 0);
1249
1250 if (serial_console_port->enable)
1251 serial_console_port->enable(port);
1252
1253 if (options)
1254 uart_parse_options(options, &baud, &parity, &bits, &flow);
1255
1256 ret = uart_set_options(port, co, baud, parity, bits, flow);
1257 #if defined(__H8300H__) || defined(__H8300S__)
1258 /* disable rx interrupt */
1259 if (ret == 0)
1260 sci_stop_rx(port);
1261 #endif
1262 return ret;
1263 }
1264
1265 static struct console serial_console = {
1266 .name = "ttySC",
1267 .device = uart_console_device,
1268 .write = serial_console_write,
1269 .setup = serial_console_setup,
1270 .flags = CON_PRINTBUFFER,
1271 .index = -1,
1272 .data = &sci_uart_driver,
1273 };
1274
1275 static int __init sci_console_init(void)
1276 {
1277 sci_init_ports();
1278 register_console(&serial_console);
1279 return 0;
1280 }
1281 console_initcall(sci_console_init);
1282 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1283
1284 #ifdef CONFIG_SH_KGDB
1285 /*
1286 * FIXME: Most of this can go away.. at the moment, we rely on
1287 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1288 * most of that can easily be done here instead.
1289 *
1290 * For the time being, just accept the values that were parsed earlier..
1291 */
1292 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1293 int *parity, int *bits)
1294 {
1295 *baud = kgdb_baud;
1296 *parity = tolower(kgdb_parity);
1297 *bits = kgdb_bits - '0';
1298 }
1299
1300 /*
1301 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1302 * care of the early-on initialization for kgdb, regardless of whether we
1303 * actually use kgdb as a console or not.
1304 *
1305 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1306 */
1307 int __init kgdb_console_setup(struct console *co, char *options)
1308 {
1309 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1310 int baud = 38400;
1311 int bits = 8;
1312 int parity = 'n';
1313 int flow = 'n';
1314
1315 if (co->index != kgdb_portnum)
1316 co->index = kgdb_portnum;
1317
1318 kgdb_sci_port = &sci_ports[co->index];
1319 port = &kgdb_sci_port->port;
1320
1321 /*
1322 * Also need to check port->type, we don't actually have any
1323 * UPIO_PORT ports, but uart_report_port() handily misreports
1324 * it anyways if we don't have a port available by the time this is
1325 * called.
1326 */
1327 if (!port->type)
1328 return -ENODEV;
1329 if (!port->membase || !port->mapbase)
1330 return -ENODEV;
1331
1332 if (options)
1333 uart_parse_options(options, &baud, &parity, &bits, &flow);
1334 else
1335 kgdb_console_get_options(port, &baud, &parity, &bits);
1336
1337 kgdb_getchar = kgdb_sci_getchar;
1338 kgdb_putchar = kgdb_sci_putchar;
1339
1340 return uart_set_options(port, co, baud, parity, bits, flow);
1341 }
1342 #endif /* CONFIG_SH_KGDB */
1343
1344 #ifdef CONFIG_SH_KGDB_CONSOLE
1345 static struct console kgdb_console = {
1346 .name = "ttySC",
1347 .device = uart_console_device,
1348 .write = kgdb_console_write,
1349 .setup = kgdb_console_setup,
1350 .flags = CON_PRINTBUFFER,
1351 .index = -1,
1352 .data = &sci_uart_driver,
1353 };
1354
1355 /* Register the KGDB console so we get messages (d'oh!) */
1356 static int __init kgdb_console_init(void)
1357 {
1358 sci_init_ports();
1359 register_console(&kgdb_console);
1360 return 0;
1361 }
1362 console_initcall(kgdb_console_init);
1363 #endif /* CONFIG_SH_KGDB_CONSOLE */
1364
1365 #if defined(CONFIG_SH_KGDB_CONSOLE)
1366 #define SCI_CONSOLE &kgdb_console
1367 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1368 #define SCI_CONSOLE &serial_console
1369 #else
1370 #define SCI_CONSOLE 0
1371 #endif
1372
1373 static char banner[] __initdata =
1374 KERN_INFO "SuperH SCI(F) driver initialized\n";
1375
1376 static struct uart_driver sci_uart_driver = {
1377 .owner = THIS_MODULE,
1378 .driver_name = "sci",
1379 .dev_name = "ttySC",
1380 .major = SCI_MAJOR,
1381 .minor = SCI_MINOR_START,
1382 .nr = SCI_NPORTS,
1383 .cons = SCI_CONSOLE,
1384 };
1385
1386 /*
1387 * Register a set of serial devices attached to a platform device. The
1388 * list is terminated with a zero flags entry, which means we expect
1389 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1390 * remapping (such as sh64) should also set UPF_IOREMAP.
1391 */
1392 static int __devinit sci_probe(struct platform_device *dev)
1393 {
1394 struct plat_sci_port *p = dev->dev.platform_data;
1395 int i;
1396
1397 for (i = 0; p && p->flags != 0; p++, i++) {
1398 struct sci_port *sciport = &sci_ports[i];
1399
1400 /* Sanity check */
1401 if (unlikely(i == SCI_NPORTS)) {
1402 dev_notice(&dev->dev, "Attempting to register port "
1403 "%d when only %d are available.\n",
1404 i+1, SCI_NPORTS);
1405 dev_notice(&dev->dev, "Consider bumping "
1406 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1407 break;
1408 }
1409
1410 sciport->port.mapbase = p->mapbase;
1411
1412 /*
1413 * For the simple (and majority of) cases where we don't need
1414 * to do any remapping, just cast the cookie directly.
1415 */
1416 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1417 p->membase = (void __iomem *)p->mapbase;
1418
1419 sciport->port.membase = p->membase;
1420
1421 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1422 sciport->port.flags = p->flags;
1423 sciport->port.dev = &dev->dev;
1424
1425 sciport->type = sciport->port.type = p->type;
1426
1427 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1428
1429 uart_add_one_port(&sci_uart_driver, &sciport->port);
1430 }
1431
1432 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1433 kgdb_sci_port = &sci_ports[kgdb_portnum];
1434 kgdb_getchar = kgdb_sci_getchar;
1435 kgdb_putchar = kgdb_sci_putchar;
1436 #endif
1437
1438 #ifdef CONFIG_CPU_FREQ
1439 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1440 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1441 #endif
1442
1443 #ifdef CONFIG_SH_STANDARD_BIOS
1444 sh_bios_gdb_detach();
1445 #endif
1446
1447 return 0;
1448 }
1449
1450 static int __devexit sci_remove(struct platform_device *dev)
1451 {
1452 int i;
1453
1454 for (i = 0; i < SCI_NPORTS; i++)
1455 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1456
1457 return 0;
1458 }
1459
1460 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1461 {
1462 int i;
1463
1464 for (i = 0; i < SCI_NPORTS; i++) {
1465 struct sci_port *p = &sci_ports[i];
1466
1467 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1468 uart_suspend_port(&sci_uart_driver, &p->port);
1469 }
1470
1471 return 0;
1472 }
1473
1474 static int sci_resume(struct platform_device *dev)
1475 {
1476 int i;
1477
1478 for (i = 0; i < SCI_NPORTS; i++) {
1479 struct sci_port *p = &sci_ports[i];
1480
1481 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1482 uart_resume_port(&sci_uart_driver, &p->port);
1483 }
1484
1485 return 0;
1486 }
1487
1488 static struct platform_driver sci_driver = {
1489 .probe = sci_probe,
1490 .remove = __devexit_p(sci_remove),
1491 .suspend = sci_suspend,
1492 .resume = sci_resume,
1493 .driver = {
1494 .name = "sh-sci",
1495 .owner = THIS_MODULE,
1496 },
1497 };
1498
1499 static int __init sci_init(void)
1500 {
1501 int ret;
1502
1503 printk(banner);
1504
1505 sci_init_ports();
1506
1507 ret = uart_register_driver(&sci_uart_driver);
1508 if (likely(ret == 0)) {
1509 ret = platform_driver_register(&sci_driver);
1510 if (unlikely(ret))
1511 uart_unregister_driver(&sci_uart_driver);
1512 }
1513
1514 return ret;
1515 }
1516
1517 static void __exit sci_exit(void)
1518 {
1519 platform_driver_unregister(&sci_driver);
1520 uart_unregister_driver(&sci_uart_driver);
1521 }
1522
1523 module_init(sci_init);
1524 module_exit(sci_exit);
1525
1526 MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror