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1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
3 * linux/drivers/serial/sh-sci.h
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
13 #include <linux/config.h>
14 #include <linux/serial_core.h>
16 #if defined(__H8300H__) || defined(__H8300S__)
18 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
19 #include <asm/regs306x.h>
21 #if defined(CONFIG_H8S2678)
22 #include <asm/regs267x.h>
26 /* Offsets into the sci_port->irqs array */
27 #define SCIx_ERI_IRQ 0
28 #define SCIx_RXI_IRQ 1
29 #define SCIx_TXI_IRQ 2
31 /* ERI, RXI, TXI, BRI */
32 #define SCI_IRQS { 23, 24, 25, 0 }
33 #define SH3_SCIF_IRQS { 56, 57, 59, 58 }
34 #define SH3_IRDA_IRQS { 52, 53, 55, 54 }
35 #define SH4_SCIF_IRQS { 40, 41, 43, 42 }
36 #define STB1_SCIF1_IRQS {23, 24, 26, 25 }
37 #define SH7760_SCIF0_IRQS { 52, 53, 55, 54 }
38 #define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
39 #define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
40 #define SH7300_SCIF0_IRQS {80, 80, 80, 80 }
41 #define SH73180_SCIF_IRQS {80, 81, 83, 82 }
42 #define H8300H_SCI_IRQS0 {52, 53, 54, 0 }
43 #define H8300H_SCI_IRQS1 {56, 57, 58, 0 }
44 #define H8300H_SCI_IRQS2 {60, 61, 62, 0 }
45 #define H8S_SCI_IRQS0 {88, 89, 90, 0 }
46 #define H8S_SCI_IRQS1 {92, 93, 94, 0 }
47 #define H8S_SCI_IRQS2 {96, 97, 98, 0 }
48 #define SH5_SCIF_IRQS {39, 40, 42, 0 }
49 #define SH7770_SCIF0_IRQS {61, 61, 61, 61 }
50 #define SH7770_SCIF1_IRQS {62, 62, 62, 62 }
51 #define SH7770_SCIF2_IRQS {63, 63, 63, 63 }
52 #define SH7780_SCIF0_IRQS {40, 41, 43, 42 }
53 #define SH7780_SCIF1_IRQS {76, 77, 79, 78 }
55 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
56 # define SCSPTR 0xffffff7c /* 8 bit */
57 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
59 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
60 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
61 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
62 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
64 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
65 # define SCIF0 0xA4400000
66 # define SCIF2 0xA4410000
67 # define SCSMR_Ir 0xA44A0000
68 # define IRDA_SCIF SCIF0
69 # define SCPCR 0xA4000116
70 # define SCPDR 0xA4000136
72 /* Set the clock source,
73 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
74 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
76 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
78 #elif defined(CONFIG_SH_RTS7751R2D)
79 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
80 # define SCIF_ORER 0x0001 /* overrun error bit */
81 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
83 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
84 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
85 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
86 # define SCIF_ORER 0x0001 /* overrun error bit */
87 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
88 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
89 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
91 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
92 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
93 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
94 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
95 # define SCIF_ORER 0x0001 /* overrun error bit */
96 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
98 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
99 # define SCPCR 0xA4050116 /* 16 bit SCIF */
100 # define SCPDR 0xA4050136 /* 16 bit SCIF */
101 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
103 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
104 # define SCPDR 0xA4050138 /* 16 bit SCIF */
105 # define SCSPTR2 SCPDR
106 # define SCIF_ORER 0x0001 /* overrun error bit */
107 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
109 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
110 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
111 # define SCIF_ORER 0x0001 /* overrun error bit */
112 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
114 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
115 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
116 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
117 # define SCIF_ORER 0x0001 /* overrun error bit */
118 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
120 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
121 # include <asm/hardware.h>
122 # define SCIF_BASE_ADDR 0x01030000
123 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
124 # define SCIF_PTR2_OFFS 0x0000020
125 # define SCIF_LSR2_OFFS 0x0000024
126 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
127 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
128 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
131 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
132 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
134 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
135 #elif defined(CONFIG_H8S2678)
136 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
138 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
139 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
140 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
141 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
142 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
143 # define SCIF_ORER 0x0001 /* overrun error bit */
144 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
146 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
147 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
148 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
149 # define SCIF_OPER 0x0001 /* Overrun error bit */
150 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
153 # error CPU subtype not defined
157 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
158 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
159 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
160 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
161 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780)
162 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
164 #define SCI_CTRL_FLAGS_REIE 0
166 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
167 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
168 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
169 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
172 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
173 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
174 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
175 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
176 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
177 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
178 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
179 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
181 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
184 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
185 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
186 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
187 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
188 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
189 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
190 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
191 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
193 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
194 #define SCIF_ORER 0x0200
195 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
196 #define SCIF_RFDC_MASK 0x007f
197 #define SCIF_TXROOM_MAX 64
199 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
200 #define SCIF_RFDC_MASK 0x001f
201 #define SCIF_TXROOM_MAX 16
204 #if defined(SCI_ONLY)
205 # define SCxSR_TEND(port) SCI_TEND
206 # define SCxSR_ERRORS(port) SCI_ERRORS
207 # define SCxSR_RDxF(port) SCI_RDRF
208 # define SCxSR_TDxE(port) SCI_TDRE
209 # define SCxSR_ORER(port) SCI_ORER
210 # define SCxSR_FER(port) SCI_FER
211 # define SCxSR_PER(port) SCI_PER
212 # define SCxSR_BRK(port) 0x00
213 # define SCxSR_RDxF_CLEAR(port) 0xbc
214 # define SCxSR_ERROR_CLEAR(port) 0xc4
215 # define SCxSR_TDxE_CLEAR(port) 0x78
216 # define SCxSR_BREAK_CLEAR(port) 0xc4
217 #elif defined(SCIF_ONLY)
218 # define SCxSR_TEND(port) SCIF_TEND
219 # define SCxSR_ERRORS(port) SCIF_ERRORS
220 # define SCxSR_RDxF(port) SCIF_RDF
221 # define SCxSR_TDxE(port) SCIF_TDFE
222 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
223 # define SCxSR_ORER(port) SCIF_ORER
225 # define SCxSR_ORER(port) 0x0000
227 # define SCxSR_FER(port) SCIF_FER
228 # define SCxSR_PER(port) SCIF_PER
229 # define SCxSR_BRK(port) SCIF_BRK
230 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
231 # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
232 # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
233 # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
234 # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
236 /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
237 # define SCxSR_RDxF_CLEAR(port) 0x00fc
238 # define SCxSR_ERROR_CLEAR(port) 0x0073
239 # define SCxSR_TDxE_CLEAR(port) 0x00df
240 # define SCxSR_BREAK_CLEAR(port) 0x00e3
243 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
244 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
245 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
246 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
247 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
248 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
249 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
250 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
251 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
252 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
253 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
254 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
258 #define SCFCR_RFRST 0x0002
259 #define SCFCR_TFRST 0x0004
260 #define SCFCR_TCRST 0x4000
261 #define SCFCR_MCE 0x0008
263 #define SCI_MAJOR 204
264 #define SCI_MINOR_START 8
266 /* Generic serial flags */
267 #define SCI_RX_THROTTLE 0x0000001
269 #define SCI_MAGIC 0xbabeface
272 * Events are used to schedule things to happen at timer-interrupt
273 * time, instead of at rs interrupt time.
275 #define SCI_EVENT_WRITE_WAKEUP 0
278 struct uart_port port
;
280 unsigned char irqs
[4]; /* ERI, RXI, TXI, BRI */
281 void (*init_pins
)(struct uart_port
*port
, unsigned int cflag
);
283 struct timer_list break_timer
;
286 #define SCI_IN(size, offset) \
287 unsigned int addr = port->mapbase + (offset); \
289 return ctrl_inb(addr); \
291 return ctrl_inw(addr); \
293 #define SCI_OUT(size, offset, value) \
294 unsigned int addr = port->mapbase + (offset); \
296 ctrl_outb(value, addr); \
298 ctrl_outw(value, addr); \
301 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
302 static inline unsigned int sci_##name##_in(struct uart_port *port) \
304 if (port->type == PORT_SCI) { \
305 SCI_IN(sci_size, sci_offset) \
307 SCI_IN(scif_size, scif_offset); \
310 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
312 if (port->type == PORT_SCI) { \
313 SCI_OUT(sci_size, sci_offset, value) \
315 SCI_OUT(scif_size, scif_offset, value); \
319 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
320 static inline unsigned int sci_##name##_in(struct uart_port *port) \
322 SCI_IN(scif_size, scif_offset); \
324 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
326 SCI_OUT(scif_size, scif_offset, value); \
329 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
330 static inline unsigned int sci_##name##_in(struct uart_port* port) \
332 SCI_IN(sci_size, sci_offset); \
334 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
336 SCI_OUT(sci_size, sci_offset, value); \
339 #ifdef CONFIG_CPU_SH3
340 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
341 #define SCIF_FNS(name, scif_offset, scif_size) \
342 CPU_SCIF_FNS(name, scif_offset, scif_size)
344 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
345 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
346 h8_sci_offset, h8_sci_size) \
347 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
348 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
349 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
351 #elif defined(__H8300H__) || defined(__H8300S__)
352 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
353 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
354 h8_sci_offset, h8_sci_size) \
355 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
356 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
358 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
359 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
360 h8_sci_offset, h8_sci_size) \
361 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
362 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
363 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
366 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
367 SCIF_FNS(SCSMR
, 0x00, 16)
368 SCIF_FNS(SCBRR
, 0x04, 8)
369 SCIF_FNS(SCSCR
, 0x08, 16)
370 SCIF_FNS(SCTDSR
, 0x0c, 8)
371 SCIF_FNS(SCFER
, 0x10, 16)
372 SCIF_FNS(SCxSR
, 0x14, 16)
373 SCIF_FNS(SCFCR
, 0x18, 16)
374 SCIF_FNS(SCFDR
, 0x1c, 16)
375 SCIF_FNS(SCxTDR
, 0x20, 8)
376 SCIF_FNS(SCxRDR
, 0x24, 8)
377 SCIF_FNS(SCLSR
, 0x24, 16)
379 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
380 /* name off sz off sz off sz off sz off sz*/
381 SCIx_FNS(SCSMR
, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
382 SCIx_FNS(SCBRR
, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
383 SCIx_FNS(SCSCR
, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
384 SCIx_FNS(SCxTDR
, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
385 SCIx_FNS(SCxSR
, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
386 SCIx_FNS(SCxRDR
, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
387 SCIF_FNS(SCFCR
, 0x0c, 8, 0x18, 16)
388 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
389 SCIF_FNS(SCTFDR
, 0x0e, 16, 0x1C, 16)
390 SCIF_FNS(SCRFDR
, 0x0e, 16, 0x20, 16)
391 SCIF_FNS(SCSPTR
, 0, 0, 0x24, 16)
392 SCIF_FNS(SCLSR
, 0, 0, 0x28, 16)
394 SCIF_FNS(SCFDR
, 0x0e, 16, 0x1C, 16)
395 SCIF_FNS(SCSPTR
, 0, 0, 0x20, 16)
396 SCIF_FNS(SCLSR
, 0, 0, 0x24, 16)
399 #define sci_in(port, reg) sci_##reg##_in(port)
400 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
402 /* H8/300 series SCI pins assignment */
403 #if defined(__H8300H__) || defined(__H8300S__)
404 static const struct __attribute__((packed
)) {
405 int port
; /* GPIO port no */
406 unsigned short rx
,tx
; /* GPIO bit no */
407 } h8300_sci_pins
[] = {
408 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
410 .port
= H8300_GPIO_P9
,
415 .port
= H8300_GPIO_P9
,
420 .port
= H8300_GPIO_PB
,
424 #elif defined(CONFIG_H8S2678)
426 .port
= H8300_GPIO_P3
,
431 .port
= H8300_GPIO_P3
,
436 .port
= H8300_GPIO_P5
,
444 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
445 static inline int sci_rxd_in(struct uart_port
*port
)
447 if (port
->mapbase
== 0xfffffe80)
448 return ctrl_inb(SCSPTR
)&0x01 ? 1 : 0; /* SCI */
451 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
452 static inline int sci_rxd_in(struct uart_port
*port
)
454 if (port
->mapbase
== 0xfffffe80)
455 return ctrl_inb(SCPDR
)&0x01 ? 1 : 0; /* SCI */
456 if (port
->mapbase
== 0xa4000150)
457 return ctrl_inb(SCPDR
)&0x10 ? 1 : 0; /* SCIF */
458 if (port
->mapbase
== 0xa4000140)
459 return ctrl_inb(SCPDR
)&0x04 ? 1 : 0; /* IRDA */
462 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
463 static inline int sci_rxd_in(struct uart_port
*port
)
465 if (port
->mapbase
== SCIF0
)
466 return ctrl_inb(SCPDR
)&0x04 ? 1 : 0; /* IRDA */
467 if (port
->mapbase
== SCIF2
)
468 return ctrl_inb(SCPDR
)&0x10 ? 1 : 0; /* SCIF */
471 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
472 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
473 defined(CONFIG_CPU_SUBTYPE_SH4_202)
474 static inline int sci_rxd_in(struct uart_port
*port
)
477 if (port
->mapbase
== 0xffe00000)
478 return ctrl_inb(SCSPTR1
)&0x01 ? 1 : 0; /* SCI */
481 if (port
->mapbase
== 0xffe80000)
482 return ctrl_inw(SCSPTR2
)&0x0001 ? 1 : 0; /* SCIF */
486 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
487 static inline int sci_rxd_in(struct uart_port
*port
)
489 if (port
->mapbase
== 0xfe600000)
490 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
491 if (port
->mapbase
== 0xfe610000)
492 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
493 if (port
->mapbase
== 0xfe620000)
494 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
496 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
497 static inline int sci_rxd_in(struct uart_port
*port
)
499 if (port
->mapbase
== 0xa4430000)
500 return ctrl_inb(SCPDR
)&0x01 ? 1 : 0; /* SCIF0 */
503 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
504 static inline int sci_rxd_in(struct uart_port
*port
)
506 return ctrl_inb(SCPDR
)&0x01 ? 1 : 0; /* SCIF0 */
508 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
509 static inline int sci_rxd_in(struct uart_port
*port
)
511 if (port
->mapbase
== 0xffe00000)
512 return ctrl_inw(SCSPTR1
)&0x0001 ? 1 : 0; /* SCIF */
514 return ctrl_inw(SCSPTR2
)&0x0001 ? 1 : 0; /* SCIF */
517 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
518 static inline int sci_rxd_in(struct uart_port
*port
)
520 return sci_in(port
, SCSPTR
)&0x0001 ? 1 : 0; /* SCIF */
522 #elif defined(__H8300H__) || defined(__H8300S__)
523 static inline int sci_rxd_in(struct uart_port
*port
)
525 int ch
= (port
->mapbase
- SMR0
) >> 3;
526 return (H8300_SCI_DR(ch
) & h8300_sci_pins
[ch
].rx
) ? 1 : 0;
528 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
529 static inline int sci_rxd_in(struct uart_port
*port
)
531 if (port
->mapbase
== 0xff923000)
532 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
533 if (port
->mapbase
== 0xff924000)
534 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
535 if (port
->mapbase
== 0xff925000)
536 return ctrl_inw(SCSPTR2
) & 0x0001 ? 1 : 0; /* SCIF */
538 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
539 static inline int sci_rxd_in(struct uart_port
*port
)
541 if (port
->mapbase
== 0xffe00000)
542 return ctrl_inw(SCSPTR0
) & 0x0001 ? 1 : 0; /* SCIF */
543 if (port
->mapbase
== 0xffe10000)
544 return ctrl_inw(SCSPTR1
) & 0x0001 ? 1 : 0; /* SCIF */
549 * Values for the BitRate Register (SCBRR)
551 * The values are actually divisors for a frequency which can
552 * be internal to the SH3 (14.7456MHz) or derived from an external
553 * clock source. This driver assumes the internal clock is used;
554 * to support using an external clock source, config options or
555 * possibly command-line options would need to be added.
557 * Also, to support speeds below 2400 (why?) the lower 2 bits of
558 * the SCSMR register would also need to be set to non-zero values.
560 * -- Greg Banks 27Feb2000
562 * Answer: The SCBRR register is only eight bits, and the value in
563 * it gets larger with lower baud rates. At around 2400 (depending on
564 * the peripherial module clock) you run out of bits. However the
565 * lower two bits of SCSMR allow the module clock to be divided down,
566 * scaling the value which is needed in SCBRR.
568 * -- Stuart Menefy - 23 May 2000
570 * I meant, why would anyone bother with bitrates below 2400.
572 * -- Greg Banks - 7Jul2000
574 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
575 * tape reader as a console!
577 * -- Mitch Davis - 15 Jul 2000
580 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780)
581 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
582 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
583 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
584 #elif defined(__H8300H__) || defined(__H8300S__)
585 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
586 #elif defined(CONFIG_SUPERH64)
587 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
588 #else /* Generic SH */
589 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)