drivers/serial/sh-sci.h

   1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
   2  *
   3  *  linux/drivers/serial/sh-sci.h
   4  *
   5  *  SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
   6  *  Copyright (C) 1999, 2000  Niibe Yutaka
   7  *  Copyright (C) 2000  Greg Banks
   8  *  Copyright (C) 2002, 2003  Paul Mundt
   9  *  Modified to support multiple serial ports. Stuart Menefy (May 2000).
  10  *  Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
  11  *  Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
  12  */
  13 #include <linux/serial_core.h>
  14 #include <asm/io.h>
  15
  16 #if defined(__H8300H__) || defined(__H8300S__)
  17 #include <asm/gpio.h>
  18 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
  19 #include <asm/regs306x.h>
  20 #endif
  21 #if defined(CONFIG_H8S2678)
  22 #include <asm/regs267x.h>
  23 #endif
  24 #endif
  25
  26 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
  27 # define SCSPTR 0xffffff7c /* 8 bit */
  28 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  29 # define SCI_ONLY
  30 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  31       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
  32       defined(CONFIG_CPU_SUBTYPE_SH7706)
  33 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  34 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  35 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  36 # define SCI_AND_SCIF
  37 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  38 # define SCIF0          0xA4400000
  39 # define SCIF2          0xA4410000
  40 # define SCSMR_Ir       0xA44A0000
  41 # define IRDA_SCIF      SCIF0
  42 # define SCPCR 0xA4000116
  43 # define SCPDR 0xA4000136
  44
  45 /* Set the clock source,
  46  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  47  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  48  */
  49 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  50 # define SCIF_ONLY
  51 #elif defined(CONFIG_SH_RTS7751R2D)
  52 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  53 # define SCIF_ORER 0x0001   /* overrun error bit */
  54 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  55 # define SCIF_ONLY
  56 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
  57 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  58 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  59 # define SCIF_ORER 0x0001   /* overrun error bit */
  60 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  61         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  62         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  63 # define SCI_AND_SCIF
  64 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  65 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  66 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  67 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  68 # define SCIF_ORER 0x0001  /* overrun error bit */
  69 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  70 # define SCIF_ONLY
  71 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
  72 # define SCPCR  0xA4050116        /* 16 bit SCIF */
  73 # define SCPDR  0xA4050136        /* 16 bit SCIF */
  74 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  75 # define SCIF_ONLY
  76 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
  77 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  78 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  79 # define SCIF_ONLY
  80 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
  81 # define SCPDR  0xA4050138        /* 16 bit SCIF */
  82 # define SCSPTR2 SCPDR
  83 # define SCIF_ORER 0x0001   /* overrun error bit */
  84 # define SCSCR_INIT(port)  0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
  85 # define SCIF_ONLY
  86 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  87 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  88 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  89 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  90 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
  91 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
  92 # define SCIF_ONLY
  93 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
  94 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
  95 # define SCIF_ORER 0x0001   /* overrun error bit */
  96 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  97 # define SCIF_ONLY
  98 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
  99 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
 100 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 101 # define SCIF_ORER 0x0001   /* overrun error bit */
 102 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 103 # define SCIF_ONLY
 104 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 105 # include <asm/hardware.h>
 106 # define SCIF_BASE_ADDR    0x01030000
 107 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 108 # define SCIF_PTR2_OFFS    0x0000020
 109 # define SCIF_LSR2_OFFS    0x0000024
 110 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 111 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 112 # define SCSCR_INIT(port)  0x38                           /* TIE=0,RIE=0,
 113                                                              TE=1,RE=1,REIE=1 */
 114 # define SCIF_ONLY
 115 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 116 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 117 # define SCI_ONLY
 118 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 119 #elif defined(CONFIG_H8S2678)
 120 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 121 # define SCI_ONLY
 122 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 123 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 124 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 125 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 126 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 127 # define SCIF_ORER 0x0001  /* overrun error bit */
 128 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 129 # define SCIF_ONLY
 130 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 131 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 132 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 133 # define SCIF_ORER      0x0001          /* Overrun error bit */
 134 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 135 # define SCIF_ONLY
 136 #else
 137 # error CPU subtype not defined
 138 #endif
 139
 140 /* SCSCR */
 141 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 142 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 143 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 144 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 145 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780)
 146 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 147 #else
 148 #define SCI_CTRL_FLAGS_REIE 0
 149 #endif
 150 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 151 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 152 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 153 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 154
 155 /* SCxSR SCI */
 156 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 157 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 158 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 159 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 160 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 161 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 162 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 163 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 164
 165 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 166
 167 /* SCxSR SCIF */
 168 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 169 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 170 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 171 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 172 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 173 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 174 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 175 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 176
 177 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 178 #define SCIF_ORER    0x0200
 179 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 180 #define SCIF_RFDC_MASK 0x007f
 181 #define SCIF_TXROOM_MAX 64
 182 #else
 183 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 184 #define SCIF_RFDC_MASK 0x001f
 185 #define SCIF_TXROOM_MAX 16
 186 #endif
 187
 188 #if defined(SCI_ONLY)
 189 # define SCxSR_TEND(port)               SCI_TEND
 190 # define SCxSR_ERRORS(port)             SCI_ERRORS
 191 # define SCxSR_RDxF(port)               SCI_RDRF
 192 # define SCxSR_TDxE(port)               SCI_TDRE
 193 # define SCxSR_ORER(port)               SCI_ORER
 194 # define SCxSR_FER(port)                SCI_FER
 195 # define SCxSR_PER(port)                SCI_PER
 196 # define SCxSR_BRK(port)                0x00
 197 # define SCxSR_RDxF_CLEAR(port)         0xbc
 198 # define SCxSR_ERROR_CLEAR(port)        0xc4
 199 # define SCxSR_TDxE_CLEAR(port)         0x78
 200 # define SCxSR_BREAK_CLEAR(port)        0xc4
 201 #elif defined(SCIF_ONLY)
 202 # define SCxSR_TEND(port)               SCIF_TEND
 203 # define SCxSR_ERRORS(port)             SCIF_ERRORS
 204 # define SCxSR_RDxF(port)               SCIF_RDF
 205 # define SCxSR_TDxE(port)               SCIF_TDFE
 206 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 207 # define SCxSR_ORER(port)               SCIF_ORER
 208 #else
 209 # define SCxSR_ORER(port)               0x0000
 210 #endif
 211 # define SCxSR_FER(port)                SCIF_FER
 212 # define SCxSR_PER(port)                SCIF_PER
 213 # define SCxSR_BRK(port)                SCIF_BRK
 214 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 215 # define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
 216 # define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
 217 # define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
 218 # define SCxSR_BREAK_CLEAR(port)        (sci_in(port,SCxSR)&0xffe3)
 219 #else
 220 /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
 221 # define SCxSR_RDxF_CLEAR(port)         0x00fc
 222 # define SCxSR_ERROR_CLEAR(port)        0x0073
 223 # define SCxSR_TDxE_CLEAR(port)         0x00df
 224 # define SCxSR_BREAK_CLEAR(port)        0x00e3
 225 #endif
 226 #else
 227 # define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 228 # define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 229 # define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 230 # define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 231 # define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : 0x0000)
 232 # define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 233 # define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 234 # define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 235 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 236 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 237 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 238 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 239 #endif
 240
 241 /* SCFCR */
 242 #define SCFCR_RFRST 0x0002
 243 #define SCFCR_TFRST 0x0004
 244 #define SCFCR_TCRST 0x4000
 245 #define SCFCR_MCE   0x0008
 246
 247 #define SCI_MAJOR               204
 248 #define SCI_MINOR_START         8
 249
 250 /* Generic serial flags */
 251 #define SCI_RX_THROTTLE         0x0000001
 252
 253 #define SCI_MAGIC 0xbabeface
 254
 255 /*
 256  * Events are used to schedule things to happen at timer-interrupt
 257  * time, instead of at rs interrupt time.
 258  */
 259 #define SCI_EVENT_WRITE_WAKEUP  0
 260
 261 #define SCI_IN(size, offset)                                    \
 262   unsigned int addr = port->mapbase + (offset);                 \
 263   if ((size) == 8) {                                            \
 264     return ctrl_inb(addr);                                      \
 265   } else {                                                      \
 266     return ctrl_inw(addr);                                      \
 267   }
 268 #define SCI_OUT(size, offset, value)                            \
 269   unsigned int addr = port->mapbase + (offset);                 \
 270   if ((size) == 8) {                                            \
 271     ctrl_outb(value, addr);                                     \
 272   } else {                                                      \
 273     ctrl_outw(value, addr);                                     \
 274   }
 275
 276 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 277   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 278   {                                                                     \
 279     if (port->type == PORT_SCI) {                                       \
 280       SCI_IN(sci_size, sci_offset)                                      \
 281     } else {                                                            \
 282       SCI_IN(scif_size, scif_offset);                                   \
 283     }                                                                   \
 284   }                                                                     \
 285   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 286   {                                                                     \
 287     if (port->type == PORT_SCI) {                                       \
 288       SCI_OUT(sci_size, sci_offset, value)                              \
 289     } else {                                                            \
 290       SCI_OUT(scif_size, scif_offset, value);                           \
 291     }                                                                   \
 292   }
 293
 294 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                              \
 295   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 296   {                                                                     \
 297     SCI_IN(scif_size, scif_offset);                                     \
 298   }                                                                     \
 299   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 300   {                                                                     \
 301     SCI_OUT(scif_size, scif_offset, value);                             \
 302   }
 303
 304 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 305   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 306   {                                                                     \
 307     SCI_IN(sci_size, sci_offset);                                       \
 308   }                                                                     \
 309   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 310   {                                                                     \
 311     SCI_OUT(sci_size, sci_offset, value);                               \
 312   }
 313
 314 #ifdef CONFIG_CPU_SH3
 315 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 316     defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 317     defined(CONFIG_CPU_SUBTYPE_SH7710)
 318 #define SCIF_FNS(name, scif_offset, scif_size) \
 319   CPU_SCIF_FNS(name, scif_offset, scif_size)
 320 #else
 321 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 322                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 323                  h8_sci_offset, h8_sci_size) \
 324   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 325 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 326   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 327 #endif
 328 #elif defined(__H8300H__) || defined(__H8300S__)
 329 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 330                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 331                  h8_sci_offset, h8_sci_size) \
 332   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 333 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
 334 #else
 335 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 336                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 337                  h8_sci_offset, h8_sci_size) \
 338   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 339 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 340   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 341 #endif
 342
 343 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 344     defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 345     defined(CONFIG_CPU_SUBTYPE_SH7710)
 346 SCIF_FNS(SCSMR,  0x00, 16)
 347 SCIF_FNS(SCBRR,  0x04,  8)
 348 SCIF_FNS(SCSCR,  0x08, 16)
 349 SCIF_FNS(SCTDSR, 0x0c,  8)
 350 SCIF_FNS(SCFER,  0x10, 16)
 351 SCIF_FNS(SCxSR,  0x14, 16)
 352 SCIF_FNS(SCFCR,  0x18, 16)
 353 SCIF_FNS(SCFDR,  0x1c, 16)
 354 SCIF_FNS(SCxTDR, 0x20,  8)
 355 SCIF_FNS(SCxRDR, 0x24,  8)
 356 SCIF_FNS(SCLSR,  0x24, 16)
 357 #else
 358 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 359 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 360 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 361 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 362 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 363 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 364 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 365 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 366 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 367 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
 368 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 369 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 370 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 371 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 372 #else
 373 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 374 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 375 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 376 #endif
 377 #endif
 378 #define sci_in(port, reg) sci_##reg##_in(port)
 379 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 380
 381 /* H8/300 series SCI pins assignment */
 382 #if defined(__H8300H__) || defined(__H8300S__)
 383 static const struct __attribute__((packed)) {
 384         int port;             /* GPIO port no */
 385         unsigned short rx,tx; /* GPIO bit no */
 386 } h8300_sci_pins[] = {
 387 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 388         {    /* SCI0 */
 389                 .port = H8300_GPIO_P9,
 390                 .rx   = H8300_GPIO_B2,
 391                 .tx   = H8300_GPIO_B0,
 392         },
 393         {    /* SCI1 */
 394                 .port = H8300_GPIO_P9,
 395                 .rx   = H8300_GPIO_B3,
 396                 .tx   = H8300_GPIO_B1,
 397         },
 398         {    /* SCI2 */
 399                 .port = H8300_GPIO_PB,
 400                 .rx   = H8300_GPIO_B7,
 401                 .tx   = H8300_GPIO_B6,
 402         }
 403 #elif defined(CONFIG_H8S2678)
 404         {    /* SCI0 */
 405                 .port = H8300_GPIO_P3,
 406                 .rx   = H8300_GPIO_B2,
 407                 .tx   = H8300_GPIO_B0,
 408         },
 409         {    /* SCI1 */
 410                 .port = H8300_GPIO_P3,
 411                 .rx   = H8300_GPIO_B3,
 412                 .tx   = H8300_GPIO_B1,
 413         },
 414         {    /* SCI2 */
 415                 .port = H8300_GPIO_P5,
 416                 .rx   = H8300_GPIO_B1,
 417                 .tx   = H8300_GPIO_B0,
 418         }
 419 #endif
 420 };
 421 #endif
 422
 423 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
 424 static inline int sci_rxd_in(struct uart_port *port)
 425 {
 426         if (port->mapbase == 0xfffffe80)
 427                 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
 428         return 1;
 429 }
 430 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 431       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 432       defined(CONFIG_CPU_SUBTYPE_SH7706)
 433 static inline int sci_rxd_in(struct uart_port *port)
 434 {
 435         if (port->mapbase == 0xfffffe80)
 436                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 437         if (port->mapbase == 0xa4000150)
 438                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 439         if (port->mapbase == 0xa4000140)
 440                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 441         return 1;
 442 }
 443 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 444 static inline int sci_rxd_in(struct uart_port *port)
 445 {
 446         if (port->mapbase == SCIF0)
 447                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 448         if (port->mapbase == SCIF2)
 449                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 450         return 1;
 451 }
 452 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
 453 static inline int sci_rxd_in(struct uart_port *port)
 454 {
 455         if (port->mapbase == SCSPTR0)
 456                 return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0;
 457         return 1;
 458 }
 459 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 460       defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 461       defined(CONFIG_CPU_SUBTYPE_SH4_202)
 462 static inline int sci_rxd_in(struct uart_port *port)
 463 {
 464 #ifndef SCIF_ONLY
 465         if (port->mapbase == 0xffe00000)
 466                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 467 #endif
 468 #ifndef SCI_ONLY
 469         if (port->mapbase == 0xffe80000)
 470                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 471 #endif
 472         return 1;
 473 }
 474 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 475 static inline int sci_rxd_in(struct uart_port *port)
 476 {
 477         if (port->mapbase == 0xfe600000)
 478                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 479         if (port->mapbase == 0xfe610000)
 480                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 481         if (port->mapbase == 0xfe620000)
 482                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 483 }
 484 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
 485 static inline int sci_rxd_in(struct uart_port *port)
 486 {
 487         if (port->mapbase == 0xa4430000)
 488                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 489         return 1;
 490 }
 491 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
 492 static inline int sci_rxd_in(struct uart_port *port)
 493 {
 494         return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 495 }
 496 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 497 static inline int sci_rxd_in(struct uart_port *port)
 498 {
 499         if (port->mapbase == 0xffe00000)
 500                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 501         if (port->mapbase == 0xffe10000)
 502                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 503         if (port->mapbase == 0xffe20000)
 504                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 505         if (port->mapbase == 0xffe30000)
 506                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 507         return 1;
 508 }
 509 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 510 static inline int sci_rxd_in(struct uart_port *port)
 511 {
 512         if (port->mapbase == 0xffe00000)
 513                 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
 514         else
 515                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 516
 517 }
 518 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 519 static inline int sci_rxd_in(struct uart_port *port)
 520 {
 521          return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
 522 }
 523 #elif defined(__H8300H__) || defined(__H8300S__)
 524 static inline int sci_rxd_in(struct uart_port *port)
 525 {
 526         int ch = (port->mapbase - SMR0) >> 3;
 527         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 528 }
 529 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 530 static inline int sci_rxd_in(struct uart_port *port)
 531 {
 532         if (port->mapbase == 0xff923000)
 533                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 534         if (port->mapbase == 0xff924000)
 535                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 536         if (port->mapbase == 0xff925000)
 537                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 538 }
 539 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 540 static inline int sci_rxd_in(struct uart_port *port)
 541 {
 542         if (port->mapbase == 0xffe00000)
 543                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 544         if (port->mapbase == 0xffe10000)
 545                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 546 }
 547 #endif
 548
 549 /*
 550  * Values for the BitRate Register (SCBRR)
 551  *
 552  * The values are actually divisors for a frequency which can
 553  * be internal to the SH3 (14.7456MHz) or derived from an external
 554  * clock source.  This driver assumes the internal clock is used;
 555  * to support using an external clock source, config options or
 556  * possibly command-line options would need to be added.
 557  *
 558  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 559  * the SCSMR register would also need to be set to non-zero values.
 560  *
 561  * -- Greg Banks 27Feb2000
 562  *
 563  * Answer: The SCBRR register is only eight bits, and the value in
 564  * it gets larger with lower baud rates. At around 2400 (depending on
 565  * the peripherial module clock) you run out of bits. However the
 566  * lower two bits of SCSMR allow the module clock to be divided down,
 567  * scaling the value which is needed in SCBRR.
 568  *
 569  * -- Stuart Menefy - 23 May 2000
 570  *
 571  * I meant, why would anyone bother with bitrates below 2400.
 572  *
 573  * -- Greg Banks - 7Jul2000
 574  *
 575  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 576  * tape reader as a console!
 577  *
 578  * -- Mitch Davis - 15 Jul 2000
 579  */
 580
 581 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780)
 582 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 583 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 584 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 585 #elif defined(__H8300H__) || defined(__H8300S__)
 586 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
 587 #elif defined(CONFIG_SUPERH64)
 588 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
 589 #else /* Generic SH */
 590 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 591 #endif