2 * Helper routines for SuperH Clock Pulse Generator blocks (CPG).
4 * Copyright (C) 2010 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk.h>
11 #include <linux/compiler.h>
12 #include <linux/slab.h>
14 #include <linux/sh_clk.h>
16 static int sh_clk_mstp32_enable(struct clk
*clk
)
18 __raw_writel(__raw_readl(clk
->enable_reg
) & ~(1 << clk
->enable_bit
),
23 static void sh_clk_mstp32_disable(struct clk
*clk
)
25 __raw_writel(__raw_readl(clk
->enable_reg
) | (1 << clk
->enable_bit
),
29 static struct clk_ops sh_clk_mstp32_clk_ops
= {
30 .enable
= sh_clk_mstp32_enable
,
31 .disable
= sh_clk_mstp32_disable
,
32 .recalc
= followparent_recalc
,
35 int __init
sh_clk_mstp32_register(struct clk
*clks
, int nr
)
41 for (k
= 0; !ret
&& (k
< nr
); k
++) {
43 clkp
->ops
= &sh_clk_mstp32_clk_ops
;
44 ret
|= clk_register(clkp
);
50 static long sh_clk_div_round_rate(struct clk
*clk
, unsigned long rate
)
52 return clk_rate_table_round(clk
, clk
->freq_table
, rate
);
55 static int sh_clk_div6_divisors
[64] = {
56 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
57 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
58 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
59 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
62 static struct clk_div_mult_table sh_clk_div6_table
= {
63 .divisors
= sh_clk_div6_divisors
,
64 .nr_divisors
= ARRAY_SIZE(sh_clk_div6_divisors
),
67 static unsigned long sh_clk_div6_recalc(struct clk
*clk
)
69 struct clk_div_mult_table
*table
= &sh_clk_div6_table
;
72 clk_rate_table_build(clk
, clk
->freq_table
, table
->nr_divisors
,
75 idx
= __raw_readl(clk
->enable_reg
) & 0x003f;
77 return clk
->freq_table
[idx
].frequency
;
80 static int sh_clk_div6_set_parent(struct clk
*clk
, struct clk
*parent
)
82 struct clk_div_mult_table
*table
= &sh_clk_div6_table
;
86 if (!clk
->parent_table
|| !clk
->parent_num
)
89 /* Search the parent */
90 for (i
= 0; i
< clk
->parent_num
; i
++)
91 if (clk
->parent_table
[i
] == parent
)
94 if (i
== clk
->parent_num
)
97 ret
= clk_reparent(clk
, parent
);
101 value
= __raw_readl(clk
->enable_reg
) &
102 ~(((1 << clk
->src_width
) - 1) << clk
->src_shift
);
104 __raw_writel(value
| (i
<< clk
->src_shift
), clk
->enable_reg
);
106 /* Rebuild the frequency table */
107 clk_rate_table_build(clk
, clk
->freq_table
, table
->nr_divisors
,
108 table
, &clk
->arch_flags
);
113 static int sh_clk_div6_set_rate(struct clk
*clk
,
114 unsigned long rate
, int algo_id
)
119 idx
= clk_rate_table_find(clk
, clk
->freq_table
, rate
);
123 value
= __raw_readl(clk
->enable_reg
);
126 __raw_writel(value
, clk
->enable_reg
);
130 static int sh_clk_div6_enable(struct clk
*clk
)
135 ret
= sh_clk_div6_set_rate(clk
, clk
->rate
, 0);
137 value
= __raw_readl(clk
->enable_reg
);
138 value
&= ~0x100; /* clear stop bit to enable clock */
139 __raw_writel(value
, clk
->enable_reg
);
144 static void sh_clk_div6_disable(struct clk
*clk
)
148 value
= __raw_readl(clk
->enable_reg
);
149 value
|= 0x100; /* stop clock */
150 value
|= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
151 __raw_writel(value
, clk
->enable_reg
);
154 static struct clk_ops sh_clk_div6_clk_ops
= {
155 .recalc
= sh_clk_div6_recalc
,
156 .round_rate
= sh_clk_div_round_rate
,
157 .set_rate
= sh_clk_div6_set_rate
,
158 .enable
= sh_clk_div6_enable
,
159 .disable
= sh_clk_div6_disable
,
162 static struct clk_ops sh_clk_div6_reparent_clk_ops
= {
163 .recalc
= sh_clk_div6_recalc
,
164 .round_rate
= sh_clk_div_round_rate
,
165 .set_rate
= sh_clk_div6_set_rate
,
166 .enable
= sh_clk_div6_enable
,
167 .disable
= sh_clk_div6_disable
,
168 .set_parent
= sh_clk_div6_set_parent
,
171 static int __init
sh_clk_div6_register_ops(struct clk
*clks
, int nr
,
176 int nr_divs
= sh_clk_div6_table
.nr_divisors
;
177 int freq_table_size
= sizeof(struct cpufreq_frequency_table
);
181 freq_table_size
*= (nr_divs
+ 1);
182 freq_table
= kzalloc(freq_table_size
* nr
, GFP_KERNEL
);
184 pr_err("sh_clk_div6_register: unable to alloc memory\n");
188 for (k
= 0; !ret
&& (k
< nr
); k
++) {
192 clkp
->freq_table
= freq_table
+ (k
* freq_table_size
);
193 clkp
->freq_table
[nr_divs
].frequency
= CPUFREQ_TABLE_END
;
195 ret
= clk_register(clkp
);
201 int __init
sh_clk_div6_register(struct clk
*clks
, int nr
)
203 return sh_clk_div6_register_ops(clks
, nr
, &sh_clk_div6_clk_ops
);
206 int __init
sh_clk_div6_reparent_register(struct clk
*clks
, int nr
)
208 return sh_clk_div6_register_ops(clks
, nr
,
209 &sh_clk_div6_reparent_clk_ops
);
212 static unsigned long sh_clk_div4_recalc(struct clk
*clk
)
214 struct clk_div4_table
*d4t
= clk
->priv
;
215 struct clk_div_mult_table
*table
= d4t
->div_mult_table
;
218 clk_rate_table_build(clk
, clk
->freq_table
, table
->nr_divisors
,
219 table
, &clk
->arch_flags
);
221 idx
= (__raw_readl(clk
->enable_reg
) >> clk
->enable_bit
) & 0x000f;
223 return clk
->freq_table
[idx
].frequency
;
226 static int sh_clk_div4_set_parent(struct clk
*clk
, struct clk
*parent
)
228 struct clk_div4_table
*d4t
= clk
->priv
;
229 struct clk_div_mult_table
*table
= d4t
->div_mult_table
;
233 /* we really need a better way to determine parent index, but for
234 * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
235 * no CLK_ENABLE_ON_INIT means external clock...
238 if (parent
->flags
& CLK_ENABLE_ON_INIT
)
239 value
= __raw_readl(clk
->enable_reg
) & ~(1 << 7);
241 value
= __raw_readl(clk
->enable_reg
) | (1 << 7);
243 ret
= clk_reparent(clk
, parent
);
247 __raw_writel(value
, clk
->enable_reg
);
249 /* Rebiuld the frequency table */
250 clk_rate_table_build(clk
, clk
->freq_table
, table
->nr_divisors
,
251 table
, &clk
->arch_flags
);
256 static int sh_clk_div4_set_rate(struct clk
*clk
, unsigned long rate
, int algo_id
)
258 struct clk_div4_table
*d4t
= clk
->priv
;
260 int idx
= clk_rate_table_find(clk
, clk
->freq_table
, rate
);
264 value
= __raw_readl(clk
->enable_reg
);
265 value
&= ~(0xf << clk
->enable_bit
);
266 value
|= (idx
<< clk
->enable_bit
);
267 __raw_writel(value
, clk
->enable_reg
);
275 static int sh_clk_div4_enable(struct clk
*clk
)
277 __raw_writel(__raw_readl(clk
->enable_reg
) & ~(1 << 8), clk
->enable_reg
);
281 static void sh_clk_div4_disable(struct clk
*clk
)
283 __raw_writel(__raw_readl(clk
->enable_reg
) | (1 << 8), clk
->enable_reg
);
286 static struct clk_ops sh_clk_div4_clk_ops
= {
287 .recalc
= sh_clk_div4_recalc
,
288 .set_rate
= sh_clk_div4_set_rate
,
289 .round_rate
= sh_clk_div_round_rate
,
292 static struct clk_ops sh_clk_div4_enable_clk_ops
= {
293 .recalc
= sh_clk_div4_recalc
,
294 .set_rate
= sh_clk_div4_set_rate
,
295 .round_rate
= sh_clk_div_round_rate
,
296 .enable
= sh_clk_div4_enable
,
297 .disable
= sh_clk_div4_disable
,
300 static struct clk_ops sh_clk_div4_reparent_clk_ops
= {
301 .recalc
= sh_clk_div4_recalc
,
302 .set_rate
= sh_clk_div4_set_rate
,
303 .round_rate
= sh_clk_div_round_rate
,
304 .enable
= sh_clk_div4_enable
,
305 .disable
= sh_clk_div4_disable
,
306 .set_parent
= sh_clk_div4_set_parent
,
309 static int __init
sh_clk_div4_register_ops(struct clk
*clks
, int nr
,
310 struct clk_div4_table
*table
, struct clk_ops
*ops
)
314 int nr_divs
= table
->div_mult_table
->nr_divisors
;
315 int freq_table_size
= sizeof(struct cpufreq_frequency_table
);
319 freq_table_size
*= (nr_divs
+ 1);
320 freq_table
= kzalloc(freq_table_size
* nr
, GFP_KERNEL
);
322 pr_err("sh_clk_div4_register: unable to alloc memory\n");
326 for (k
= 0; !ret
&& (k
< nr
); k
++) {
332 clkp
->freq_table
= freq_table
+ (k
* freq_table_size
);
333 clkp
->freq_table
[nr_divs
].frequency
= CPUFREQ_TABLE_END
;
335 ret
= clk_register(clkp
);
341 int __init
sh_clk_div4_register(struct clk
*clks
, int nr
,
342 struct clk_div4_table
*table
)
344 return sh_clk_div4_register_ops(clks
, nr
, table
, &sh_clk_div4_clk_ops
);
347 int __init
sh_clk_div4_enable_register(struct clk
*clks
, int nr
,
348 struct clk_div4_table
*table
)
350 return sh_clk_div4_register_ops(clks
, nr
, table
,
351 &sh_clk_div4_enable_clk_ops
);
354 int __init
sh_clk_div4_reparent_register(struct clk
*clks
, int nr
,
355 struct clk_div4_table
*table
)
357 return sh_clk_div4_register_ops(clks
, nr
, table
,
358 &sh_clk_div4_reparent_clk_ops
);