drivers/soc/fsl/qe/qe_io.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * arch/powerpc/sysdev/qe_lib/qe_io.c
   4  *
   5  * QE Parallel I/O ports configuration routines
   6  *
   7  * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
   8  *
   9  * Author: Li Yang <LeoLi@freescale.com>
  10  * Based on code from Shlomi Gridish <gridish@freescale.com>
  11  */
  12
  13 #include <linux/stddef.h>
  14 #include <linux/kernel.h>
  15 #include <linux/errno.h>
  16 #include <linux/module.h>
  17 #include <linux/ioport.h>
  18
  19 #include <asm/io.h>
  20 #include <soc/fsl/qe/qe.h>
  21
  22 #undef DEBUG
  23
  24 static struct qe_pio_regs __iomem *par_io;
  25 static int num_par_io_ports = 0;
  26
  27 int par_io_init(struct device_node *np)
  28 {
  29         struct resource res;
  30         int ret;
  31         u32 num_ports;
  32
  33         /* Map Parallel I/O ports registers */
  34         ret = of_address_to_resource(np, 0, &res);
  35         if (ret)
  36                 return ret;
  37         par_io = ioremap(res.start, resource_size(&res));
  38
  39         if (!of_property_read_u32(np, "num-ports", &num_ports))
  40                 num_par_io_ports = num_ports;
  41
  42         return 0;
  43 }
  44
  45 void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
  46                          int open_drain, int assignment, int has_irq)
  47 {
  48         u32 pin_mask1bit;
  49         u32 pin_mask2bits;
  50         u32 new_mask2bits;
  51         u32 tmp_val;
  52
  53         /* calculate pin location for single and 2 bits information */
  54         pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
  55
  56         /* Set open drain, if required */
  57         tmp_val = ioread32be(&par_io->cpodr);
  58         if (open_drain)
  59                 iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
  60         else
  61                 iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
  62
  63         /* define direction */
  64         tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
  65                 ioread32be(&par_io->cpdir2) :
  66                 ioread32be(&par_io->cpdir1);
  67
  68         /* get all bits mask for 2 bit per port */
  69         pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
  70                                 (pin % (QE_PIO_PINS / 2) + 1) * 2));
  71
  72         /* Get the final mask we need for the right definition */
  73         new_mask2bits = (u32) (dir << (QE_PIO_PINS -
  74                                 (pin % (QE_PIO_PINS / 2) + 1) * 2));
  75
  76         /* clear and set 2 bits mask */
  77         if (pin > (QE_PIO_PINS / 2) - 1) {
  78                 iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
  79                 tmp_val &= ~pin_mask2bits;
  80                 iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
  81         } else {
  82                 iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
  83                 tmp_val &= ~pin_mask2bits;
  84                 iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
  85         }
  86         /* define pin assignment */
  87         tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
  88                 ioread32be(&par_io->cppar2) :
  89                 ioread32be(&par_io->cppar1);
  90
  91         new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
  92                         (pin % (QE_PIO_PINS / 2) + 1) * 2));
  93         /* clear and set 2 bits mask */
  94         if (pin > (QE_PIO_PINS / 2) - 1) {
  95                 iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
  96                 tmp_val &= ~pin_mask2bits;
  97                 iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
  98         } else {
  99                 iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
 100                 tmp_val &= ~pin_mask2bits;
 101                 iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
 102         }
 103 }
 104 EXPORT_SYMBOL(__par_io_config_pin);
 105
 106 int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
 107                       int assignment, int has_irq)
 108 {
 109         if (!par_io || port >= num_par_io_ports)
 110                 return -EINVAL;
 111
 112         __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment,
 113                             has_irq);
 114         return 0;
 115 }
 116 EXPORT_SYMBOL(par_io_config_pin);
 117
 118 int par_io_data_set(u8 port, u8 pin, u8 val)
 119 {
 120         u32 pin_mask, tmp_val;
 121
 122         if (port >= num_par_io_ports)
 123                 return -EINVAL;
 124         if (pin >= QE_PIO_PINS)
 125                 return -EINVAL;
 126         /* calculate pin location */
 127         pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
 128
 129         tmp_val = ioread32be(&par_io[port].cpdata);
 130
 131         if (val == 0)           /* clear */
 132                 iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
 133         else                    /* set */
 134                 iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
 135
 136         return 0;
 137 }
 138 EXPORT_SYMBOL(par_io_data_set);
 139
 140 int par_io_of_config(struct device_node *np)
 141 {
 142         struct device_node *pio;
 143         int pio_map_len;
 144         const __be32 *pio_map;
 145
 146         if (par_io == NULL) {
 147                 printk(KERN_ERR "par_io not initialized\n");
 148                 return -1;
 149         }
 150
 151         pio = of_parse_phandle(np, "pio-handle", 0);
 152         if (pio == NULL) {
 153                 printk(KERN_ERR "pio-handle not available\n");
 154                 return -1;
 155         }
 156
 157         pio_map = of_get_property(pio, "pio-map", &pio_map_len);
 158         if (pio_map == NULL) {
 159                 printk(KERN_ERR "pio-map is not set!\n");
 160                 return -1;
 161         }
 162         pio_map_len /= sizeof(unsigned int);
 163         if ((pio_map_len % 6) != 0) {
 164                 printk(KERN_ERR "pio-map format wrong!\n");
 165                 return -1;
 166         }
 167
 168         while (pio_map_len > 0) {
 169                 u8 port        = be32_to_cpu(pio_map[0]);
 170                 u8 pin         = be32_to_cpu(pio_map[1]);
 171                 int dir        = be32_to_cpu(pio_map[2]);
 172                 int open_drain = be32_to_cpu(pio_map[3]);
 173                 int assignment = be32_to_cpu(pio_map[4]);
 174                 int has_irq    = be32_to_cpu(pio_map[5]);
 175
 176                 par_io_config_pin(port, pin, dir, open_drain,
 177                                   assignment, has_irq);
 178                 pio_map += 6;
 179                 pio_map_len -= 6;
 180         }
 181         of_node_put(pio);
 182         return 0;
 183 }
 184 EXPORT_SYMBOL(par_io_of_config);