2 * Rockchip Generic power domain support.
4 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/iopoll.h>
13 #include <linux/err.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_platform.h>
19 #include <linux/clk.h>
20 #include <linux/regmap.h>
21 #include <linux/mfd/syscon.h>
22 #include <dt-bindings/power/px30-power.h>
23 #include <dt-bindings/power/rk3036-power.h>
24 #include <dt-bindings/power/rk3066-power.h>
25 #include <dt-bindings/power/rk3128-power.h>
26 #include <dt-bindings/power/rk3188-power.h>
27 #include <dt-bindings/power/rk3228-power.h>
28 #include <dt-bindings/power/rk3288-power.h>
29 #include <dt-bindings/power/rk3328-power.h>
30 #include <dt-bindings/power/rk3366-power.h>
31 #include <dt-bindings/power/rk3368-power.h>
32 #include <dt-bindings/power/rk3399-power.h>
34 struct rockchip_domain_info
{
45 struct rockchip_pmu_info
{
52 u32 core_pwrcnt_offset
;
53 u32 gpu_pwrcnt_offset
;
55 unsigned int core_power_transition_time
;
56 unsigned int gpu_power_transition_time
;
59 const struct rockchip_domain_info
*domain_info
;
62 #define MAX_QOS_REGS_NUM 5
63 #define QOS_PRIORITY 0x08
65 #define QOS_BANDWIDTH 0x10
66 #define QOS_SATURATION 0x14
67 #define QOS_EXTCONTROL 0x18
69 struct rockchip_pm_domain
{
70 struct generic_pm_domain genpd
;
71 const struct rockchip_domain_info
*info
;
72 struct rockchip_pmu
*pmu
;
74 struct regmap
**qos_regmap
;
75 u32
*qos_save_regs
[MAX_QOS_REGS_NUM
];
77 struct clk_bulk_data
*clks
;
82 struct regmap
*regmap
;
83 const struct rockchip_pmu_info
*info
;
84 struct mutex mutex
; /* mutex lock for pmu */
85 struct genpd_onecell_data genpd_data
;
86 struct generic_pm_domain
*domains
[];
89 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
91 #define DOMAIN(pwr, status, req, idle, ack, wakeup) \
93 .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
94 .status_mask = (status >= 0) ? BIT(status) : 0, \
95 .req_mask = (req >= 0) ? BIT(req) : 0, \
96 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
97 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
98 .active_wakeup = wakeup, \
101 #define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
103 .pwr_w_mask = (pwr >= 0) ? BIT(pwr + 16) : 0, \
104 .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
105 .status_mask = (status >= 0) ? BIT(status) : 0, \
106 .req_w_mask = (req >= 0) ? BIT(req + 16) : 0, \
107 .req_mask = (req >= 0) ? BIT(req) : 0, \
108 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
109 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
110 .active_wakeup = wakeup, \
113 #define DOMAIN_RK3036(req, ack, idle, wakeup) \
115 .req_mask = (req >= 0) ? BIT(req) : 0, \
116 .req_w_mask = (req >= 0) ? BIT(req + 16) : 0, \
117 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
118 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
119 .active_wakeup = wakeup, \
122 #define DOMAIN_PX30(pwr, status, req, wakeup) \
123 DOMAIN_M(pwr, status, req, (req) + 16, req, wakeup)
125 #define DOMAIN_RK3288(pwr, status, req, wakeup) \
126 DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
128 #define DOMAIN_RK3328(pwr, status, req, wakeup) \
129 DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup)
131 #define DOMAIN_RK3368(pwr, status, req, wakeup) \
132 DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
134 #define DOMAIN_RK3399(pwr, status, req, wakeup) \
135 DOMAIN(pwr, status, req, req, req, wakeup)
137 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain
*pd
)
139 struct rockchip_pmu
*pmu
= pd
->pmu
;
140 const struct rockchip_domain_info
*pd_info
= pd
->info
;
143 regmap_read(pmu
->regmap
, pmu
->info
->idle_offset
, &val
);
144 return (val
& pd_info
->idle_mask
) == pd_info
->idle_mask
;
147 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu
*pmu
)
151 regmap_read(pmu
->regmap
, pmu
->info
->ack_offset
, &val
);
155 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain
*pd
,
158 const struct rockchip_domain_info
*pd_info
= pd
->info
;
159 struct generic_pm_domain
*genpd
= &pd
->genpd
;
160 struct rockchip_pmu
*pmu
= pd
->pmu
;
161 unsigned int target_ack
;
166 if (pd_info
->req_mask
== 0)
168 else if (pd_info
->req_w_mask
)
169 regmap_write(pmu
->regmap
, pmu
->info
->req_offset
,
170 idle
? (pd_info
->req_mask
| pd_info
->req_w_mask
) :
171 pd_info
->req_w_mask
);
173 regmap_update_bits(pmu
->regmap
, pmu
->info
->req_offset
,
174 pd_info
->req_mask
, idle
? -1U : 0);
178 /* Wait util idle_ack = 1 */
179 target_ack
= idle
? pd_info
->ack_mask
: 0;
180 ret
= readx_poll_timeout_atomic(rockchip_pmu_read_ack
, pmu
, val
,
181 (val
& pd_info
->ack_mask
) == target_ack
,
185 "failed to get ack on domain '%s', val=0x%x\n",
190 ret
= readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle
, pd
,
191 is_idle
, is_idle
== idle
, 0, 10000);
194 "failed to set idle on domain '%s', val=%d\n",
195 genpd
->name
, is_idle
);
202 static int rockchip_pmu_save_qos(struct rockchip_pm_domain
*pd
)
206 for (i
= 0; i
< pd
->num_qos
; i
++) {
207 regmap_read(pd
->qos_regmap
[i
],
209 &pd
->qos_save_regs
[0][i
]);
210 regmap_read(pd
->qos_regmap
[i
],
212 &pd
->qos_save_regs
[1][i
]);
213 regmap_read(pd
->qos_regmap
[i
],
215 &pd
->qos_save_regs
[2][i
]);
216 regmap_read(pd
->qos_regmap
[i
],
218 &pd
->qos_save_regs
[3][i
]);
219 regmap_read(pd
->qos_regmap
[i
],
221 &pd
->qos_save_regs
[4][i
]);
226 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain
*pd
)
230 for (i
= 0; i
< pd
->num_qos
; i
++) {
231 regmap_write(pd
->qos_regmap
[i
],
233 pd
->qos_save_regs
[0][i
]);
234 regmap_write(pd
->qos_regmap
[i
],
236 pd
->qos_save_regs
[1][i
]);
237 regmap_write(pd
->qos_regmap
[i
],
239 pd
->qos_save_regs
[2][i
]);
240 regmap_write(pd
->qos_regmap
[i
],
242 pd
->qos_save_regs
[3][i
]);
243 regmap_write(pd
->qos_regmap
[i
],
245 pd
->qos_save_regs
[4][i
]);
251 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain
*pd
)
253 struct rockchip_pmu
*pmu
= pd
->pmu
;
256 /* check idle status for idle-only domains */
257 if (pd
->info
->status_mask
== 0)
258 return !rockchip_pmu_domain_is_idle(pd
);
260 regmap_read(pmu
->regmap
, pmu
->info
->status_offset
, &val
);
262 /* 1'b0: power on, 1'b1: power off */
263 return !(val
& pd
->info
->status_mask
);
266 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain
*pd
,
269 struct rockchip_pmu
*pmu
= pd
->pmu
;
270 struct generic_pm_domain
*genpd
= &pd
->genpd
;
273 if (pd
->info
->pwr_mask
== 0)
275 else if (pd
->info
->pwr_w_mask
)
276 regmap_write(pmu
->regmap
, pmu
->info
->pwr_offset
,
277 on
? pd
->info
->pwr_w_mask
:
278 (pd
->info
->pwr_mask
| pd
->info
->pwr_w_mask
));
280 regmap_update_bits(pmu
->regmap
, pmu
->info
->pwr_offset
,
281 pd
->info
->pwr_mask
, on
? 0 : -1U);
285 if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on
, pd
, is_on
,
286 is_on
== on
, 0, 10000)) {
288 "failed to set domain '%s', val=%d\n",
294 static int rockchip_pd_power(struct rockchip_pm_domain
*pd
, bool power_on
)
296 struct rockchip_pmu
*pmu
= pd
->pmu
;
299 mutex_lock(&pmu
->mutex
);
301 if (rockchip_pmu_domain_is_on(pd
) != power_on
) {
302 ret
= clk_bulk_enable(pd
->num_clks
, pd
->clks
);
304 dev_err(pmu
->dev
, "failed to enable clocks\n");
305 mutex_unlock(&pmu
->mutex
);
310 rockchip_pmu_save_qos(pd
);
312 /* if powering down, idle request to NIU first */
313 rockchip_pmu_set_idle_request(pd
, true);
316 rockchip_do_pmu_set_power_domain(pd
, power_on
);
319 /* if powering up, leave idle mode */
320 rockchip_pmu_set_idle_request(pd
, false);
322 rockchip_pmu_restore_qos(pd
);
325 clk_bulk_disable(pd
->num_clks
, pd
->clks
);
328 mutex_unlock(&pmu
->mutex
);
332 static int rockchip_pd_power_on(struct generic_pm_domain
*domain
)
334 struct rockchip_pm_domain
*pd
= to_rockchip_pd(domain
);
336 return rockchip_pd_power(pd
, true);
339 static int rockchip_pd_power_off(struct generic_pm_domain
*domain
)
341 struct rockchip_pm_domain
*pd
= to_rockchip_pd(domain
);
343 return rockchip_pd_power(pd
, false);
346 static int rockchip_pd_attach_dev(struct generic_pm_domain
*genpd
,
353 dev_dbg(dev
, "attaching to power domain '%s'\n", genpd
->name
);
355 error
= pm_clk_create(dev
);
357 dev_err(dev
, "pm_clk_create failed %d\n", error
);
362 while ((clk
= of_clk_get(dev
->of_node
, i
++)) && !IS_ERR(clk
)) {
363 dev_dbg(dev
, "adding clock '%pC' to list of PM clocks\n", clk
);
364 error
= pm_clk_add_clk(dev
, clk
);
366 dev_err(dev
, "pm_clk_add_clk failed %d\n", error
);
376 static void rockchip_pd_detach_dev(struct generic_pm_domain
*genpd
,
379 dev_dbg(dev
, "detaching from power domain '%s'\n", genpd
->name
);
384 static int rockchip_pm_add_one_domain(struct rockchip_pmu
*pmu
,
385 struct device_node
*node
)
387 const struct rockchip_domain_info
*pd_info
;
388 struct rockchip_pm_domain
*pd
;
389 struct device_node
*qos_node
;
394 error
= of_property_read_u32(node
, "reg", &id
);
397 "%pOFn: failed to retrieve domain id (reg): %d\n",
402 if (id
>= pmu
->info
->num_domains
) {
403 dev_err(pmu
->dev
, "%pOFn: invalid domain id %d\n",
408 pd_info
= &pmu
->info
->domain_info
[id
];
410 dev_err(pmu
->dev
, "%pOFn: undefined domain id %d\n",
415 pd
= devm_kzalloc(pmu
->dev
, sizeof(*pd
), GFP_KERNEL
);
422 pd
->num_clks
= of_clk_get_parent_count(node
);
423 if (pd
->num_clks
> 0) {
424 pd
->clks
= devm_kcalloc(pmu
->dev
, pd
->num_clks
,
425 sizeof(*pd
->clks
), GFP_KERNEL
);
429 dev_dbg(pmu
->dev
, "%pOFn: doesn't have clocks: %d\n",
434 for (i
= 0; i
< pd
->num_clks
; i
++) {
435 pd
->clks
[i
].clk
= of_clk_get(node
, i
);
436 if (IS_ERR(pd
->clks
[i
].clk
)) {
437 error
= PTR_ERR(pd
->clks
[i
].clk
);
439 "%pOFn: failed to get clk at index %d: %d\n",
445 error
= clk_bulk_prepare(pd
->num_clks
, pd
->clks
);
449 pd
->num_qos
= of_count_phandle_with_args(node
, "pm_qos",
452 if (pd
->num_qos
> 0) {
453 pd
->qos_regmap
= devm_kcalloc(pmu
->dev
, pd
->num_qos
,
454 sizeof(*pd
->qos_regmap
),
456 if (!pd
->qos_regmap
) {
458 goto err_unprepare_clocks
;
461 for (j
= 0; j
< MAX_QOS_REGS_NUM
; j
++) {
462 pd
->qos_save_regs
[j
] = devm_kcalloc(pmu
->dev
,
466 if (!pd
->qos_save_regs
[j
]) {
468 goto err_unprepare_clocks
;
472 for (j
= 0; j
< pd
->num_qos
; j
++) {
473 qos_node
= of_parse_phandle(node
, "pm_qos", j
);
476 goto err_unprepare_clocks
;
478 pd
->qos_regmap
[j
] = syscon_node_to_regmap(qos_node
);
479 if (IS_ERR(pd
->qos_regmap
[j
])) {
481 of_node_put(qos_node
);
482 goto err_unprepare_clocks
;
484 of_node_put(qos_node
);
488 error
= rockchip_pd_power(pd
, true);
491 "failed to power on domain '%pOFn': %d\n",
493 goto err_unprepare_clocks
;
496 pd
->genpd
.name
= node
->name
;
497 pd
->genpd
.power_off
= rockchip_pd_power_off
;
498 pd
->genpd
.power_on
= rockchip_pd_power_on
;
499 pd
->genpd
.attach_dev
= rockchip_pd_attach_dev
;
500 pd
->genpd
.detach_dev
= rockchip_pd_detach_dev
;
501 pd
->genpd
.flags
= GENPD_FLAG_PM_CLK
;
502 if (pd_info
->active_wakeup
)
503 pd
->genpd
.flags
|= GENPD_FLAG_ACTIVE_WAKEUP
;
504 pm_genpd_init(&pd
->genpd
, NULL
, false);
506 pmu
->genpd_data
.domains
[id
] = &pd
->genpd
;
509 err_unprepare_clocks
:
510 clk_bulk_unprepare(pd
->num_clks
, pd
->clks
);
512 clk_bulk_put(pd
->num_clks
, pd
->clks
);
516 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain
*pd
)
521 * We're in the error cleanup already, so we only complain,
522 * but won't emit another error on top of the original one.
524 ret
= pm_genpd_remove(&pd
->genpd
);
526 dev_err(pd
->pmu
->dev
, "failed to remove domain '%s' : %d - state may be inconsistent\n",
527 pd
->genpd
.name
, ret
);
529 clk_bulk_unprepare(pd
->num_clks
, pd
->clks
);
530 clk_bulk_put(pd
->num_clks
, pd
->clks
);
532 /* protect the zeroing of pm->num_clks */
533 mutex_lock(&pd
->pmu
->mutex
);
535 mutex_unlock(&pd
->pmu
->mutex
);
537 /* devm will free our memory */
540 static void rockchip_pm_domain_cleanup(struct rockchip_pmu
*pmu
)
542 struct generic_pm_domain
*genpd
;
543 struct rockchip_pm_domain
*pd
;
546 for (i
= 0; i
< pmu
->genpd_data
.num_domains
; i
++) {
547 genpd
= pmu
->genpd_data
.domains
[i
];
549 pd
= to_rockchip_pd(genpd
);
550 rockchip_pm_remove_one_domain(pd
);
554 /* devm will free our memory */
557 static void rockchip_configure_pd_cnt(struct rockchip_pmu
*pmu
,
558 u32 domain_reg_offset
,
561 /* First configure domain power down transition count ... */
562 regmap_write(pmu
->regmap
, domain_reg_offset
, count
);
563 /* ... and then power up count. */
564 regmap_write(pmu
->regmap
, domain_reg_offset
+ 4, count
);
567 static int rockchip_pm_add_subdomain(struct rockchip_pmu
*pmu
,
568 struct device_node
*parent
)
570 struct device_node
*np
;
571 struct generic_pm_domain
*child_domain
, *parent_domain
;
574 for_each_child_of_node(parent
, np
) {
577 error
= of_property_read_u32(parent
, "reg", &idx
);
580 "%pOFn: failed to retrieve domain id (reg): %d\n",
584 parent_domain
= pmu
->genpd_data
.domains
[idx
];
586 error
= rockchip_pm_add_one_domain(pmu
, np
);
588 dev_err(pmu
->dev
, "failed to handle node %pOFn: %d\n",
593 error
= of_property_read_u32(np
, "reg", &idx
);
596 "%pOFn: failed to retrieve domain id (reg): %d\n",
600 child_domain
= pmu
->genpd_data
.domains
[idx
];
602 error
= pm_genpd_add_subdomain(parent_domain
, child_domain
);
604 dev_err(pmu
->dev
, "%s failed to add subdomain %s: %d\n",
605 parent_domain
->name
, child_domain
->name
, error
);
608 dev_dbg(pmu
->dev
, "%s add subdomain: %s\n",
609 parent_domain
->name
, child_domain
->name
);
612 rockchip_pm_add_subdomain(pmu
, np
);
622 static int rockchip_pm_domain_probe(struct platform_device
*pdev
)
624 struct device
*dev
= &pdev
->dev
;
625 struct device_node
*np
= dev
->of_node
;
626 struct device_node
*node
;
627 struct device
*parent
;
628 struct rockchip_pmu
*pmu
;
629 const struct of_device_id
*match
;
630 const struct rockchip_pmu_info
*pmu_info
;
634 dev_err(dev
, "device tree node not found\n");
638 match
= of_match_device(dev
->driver
->of_match_table
, dev
);
639 if (!match
|| !match
->data
) {
640 dev_err(dev
, "missing pmu data\n");
644 pmu_info
= match
->data
;
646 pmu
= devm_kzalloc(dev
,
647 struct_size(pmu
, domains
, pmu_info
->num_domains
),
652 pmu
->dev
= &pdev
->dev
;
653 mutex_init(&pmu
->mutex
);
655 pmu
->info
= pmu_info
;
657 pmu
->genpd_data
.domains
= pmu
->domains
;
658 pmu
->genpd_data
.num_domains
= pmu_info
->num_domains
;
660 parent
= dev
->parent
;
662 dev_err(dev
, "no parent for syscon devices\n");
666 pmu
->regmap
= syscon_node_to_regmap(parent
->of_node
);
667 if (IS_ERR(pmu
->regmap
)) {
668 dev_err(dev
, "no regmap available\n");
669 return PTR_ERR(pmu
->regmap
);
673 * Configure power up and down transition delays for CORE
676 if (pmu_info
->core_power_transition_time
)
677 rockchip_configure_pd_cnt(pmu
, pmu_info
->core_pwrcnt_offset
,
678 pmu_info
->core_power_transition_time
);
679 if (pmu_info
->gpu_pwrcnt_offset
)
680 rockchip_configure_pd_cnt(pmu
, pmu_info
->gpu_pwrcnt_offset
,
681 pmu_info
->gpu_power_transition_time
);
685 for_each_available_child_of_node(np
, node
) {
686 error
= rockchip_pm_add_one_domain(pmu
, node
);
688 dev_err(dev
, "failed to handle node %pOFn: %d\n",
694 error
= rockchip_pm_add_subdomain(pmu
, node
);
696 dev_err(dev
, "failed to handle subdomain node %pOFn: %d\n",
704 dev_dbg(dev
, "no power domains defined\n");
708 error
= of_genpd_add_provider_onecell(np
, &pmu
->genpd_data
);
710 dev_err(dev
, "failed to add provider: %d\n", error
);
717 rockchip_pm_domain_cleanup(pmu
);
721 static const struct rockchip_domain_info px30_pm_domains
[] = {
722 [PX30_PD_USB
] = DOMAIN_PX30(5, 5, 10, false),
723 [PX30_PD_SDCARD
] = DOMAIN_PX30(8, 8, 9, false),
724 [PX30_PD_GMAC
] = DOMAIN_PX30(10, 10, 6, false),
725 [PX30_PD_MMC_NAND
] = DOMAIN_PX30(11, 11, 5, false),
726 [PX30_PD_VPU
] = DOMAIN_PX30(12, 12, 14, false),
727 [PX30_PD_VO
] = DOMAIN_PX30(13, 13, 7, false),
728 [PX30_PD_VI
] = DOMAIN_PX30(14, 14, 8, false),
729 [PX30_PD_GPU
] = DOMAIN_PX30(15, 15, 2, false),
732 static const struct rockchip_domain_info rk3036_pm_domains
[] = {
733 [RK3036_PD_MSCH
] = DOMAIN_RK3036(14, 23, 30, true),
734 [RK3036_PD_CORE
] = DOMAIN_RK3036(13, 17, 24, false),
735 [RK3036_PD_PERI
] = DOMAIN_RK3036(12, 18, 25, false),
736 [RK3036_PD_VIO
] = DOMAIN_RK3036(11, 19, 26, false),
737 [RK3036_PD_VPU
] = DOMAIN_RK3036(10, 20, 27, false),
738 [RK3036_PD_GPU
] = DOMAIN_RK3036(9, 21, 28, false),
739 [RK3036_PD_SYS
] = DOMAIN_RK3036(8, 22, 29, false),
742 static const struct rockchip_domain_info rk3066_pm_domains
[] = {
743 [RK3066_PD_GPU
] = DOMAIN(9, 9, 3, 24, 29, false),
744 [RK3066_PD_VIDEO
] = DOMAIN(8, 8, 4, 23, 28, false),
745 [RK3066_PD_VIO
] = DOMAIN(7, 7, 5, 22, 27, false),
746 [RK3066_PD_PERI
] = DOMAIN(6, 6, 2, 25, 30, false),
747 [RK3066_PD_CPU
] = DOMAIN(-1, 5, 1, 26, 31, false),
750 static const struct rockchip_domain_info rk3128_pm_domains
[] = {
751 [RK3128_PD_CORE
] = DOMAIN_RK3288(0, 0, 4, false),
752 [RK3128_PD_MSCH
] = DOMAIN_RK3288(-1, -1, 6, true),
753 [RK3128_PD_VIO
] = DOMAIN_RK3288(3, 3, 2, false),
754 [RK3128_PD_VIDEO
] = DOMAIN_RK3288(2, 2, 1, false),
755 [RK3128_PD_GPU
] = DOMAIN_RK3288(1, 1, 3, false),
758 static const struct rockchip_domain_info rk3188_pm_domains
[] = {
759 [RK3188_PD_GPU
] = DOMAIN(9, 9, 3, 24, 29, false),
760 [RK3188_PD_VIDEO
] = DOMAIN(8, 8, 4, 23, 28, false),
761 [RK3188_PD_VIO
] = DOMAIN(7, 7, 5, 22, 27, false),
762 [RK3188_PD_PERI
] = DOMAIN(6, 6, 2, 25, 30, false),
763 [RK3188_PD_CPU
] = DOMAIN(5, 5, 1, 26, 31, false),
766 static const struct rockchip_domain_info rk3228_pm_domains
[] = {
767 [RK3228_PD_CORE
] = DOMAIN_RK3036(0, 0, 16, true),
768 [RK3228_PD_MSCH
] = DOMAIN_RK3036(1, 1, 17, true),
769 [RK3228_PD_BUS
] = DOMAIN_RK3036(2, 2, 18, true),
770 [RK3228_PD_SYS
] = DOMAIN_RK3036(3, 3, 19, true),
771 [RK3228_PD_VIO
] = DOMAIN_RK3036(4, 4, 20, false),
772 [RK3228_PD_VOP
] = DOMAIN_RK3036(5, 5, 21, false),
773 [RK3228_PD_VPU
] = DOMAIN_RK3036(6, 6, 22, false),
774 [RK3228_PD_RKVDEC
] = DOMAIN_RK3036(7, 7, 23, false),
775 [RK3228_PD_GPU
] = DOMAIN_RK3036(8, 8, 24, false),
776 [RK3228_PD_PERI
] = DOMAIN_RK3036(9, 9, 25, true),
777 [RK3228_PD_GMAC
] = DOMAIN_RK3036(10, 10, 26, false),
780 static const struct rockchip_domain_info rk3288_pm_domains
[] = {
781 [RK3288_PD_VIO
] = DOMAIN_RK3288(7, 7, 4, false),
782 [RK3288_PD_HEVC
] = DOMAIN_RK3288(14, 10, 9, false),
783 [RK3288_PD_VIDEO
] = DOMAIN_RK3288(8, 8, 3, false),
784 [RK3288_PD_GPU
] = DOMAIN_RK3288(9, 9, 2, false),
787 static const struct rockchip_domain_info rk3328_pm_domains
[] = {
788 [RK3328_PD_CORE
] = DOMAIN_RK3328(-1, 0, 0, false),
789 [RK3328_PD_GPU
] = DOMAIN_RK3328(-1, 1, 1, false),
790 [RK3328_PD_BUS
] = DOMAIN_RK3328(-1, 2, 2, true),
791 [RK3328_PD_MSCH
] = DOMAIN_RK3328(-1, 3, 3, true),
792 [RK3328_PD_PERI
] = DOMAIN_RK3328(-1, 4, 4, true),
793 [RK3328_PD_VIDEO
] = DOMAIN_RK3328(-1, 5, 5, false),
794 [RK3328_PD_HEVC
] = DOMAIN_RK3328(-1, 6, 6, false),
795 [RK3328_PD_VIO
] = DOMAIN_RK3328(-1, 8, 8, false),
796 [RK3328_PD_VPU
] = DOMAIN_RK3328(-1, 9, 9, false),
799 static const struct rockchip_domain_info rk3366_pm_domains
[] = {
800 [RK3366_PD_PERI
] = DOMAIN_RK3368(10, 10, 6, true),
801 [RK3366_PD_VIO
] = DOMAIN_RK3368(14, 14, 8, false),
802 [RK3366_PD_VIDEO
] = DOMAIN_RK3368(13, 13, 7, false),
803 [RK3366_PD_RKVDEC
] = DOMAIN_RK3368(11, 11, 7, false),
804 [RK3366_PD_WIFIBT
] = DOMAIN_RK3368(8, 8, 9, false),
805 [RK3366_PD_VPU
] = DOMAIN_RK3368(12, 12, 7, false),
806 [RK3366_PD_GPU
] = DOMAIN_RK3368(15, 15, 2, false),
809 static const struct rockchip_domain_info rk3368_pm_domains
[] = {
810 [RK3368_PD_PERI
] = DOMAIN_RK3368(13, 12, 6, true),
811 [RK3368_PD_VIO
] = DOMAIN_RK3368(15, 14, 8, false),
812 [RK3368_PD_VIDEO
] = DOMAIN_RK3368(14, 13, 7, false),
813 [RK3368_PD_GPU_0
] = DOMAIN_RK3368(16, 15, 2, false),
814 [RK3368_PD_GPU_1
] = DOMAIN_RK3368(17, 16, 2, false),
817 static const struct rockchip_domain_info rk3399_pm_domains
[] = {
818 [RK3399_PD_TCPD0
] = DOMAIN_RK3399(8, 8, -1, false),
819 [RK3399_PD_TCPD1
] = DOMAIN_RK3399(9, 9, -1, false),
820 [RK3399_PD_CCI
] = DOMAIN_RK3399(10, 10, -1, true),
821 [RK3399_PD_CCI0
] = DOMAIN_RK3399(-1, -1, 15, true),
822 [RK3399_PD_CCI1
] = DOMAIN_RK3399(-1, -1, 16, true),
823 [RK3399_PD_PERILP
] = DOMAIN_RK3399(11, 11, 1, true),
824 [RK3399_PD_PERIHP
] = DOMAIN_RK3399(12, 12, 2, true),
825 [RK3399_PD_CENTER
] = DOMAIN_RK3399(13, 13, 14, true),
826 [RK3399_PD_VIO
] = DOMAIN_RK3399(14, 14, 17, false),
827 [RK3399_PD_GPU
] = DOMAIN_RK3399(15, 15, 0, false),
828 [RK3399_PD_VCODEC
] = DOMAIN_RK3399(16, 16, 3, false),
829 [RK3399_PD_VDU
] = DOMAIN_RK3399(17, 17, 4, false),
830 [RK3399_PD_RGA
] = DOMAIN_RK3399(18, 18, 5, false),
831 [RK3399_PD_IEP
] = DOMAIN_RK3399(19, 19, 6, false),
832 [RK3399_PD_VO
] = DOMAIN_RK3399(20, 20, -1, false),
833 [RK3399_PD_VOPB
] = DOMAIN_RK3399(-1, -1, 7, false),
834 [RK3399_PD_VOPL
] = DOMAIN_RK3399(-1, -1, 8, false),
835 [RK3399_PD_ISP0
] = DOMAIN_RK3399(22, 22, 9, false),
836 [RK3399_PD_ISP1
] = DOMAIN_RK3399(23, 23, 10, false),
837 [RK3399_PD_HDCP
] = DOMAIN_RK3399(24, 24, 11, false),
838 [RK3399_PD_GMAC
] = DOMAIN_RK3399(25, 25, 23, true),
839 [RK3399_PD_EMMC
] = DOMAIN_RK3399(26, 26, 24, true),
840 [RK3399_PD_USB3
] = DOMAIN_RK3399(27, 27, 12, true),
841 [RK3399_PD_EDP
] = DOMAIN_RK3399(28, 28, 22, false),
842 [RK3399_PD_GIC
] = DOMAIN_RK3399(29, 29, 27, true),
843 [RK3399_PD_SD
] = DOMAIN_RK3399(30, 30, 28, true),
844 [RK3399_PD_SDIOAUDIO
] = DOMAIN_RK3399(31, 31, 29, true),
847 static const struct rockchip_pmu_info px30_pmu
= {
849 .status_offset
= 0x20,
854 .num_domains
= ARRAY_SIZE(px30_pm_domains
),
855 .domain_info
= px30_pm_domains
,
858 static const struct rockchip_pmu_info rk3036_pmu
= {
860 .idle_offset
= 0x14c,
863 .num_domains
= ARRAY_SIZE(rk3036_pm_domains
),
864 .domain_info
= rk3036_pm_domains
,
867 static const struct rockchip_pmu_info rk3066_pmu
= {
869 .status_offset
= 0x0c,
870 .req_offset
= 0x38, /* PMU_MISC_CON1 */
874 .num_domains
= ARRAY_SIZE(rk3066_pm_domains
),
875 .domain_info
= rk3066_pm_domains
,
878 static const struct rockchip_pmu_info rk3128_pmu
= {
880 .status_offset
= 0x08,
885 .num_domains
= ARRAY_SIZE(rk3128_pm_domains
),
886 .domain_info
= rk3128_pm_domains
,
889 static const struct rockchip_pmu_info rk3188_pmu
= {
891 .status_offset
= 0x0c,
892 .req_offset
= 0x38, /* PMU_MISC_CON1 */
896 .num_domains
= ARRAY_SIZE(rk3188_pm_domains
),
897 .domain_info
= rk3188_pm_domains
,
900 static const struct rockchip_pmu_info rk3228_pmu
= {
902 .idle_offset
= 0x488,
905 .num_domains
= ARRAY_SIZE(rk3228_pm_domains
),
906 .domain_info
= rk3228_pm_domains
,
909 static const struct rockchip_pmu_info rk3288_pmu
= {
911 .status_offset
= 0x0c,
916 .core_pwrcnt_offset
= 0x34,
917 .gpu_pwrcnt_offset
= 0x3c,
919 .core_power_transition_time
= 24, /* 1us */
920 .gpu_power_transition_time
= 24, /* 1us */
922 .num_domains
= ARRAY_SIZE(rk3288_pm_domains
),
923 .domain_info
= rk3288_pm_domains
,
926 static const struct rockchip_pmu_info rk3328_pmu
= {
928 .idle_offset
= 0x484,
931 .num_domains
= ARRAY_SIZE(rk3328_pm_domains
),
932 .domain_info
= rk3328_pm_domains
,
935 static const struct rockchip_pmu_info rk3366_pmu
= {
937 .status_offset
= 0x10,
942 .core_pwrcnt_offset
= 0x48,
943 .gpu_pwrcnt_offset
= 0x50,
945 .core_power_transition_time
= 24,
946 .gpu_power_transition_time
= 24,
948 .num_domains
= ARRAY_SIZE(rk3366_pm_domains
),
949 .domain_info
= rk3366_pm_domains
,
952 static const struct rockchip_pmu_info rk3368_pmu
= {
954 .status_offset
= 0x10,
959 .core_pwrcnt_offset
= 0x48,
960 .gpu_pwrcnt_offset
= 0x50,
962 .core_power_transition_time
= 24,
963 .gpu_power_transition_time
= 24,
965 .num_domains
= ARRAY_SIZE(rk3368_pm_domains
),
966 .domain_info
= rk3368_pm_domains
,
969 static const struct rockchip_pmu_info rk3399_pmu
= {
971 .status_offset
= 0x18,
976 /* ARM Trusted Firmware manages power transition times */
978 .num_domains
= ARRAY_SIZE(rk3399_pm_domains
),
979 .domain_info
= rk3399_pm_domains
,
982 static const struct of_device_id rockchip_pm_domain_dt_match
[] = {
984 .compatible
= "rockchip,px30-power-controller",
985 .data
= (void *)&px30_pmu
,
988 .compatible
= "rockchip,rk3036-power-controller",
989 .data
= (void *)&rk3036_pmu
,
992 .compatible
= "rockchip,rk3066-power-controller",
993 .data
= (void *)&rk3066_pmu
,
996 .compatible
= "rockchip,rk3128-power-controller",
997 .data
= (void *)&rk3128_pmu
,
1000 .compatible
= "rockchip,rk3188-power-controller",
1001 .data
= (void *)&rk3188_pmu
,
1004 .compatible
= "rockchip,rk3228-power-controller",
1005 .data
= (void *)&rk3228_pmu
,
1008 .compatible
= "rockchip,rk3288-power-controller",
1009 .data
= (void *)&rk3288_pmu
,
1012 .compatible
= "rockchip,rk3328-power-controller",
1013 .data
= (void *)&rk3328_pmu
,
1016 .compatible
= "rockchip,rk3366-power-controller",
1017 .data
= (void *)&rk3366_pmu
,
1020 .compatible
= "rockchip,rk3368-power-controller",
1021 .data
= (void *)&rk3368_pmu
,
1024 .compatible
= "rockchip,rk3399-power-controller",
1025 .data
= (void *)&rk3399_pmu
,
1030 static struct platform_driver rockchip_pm_domain_driver
= {
1031 .probe
= rockchip_pm_domain_probe
,
1033 .name
= "rockchip-pm-domain",
1034 .of_match_table
= rockchip_pm_domain_dt_match
,
1036 * We can't forcibly eject devices form power domain,
1037 * so we can't really remove power domains once they
1040 .suppress_bind_attrs
= true,
1044 static int __init
rockchip_pm_domain_drv_register(void)
1046 return platform_driver_register(&rockchip_pm_domain_driver
);
1048 postcore_initcall(rockchip_pm_domain_drv_register
);