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[mirror_ubuntu-bionic-kernel.git] / drivers / soc / tegra / pmc.c
1 /*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
21
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
30 #include <linux/io.h>
31 #include <linux/iopoll.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
46
47 #define PMC_CNTRL 0x0
48 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
49 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
50 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
51 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
52 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
53 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
54 #define PMC_CNTRL_MAIN_RST BIT(4)
55
56 #define DPD_SAMPLE 0x020
57 #define DPD_SAMPLE_ENABLE BIT(0)
58 #define DPD_SAMPLE_DISABLE (0 << 0)
59
60 #define PWRGATE_TOGGLE 0x30
61 #define PWRGATE_TOGGLE_START BIT(8)
62
63 #define REMOVE_CLAMPING 0x34
64
65 #define PWRGATE_STATUS 0x38
66
67 #define PMC_PWR_DET 0x48
68
69 #define PMC_SCRATCH0 0x50
70 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
71 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
72 #define PMC_SCRATCH0_MODE_RCM BIT(1)
73 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
74 PMC_SCRATCH0_MODE_BOOTLOADER | \
75 PMC_SCRATCH0_MODE_RCM)
76
77 #define PMC_CPUPWRGOOD_TIMER 0xc8
78 #define PMC_CPUPWROFF_TIMER 0xcc
79
80 #define PMC_PWR_DET_VALUE 0xe4
81
82 #define PMC_SCRATCH41 0x140
83
84 #define PMC_SENSOR_CTRL 0x1b0
85 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
86 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
87
88 #define PMC_RST_STATUS 0x1b4
89 #define PMC_RST_STATUS_POR 0
90 #define PMC_RST_STATUS_WATCHDOG 1
91 #define PMC_RST_STATUS_SENSOR 2
92 #define PMC_RST_STATUS_SW_MAIN 3
93 #define PMC_RST_STATUS_LP0 4
94 #define PMC_RST_STATUS_AOTAG 5
95
96 #define IO_DPD_REQ 0x1b8
97 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
98 #define IO_DPD_REQ_CODE_OFF (1U << 30)
99 #define IO_DPD_REQ_CODE_ON (2U << 30)
100 #define IO_DPD_REQ_CODE_MASK (3U << 30)
101
102 #define IO_DPD_STATUS 0x1bc
103 #define IO_DPD2_REQ 0x1c0
104 #define IO_DPD2_STATUS 0x1c4
105 #define SEL_DPD_TIM 0x1c8
106
107 #define PMC_SCRATCH54 0x258
108 #define PMC_SCRATCH54_DATA_SHIFT 8
109 #define PMC_SCRATCH54_ADDR_SHIFT 0
110
111 #define PMC_SCRATCH55 0x25c
112 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
113 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
114 #define PMC_SCRATCH55_PINMUX_SHIFT 24
115 #define PMC_SCRATCH55_16BITOP BIT(15)
116 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
117 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
118
119 #define GPU_RG_CNTRL 0x2d4
120
121 struct tegra_powergate {
122 struct generic_pm_domain genpd;
123 struct tegra_pmc *pmc;
124 unsigned int id;
125 struct clk **clks;
126 unsigned int num_clks;
127 struct reset_control **resets;
128 unsigned int num_resets;
129 };
130
131 struct tegra_io_pad_soc {
132 enum tegra_io_pad id;
133 unsigned int dpd;
134 unsigned int voltage;
135 };
136
137 struct tegra_pmc_soc {
138 unsigned int num_powergates;
139 const char *const *powergates;
140 unsigned int num_cpu_powergates;
141 const u8 *cpu_powergates;
142
143 bool has_tsense_reset;
144 bool has_gpu_clamps;
145
146 const struct tegra_io_pad_soc *io_pads;
147 unsigned int num_io_pads;
148 };
149
150 /**
151 * struct tegra_pmc - NVIDIA Tegra PMC
152 * @dev: pointer to PMC device structure
153 * @base: pointer to I/O remapped register region
154 * @clk: pointer to pclk clock
155 * @soc: pointer to SoC data structure
156 * @debugfs: pointer to debugfs entry
157 * @rate: currently configured rate of pclk
158 * @suspend_mode: lowest suspend mode available
159 * @cpu_good_time: CPU power good time (in microseconds)
160 * @cpu_off_time: CPU power off time (in microsecends)
161 * @core_osc_time: core power good OSC time (in microseconds)
162 * @core_pmu_time: core power good PMU time (in microseconds)
163 * @core_off_time: core power off time (in microseconds)
164 * @corereq_high: core power request is active-high
165 * @sysclkreq_high: system clock request is active-high
166 * @combined_req: combined power request for CPU & core
167 * @cpu_pwr_good_en: CPU power good signal is enabled
168 * @lp0_vec_phys: physical base address of the LP0 warm boot code
169 * @lp0_vec_size: size of the LP0 warm boot code
170 * @powergates_available: Bitmap of available power gates
171 * @powergates_lock: mutex for power gate register access
172 */
173 struct tegra_pmc {
174 struct device *dev;
175 void __iomem *base;
176 struct clk *clk;
177 struct dentry *debugfs;
178
179 const struct tegra_pmc_soc *soc;
180
181 unsigned long rate;
182
183 enum tegra_suspend_mode suspend_mode;
184 u32 cpu_good_time;
185 u32 cpu_off_time;
186 u32 core_osc_time;
187 u32 core_pmu_time;
188 u32 core_off_time;
189 bool corereq_high;
190 bool sysclkreq_high;
191 bool combined_req;
192 bool cpu_pwr_good_en;
193 u32 lp0_vec_phys;
194 u32 lp0_vec_size;
195 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
196
197 struct mutex powergates_lock;
198 };
199
200 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
201 .base = NULL,
202 .suspend_mode = TEGRA_SUSPEND_NONE,
203 };
204
205 static inline struct tegra_powergate *
206 to_powergate(struct generic_pm_domain *domain)
207 {
208 return container_of(domain, struct tegra_powergate, genpd);
209 }
210
211 static u32 tegra_pmc_readl(unsigned long offset)
212 {
213 return readl(pmc->base + offset);
214 }
215
216 static void tegra_pmc_writel(u32 value, unsigned long offset)
217 {
218 writel(value, pmc->base + offset);
219 }
220
221 static inline bool tegra_powergate_state(int id)
222 {
223 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
224 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
225 else
226 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
227 }
228
229 static inline bool tegra_powergate_is_valid(int id)
230 {
231 return (pmc->soc && pmc->soc->powergates[id]);
232 }
233
234 static inline bool tegra_powergate_is_available(int id)
235 {
236 return test_bit(id, pmc->powergates_available);
237 }
238
239 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
240 {
241 unsigned int i;
242
243 if (!pmc || !pmc->soc || !name)
244 return -EINVAL;
245
246 for (i = 0; i < pmc->soc->num_powergates; i++) {
247 if (!tegra_powergate_is_valid(i))
248 continue;
249
250 if (!strcmp(name, pmc->soc->powergates[i]))
251 return i;
252 }
253
254 return -ENODEV;
255 }
256
257 /**
258 * tegra_powergate_set() - set the state of a partition
259 * @id: partition ID
260 * @new_state: new state of the partition
261 */
262 static int tegra_powergate_set(unsigned int id, bool new_state)
263 {
264 bool status;
265 int err;
266
267 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
268 return -EINVAL;
269
270 mutex_lock(&pmc->powergates_lock);
271
272 if (tegra_powergate_state(id) == new_state) {
273 mutex_unlock(&pmc->powergates_lock);
274 return 0;
275 }
276
277 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
278
279 err = readx_poll_timeout(tegra_powergate_state, id, status,
280 status == new_state, 10, 100000);
281
282 mutex_unlock(&pmc->powergates_lock);
283
284 return err;
285 }
286
287 static int __tegra_powergate_remove_clamping(unsigned int id)
288 {
289 u32 mask;
290
291 mutex_lock(&pmc->powergates_lock);
292
293 /*
294 * On Tegra124 and later, the clamps for the GPU are controlled by a
295 * separate register (with different semantics).
296 */
297 if (id == TEGRA_POWERGATE_3D) {
298 if (pmc->soc->has_gpu_clamps) {
299 tegra_pmc_writel(0, GPU_RG_CNTRL);
300 goto out;
301 }
302 }
303
304 /*
305 * Tegra 2 has a bug where PCIE and VDE clamping masks are
306 * swapped relatively to the partition ids
307 */
308 if (id == TEGRA_POWERGATE_VDEC)
309 mask = (1 << TEGRA_POWERGATE_PCIE);
310 else if (id == TEGRA_POWERGATE_PCIE)
311 mask = (1 << TEGRA_POWERGATE_VDEC);
312 else
313 mask = (1 << id);
314
315 tegra_pmc_writel(mask, REMOVE_CLAMPING);
316
317 out:
318 mutex_unlock(&pmc->powergates_lock);
319
320 return 0;
321 }
322
323 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
324 {
325 unsigned int i;
326
327 for (i = 0; i < pg->num_clks; i++)
328 clk_disable_unprepare(pg->clks[i]);
329 }
330
331 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
332 {
333 unsigned int i;
334 int err;
335
336 for (i = 0; i < pg->num_clks; i++) {
337 err = clk_prepare_enable(pg->clks[i]);
338 if (err)
339 goto out;
340 }
341
342 return 0;
343
344 out:
345 while (i--)
346 clk_disable_unprepare(pg->clks[i]);
347
348 return err;
349 }
350
351 static int tegra_powergate_reset_assert(struct tegra_powergate *pg)
352 {
353 unsigned int i;
354 int err;
355
356 for (i = 0; i < pg->num_resets; i++) {
357 err = reset_control_assert(pg->resets[i]);
358 if (err)
359 return err;
360 }
361
362 return 0;
363 }
364
365 static int tegra_powergate_reset_deassert(struct tegra_powergate *pg)
366 {
367 unsigned int i;
368 int err;
369
370 for (i = 0; i < pg->num_resets; i++) {
371 err = reset_control_deassert(pg->resets[i]);
372 if (err)
373 return err;
374 }
375
376 return 0;
377 }
378
379 static int tegra_powergate_power_up(struct tegra_powergate *pg,
380 bool disable_clocks)
381 {
382 int err;
383
384 err = tegra_powergate_reset_assert(pg);
385 if (err)
386 return err;
387
388 usleep_range(10, 20);
389
390 err = tegra_powergate_set(pg->id, true);
391 if (err < 0)
392 return err;
393
394 usleep_range(10, 20);
395
396 err = tegra_powergate_enable_clocks(pg);
397 if (err)
398 goto disable_clks;
399
400 usleep_range(10, 20);
401
402 err = __tegra_powergate_remove_clamping(pg->id);
403 if (err)
404 goto disable_clks;
405
406 usleep_range(10, 20);
407
408 err = tegra_powergate_reset_deassert(pg);
409 if (err)
410 goto powergate_off;
411
412 usleep_range(10, 20);
413
414 if (disable_clocks)
415 tegra_powergate_disable_clocks(pg);
416
417 return 0;
418
419 disable_clks:
420 tegra_powergate_disable_clocks(pg);
421 usleep_range(10, 20);
422
423 powergate_off:
424 tegra_powergate_set(pg->id, false);
425
426 return err;
427 }
428
429 static int tegra_powergate_power_down(struct tegra_powergate *pg)
430 {
431 int err;
432
433 err = tegra_powergate_enable_clocks(pg);
434 if (err)
435 return err;
436
437 usleep_range(10, 20);
438
439 err = tegra_powergate_reset_assert(pg);
440 if (err)
441 goto disable_clks;
442
443 usleep_range(10, 20);
444
445 tegra_powergate_disable_clocks(pg);
446
447 usleep_range(10, 20);
448
449 err = tegra_powergate_set(pg->id, false);
450 if (err)
451 goto assert_resets;
452
453 return 0;
454
455 assert_resets:
456 tegra_powergate_enable_clocks(pg);
457 usleep_range(10, 20);
458 tegra_powergate_reset_deassert(pg);
459 usleep_range(10, 20);
460
461 disable_clks:
462 tegra_powergate_disable_clocks(pg);
463
464 return err;
465 }
466
467 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
468 {
469 struct tegra_powergate *pg = to_powergate(domain);
470 int err;
471
472 err = tegra_powergate_power_up(pg, true);
473 if (err)
474 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
475 err);
476
477 return err;
478 }
479
480 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
481 {
482 struct tegra_powergate *pg = to_powergate(domain);
483 int err;
484
485 err = tegra_powergate_power_down(pg);
486 if (err)
487 pr_err("failed to turn off PM domain %s: %d\n",
488 pg->genpd.name, err);
489
490 return err;
491 }
492
493 /**
494 * tegra_powergate_power_on() - power on partition
495 * @id: partition ID
496 */
497 int tegra_powergate_power_on(unsigned int id)
498 {
499 if (!tegra_powergate_is_available(id))
500 return -EINVAL;
501
502 return tegra_powergate_set(id, true);
503 }
504
505 /**
506 * tegra_powergate_power_off() - power off partition
507 * @id: partition ID
508 */
509 int tegra_powergate_power_off(unsigned int id)
510 {
511 if (!tegra_powergate_is_available(id))
512 return -EINVAL;
513
514 return tegra_powergate_set(id, false);
515 }
516 EXPORT_SYMBOL(tegra_powergate_power_off);
517
518 /**
519 * tegra_powergate_is_powered() - check if partition is powered
520 * @id: partition ID
521 */
522 int tegra_powergate_is_powered(unsigned int id)
523 {
524 int status;
525
526 if (!tegra_powergate_is_valid(id))
527 return -EINVAL;
528
529 mutex_lock(&pmc->powergates_lock);
530 status = tegra_powergate_state(id);
531 mutex_unlock(&pmc->powergates_lock);
532
533 return status;
534 }
535
536 /**
537 * tegra_powergate_remove_clamping() - remove power clamps for partition
538 * @id: partition ID
539 */
540 int tegra_powergate_remove_clamping(unsigned int id)
541 {
542 if (!tegra_powergate_is_available(id))
543 return -EINVAL;
544
545 return __tegra_powergate_remove_clamping(id);
546 }
547 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
548
549 /**
550 * tegra_powergate_sequence_power_up() - power up partition
551 * @id: partition ID
552 * @clk: clock for partition
553 * @rst: reset for partition
554 *
555 * Must be called with clk disabled, and returns with clk enabled.
556 */
557 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
558 struct reset_control *rst)
559 {
560 struct tegra_powergate *pg;
561 int err;
562
563 if (!tegra_powergate_is_available(id))
564 return -EINVAL;
565
566 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
567 if (!pg)
568 return -ENOMEM;
569
570 pg->id = id;
571 pg->clks = &clk;
572 pg->num_clks = 1;
573 pg->resets = &rst;
574 pg->num_resets = 1;
575
576 err = tegra_powergate_power_up(pg, false);
577 if (err)
578 pr_err("failed to turn on partition %d: %d\n", id, err);
579
580 kfree(pg);
581
582 return err;
583 }
584 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
585
586 #ifdef CONFIG_SMP
587 /**
588 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
589 * @cpuid: CPU partition ID
590 *
591 * Returns the partition ID corresponding to the CPU partition ID or a
592 * negative error code on failure.
593 */
594 static int tegra_get_cpu_powergate_id(unsigned int cpuid)
595 {
596 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
597 return pmc->soc->cpu_powergates[cpuid];
598
599 return -EINVAL;
600 }
601
602 /**
603 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
604 * @cpuid: CPU partition ID
605 */
606 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
607 {
608 int id;
609
610 id = tegra_get_cpu_powergate_id(cpuid);
611 if (id < 0)
612 return false;
613
614 return tegra_powergate_is_powered(id);
615 }
616
617 /**
618 * tegra_pmc_cpu_power_on() - power on CPU partition
619 * @cpuid: CPU partition ID
620 */
621 int tegra_pmc_cpu_power_on(unsigned int cpuid)
622 {
623 int id;
624
625 id = tegra_get_cpu_powergate_id(cpuid);
626 if (id < 0)
627 return id;
628
629 return tegra_powergate_set(id, true);
630 }
631
632 /**
633 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
634 * @cpuid: CPU partition ID
635 */
636 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
637 {
638 int id;
639
640 id = tegra_get_cpu_powergate_id(cpuid);
641 if (id < 0)
642 return id;
643
644 return tegra_powergate_remove_clamping(id);
645 }
646 #endif /* CONFIG_SMP */
647
648 static int tegra_pmc_restart_notify(struct notifier_block *this,
649 unsigned long action, void *data)
650 {
651 const char *cmd = data;
652 u32 value;
653
654 value = tegra_pmc_readl(PMC_SCRATCH0);
655 value &= ~PMC_SCRATCH0_MODE_MASK;
656
657 if (cmd) {
658 if (strcmp(cmd, "recovery") == 0)
659 value |= PMC_SCRATCH0_MODE_RECOVERY;
660
661 if (strcmp(cmd, "bootloader") == 0)
662 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
663
664 if (strcmp(cmd, "forced-recovery") == 0)
665 value |= PMC_SCRATCH0_MODE_RCM;
666 }
667
668 tegra_pmc_writel(value, PMC_SCRATCH0);
669
670 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
671 value = tegra_pmc_readl(PMC_CNTRL);
672 value |= PMC_CNTRL_MAIN_RST;
673 tegra_pmc_writel(value, PMC_CNTRL);
674
675 return NOTIFY_DONE;
676 }
677
678 static struct notifier_block tegra_pmc_restart_handler = {
679 .notifier_call = tegra_pmc_restart_notify,
680 .priority = 128,
681 };
682
683 static int powergate_show(struct seq_file *s, void *data)
684 {
685 unsigned int i;
686 int status;
687
688 seq_printf(s, " powergate powered\n");
689 seq_printf(s, "------------------\n");
690
691 for (i = 0; i < pmc->soc->num_powergates; i++) {
692 status = tegra_powergate_is_powered(i);
693 if (status < 0)
694 continue;
695
696 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
697 status ? "yes" : "no");
698 }
699
700 return 0;
701 }
702
703 static int powergate_open(struct inode *inode, struct file *file)
704 {
705 return single_open(file, powergate_show, inode->i_private);
706 }
707
708 static const struct file_operations powergate_fops = {
709 .open = powergate_open,
710 .read = seq_read,
711 .llseek = seq_lseek,
712 .release = single_release,
713 };
714
715 static int tegra_powergate_debugfs_init(void)
716 {
717 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
718 &powergate_fops);
719 if (!pmc->debugfs)
720 return -ENOMEM;
721
722 return 0;
723 }
724
725 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
726 struct device_node *np)
727 {
728 struct clk *clk;
729 unsigned int i, count;
730 int err;
731
732 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
733 if (count == 0)
734 return -ENODEV;
735
736 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
737 if (!pg->clks)
738 return -ENOMEM;
739
740 for (i = 0; i < count; i++) {
741 pg->clks[i] = of_clk_get(np, i);
742 if (IS_ERR(pg->clks[i])) {
743 err = PTR_ERR(pg->clks[i]);
744 goto err;
745 }
746 }
747
748 pg->num_clks = count;
749
750 return 0;
751
752 err:
753 while (i--)
754 clk_put(pg->clks[i]);
755
756 kfree(pg->clks);
757
758 return err;
759 }
760
761 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
762 struct device_node *np, bool off)
763 {
764 struct reset_control *rst;
765 unsigned int i, count;
766 int err;
767
768 count = of_count_phandle_with_args(np, "resets", "#reset-cells");
769 if (count == 0)
770 return -ENODEV;
771
772 pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL);
773 if (!pg->resets)
774 return -ENOMEM;
775
776 for (i = 0; i < count; i++) {
777 pg->resets[i] = of_reset_control_get_by_index(np, i);
778 if (IS_ERR(pg->resets[i])) {
779 err = PTR_ERR(pg->resets[i]);
780 goto error;
781 }
782
783 if (off)
784 err = reset_control_assert(pg->resets[i]);
785 else
786 err = reset_control_deassert(pg->resets[i]);
787
788 if (err) {
789 reset_control_put(pg->resets[i]);
790 goto error;
791 }
792 }
793
794 pg->num_resets = count;
795
796 return 0;
797
798 error:
799 while (i--)
800 reset_control_put(pg->resets[i]);
801
802 kfree(pg->resets);
803
804 return err;
805 }
806
807 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
808 {
809 struct tegra_powergate *pg;
810 int id, err;
811 bool off;
812
813 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
814 if (!pg)
815 return;
816
817 id = tegra_powergate_lookup(pmc, np->name);
818 if (id < 0) {
819 pr_err("powergate lookup failed for %s: %d\n", np->name, id);
820 goto free_mem;
821 }
822
823 /*
824 * Clear the bit for this powergate so it cannot be managed
825 * directly via the legacy APIs for controlling powergates.
826 */
827 clear_bit(id, pmc->powergates_available);
828
829 pg->id = id;
830 pg->genpd.name = np->name;
831 pg->genpd.power_off = tegra_genpd_power_off;
832 pg->genpd.power_on = tegra_genpd_power_on;
833 pg->pmc = pmc;
834
835 off = !tegra_powergate_is_powered(pg->id);
836
837 err = tegra_powergate_of_get_clks(pg, np);
838 if (err < 0) {
839 pr_err("failed to get clocks for %s: %d\n", np->name, err);
840 goto set_available;
841 }
842
843 err = tegra_powergate_of_get_resets(pg, np, off);
844 if (err < 0) {
845 pr_err("failed to get resets for %s: %d\n", np->name, err);
846 goto remove_clks;
847 }
848
849 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
850 if (off)
851 WARN_ON(tegra_powergate_power_up(pg, true));
852
853 goto remove_resets;
854 }
855
856 /*
857 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
858 * host and super-speed partitions. Once the XHCI driver
859 * manages the partitions itself this code can be removed. Note
860 * that we don't register these partitions with the genpd core
861 * to avoid it from powering down the partitions as they appear
862 * to be unused.
863 */
864 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
865 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
866 if (off)
867 WARN_ON(tegra_powergate_power_up(pg, true));
868
869 goto remove_resets;
870 }
871
872 err = pm_genpd_init(&pg->genpd, NULL, off);
873 if (err < 0) {
874 pr_err("failed to initialise PM domain %s: %d\n", np->name,
875 err);
876 goto remove_resets;
877 }
878
879 err = of_genpd_add_provider_simple(np, &pg->genpd);
880 if (err < 0) {
881 pr_err("failed to add PM domain provider for %s: %d\n",
882 np->name, err);
883 goto remove_genpd;
884 }
885
886 pr_debug("added PM domain %s\n", pg->genpd.name);
887
888 return;
889
890 remove_genpd:
891 pm_genpd_remove(&pg->genpd);
892
893 remove_resets:
894 while (pg->num_resets--)
895 reset_control_put(pg->resets[pg->num_resets]);
896
897 kfree(pg->resets);
898
899 remove_clks:
900 while (pg->num_clks--)
901 clk_put(pg->clks[pg->num_clks]);
902
903 kfree(pg->clks);
904
905 set_available:
906 set_bit(id, pmc->powergates_available);
907
908 free_mem:
909 kfree(pg);
910 }
911
912 static void tegra_powergate_init(struct tegra_pmc *pmc,
913 struct device_node *parent)
914 {
915 struct device_node *np, *child;
916 unsigned int i;
917
918 /* Create a bitmap of the available and valid partitions */
919 for (i = 0; i < pmc->soc->num_powergates; i++)
920 if (pmc->soc->powergates[i])
921 set_bit(i, pmc->powergates_available);
922
923 np = of_get_child_by_name(parent, "powergates");
924 if (!np)
925 return;
926
927 for_each_child_of_node(np, child)
928 tegra_powergate_add(pmc, child);
929
930 of_node_put(np);
931 }
932
933 static const struct tegra_io_pad_soc *
934 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
935 {
936 unsigned int i;
937
938 for (i = 0; i < pmc->soc->num_io_pads; i++)
939 if (pmc->soc->io_pads[i].id == id)
940 return &pmc->soc->io_pads[i];
941
942 return NULL;
943 }
944
945 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
946 unsigned long *status, u32 *mask)
947 {
948 const struct tegra_io_pad_soc *pad;
949 unsigned long rate, value;
950
951 pad = tegra_io_pad_find(pmc, id);
952 if (!pad) {
953 pr_err("invalid I/O pad ID %u\n", id);
954 return -ENOENT;
955 }
956
957 if (pad->dpd == UINT_MAX)
958 return -ENOTSUPP;
959
960 *mask = BIT(pad->dpd % 32);
961
962 if (pad->dpd < 32) {
963 *status = IO_DPD_STATUS;
964 *request = IO_DPD_REQ;
965 } else {
966 *status = IO_DPD2_STATUS;
967 *request = IO_DPD2_REQ;
968 }
969
970 rate = clk_get_rate(pmc->clk);
971 if (!rate) {
972 pr_err("failed to get clock rate\n");
973 return -ENODEV;
974 }
975
976 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
977
978 /* must be at least 200 ns, in APB (PCLK) clock cycles */
979 value = DIV_ROUND_UP(1000000000, rate);
980 value = DIV_ROUND_UP(200, value);
981 tegra_pmc_writel(value, SEL_DPD_TIM);
982
983 return 0;
984 }
985
986 static int tegra_io_pad_poll(unsigned long offset, u32 mask,
987 u32 val, unsigned long timeout)
988 {
989 u32 value;
990
991 timeout = jiffies + msecs_to_jiffies(timeout);
992
993 while (time_after(timeout, jiffies)) {
994 value = tegra_pmc_readl(offset);
995 if ((value & mask) == val)
996 return 0;
997
998 usleep_range(250, 1000);
999 }
1000
1001 return -ETIMEDOUT;
1002 }
1003
1004 static void tegra_io_pad_unprepare(void)
1005 {
1006 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1007 }
1008
1009 /**
1010 * tegra_io_pad_power_enable() - enable power to I/O pad
1011 * @id: Tegra I/O pad ID for which to enable power
1012 *
1013 * Returns: 0 on success or a negative error code on failure.
1014 */
1015 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1016 {
1017 unsigned long request, status;
1018 u32 mask;
1019 int err;
1020
1021 mutex_lock(&pmc->powergates_lock);
1022
1023 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1024 if (err < 0) {
1025 pr_err("failed to prepare I/O pad: %d\n", err);
1026 goto unlock;
1027 }
1028
1029 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
1030
1031 err = tegra_io_pad_poll(status, mask, 0, 250);
1032 if (err < 0) {
1033 pr_err("failed to enable I/O pad: %d\n", err);
1034 goto unlock;
1035 }
1036
1037 tegra_io_pad_unprepare();
1038
1039 unlock:
1040 mutex_unlock(&pmc->powergates_lock);
1041 return err;
1042 }
1043 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1044
1045 /**
1046 * tegra_io_pad_power_disable() - disable power to I/O pad
1047 * @id: Tegra I/O pad ID for which to disable power
1048 *
1049 * Returns: 0 on success or a negative error code on failure.
1050 */
1051 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1052 {
1053 unsigned long request, status;
1054 u32 mask;
1055 int err;
1056
1057 mutex_lock(&pmc->powergates_lock);
1058
1059 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1060 if (err < 0) {
1061 pr_err("failed to prepare I/O pad: %d\n", err);
1062 goto unlock;
1063 }
1064
1065 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
1066
1067 err = tegra_io_pad_poll(status, mask, mask, 250);
1068 if (err < 0) {
1069 pr_err("failed to disable I/O pad: %d\n", err);
1070 goto unlock;
1071 }
1072
1073 tegra_io_pad_unprepare();
1074
1075 unlock:
1076 mutex_unlock(&pmc->powergates_lock);
1077 return err;
1078 }
1079 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1080
1081 int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1082 enum tegra_io_pad_voltage voltage)
1083 {
1084 const struct tegra_io_pad_soc *pad;
1085 u32 value;
1086
1087 pad = tegra_io_pad_find(pmc, id);
1088 if (!pad)
1089 return -ENOENT;
1090
1091 if (pad->voltage == UINT_MAX)
1092 return -ENOTSUPP;
1093
1094 mutex_lock(&pmc->powergates_lock);
1095
1096 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1097 value = tegra_pmc_readl(PMC_PWR_DET);
1098 value |= BIT(pad->voltage);
1099 tegra_pmc_writel(value, PMC_PWR_DET);
1100
1101 /* update I/O voltage */
1102 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1103
1104 if (voltage == TEGRA_IO_PAD_1800000UV)
1105 value &= ~BIT(pad->voltage);
1106 else
1107 value |= BIT(pad->voltage);
1108
1109 tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
1110
1111 mutex_unlock(&pmc->powergates_lock);
1112
1113 usleep_range(100, 250);
1114
1115 return 0;
1116 }
1117 EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1118
1119 int tegra_io_pad_get_voltage(enum tegra_io_pad id)
1120 {
1121 const struct tegra_io_pad_soc *pad;
1122 u32 value;
1123
1124 pad = tegra_io_pad_find(pmc, id);
1125 if (!pad)
1126 return -ENOENT;
1127
1128 if (pad->voltage == UINT_MAX)
1129 return -ENOTSUPP;
1130
1131 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1132
1133 if ((value & BIT(pad->voltage)) == 0)
1134 return TEGRA_IO_PAD_1800000UV;
1135
1136 return TEGRA_IO_PAD_3300000UV;
1137 }
1138 EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1139
1140 /**
1141 * tegra_io_rail_power_on() - enable power to I/O rail
1142 * @id: Tegra I/O pad ID for which to enable power
1143 *
1144 * See also: tegra_io_pad_power_enable()
1145 */
1146 int tegra_io_rail_power_on(unsigned int id)
1147 {
1148 return tegra_io_pad_power_enable(id);
1149 }
1150 EXPORT_SYMBOL(tegra_io_rail_power_on);
1151
1152 /**
1153 * tegra_io_rail_power_off() - disable power to I/O rail
1154 * @id: Tegra I/O pad ID for which to disable power
1155 *
1156 * See also: tegra_io_pad_power_disable()
1157 */
1158 int tegra_io_rail_power_off(unsigned int id)
1159 {
1160 return tegra_io_pad_power_disable(id);
1161 }
1162 EXPORT_SYMBOL(tegra_io_rail_power_off);
1163
1164 #ifdef CONFIG_PM_SLEEP
1165 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1166 {
1167 return pmc->suspend_mode;
1168 }
1169
1170 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1171 {
1172 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1173 return;
1174
1175 pmc->suspend_mode = mode;
1176 }
1177
1178 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1179 {
1180 unsigned long long rate = 0;
1181 u32 value;
1182
1183 switch (mode) {
1184 case TEGRA_SUSPEND_LP1:
1185 rate = 32768;
1186 break;
1187
1188 case TEGRA_SUSPEND_LP2:
1189 rate = clk_get_rate(pmc->clk);
1190 break;
1191
1192 default:
1193 break;
1194 }
1195
1196 if (WARN_ON_ONCE(rate == 0))
1197 rate = 100000000;
1198
1199 if (rate != pmc->rate) {
1200 u64 ticks;
1201
1202 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1203 do_div(ticks, USEC_PER_SEC);
1204 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
1205
1206 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1207 do_div(ticks, USEC_PER_SEC);
1208 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
1209
1210 wmb();
1211
1212 pmc->rate = rate;
1213 }
1214
1215 value = tegra_pmc_readl(PMC_CNTRL);
1216 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1217 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1218 tegra_pmc_writel(value, PMC_CNTRL);
1219 }
1220 #endif
1221
1222 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1223 {
1224 u32 value, values[2];
1225
1226 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1227 } else {
1228 switch (value) {
1229 case 0:
1230 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1231 break;
1232
1233 case 1:
1234 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1235 break;
1236
1237 case 2:
1238 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1239 break;
1240
1241 default:
1242 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1243 break;
1244 }
1245 }
1246
1247 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1248
1249 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1250 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1251
1252 pmc->cpu_good_time = value;
1253
1254 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1255 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1256
1257 pmc->cpu_off_time = value;
1258
1259 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1260 values, ARRAY_SIZE(values)))
1261 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1262
1263 pmc->core_osc_time = values[0];
1264 pmc->core_pmu_time = values[1];
1265
1266 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1267 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1268
1269 pmc->core_off_time = value;
1270
1271 pmc->corereq_high = of_property_read_bool(np,
1272 "nvidia,core-power-req-active-high");
1273
1274 pmc->sysclkreq_high = of_property_read_bool(np,
1275 "nvidia,sys-clock-req-active-high");
1276
1277 pmc->combined_req = of_property_read_bool(np,
1278 "nvidia,combined-power-req");
1279
1280 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1281 "nvidia,cpu-pwr-good-en");
1282
1283 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1284 ARRAY_SIZE(values)))
1285 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1286 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1287
1288 pmc->lp0_vec_phys = values[0];
1289 pmc->lp0_vec_size = values[1];
1290
1291 return 0;
1292 }
1293
1294 static void tegra_pmc_init(struct tegra_pmc *pmc)
1295 {
1296 u32 value;
1297
1298 /* Always enable CPU power request */
1299 value = tegra_pmc_readl(PMC_CNTRL);
1300 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1301 tegra_pmc_writel(value, PMC_CNTRL);
1302
1303 value = tegra_pmc_readl(PMC_CNTRL);
1304
1305 if (pmc->sysclkreq_high)
1306 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
1307 else
1308 value |= PMC_CNTRL_SYSCLK_POLARITY;
1309
1310 /* configure the output polarity while the request is tristated */
1311 tegra_pmc_writel(value, PMC_CNTRL);
1312
1313 /* now enable the request */
1314 value = tegra_pmc_readl(PMC_CNTRL);
1315 value |= PMC_CNTRL_SYSCLK_OE;
1316 tegra_pmc_writel(value, PMC_CNTRL);
1317 }
1318
1319 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1320 {
1321 static const char disabled[] = "emergency thermal reset disabled";
1322 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1323 struct device *dev = pmc->dev;
1324 struct device_node *np;
1325 u32 value, checksum;
1326
1327 if (!pmc->soc->has_tsense_reset)
1328 return;
1329
1330 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
1331 if (!np) {
1332 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1333 return;
1334 }
1335
1336 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1337 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1338 goto out;
1339 }
1340
1341 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1342 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1343 goto out;
1344 }
1345
1346 if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
1347 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1348 goto out;
1349 }
1350
1351 if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
1352 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1353 goto out;
1354 }
1355
1356 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1357 pinmux = 0;
1358
1359 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1360 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1361 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1362
1363 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1364 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1365 tegra_pmc_writel(value, PMC_SCRATCH54);
1366
1367 value = PMC_SCRATCH55_RESET_TEGRA;
1368 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1369 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1370 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1371
1372 /*
1373 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1374 * contain the checksum and are currently zero, so they are not added.
1375 */
1376 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1377 + ((value >> 24) & 0xff);
1378 checksum &= 0xff;
1379 checksum = 0x100 - checksum;
1380
1381 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1382
1383 tegra_pmc_writel(value, PMC_SCRATCH55);
1384
1385 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1386 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1387 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1388
1389 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1390
1391 out:
1392 of_node_put(np);
1393 }
1394
1395 static int tegra_pmc_probe(struct platform_device *pdev)
1396 {
1397 void __iomem *base;
1398 struct resource *res;
1399 int err;
1400
1401 /*
1402 * Early initialisation should have configured an initial
1403 * register mapping and setup the soc data pointer. If these
1404 * are not valid then something went badly wrong!
1405 */
1406 if (WARN_ON(!pmc->base || !pmc->soc))
1407 return -ENODEV;
1408
1409 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
1410 if (err < 0)
1411 return err;
1412
1413 /* take over the memory region from the early initialization */
1414 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1415 base = devm_ioremap_resource(&pdev->dev, res);
1416 if (IS_ERR(base))
1417 return PTR_ERR(base);
1418
1419 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
1420 if (IS_ERR(pmc->clk)) {
1421 err = PTR_ERR(pmc->clk);
1422 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
1423 return err;
1424 }
1425
1426 pmc->dev = &pdev->dev;
1427
1428 tegra_pmc_init(pmc);
1429
1430 tegra_pmc_init_tsense_reset(pmc);
1431
1432 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1433 err = tegra_powergate_debugfs_init();
1434 if (err < 0)
1435 return err;
1436 }
1437
1438 err = register_restart_handler(&tegra_pmc_restart_handler);
1439 if (err) {
1440 debugfs_remove(pmc->debugfs);
1441 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
1442 err);
1443 return err;
1444 }
1445
1446 mutex_lock(&pmc->powergates_lock);
1447 iounmap(pmc->base);
1448 pmc->base = base;
1449 mutex_unlock(&pmc->powergates_lock);
1450
1451 return 0;
1452 }
1453
1454 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1455 static int tegra_pmc_suspend(struct device *dev)
1456 {
1457 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
1458
1459 return 0;
1460 }
1461
1462 static int tegra_pmc_resume(struct device *dev)
1463 {
1464 tegra_pmc_writel(0x0, PMC_SCRATCH41);
1465
1466 return 0;
1467 }
1468
1469 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
1470
1471 #endif
1472
1473 static const char * const tegra20_powergates[] = {
1474 [TEGRA_POWERGATE_CPU] = "cpu",
1475 [TEGRA_POWERGATE_3D] = "3d",
1476 [TEGRA_POWERGATE_VENC] = "venc",
1477 [TEGRA_POWERGATE_VDEC] = "vdec",
1478 [TEGRA_POWERGATE_PCIE] = "pcie",
1479 [TEGRA_POWERGATE_L2] = "l2",
1480 [TEGRA_POWERGATE_MPE] = "mpe",
1481 };
1482
1483 static const struct tegra_pmc_soc tegra20_pmc_soc = {
1484 .num_powergates = ARRAY_SIZE(tegra20_powergates),
1485 .powergates = tegra20_powergates,
1486 .num_cpu_powergates = 0,
1487 .cpu_powergates = NULL,
1488 .has_tsense_reset = false,
1489 .has_gpu_clamps = false,
1490 };
1491
1492 static const char * const tegra30_powergates[] = {
1493 [TEGRA_POWERGATE_CPU] = "cpu0",
1494 [TEGRA_POWERGATE_3D] = "3d0",
1495 [TEGRA_POWERGATE_VENC] = "venc",
1496 [TEGRA_POWERGATE_VDEC] = "vdec",
1497 [TEGRA_POWERGATE_PCIE] = "pcie",
1498 [TEGRA_POWERGATE_L2] = "l2",
1499 [TEGRA_POWERGATE_MPE] = "mpe",
1500 [TEGRA_POWERGATE_HEG] = "heg",
1501 [TEGRA_POWERGATE_SATA] = "sata",
1502 [TEGRA_POWERGATE_CPU1] = "cpu1",
1503 [TEGRA_POWERGATE_CPU2] = "cpu2",
1504 [TEGRA_POWERGATE_CPU3] = "cpu3",
1505 [TEGRA_POWERGATE_CELP] = "celp",
1506 [TEGRA_POWERGATE_3D1] = "3d1",
1507 };
1508
1509 static const u8 tegra30_cpu_powergates[] = {
1510 TEGRA_POWERGATE_CPU,
1511 TEGRA_POWERGATE_CPU1,
1512 TEGRA_POWERGATE_CPU2,
1513 TEGRA_POWERGATE_CPU3,
1514 };
1515
1516 static const struct tegra_pmc_soc tegra30_pmc_soc = {
1517 .num_powergates = ARRAY_SIZE(tegra30_powergates),
1518 .powergates = tegra30_powergates,
1519 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
1520 .cpu_powergates = tegra30_cpu_powergates,
1521 .has_tsense_reset = true,
1522 .has_gpu_clamps = false,
1523 };
1524
1525 static const char * const tegra114_powergates[] = {
1526 [TEGRA_POWERGATE_CPU] = "crail",
1527 [TEGRA_POWERGATE_3D] = "3d",
1528 [TEGRA_POWERGATE_VENC] = "venc",
1529 [TEGRA_POWERGATE_VDEC] = "vdec",
1530 [TEGRA_POWERGATE_MPE] = "mpe",
1531 [TEGRA_POWERGATE_HEG] = "heg",
1532 [TEGRA_POWERGATE_CPU1] = "cpu1",
1533 [TEGRA_POWERGATE_CPU2] = "cpu2",
1534 [TEGRA_POWERGATE_CPU3] = "cpu3",
1535 [TEGRA_POWERGATE_CELP] = "celp",
1536 [TEGRA_POWERGATE_CPU0] = "cpu0",
1537 [TEGRA_POWERGATE_C0NC] = "c0nc",
1538 [TEGRA_POWERGATE_C1NC] = "c1nc",
1539 [TEGRA_POWERGATE_DIS] = "dis",
1540 [TEGRA_POWERGATE_DISB] = "disb",
1541 [TEGRA_POWERGATE_XUSBA] = "xusba",
1542 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1543 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1544 };
1545
1546 static const u8 tegra114_cpu_powergates[] = {
1547 TEGRA_POWERGATE_CPU0,
1548 TEGRA_POWERGATE_CPU1,
1549 TEGRA_POWERGATE_CPU2,
1550 TEGRA_POWERGATE_CPU3,
1551 };
1552
1553 static const struct tegra_pmc_soc tegra114_pmc_soc = {
1554 .num_powergates = ARRAY_SIZE(tegra114_powergates),
1555 .powergates = tegra114_powergates,
1556 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
1557 .cpu_powergates = tegra114_cpu_powergates,
1558 .has_tsense_reset = true,
1559 .has_gpu_clamps = false,
1560 };
1561
1562 static const char * const tegra124_powergates[] = {
1563 [TEGRA_POWERGATE_CPU] = "crail",
1564 [TEGRA_POWERGATE_3D] = "3d",
1565 [TEGRA_POWERGATE_VENC] = "venc",
1566 [TEGRA_POWERGATE_PCIE] = "pcie",
1567 [TEGRA_POWERGATE_VDEC] = "vdec",
1568 [TEGRA_POWERGATE_MPE] = "mpe",
1569 [TEGRA_POWERGATE_HEG] = "heg",
1570 [TEGRA_POWERGATE_SATA] = "sata",
1571 [TEGRA_POWERGATE_CPU1] = "cpu1",
1572 [TEGRA_POWERGATE_CPU2] = "cpu2",
1573 [TEGRA_POWERGATE_CPU3] = "cpu3",
1574 [TEGRA_POWERGATE_CELP] = "celp",
1575 [TEGRA_POWERGATE_CPU0] = "cpu0",
1576 [TEGRA_POWERGATE_C0NC] = "c0nc",
1577 [TEGRA_POWERGATE_C1NC] = "c1nc",
1578 [TEGRA_POWERGATE_SOR] = "sor",
1579 [TEGRA_POWERGATE_DIS] = "dis",
1580 [TEGRA_POWERGATE_DISB] = "disb",
1581 [TEGRA_POWERGATE_XUSBA] = "xusba",
1582 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1583 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1584 [TEGRA_POWERGATE_VIC] = "vic",
1585 [TEGRA_POWERGATE_IRAM] = "iram",
1586 };
1587
1588 static const u8 tegra124_cpu_powergates[] = {
1589 TEGRA_POWERGATE_CPU0,
1590 TEGRA_POWERGATE_CPU1,
1591 TEGRA_POWERGATE_CPU2,
1592 TEGRA_POWERGATE_CPU3,
1593 };
1594
1595 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1596 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1597 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1598 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1599 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1600 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1601 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1602 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1603 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1604 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1605 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1606 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1607 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1608 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1609 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1610 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1611 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1612 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1613 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1614 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1615 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1616 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1617 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1618 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1619 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1620 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1621 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1622 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1623 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1624 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1625 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1626 };
1627
1628 static const struct tegra_pmc_soc tegra124_pmc_soc = {
1629 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1630 .powergates = tegra124_powergates,
1631 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1632 .cpu_powergates = tegra124_cpu_powergates,
1633 .has_tsense_reset = true,
1634 .has_gpu_clamps = true,
1635 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1636 .io_pads = tegra124_io_pads,
1637 };
1638
1639 static const char * const tegra210_powergates[] = {
1640 [TEGRA_POWERGATE_CPU] = "crail",
1641 [TEGRA_POWERGATE_3D] = "3d",
1642 [TEGRA_POWERGATE_VENC] = "venc",
1643 [TEGRA_POWERGATE_PCIE] = "pcie",
1644 [TEGRA_POWERGATE_MPE] = "mpe",
1645 [TEGRA_POWERGATE_SATA] = "sata",
1646 [TEGRA_POWERGATE_CPU1] = "cpu1",
1647 [TEGRA_POWERGATE_CPU2] = "cpu2",
1648 [TEGRA_POWERGATE_CPU3] = "cpu3",
1649 [TEGRA_POWERGATE_CPU0] = "cpu0",
1650 [TEGRA_POWERGATE_C0NC] = "c0nc",
1651 [TEGRA_POWERGATE_SOR] = "sor",
1652 [TEGRA_POWERGATE_DIS] = "dis",
1653 [TEGRA_POWERGATE_DISB] = "disb",
1654 [TEGRA_POWERGATE_XUSBA] = "xusba",
1655 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1656 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1657 [TEGRA_POWERGATE_VIC] = "vic",
1658 [TEGRA_POWERGATE_IRAM] = "iram",
1659 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1660 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1661 [TEGRA_POWERGATE_AUD] = "aud",
1662 [TEGRA_POWERGATE_DFD] = "dfd",
1663 [TEGRA_POWERGATE_VE2] = "ve2",
1664 };
1665
1666 static const u8 tegra210_cpu_powergates[] = {
1667 TEGRA_POWERGATE_CPU0,
1668 TEGRA_POWERGATE_CPU1,
1669 TEGRA_POWERGATE_CPU2,
1670 TEGRA_POWERGATE_CPU3,
1671 };
1672
1673 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1674 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1675 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1676 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1677 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1678 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1679 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1680 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1681 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1682 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1683 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1684 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1685 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1686 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1687 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1688 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1689 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1690 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1691 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1692 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1693 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1694 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1695 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1696 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1697 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1698 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1699 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1700 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1701 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1702 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1703 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1704 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1705 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1706 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1707 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1708 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1709 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1710 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1711 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1712 };
1713
1714 static const struct tegra_pmc_soc tegra210_pmc_soc = {
1715 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1716 .powergates = tegra210_powergates,
1717 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1718 .cpu_powergates = tegra210_cpu_powergates,
1719 .has_tsense_reset = true,
1720 .has_gpu_clamps = true,
1721 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1722 .io_pads = tegra210_io_pads,
1723 };
1724
1725 static const struct of_device_id tegra_pmc_match[] = {
1726 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1727 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1728 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1729 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1730 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1731 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1732 { }
1733 };
1734
1735 static struct platform_driver tegra_pmc_driver = {
1736 .driver = {
1737 .name = "tegra-pmc",
1738 .suppress_bind_attrs = true,
1739 .of_match_table = tegra_pmc_match,
1740 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1741 .pm = &tegra_pmc_pm_ops,
1742 #endif
1743 },
1744 .probe = tegra_pmc_probe,
1745 };
1746 builtin_platform_driver(tegra_pmc_driver);
1747
1748 /*
1749 * Early initialization to allow access to registers in the very early boot
1750 * process.
1751 */
1752 static int __init tegra_pmc_early_init(void)
1753 {
1754 const struct of_device_id *match;
1755 struct device_node *np;
1756 struct resource regs;
1757 bool invert;
1758 u32 value;
1759
1760 mutex_init(&pmc->powergates_lock);
1761
1762 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1763 if (!np) {
1764 /*
1765 * Fall back to legacy initialization for 32-bit ARM only. All
1766 * 64-bit ARM device tree files for Tegra are required to have
1767 * a PMC node.
1768 *
1769 * This is for backwards-compatibility with old device trees
1770 * that didn't contain a PMC node. Note that in this case the
1771 * SoC data can't be matched and therefore powergating is
1772 * disabled.
1773 */
1774 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1775 pr_warn("DT node not found, powergating disabled\n");
1776
1777 regs.start = 0x7000e400;
1778 regs.end = 0x7000e7ff;
1779 regs.flags = IORESOURCE_MEM;
1780
1781 pr_warn("Using memory region %pR\n", &regs);
1782 } else {
1783 /*
1784 * At this point we're not running on Tegra, so play
1785 * nice with multi-platform kernels.
1786 */
1787 return 0;
1788 }
1789 } else {
1790 /*
1791 * Extract information from the device tree if we've found a
1792 * matching node.
1793 */
1794 if (of_address_to_resource(np, 0, &regs) < 0) {
1795 pr_err("failed to get PMC registers\n");
1796 of_node_put(np);
1797 return -ENXIO;
1798 }
1799 }
1800
1801 pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
1802 if (!pmc->base) {
1803 pr_err("failed to map PMC registers\n");
1804 of_node_put(np);
1805 return -ENXIO;
1806 }
1807
1808 if (np) {
1809 pmc->soc = match->data;
1810
1811 tegra_powergate_init(pmc, np);
1812
1813 /*
1814 * Invert the interrupt polarity if a PMC device tree node
1815 * exists and contains the nvidia,invert-interrupt property.
1816 */
1817 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1818
1819 value = tegra_pmc_readl(PMC_CNTRL);
1820
1821 if (invert)
1822 value |= PMC_CNTRL_INTR_POLARITY;
1823 else
1824 value &= ~PMC_CNTRL_INTR_POLARITY;
1825
1826 tegra_pmc_writel(value, PMC_CNTRL);
1827
1828 of_node_put(np);
1829 }
1830
1831 return 0;
1832 }
1833 early_initcall(tegra_pmc_early_init);
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