1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
5 * Soundwire Intel Master Driver
8 #include <linux/acpi.h>
9 #include <linux/debugfs.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
14 #include <linux/auxiliary_bus.h>
15 #include <sound/pcm_params.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/soc.h>
18 #include <linux/soundwire/sdw_registers.h>
19 #include <linux/soundwire/sdw.h>
20 #include <linux/soundwire/sdw_intel.h>
21 #include "cadence_master.h"
25 #define INTEL_MASTER_SUSPEND_DELAY_MS 3000
26 #define INTEL_MASTER_RESET_ITERATIONS 10
29 * debug/config flags for the Intel SoundWire Master.
31 * Since we may have multiple masters active, we can have up to 8
32 * flags reused in each byte, with master0 using the ls-byte, etc.
35 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME BIT(0)
36 #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP BIT(1)
37 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE BIT(2)
38 #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK BIT(3)
41 module_param_named(sdw_md_flags
, md_flags
, int, 0444);
42 MODULE_PARM_DESC(sdw_md_flags
, "SoundWire Intel Master device flags (0x0 all off)");
50 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
53 * Read, write helpers for HW registers
55 static inline int intel_readl(void __iomem
*base
, int offset
)
57 return readl(base
+ offset
);
60 static inline void intel_writel(void __iomem
*base
, int offset
, int value
)
62 writel(value
, base
+ offset
);
65 static inline u16
intel_readw(void __iomem
*base
, int offset
)
67 return readw(base
+ offset
);
70 static inline void intel_writew(void __iomem
*base
, int offset
, u16 value
)
72 writew(value
, base
+ offset
);
75 static int intel_wait_bit(void __iomem
*base
, int offset
, u32 mask
, u32 target
)
81 reg_read
= readl(base
+ offset
);
82 if ((reg_read
& mask
) == target
)
86 usleep_range(50, 100);
87 } while (timeout
!= 0);
92 static int intel_clear_bit(void __iomem
*base
, int offset
, u32 value
, u32 mask
)
94 writel(value
, base
+ offset
);
95 return intel_wait_bit(base
, offset
, mask
, 0);
98 static int intel_set_bit(void __iomem
*base
, int offset
, u32 value
, u32 mask
)
100 writel(value
, base
+ offset
);
101 return intel_wait_bit(base
, offset
, mask
, mask
);
107 #ifdef CONFIG_DEBUG_FS
109 #define RD_BUF (2 * PAGE_SIZE)
111 static ssize_t
intel_sprintf(void __iomem
*mem
, bool l
,
112 char *buf
, size_t pos
, unsigned int reg
)
117 value
= intel_readl(mem
, reg
);
119 value
= intel_readw(mem
, reg
);
121 return scnprintf(buf
+ pos
, RD_BUF
- pos
, "%4x\t%4x\n", reg
, value
);
124 static int intel_reg_show(struct seq_file
*s_file
, void *data
)
126 struct sdw_intel
*sdw
= s_file
->private;
127 void __iomem
*s
= sdw
->link_res
->shim
;
128 void __iomem
*a
= sdw
->link_res
->alh
;
132 unsigned int links
, reg
;
134 buf
= kzalloc(RD_BUF
, GFP_KERNEL
);
138 links
= intel_readl(s
, SDW_SHIM_LCAP
) & GENMASK(2, 0);
140 ret
= scnprintf(buf
, RD_BUF
, "Register Value\n");
141 ret
+= scnprintf(buf
+ ret
, RD_BUF
- ret
, "\nShim\n");
143 for (i
= 0; i
< links
; i
++) {
144 reg
= SDW_SHIM_LCAP
+ i
* 4;
145 ret
+= intel_sprintf(s
, true, buf
, ret
, reg
);
148 for (i
= 0; i
< links
; i
++) {
149 ret
+= scnprintf(buf
+ ret
, RD_BUF
- ret
, "\nLink%d\n", i
);
150 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_CTLSCAP(i
));
151 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_CTLS0CM(i
));
152 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_CTLS1CM(i
));
153 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_CTLS2CM(i
));
154 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_CTLS3CM(i
));
155 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_PCMSCAP(i
));
157 ret
+= scnprintf(buf
+ ret
, RD_BUF
- ret
, "\n PCMSyCH registers\n");
160 * the value 10 is the number of PDIs. We will need a
161 * cleanup to remove hard-coded Intel configurations
162 * from cadence_master.c
164 for (j
= 0; j
< 10; j
++) {
165 ret
+= intel_sprintf(s
, false, buf
, ret
,
166 SDW_SHIM_PCMSYCHM(i
, j
));
167 ret
+= intel_sprintf(s
, false, buf
, ret
,
168 SDW_SHIM_PCMSYCHC(i
, j
));
170 ret
+= scnprintf(buf
+ ret
, RD_BUF
- ret
, "\n PDMSCAP, IOCTL, CTMCTL\n");
172 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_PDMSCAP(i
));
173 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_IOCTL(i
));
174 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_CTMCTL(i
));
177 ret
+= scnprintf(buf
+ ret
, RD_BUF
- ret
, "\nWake registers\n");
178 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_WAKEEN
);
179 ret
+= intel_sprintf(s
, false, buf
, ret
, SDW_SHIM_WAKESTS
);
181 ret
+= scnprintf(buf
+ ret
, RD_BUF
- ret
, "\nALH STRMzCFG\n");
182 for (i
= 0; i
< SDW_ALH_NUM_STREAMS
; i
++)
183 ret
+= intel_sprintf(a
, true, buf
, ret
, SDW_ALH_STRMZCFG(i
));
185 seq_printf(s_file
, "%s", buf
);
190 DEFINE_SHOW_ATTRIBUTE(intel_reg
);
192 static int intel_set_m_datamode(void *data
, u64 value
)
194 struct sdw_intel
*sdw
= data
;
195 struct sdw_bus
*bus
= &sdw
->cdns
.bus
;
197 if (value
> SDW_PORT_DATA_MODE_STATIC_1
)
200 /* Userspace changed the hardware state behind the kernel's back */
201 add_taint(TAINT_USER
, LOCKDEP_STILL_OK
);
203 bus
->params
.m_data_mode
= value
;
207 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops
, NULL
,
208 intel_set_m_datamode
, "%llu\n");
210 static int intel_set_s_datamode(void *data
, u64 value
)
212 struct sdw_intel
*sdw
= data
;
213 struct sdw_bus
*bus
= &sdw
->cdns
.bus
;
215 if (value
> SDW_PORT_DATA_MODE_STATIC_1
)
218 /* Userspace changed the hardware state behind the kernel's back */
219 add_taint(TAINT_USER
, LOCKDEP_STILL_OK
);
221 bus
->params
.s_data_mode
= value
;
225 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops
, NULL
,
226 intel_set_s_datamode
, "%llu\n");
228 static void intel_debugfs_init(struct sdw_intel
*sdw
)
230 struct dentry
*root
= sdw
->cdns
.bus
.debugfs
;
235 sdw
->debugfs
= debugfs_create_dir("intel-sdw", root
);
237 debugfs_create_file("intel-registers", 0400, sdw
->debugfs
, sdw
,
240 debugfs_create_file("intel-m-datamode", 0200, sdw
->debugfs
, sdw
,
241 &intel_set_m_datamode_fops
);
243 debugfs_create_file("intel-s-datamode", 0200, sdw
->debugfs
, sdw
,
244 &intel_set_s_datamode_fops
);
246 sdw_cdns_debugfs_init(&sdw
->cdns
, sdw
->debugfs
);
249 static void intel_debugfs_exit(struct sdw_intel
*sdw
)
251 debugfs_remove_recursive(sdw
->debugfs
);
254 static void intel_debugfs_init(struct sdw_intel
*sdw
) {}
255 static void intel_debugfs_exit(struct sdw_intel
*sdw
) {}
256 #endif /* CONFIG_DEBUG_FS */
262 static int intel_link_power_up(struct sdw_intel
*sdw
)
264 unsigned int link_id
= sdw
->instance
;
265 void __iomem
*shim
= sdw
->link_res
->shim
;
266 u32
*shim_mask
= sdw
->link_res
->shim_mask
;
267 struct sdw_bus
*bus
= &sdw
->cdns
.bus
;
268 struct sdw_master_prop
*prop
= &bus
->prop
;
269 u32 spa_mask
, cpa_mask
;
275 mutex_lock(sdw
->link_res
->shim_lock
);
278 * The hardware relies on an internal counter, typically 4kHz,
279 * to generate the SoundWire SSP - which defines a 'safe'
280 * synchronization point between commands and audio transport
281 * and allows for multi link synchronization. The SYNCPRD value
282 * is only dependent on the oscillator clock provided to
283 * the IP, so adjust based on _DSD properties reported in DSDT
284 * tables. The values reported are based on either 24MHz
285 * (CNL/CML) or 38.4 MHz (ICL/TGL+).
287 if (prop
->mclk_freq
% 6000000)
288 syncprd
= SDW_SHIM_SYNC_SYNCPRD_VAL_38_4
;
290 syncprd
= SDW_SHIM_SYNC_SYNCPRD_VAL_24
;
293 dev_dbg(sdw
->cdns
.dev
, "%s: powering up all links\n", __func__
);
295 /* we first need to program the SyncPRD/CPU registers */
296 dev_dbg(sdw
->cdns
.dev
,
297 "%s: first link up, programming SYNCPRD\n", __func__
);
299 /* set SyncPRD period */
300 sync_reg
= intel_readl(shim
, SDW_SHIM_SYNC
);
301 u32p_replace_bits(&sync_reg
, syncprd
, SDW_SHIM_SYNC_SYNCPRD
);
303 /* Set SyncCPU bit */
304 sync_reg
|= SDW_SHIM_SYNC_SYNCCPU
;
305 intel_writel(shim
, SDW_SHIM_SYNC
, sync_reg
);
307 /* Link power up sequence */
308 link_control
= intel_readl(shim
, SDW_SHIM_LCTL
);
310 /* only power-up enabled links */
311 spa_mask
= FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK
, sdw
->link_res
->link_mask
);
312 cpa_mask
= FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK
, sdw
->link_res
->link_mask
);
314 link_control
|= spa_mask
;
316 ret
= intel_set_bit(shim
, SDW_SHIM_LCTL
, link_control
, cpa_mask
);
318 dev_err(sdw
->cdns
.dev
, "Failed to power up link: %d\n", ret
);
322 /* SyncCPU will change once link is active */
323 ret
= intel_wait_bit(shim
, SDW_SHIM_SYNC
,
324 SDW_SHIM_SYNC_SYNCCPU
, 0);
326 dev_err(sdw
->cdns
.dev
,
327 "Failed to set SHIM_SYNC: %d\n", ret
);
332 *shim_mask
|= BIT(link_id
);
334 sdw
->cdns
.link_up
= true;
336 mutex_unlock(sdw
->link_res
->shim_lock
);
341 /* this needs to be called with shim_lock */
342 static void intel_shim_glue_to_master_ip(struct sdw_intel
*sdw
)
344 void __iomem
*shim
= sdw
->link_res
->shim
;
345 unsigned int link_id
= sdw
->instance
;
348 /* Switch to MIP from Glue logic */
349 ioctl
= intel_readw(shim
, SDW_SHIM_IOCTL(link_id
));
351 ioctl
&= ~(SDW_SHIM_IOCTL_DOE
);
352 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
353 usleep_range(10, 15);
355 ioctl
&= ~(SDW_SHIM_IOCTL_DO
);
356 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
357 usleep_range(10, 15);
359 ioctl
|= (SDW_SHIM_IOCTL_MIF
);
360 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
361 usleep_range(10, 15);
363 ioctl
&= ~(SDW_SHIM_IOCTL_BKE
);
364 ioctl
&= ~(SDW_SHIM_IOCTL_COE
);
365 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
366 usleep_range(10, 15);
368 /* at this point Master IP has full control of the I/Os */
371 /* this needs to be called with shim_lock */
372 static void intel_shim_master_ip_to_glue(struct sdw_intel
*sdw
)
374 unsigned int link_id
= sdw
->instance
;
375 void __iomem
*shim
= sdw
->link_res
->shim
;
379 ioctl
= intel_readw(shim
, SDW_SHIM_IOCTL(link_id
));
380 ioctl
|= SDW_SHIM_IOCTL_BKE
;
381 ioctl
|= SDW_SHIM_IOCTL_COE
;
382 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
383 usleep_range(10, 15);
385 ioctl
&= ~(SDW_SHIM_IOCTL_MIF
);
386 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
387 usleep_range(10, 15);
389 /* at this point Integration Glue has full control of the I/Os */
392 static int intel_shim_init(struct sdw_intel
*sdw
, bool clock_stop
)
394 void __iomem
*shim
= sdw
->link_res
->shim
;
395 unsigned int link_id
= sdw
->instance
;
397 u16 ioctl
= 0, act
= 0;
399 mutex_lock(sdw
->link_res
->shim_lock
);
401 /* Initialize Shim */
402 ioctl
|= SDW_SHIM_IOCTL_BKE
;
403 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
404 usleep_range(10, 15);
406 ioctl
|= SDW_SHIM_IOCTL_WPDD
;
407 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
408 usleep_range(10, 15);
410 ioctl
|= SDW_SHIM_IOCTL_DO
;
411 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
412 usleep_range(10, 15);
414 ioctl
|= SDW_SHIM_IOCTL_DOE
;
415 intel_writew(shim
, SDW_SHIM_IOCTL(link_id
), ioctl
);
416 usleep_range(10, 15);
418 intel_shim_glue_to_master_ip(sdw
);
420 u16p_replace_bits(&act
, 0x1, SDW_SHIM_CTMCTL_DOAIS
);
421 act
|= SDW_SHIM_CTMCTL_DACTQE
;
422 act
|= SDW_SHIM_CTMCTL_DODS
;
423 intel_writew(shim
, SDW_SHIM_CTMCTL(link_id
), act
);
424 usleep_range(10, 15);
426 mutex_unlock(sdw
->link_res
->shim_lock
);
431 static void intel_shim_wake(struct sdw_intel
*sdw
, bool wake_enable
)
433 void __iomem
*shim
= sdw
->link_res
->shim
;
434 unsigned int link_id
= sdw
->instance
;
435 u16 wake_en
, wake_sts
;
437 mutex_lock(sdw
->link_res
->shim_lock
);
438 wake_en
= intel_readw(shim
, SDW_SHIM_WAKEEN
);
441 /* Enable the wakeup */
442 wake_en
|= (SDW_SHIM_WAKEEN_ENABLE
<< link_id
);
443 intel_writew(shim
, SDW_SHIM_WAKEEN
, wake_en
);
445 /* Disable the wake up interrupt */
446 wake_en
&= ~(SDW_SHIM_WAKEEN_ENABLE
<< link_id
);
447 intel_writew(shim
, SDW_SHIM_WAKEEN
, wake_en
);
449 /* Clear wake status */
450 wake_sts
= intel_readw(shim
, SDW_SHIM_WAKESTS
);
451 wake_sts
|= (SDW_SHIM_WAKESTS_STATUS
<< link_id
);
452 intel_writew(shim
, SDW_SHIM_WAKESTS
, wake_sts
);
454 mutex_unlock(sdw
->link_res
->shim_lock
);
457 static int intel_link_power_down(struct sdw_intel
*sdw
)
459 u32 link_control
, spa_mask
, cpa_mask
;
460 unsigned int link_id
= sdw
->instance
;
461 void __iomem
*shim
= sdw
->link_res
->shim
;
462 u32
*shim_mask
= sdw
->link_res
->shim_mask
;
465 mutex_lock(sdw
->link_res
->shim_lock
);
467 if (!(*shim_mask
& BIT(link_id
)))
468 dev_err(sdw
->cdns
.dev
,
469 "%s: Unbalanced power-up/down calls\n", __func__
);
471 sdw
->cdns
.link_up
= false;
473 intel_shim_master_ip_to_glue(sdw
);
475 *shim_mask
&= ~BIT(link_id
);
479 dev_dbg(sdw
->cdns
.dev
, "%s: powering down all links\n", __func__
);
481 /* Link power down sequence */
482 link_control
= intel_readl(shim
, SDW_SHIM_LCTL
);
484 /* only power-down enabled links */
485 spa_mask
= FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK
, ~sdw
->link_res
->link_mask
);
486 cpa_mask
= FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK
, sdw
->link_res
->link_mask
);
488 link_control
&= spa_mask
;
490 ret
= intel_clear_bit(shim
, SDW_SHIM_LCTL
, link_control
, cpa_mask
);
492 dev_err(sdw
->cdns
.dev
, "%s: could not power down link\n", __func__
);
495 * we leave the sdw->cdns.link_up flag as false since we've disabled
496 * the link at this point and cannot handle interrupts any longer.
501 mutex_unlock(sdw
->link_res
->shim_lock
);
506 static void intel_shim_sync_arm(struct sdw_intel
*sdw
)
508 void __iomem
*shim
= sdw
->link_res
->shim
;
511 mutex_lock(sdw
->link_res
->shim_lock
);
513 /* update SYNC register */
514 sync_reg
= intel_readl(shim
, SDW_SHIM_SYNC
);
515 sync_reg
|= (SDW_SHIM_SYNC_CMDSYNC
<< sdw
->instance
);
516 intel_writel(shim
, SDW_SHIM_SYNC
, sync_reg
);
518 mutex_unlock(sdw
->link_res
->shim_lock
);
521 static int intel_shim_sync_go_unlocked(struct sdw_intel
*sdw
)
523 void __iomem
*shim
= sdw
->link_res
->shim
;
527 /* Read SYNC register */
528 sync_reg
= intel_readl(shim
, SDW_SHIM_SYNC
);
531 * Set SyncGO bit to synchronously trigger a bank switch for
532 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
535 sync_reg
|= SDW_SHIM_SYNC_SYNCGO
;
537 ret
= intel_clear_bit(shim
, SDW_SHIM_SYNC
, sync_reg
,
538 SDW_SHIM_SYNC_SYNCGO
);
541 dev_err(sdw
->cdns
.dev
, "SyncGO clear failed: %d\n", ret
);
546 static int intel_shim_sync_go(struct sdw_intel
*sdw
)
550 mutex_lock(sdw
->link_res
->shim_lock
);
552 ret
= intel_shim_sync_go_unlocked(sdw
);
554 mutex_unlock(sdw
->link_res
->shim_lock
);
562 static void intel_pdi_init(struct sdw_intel
*sdw
,
563 struct sdw_cdns_stream_config
*config
)
565 void __iomem
*shim
= sdw
->link_res
->shim
;
566 unsigned int link_id
= sdw
->instance
;
567 int pcm_cap
, pdm_cap
;
569 /* PCM Stream Capability */
570 pcm_cap
= intel_readw(shim
, SDW_SHIM_PCMSCAP(link_id
));
572 config
->pcm_bd
= FIELD_GET(SDW_SHIM_PCMSCAP_BSS
, pcm_cap
);
573 config
->pcm_in
= FIELD_GET(SDW_SHIM_PCMSCAP_ISS
, pcm_cap
);
574 config
->pcm_out
= FIELD_GET(SDW_SHIM_PCMSCAP_OSS
, pcm_cap
);
576 dev_dbg(sdw
->cdns
.dev
, "PCM cap bd:%d in:%d out:%d\n",
577 config
->pcm_bd
, config
->pcm_in
, config
->pcm_out
);
579 /* PDM Stream Capability */
580 pdm_cap
= intel_readw(shim
, SDW_SHIM_PDMSCAP(link_id
));
582 config
->pdm_bd
= FIELD_GET(SDW_SHIM_PDMSCAP_BSS
, pdm_cap
);
583 config
->pdm_in
= FIELD_GET(SDW_SHIM_PDMSCAP_ISS
, pdm_cap
);
584 config
->pdm_out
= FIELD_GET(SDW_SHIM_PDMSCAP_OSS
, pdm_cap
);
586 dev_dbg(sdw
->cdns
.dev
, "PDM cap bd:%d in:%d out:%d\n",
587 config
->pdm_bd
, config
->pdm_in
, config
->pdm_out
);
591 intel_pdi_get_ch_cap(struct sdw_intel
*sdw
, unsigned int pdi_num
, bool pcm
)
593 void __iomem
*shim
= sdw
->link_res
->shim
;
594 unsigned int link_id
= sdw
->instance
;
598 count
= intel_readw(shim
, SDW_SHIM_PCMSYCHC(link_id
, pdi_num
));
601 * WORKAROUND: on all existing Intel controllers, pdi
602 * number 2 reports channel count as 1 even though it
603 * supports 8 channels. Performing hardcoding for pdi
610 count
= intel_readw(shim
, SDW_SHIM_PDMSCAP(link_id
));
611 count
= FIELD_GET(SDW_SHIM_PDMSCAP_CPSS
, count
);
614 /* zero based values for channel count in register */
620 static int intel_pdi_get_ch_update(struct sdw_intel
*sdw
,
621 struct sdw_cdns_pdi
*pdi
,
622 unsigned int num_pdi
,
623 unsigned int *num_ch
, bool pcm
)
627 for (i
= 0; i
< num_pdi
; i
++) {
628 pdi
->ch_count
= intel_pdi_get_ch_cap(sdw
, pdi
->num
, pcm
);
629 ch_count
+= pdi
->ch_count
;
637 static int intel_pdi_stream_ch_update(struct sdw_intel
*sdw
,
638 struct sdw_cdns_streams
*stream
, bool pcm
)
640 intel_pdi_get_ch_update(sdw
, stream
->bd
, stream
->num_bd
,
641 &stream
->num_ch_bd
, pcm
);
643 intel_pdi_get_ch_update(sdw
, stream
->in
, stream
->num_in
,
644 &stream
->num_ch_in
, pcm
);
646 intel_pdi_get_ch_update(sdw
, stream
->out
, stream
->num_out
,
647 &stream
->num_ch_out
, pcm
);
652 static int intel_pdi_ch_update(struct sdw_intel
*sdw
)
654 /* First update PCM streams followed by PDM streams */
655 intel_pdi_stream_ch_update(sdw
, &sdw
->cdns
.pcm
, true);
656 intel_pdi_stream_ch_update(sdw
, &sdw
->cdns
.pdm
, false);
662 intel_pdi_shim_configure(struct sdw_intel
*sdw
, struct sdw_cdns_pdi
*pdi
)
664 void __iomem
*shim
= sdw
->link_res
->shim
;
665 unsigned int link_id
= sdw
->instance
;
668 /* the Bulk and PCM streams are not contiguous */
669 pdi
->intel_alh_id
= (link_id
* 16) + pdi
->num
+ 3;
671 pdi
->intel_alh_id
+= 2;
674 * Program stream parameters to stream SHIM register
675 * This is applicable for PCM stream only.
677 if (pdi
->type
!= SDW_STREAM_PCM
)
680 if (pdi
->dir
== SDW_DATA_DIR_RX
)
681 pdi_conf
|= SDW_SHIM_PCMSYCM_DIR
;
683 pdi_conf
&= ~(SDW_SHIM_PCMSYCM_DIR
);
685 u32p_replace_bits(&pdi_conf
, pdi
->intel_alh_id
, SDW_SHIM_PCMSYCM_STREAM
);
686 u32p_replace_bits(&pdi_conf
, pdi
->l_ch_num
, SDW_SHIM_PCMSYCM_LCHN
);
687 u32p_replace_bits(&pdi_conf
, pdi
->h_ch_num
, SDW_SHIM_PCMSYCM_HCHN
);
689 intel_writew(shim
, SDW_SHIM_PCMSYCHM(link_id
, pdi
->num
), pdi_conf
);
693 intel_pdi_alh_configure(struct sdw_intel
*sdw
, struct sdw_cdns_pdi
*pdi
)
695 void __iomem
*alh
= sdw
->link_res
->alh
;
696 unsigned int link_id
= sdw
->instance
;
699 /* the Bulk and PCM streams are not contiguous */
700 pdi
->intel_alh_id
= (link_id
* 16) + pdi
->num
+ 3;
702 pdi
->intel_alh_id
+= 2;
704 /* Program Stream config ALH register */
705 conf
= intel_readl(alh
, SDW_ALH_STRMZCFG(pdi
->intel_alh_id
));
707 u32p_replace_bits(&conf
, SDW_ALH_STRMZCFG_DMAT_VAL
, SDW_ALH_STRMZCFG_DMAT
);
708 u32p_replace_bits(&conf
, pdi
->ch_count
- 1, SDW_ALH_STRMZCFG_CHN
);
710 intel_writel(alh
, SDW_ALH_STRMZCFG(pdi
->intel_alh_id
), conf
);
713 static int intel_params_stream(struct sdw_intel
*sdw
,
714 struct snd_pcm_substream
*substream
,
715 struct snd_soc_dai
*dai
,
716 struct snd_pcm_hw_params
*hw_params
,
717 int link_id
, int alh_stream_id
)
719 struct sdw_intel_link_res
*res
= sdw
->link_res
;
720 struct sdw_intel_stream_params_data params_data
;
722 params_data
.substream
= substream
;
723 params_data
.dai
= dai
;
724 params_data
.hw_params
= hw_params
;
725 params_data
.link_id
= link_id
;
726 params_data
.alh_stream_id
= alh_stream_id
;
728 if (res
->ops
&& res
->ops
->params_stream
&& res
->dev
)
729 return res
->ops
->params_stream(res
->dev
,
734 static int intel_free_stream(struct sdw_intel
*sdw
,
735 struct snd_pcm_substream
*substream
,
736 struct snd_soc_dai
*dai
,
739 struct sdw_intel_link_res
*res
= sdw
->link_res
;
740 struct sdw_intel_stream_free_data free_data
;
742 free_data
.substream
= substream
;
744 free_data
.link_id
= link_id
;
746 if (res
->ops
&& res
->ops
->free_stream
&& res
->dev
)
747 return res
->ops
->free_stream(res
->dev
,
754 * bank switch routines
757 static int intel_pre_bank_switch(struct sdw_bus
*bus
)
759 struct sdw_cdns
*cdns
= bus_to_cdns(bus
);
760 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
762 /* Write to register only for multi-link */
763 if (!bus
->multi_link
)
766 intel_shim_sync_arm(sdw
);
771 static int intel_post_bank_switch(struct sdw_bus
*bus
)
773 struct sdw_cdns
*cdns
= bus_to_cdns(bus
);
774 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
775 void __iomem
*shim
= sdw
->link_res
->shim
;
778 /* Write to register only for multi-link */
779 if (!bus
->multi_link
)
782 mutex_lock(sdw
->link_res
->shim_lock
);
784 /* Read SYNC register */
785 sync_reg
= intel_readl(shim
, SDW_SHIM_SYNC
);
788 * post_bank_switch() ops is called from the bus in loop for
789 * all the Masters in the steam with the expectation that
790 * we trigger the bankswitch for the only first Master in the list
791 * and do nothing for the other Masters
793 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
795 if (!(sync_reg
& SDW_SHIM_SYNC_CMDSYNC_MASK
)) {
800 ret
= intel_shim_sync_go_unlocked(sdw
);
802 mutex_unlock(sdw
->link_res
->shim_lock
);
805 dev_err(sdw
->cdns
.dev
, "Post bank switch failed: %d\n", ret
);
814 static int intel_startup(struct snd_pcm_substream
*substream
,
815 struct snd_soc_dai
*dai
)
817 struct sdw_cdns
*cdns
= snd_soc_dai_get_drvdata(dai
);
820 ret
= pm_runtime_get_sync(cdns
->dev
);
821 if (ret
< 0 && ret
!= -EACCES
) {
822 dev_err_ratelimited(cdns
->dev
,
823 "pm_runtime_get_sync failed in %s, ret %d\n",
825 pm_runtime_put_noidle(cdns
->dev
);
831 static int intel_hw_params(struct snd_pcm_substream
*substream
,
832 struct snd_pcm_hw_params
*params
,
833 struct snd_soc_dai
*dai
)
835 struct sdw_cdns
*cdns
= snd_soc_dai_get_drvdata(dai
);
836 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
837 struct sdw_cdns_dma_data
*dma
;
838 struct sdw_cdns_pdi
*pdi
;
839 struct sdw_stream_config sconfig
;
840 struct sdw_port_config
*pconfig
;
845 dma
= snd_soc_dai_get_dma_data(dai
, substream
);
849 ch
= params_channels(params
);
850 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
851 dir
= SDW_DATA_DIR_RX
;
853 dir
= SDW_DATA_DIR_TX
;
855 if (dma
->stream_type
== SDW_STREAM_PDM
)
859 pdi
= sdw_cdns_alloc_pdi(cdns
, &cdns
->pcm
, ch
, dir
, dai
->id
);
861 pdi
= sdw_cdns_alloc_pdi(cdns
, &cdns
->pdm
, ch
, dir
, dai
->id
);
868 /* do run-time configurations for SHIM, ALH and PDI/PORT */
869 intel_pdi_shim_configure(sdw
, pdi
);
870 intel_pdi_alh_configure(sdw
, pdi
);
871 sdw_cdns_config_stream(cdns
, ch
, dir
, pdi
);
873 /* store pdi and hw_params, may be needed in prepare step */
874 dma
->suspended
= false;
876 dma
->hw_params
= params
;
878 /* Inform DSP about PDI stream number */
879 ret
= intel_params_stream(sdw
, substream
, dai
, params
,
885 sconfig
.direction
= dir
;
886 sconfig
.ch_count
= ch
;
887 sconfig
.frame_rate
= params_rate(params
);
888 sconfig
.type
= dma
->stream_type
;
890 if (dma
->stream_type
== SDW_STREAM_PDM
) {
891 sconfig
.frame_rate
*= 50;
894 sconfig
.bps
= snd_pcm_format_width(params_format(params
));
897 /* Port configuration */
898 pconfig
= kzalloc(sizeof(*pconfig
), GFP_KERNEL
);
904 pconfig
->num
= pdi
->num
;
905 pconfig
->ch_mask
= (1 << ch
) - 1;
907 ret
= sdw_stream_add_master(&cdns
->bus
, &sconfig
,
908 pconfig
, 1, dma
->stream
);
910 dev_err(cdns
->dev
, "add master to stream failed:%d\n", ret
);
917 static int intel_prepare(struct snd_pcm_substream
*substream
,
918 struct snd_soc_dai
*dai
)
920 struct sdw_cdns
*cdns
= snd_soc_dai_get_drvdata(dai
);
921 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
922 struct sdw_cdns_dma_data
*dma
;
926 dma
= snd_soc_dai_get_dma_data(dai
, substream
);
928 dev_err(dai
->dev
, "failed to get dma data in %s\n",
933 if (dma
->suspended
) {
934 dma
->suspended
= false;
937 * .prepare() is called after system resume, where we
938 * need to reinitialize the SHIM/ALH/Cadence IP.
939 * .prepare() is also called to deal with underflows,
940 * but in those cases we cannot touch ALH/SHIM
944 /* configure stream */
945 ch
= params_channels(dma
->hw_params
);
946 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
947 dir
= SDW_DATA_DIR_RX
;
949 dir
= SDW_DATA_DIR_TX
;
951 intel_pdi_shim_configure(sdw
, dma
->pdi
);
952 intel_pdi_alh_configure(sdw
, dma
->pdi
);
953 sdw_cdns_config_stream(cdns
, ch
, dir
, dma
->pdi
);
955 /* Inform DSP about PDI stream number */
956 ret
= intel_params_stream(sdw
, substream
, dai
,
959 dma
->pdi
->intel_alh_id
);
966 intel_hw_free(struct snd_pcm_substream
*substream
, struct snd_soc_dai
*dai
)
968 struct sdw_cdns
*cdns
= snd_soc_dai_get_drvdata(dai
);
969 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
970 struct sdw_cdns_dma_data
*dma
;
973 dma
= snd_soc_dai_get_dma_data(dai
, substream
);
978 * The sdw stream state will transition to RELEASED when stream->
979 * master_list is empty. So the stream state will transition to
980 * DEPREPARED for the first cpu-dai and to RELEASED for the last
983 ret
= sdw_stream_remove_master(&cdns
->bus
, dma
->stream
);
985 dev_err(dai
->dev
, "remove master from stream %s failed: %d\n",
986 dma
->stream
->name
, ret
);
990 ret
= intel_free_stream(sdw
, substream
, dai
, sdw
->instance
);
992 dev_err(dai
->dev
, "intel_free_stream: failed %d\n", ret
);
996 dma
->hw_params
= NULL
;
1002 static void intel_shutdown(struct snd_pcm_substream
*substream
,
1003 struct snd_soc_dai
*dai
)
1005 struct sdw_cdns
*cdns
= snd_soc_dai_get_drvdata(dai
);
1007 pm_runtime_mark_last_busy(cdns
->dev
);
1008 pm_runtime_put_autosuspend(cdns
->dev
);
1011 static int intel_component_dais_suspend(struct snd_soc_component
*component
)
1013 struct sdw_cdns_dma_data
*dma
;
1014 struct snd_soc_dai
*dai
;
1016 for_each_component_dais(component
, dai
) {
1018 * we don't have a .suspend dai_ops, and we don't have access
1019 * to the substream, so let's mark both capture and playback
1020 * DMA contexts as suspended
1022 dma
= dai
->playback_dma_data
;
1024 dma
->suspended
= true;
1026 dma
= dai
->capture_dma_data
;
1028 dma
->suspended
= true;
1034 static int intel_pcm_set_sdw_stream(struct snd_soc_dai
*dai
,
1035 void *stream
, int direction
)
1037 return cdns_set_sdw_stream(dai
, stream
, true, direction
);
1040 static int intel_pdm_set_sdw_stream(struct snd_soc_dai
*dai
,
1041 void *stream
, int direction
)
1043 return cdns_set_sdw_stream(dai
, stream
, false, direction
);
1046 static void *intel_get_sdw_stream(struct snd_soc_dai
*dai
,
1049 struct sdw_cdns_dma_data
*dma
;
1051 if (direction
== SNDRV_PCM_STREAM_PLAYBACK
)
1052 dma
= dai
->playback_dma_data
;
1054 dma
= dai
->capture_dma_data
;
1057 return ERR_PTR(-EINVAL
);
1062 static const struct snd_soc_dai_ops intel_pcm_dai_ops
= {
1063 .startup
= intel_startup
,
1064 .hw_params
= intel_hw_params
,
1065 .prepare
= intel_prepare
,
1066 .hw_free
= intel_hw_free
,
1067 .shutdown
= intel_shutdown
,
1068 .set_sdw_stream
= intel_pcm_set_sdw_stream
,
1069 .get_sdw_stream
= intel_get_sdw_stream
,
1072 static const struct snd_soc_dai_ops intel_pdm_dai_ops
= {
1073 .startup
= intel_startup
,
1074 .hw_params
= intel_hw_params
,
1075 .prepare
= intel_prepare
,
1076 .hw_free
= intel_hw_free
,
1077 .shutdown
= intel_shutdown
,
1078 .set_sdw_stream
= intel_pdm_set_sdw_stream
,
1079 .get_sdw_stream
= intel_get_sdw_stream
,
1082 static const struct snd_soc_component_driver dai_component
= {
1083 .name
= "soundwire",
1084 .suspend
= intel_component_dais_suspend
1087 static int intel_create_dai(struct sdw_cdns
*cdns
,
1088 struct snd_soc_dai_driver
*dais
,
1089 enum intel_pdi_type type
,
1090 u32 num
, u32 off
, u32 max_ch
, bool pcm
)
1097 /* TODO: Read supported rates/formats from hardware */
1098 for (i
= off
; i
< (off
+ num
); i
++) {
1099 dais
[i
].name
= devm_kasprintf(cdns
->dev
, GFP_KERNEL
,
1105 if (type
== INTEL_PDI_BD
|| type
== INTEL_PDI_OUT
) {
1106 dais
[i
].playback
.channels_min
= 1;
1107 dais
[i
].playback
.channels_max
= max_ch
;
1108 dais
[i
].playback
.rates
= SNDRV_PCM_RATE_48000
;
1109 dais
[i
].playback
.formats
= SNDRV_PCM_FMTBIT_S16_LE
;
1112 if (type
== INTEL_PDI_BD
|| type
== INTEL_PDI_IN
) {
1113 dais
[i
].capture
.channels_min
= 1;
1114 dais
[i
].capture
.channels_max
= max_ch
;
1115 dais
[i
].capture
.rates
= SNDRV_PCM_RATE_48000
;
1116 dais
[i
].capture
.formats
= SNDRV_PCM_FMTBIT_S16_LE
;
1120 dais
[i
].ops
= &intel_pcm_dai_ops
;
1122 dais
[i
].ops
= &intel_pdm_dai_ops
;
1128 static int intel_register_dai(struct sdw_intel
*sdw
)
1130 struct sdw_cdns
*cdns
= &sdw
->cdns
;
1131 struct sdw_cdns_streams
*stream
;
1132 struct snd_soc_dai_driver
*dais
;
1133 int num_dai
, ret
, off
= 0;
1135 /* DAIs are created based on total number of PDIs supported */
1136 num_dai
= cdns
->pcm
.num_pdi
+ cdns
->pdm
.num_pdi
;
1138 dais
= devm_kcalloc(cdns
->dev
, num_dai
, sizeof(*dais
), GFP_KERNEL
);
1142 /* Create PCM DAIs */
1143 stream
= &cdns
->pcm
;
1145 ret
= intel_create_dai(cdns
, dais
, INTEL_PDI_IN
, cdns
->pcm
.num_in
,
1146 off
, stream
->num_ch_in
, true);
1150 off
+= cdns
->pcm
.num_in
;
1151 ret
= intel_create_dai(cdns
, dais
, INTEL_PDI_OUT
, cdns
->pcm
.num_out
,
1152 off
, stream
->num_ch_out
, true);
1156 off
+= cdns
->pcm
.num_out
;
1157 ret
= intel_create_dai(cdns
, dais
, INTEL_PDI_BD
, cdns
->pcm
.num_bd
,
1158 off
, stream
->num_ch_bd
, true);
1162 /* Create PDM DAIs */
1163 stream
= &cdns
->pdm
;
1164 off
+= cdns
->pcm
.num_bd
;
1165 ret
= intel_create_dai(cdns
, dais
, INTEL_PDI_IN
, cdns
->pdm
.num_in
,
1166 off
, stream
->num_ch_in
, false);
1170 off
+= cdns
->pdm
.num_in
;
1171 ret
= intel_create_dai(cdns
, dais
, INTEL_PDI_OUT
, cdns
->pdm
.num_out
,
1172 off
, stream
->num_ch_out
, false);
1176 off
+= cdns
->pdm
.num_out
;
1177 ret
= intel_create_dai(cdns
, dais
, INTEL_PDI_BD
, cdns
->pdm
.num_bd
,
1178 off
, stream
->num_ch_bd
, false);
1182 return snd_soc_register_component(cdns
->dev
, &dai_component
,
1186 static int sdw_master_read_intel_prop(struct sdw_bus
*bus
)
1188 struct sdw_master_prop
*prop
= &bus
->prop
;
1189 struct fwnode_handle
*link
;
1193 /* Find master handle */
1194 snprintf(name
, sizeof(name
),
1195 "mipi-sdw-link-%d-subproperties", bus
->link_id
);
1197 link
= device_get_named_child_node(bus
->dev
, name
);
1199 dev_err(bus
->dev
, "Master node %s not found\n", name
);
1203 fwnode_property_read_u32(link
,
1204 "intel-sdw-ip-clock",
1207 /* the values reported by BIOS are the 2x clock, not the bus clock */
1208 prop
->mclk_freq
/= 2;
1210 fwnode_property_read_u32(link
,
1214 if (quirk_mask
& SDW_INTEL_QUIRK_MASK_BUS_DISABLE
)
1215 prop
->hw_disabled
= true;
1217 prop
->quirks
= SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH
|
1218 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY
;
1223 static int intel_prop_read(struct sdw_bus
*bus
)
1225 /* Initialize with default handler to read all DisCo properties */
1226 sdw_master_read_prop(bus
);
1228 /* read Intel-specific properties */
1229 sdw_master_read_intel_prop(bus
);
1234 static struct sdw_master_ops sdw_intel_ops
= {
1235 .read_prop
= sdw_master_read_prop
,
1236 .override_adr
= sdw_dmi_override_adr
,
1237 .xfer_msg
= cdns_xfer_msg
,
1238 .xfer_msg_defer
= cdns_xfer_msg_defer
,
1239 .reset_page_addr
= cdns_reset_page_addr
,
1240 .set_bus_conf
= cdns_bus_conf
,
1241 .pre_bank_switch
= intel_pre_bank_switch
,
1242 .post_bank_switch
= intel_post_bank_switch
,
1245 static int intel_init(struct sdw_intel
*sdw
)
1249 /* Initialize shim and controller */
1250 intel_link_power_up(sdw
);
1252 clock_stop
= sdw_cdns_is_clock_stop(&sdw
->cdns
);
1254 intel_shim_init(sdw
, clock_stop
);
1260 * probe and init (aux_dev_id argument is required by function prototype but not used)
1262 static int intel_link_probe(struct auxiliary_device
*auxdev
,
1263 const struct auxiliary_device_id
*aux_dev_id
)
1266 struct device
*dev
= &auxdev
->dev
;
1267 struct sdw_intel_link_dev
*ldev
= auxiliary_dev_to_sdw_intel_link_dev(auxdev
);
1268 struct sdw_intel
*sdw
;
1269 struct sdw_cdns
*cdns
;
1270 struct sdw_bus
*bus
;
1273 sdw
= devm_kzalloc(dev
, sizeof(*sdw
), GFP_KERNEL
);
1280 sdw
->instance
= auxdev
->id
;
1281 sdw
->link_res
= &ldev
->link_res
;
1283 cdns
->registers
= sdw
->link_res
->registers
;
1284 cdns
->instance
= sdw
->instance
;
1285 cdns
->msg_count
= 0;
1287 bus
->link_id
= auxdev
->id
;
1289 sdw_cdns_probe(cdns
);
1291 /* Set property read ops */
1292 sdw_intel_ops
.read_prop
= intel_prop_read
;
1293 bus
->ops
= &sdw_intel_ops
;
1295 /* set driver data, accessed by snd_soc_dai_get_drvdata() */
1296 dev_set_drvdata(dev
, cdns
);
1298 /* use generic bandwidth allocation algorithm */
1299 sdw
->cdns
.bus
.compute_params
= sdw_compute_params
;
1301 ret
= sdw_bus_master_add(bus
, dev
, dev
->fwnode
);
1303 dev_err(dev
, "sdw_bus_master_add fail: %d\n", ret
);
1307 if (bus
->prop
.hw_disabled
)
1309 "SoundWire master %d is disabled, will be ignored\n",
1312 * Ignore BIOS err_threshold, it's a really bad idea when dealing
1313 * with multiple hardware synchronized links
1315 bus
->prop
.err_threshold
= 0;
1320 int intel_link_startup(struct auxiliary_device
*auxdev
)
1322 struct sdw_cdns_stream_config config
;
1323 struct device
*dev
= &auxdev
->dev
;
1324 struct sdw_cdns
*cdns
= dev_get_drvdata(dev
);
1325 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
1326 struct sdw_bus
*bus
= &cdns
->bus
;
1329 u32 clock_stop_quirks
;
1332 if (bus
->prop
.hw_disabled
) {
1334 "SoundWire master %d is disabled, ignoring\n",
1339 link_flags
= md_flags
>> (bus
->link_id
* 8);
1340 multi_link
= !(link_flags
& SDW_INTEL_MASTER_DISABLE_MULTI_LINK
);
1342 dev_dbg(dev
, "Multi-link is disabled\n");
1343 bus
->multi_link
= false;
1346 * hardware-based synchronization is required regardless
1347 * of the number of segments used by a stream: SSP-based
1348 * synchronization is gated by gsync when the multi-master
1351 bus
->multi_link
= true;
1352 bus
->hw_sync_min_links
= 1;
1355 /* Initialize shim, controller */
1356 ret
= intel_init(sdw
);
1360 /* Read the PDI config and initialize cadence PDI */
1361 intel_pdi_init(sdw
, &config
);
1362 ret
= sdw_cdns_pdi_init(cdns
, config
);
1366 intel_pdi_ch_update(sdw
);
1368 ret
= sdw_cdns_enable_interrupt(cdns
, true);
1370 dev_err(dev
, "cannot enable interrupts\n");
1375 * follow recommended programming flows to avoid timeouts when
1379 intel_shim_sync_arm(sdw
);
1381 ret
= sdw_cdns_init(cdns
);
1383 dev_err(dev
, "unable to initialize Cadence IP\n");
1387 ret
= sdw_cdns_exit_reset(cdns
);
1389 dev_err(dev
, "unable to exit bus reset sequence\n");
1394 ret
= intel_shim_sync_go(sdw
);
1396 dev_err(dev
, "sync go failed: %d\n", ret
);
1400 sdw_cdns_check_self_clearing_bits(cdns
, __func__
,
1401 true, INTEL_MASTER_RESET_ITERATIONS
);
1404 ret
= intel_register_dai(sdw
);
1406 dev_err(dev
, "DAI registration failed: %d\n", ret
);
1407 snd_soc_unregister_component(dev
);
1411 intel_debugfs_init(sdw
);
1413 /* Enable runtime PM */
1414 if (!(link_flags
& SDW_INTEL_MASTER_DISABLE_PM_RUNTIME
)) {
1415 pm_runtime_set_autosuspend_delay(dev
,
1416 INTEL_MASTER_SUSPEND_DELAY_MS
);
1417 pm_runtime_use_autosuspend(dev
);
1418 pm_runtime_mark_last_busy(dev
);
1420 pm_runtime_set_active(dev
);
1421 pm_runtime_enable(dev
);
1424 clock_stop_quirks
= sdw
->link_res
->clock_stop_quirks
;
1425 if (clock_stop_quirks
& SDW_INTEL_CLK_STOP_NOT_ALLOWED
) {
1427 * To keep the clock running we need to prevent
1428 * pm_runtime suspend from happening by increasing the
1430 * This quirk is specified by the parent PCI device in
1431 * case of specific latency requirements. It will have
1432 * no effect if pm_runtime is disabled by the user via
1433 * a module parameter for testing purposes.
1435 pm_runtime_get_noresume(dev
);
1439 * The runtime PM status of Slave devices is "Unsupported"
1440 * until they report as ATTACHED. If they don't, e.g. because
1441 * there are no Slave devices populated or if the power-on is
1442 * delayed or dependent on a power switch, the Master will
1443 * remain active and prevent its parent from suspending.
1445 * Conditionally force the pm_runtime core to re-evaluate the
1446 * Master status in the absence of any Slave activity. A quirk
1447 * is provided to e.g. deal with Slaves that may be powered on
1448 * with a delay. A more complete solution would require the
1449 * definition of Master properties.
1451 if (!(link_flags
& SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE
))
1452 pm_runtime_idle(dev
);
1454 sdw
->startup_done
= true;
1458 sdw_cdns_enable_interrupt(cdns
, false);
1463 static void intel_link_remove(struct auxiliary_device
*auxdev
)
1465 struct device
*dev
= &auxdev
->dev
;
1466 struct sdw_cdns
*cdns
= dev_get_drvdata(dev
);
1467 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
1468 struct sdw_bus
*bus
= &cdns
->bus
;
1471 * Since pm_runtime is already disabled, we don't decrease
1472 * the refcount when the clock_stop_quirk is
1473 * SDW_INTEL_CLK_STOP_NOT_ALLOWED
1475 if (!bus
->prop
.hw_disabled
) {
1476 intel_debugfs_exit(sdw
);
1477 sdw_cdns_enable_interrupt(cdns
, false);
1478 snd_soc_unregister_component(dev
);
1480 sdw_bus_master_delete(bus
);
1483 int intel_link_process_wakeen_event(struct auxiliary_device
*auxdev
)
1485 struct device
*dev
= &auxdev
->dev
;
1486 struct sdw_intel
*sdw
;
1487 struct sdw_bus
*bus
;
1491 sdw
= dev_get_drvdata(dev
);
1492 bus
= &sdw
->cdns
.bus
;
1494 if (bus
->prop
.hw_disabled
|| !sdw
->startup_done
) {
1495 dev_dbg(dev
, "SoundWire master %d is disabled or not-started, ignoring\n",
1500 shim
= sdw
->link_res
->shim
;
1501 wake_sts
= intel_readw(shim
, SDW_SHIM_WAKESTS
);
1503 if (!(wake_sts
& BIT(sdw
->instance
)))
1506 /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1507 intel_shim_wake(sdw
, false);
1510 * resume the Master, which will generate a bus reset and result in
1511 * Slaves re-attaching and be re-enumerated. The SoundWire physical
1512 * device which generated the wake will trigger an interrupt, which
1513 * will in turn cause the corresponding Linux Slave device to be
1514 * resumed and the Slave codec driver to check the status.
1516 pm_request_resume(dev
);
1525 static int intel_resume_child_device(struct device
*dev
, void *data
)
1528 struct sdw_slave
*slave
= dev_to_sdw_dev(dev
);
1530 if (!slave
->probed
) {
1531 dev_dbg(dev
, "%s: skipping device, no probed driver\n", __func__
);
1534 if (!slave
->dev_num_sticky
) {
1535 dev_dbg(dev
, "%s: skipping device, never detected on bus\n", __func__
);
1539 ret
= pm_request_resume(dev
);
1541 dev_err(dev
, "%s: pm_request_resume failed: %d\n", __func__
, ret
);
1546 static int __maybe_unused
intel_pm_prepare(struct device
*dev
)
1548 struct sdw_cdns
*cdns
= dev_get_drvdata(dev
);
1549 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
1550 struct sdw_bus
*bus
= &cdns
->bus
;
1551 u32 clock_stop_quirks
;
1554 if (bus
->prop
.hw_disabled
|| !sdw
->startup_done
) {
1555 dev_dbg(dev
, "SoundWire master %d is disabled or not-started, ignoring\n",
1560 clock_stop_quirks
= sdw
->link_res
->clock_stop_quirks
;
1562 if (pm_runtime_suspended(dev
) &&
1563 pm_runtime_suspended(dev
->parent
) &&
1564 ((clock_stop_quirks
& SDW_INTEL_CLK_STOP_BUS_RESET
) ||
1565 !clock_stop_quirks
)) {
1567 * if we've enabled clock stop, and the parent is suspended, the SHIM registers
1568 * are not accessible and the shim wake cannot be disabled.
1569 * The only solution is to resume the entire bus to full power
1573 * If any operation in this block fails, we keep going since we don't want
1574 * to prevent system suspend from happening and errors should be recoverable
1579 * first resume the device for this link. This will also by construction
1580 * resume the PCI parent device.
1582 ret
= pm_request_resume(dev
);
1584 dev_err(dev
, "%s: pm_request_resume failed: %d\n", __func__
, ret
);
1589 * Continue resuming the entire bus (parent + child devices) to exit
1590 * the clock stop mode. If there are no devices connected on this link
1592 * The resume to full power could have been implemented with a .prepare
1593 * step in SoundWire codec drivers. This would however require a lot
1594 * of code to handle an Intel-specific corner case. It is simpler in
1595 * practice to add a loop at the link level.
1597 ret
= device_for_each_child(bus
->dev
, NULL
, intel_resume_child_device
);
1600 dev_err(dev
, "%s: intel_resume_child_device failed: %d\n", __func__
, ret
);
1606 static int __maybe_unused
intel_suspend(struct device
*dev
)
1608 struct sdw_cdns
*cdns
= dev_get_drvdata(dev
);
1609 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
1610 struct sdw_bus
*bus
= &cdns
->bus
;
1611 u32 clock_stop_quirks
;
1614 if (bus
->prop
.hw_disabled
|| !sdw
->startup_done
) {
1615 dev_dbg(dev
, "SoundWire master %d is disabled or not-started, ignoring\n",
1620 if (pm_runtime_suspended(dev
)) {
1621 dev_dbg(dev
, "%s: pm_runtime status: suspended\n", __func__
);
1623 clock_stop_quirks
= sdw
->link_res
->clock_stop_quirks
;
1625 if ((clock_stop_quirks
& SDW_INTEL_CLK_STOP_BUS_RESET
) ||
1626 !clock_stop_quirks
) {
1628 if (pm_runtime_suspended(dev
->parent
)) {
1630 * paranoia check: this should not happen with the .prepare
1631 * resume to full power
1633 dev_err(dev
, "%s: invalid config: parent is suspended\n", __func__
);
1635 intel_shim_wake(sdw
, false);
1642 ret
= sdw_cdns_enable_interrupt(cdns
, false);
1644 dev_err(dev
, "cannot disable interrupts on suspend\n");
1648 ret
= intel_link_power_down(sdw
);
1650 dev_err(dev
, "Link power down failed: %d\n", ret
);
1654 intel_shim_wake(sdw
, false);
1659 static int __maybe_unused
intel_suspend_runtime(struct device
*dev
)
1661 struct sdw_cdns
*cdns
= dev_get_drvdata(dev
);
1662 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
1663 struct sdw_bus
*bus
= &cdns
->bus
;
1664 u32 clock_stop_quirks
;
1667 if (bus
->prop
.hw_disabled
|| !sdw
->startup_done
) {
1668 dev_dbg(dev
, "SoundWire master %d is disabled or not-started, ignoring\n",
1673 clock_stop_quirks
= sdw
->link_res
->clock_stop_quirks
;
1675 if (clock_stop_quirks
& SDW_INTEL_CLK_STOP_TEARDOWN
) {
1677 ret
= sdw_cdns_enable_interrupt(cdns
, false);
1679 dev_err(dev
, "cannot disable interrupts on suspend\n");
1683 ret
= intel_link_power_down(sdw
);
1685 dev_err(dev
, "Link power down failed: %d\n", ret
);
1689 intel_shim_wake(sdw
, false);
1691 } else if (clock_stop_quirks
& SDW_INTEL_CLK_STOP_BUS_RESET
||
1692 !clock_stop_quirks
) {
1693 bool wake_enable
= true;
1695 ret
= sdw_cdns_clock_stop(cdns
, true);
1697 dev_err(dev
, "cannot enable clock stop on suspend\n");
1698 wake_enable
= false;
1701 ret
= sdw_cdns_enable_interrupt(cdns
, false);
1703 dev_err(dev
, "cannot disable interrupts on suspend\n");
1707 ret
= intel_link_power_down(sdw
);
1709 dev_err(dev
, "Link power down failed: %d\n", ret
);
1713 intel_shim_wake(sdw
, wake_enable
);
1715 dev_err(dev
, "%s clock_stop_quirks %x unsupported\n",
1716 __func__
, clock_stop_quirks
);
1723 static int __maybe_unused
intel_resume(struct device
*dev
)
1725 struct sdw_cdns
*cdns
= dev_get_drvdata(dev
);
1726 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
1727 struct sdw_bus
*bus
= &cdns
->bus
;
1732 if (bus
->prop
.hw_disabled
|| !sdw
->startup_done
) {
1733 dev_dbg(dev
, "SoundWire master %d is disabled or not-started, ignoring\n",
1738 link_flags
= md_flags
>> (bus
->link_id
* 8);
1739 multi_link
= !(link_flags
& SDW_INTEL_MASTER_DISABLE_MULTI_LINK
);
1741 if (pm_runtime_suspended(dev
)) {
1742 dev_dbg(dev
, "%s: pm_runtime status was suspended, forcing active\n", __func__
);
1744 /* follow required sequence from runtime_pm.rst */
1745 pm_runtime_disable(dev
);
1746 pm_runtime_set_active(dev
);
1747 pm_runtime_mark_last_busy(dev
);
1748 pm_runtime_enable(dev
);
1750 link_flags
= md_flags
>> (bus
->link_id
* 8);
1752 if (!(link_flags
& SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE
))
1753 pm_runtime_idle(dev
);
1756 ret
= intel_init(sdw
);
1758 dev_err(dev
, "%s failed: %d\n", __func__
, ret
);
1763 * make sure all Slaves are tagged as UNATTACHED and provide
1764 * reason for reinitialization
1766 sdw_clear_slave_status(bus
, SDW_UNATTACH_REQUEST_MASTER_RESET
);
1768 ret
= sdw_cdns_enable_interrupt(cdns
, true);
1770 dev_err(dev
, "cannot enable interrupts during resume\n");
1775 * follow recommended programming flows to avoid timeouts when
1779 intel_shim_sync_arm(sdw
);
1781 ret
= sdw_cdns_init(&sdw
->cdns
);
1783 dev_err(dev
, "unable to initialize Cadence IP during resume\n");
1787 ret
= sdw_cdns_exit_reset(cdns
);
1789 dev_err(dev
, "unable to exit bus reset sequence during resume\n");
1794 ret
= intel_shim_sync_go(sdw
);
1796 dev_err(dev
, "sync go failed during resume\n");
1800 sdw_cdns_check_self_clearing_bits(cdns
, __func__
,
1801 true, INTEL_MASTER_RESET_ITERATIONS
);
1804 * after system resume, the pm_runtime suspend() may kick in
1805 * during the enumeration, before any children device force the
1806 * master device to remain active. Using pm_runtime_get()
1807 * routines is not really possible, since it'd prevent the
1808 * master from suspending.
1809 * A reasonable compromise is to update the pm_runtime
1810 * counters and delay the pm_runtime suspend by several
1811 * seconds, by when all enumeration should be complete.
1813 pm_runtime_mark_last_busy(dev
);
1818 static int __maybe_unused
intel_resume_runtime(struct device
*dev
)
1820 struct sdw_cdns
*cdns
= dev_get_drvdata(dev
);
1821 struct sdw_intel
*sdw
= cdns_to_intel(cdns
);
1822 struct sdw_bus
*bus
= &cdns
->bus
;
1823 u32 clock_stop_quirks
;
1830 if (bus
->prop
.hw_disabled
|| !sdw
->startup_done
) {
1831 dev_dbg(dev
, "SoundWire master %d is disabled or not-started, ignoring\n",
1836 link_flags
= md_flags
>> (bus
->link_id
* 8);
1837 multi_link
= !(link_flags
& SDW_INTEL_MASTER_DISABLE_MULTI_LINK
);
1839 clock_stop_quirks
= sdw
->link_res
->clock_stop_quirks
;
1841 if (clock_stop_quirks
& SDW_INTEL_CLK_STOP_TEARDOWN
) {
1842 ret
= intel_init(sdw
);
1844 dev_err(dev
, "%s failed: %d\n", __func__
, ret
);
1849 * make sure all Slaves are tagged as UNATTACHED and provide
1850 * reason for reinitialization
1852 sdw_clear_slave_status(bus
, SDW_UNATTACH_REQUEST_MASTER_RESET
);
1854 ret
= sdw_cdns_enable_interrupt(cdns
, true);
1856 dev_err(dev
, "cannot enable interrupts during resume\n");
1861 * follow recommended programming flows to avoid
1862 * timeouts when gsync is enabled
1865 intel_shim_sync_arm(sdw
);
1867 ret
= sdw_cdns_init(&sdw
->cdns
);
1869 dev_err(dev
, "unable to initialize Cadence IP during resume\n");
1873 ret
= sdw_cdns_exit_reset(cdns
);
1875 dev_err(dev
, "unable to exit bus reset sequence during resume\n");
1880 ret
= intel_shim_sync_go(sdw
);
1882 dev_err(dev
, "sync go failed during resume\n");
1886 sdw_cdns_check_self_clearing_bits(cdns
, "intel_resume_runtime TEARDOWN",
1887 true, INTEL_MASTER_RESET_ITERATIONS
);
1889 } else if (clock_stop_quirks
& SDW_INTEL_CLK_STOP_BUS_RESET
) {
1890 ret
= intel_init(sdw
);
1892 dev_err(dev
, "%s failed: %d\n", __func__
, ret
);
1897 * An exception condition occurs for the CLK_STOP_BUS_RESET
1898 * case if one or more masters remain active. In this condition,
1899 * all the masters are powered on for they are in the same power
1900 * domain. Master can preserve its context for clock stop0, so
1901 * there is no need to clear slave status and reset bus.
1903 clock_stop0
= sdw_cdns_is_clock_stop(&sdw
->cdns
);
1908 * make sure all Slaves are tagged as UNATTACHED and
1909 * provide reason for reinitialization
1912 status
= SDW_UNATTACH_REQUEST_MASTER_RESET
;
1913 sdw_clear_slave_status(bus
, status
);
1915 ret
= sdw_cdns_enable_interrupt(cdns
, true);
1917 dev_err(dev
, "cannot enable interrupts during resume\n");
1922 * follow recommended programming flows to avoid
1923 * timeouts when gsync is enabled
1926 intel_shim_sync_arm(sdw
);
1929 * Re-initialize the IP since it was powered-off
1931 sdw_cdns_init(&sdw
->cdns
);
1934 ret
= sdw_cdns_enable_interrupt(cdns
, true);
1936 dev_err(dev
, "cannot enable interrupts during resume\n");
1941 ret
= sdw_cdns_clock_restart(cdns
, !clock_stop0
);
1943 dev_err(dev
, "unable to restart clock during resume\n");
1948 ret
= sdw_cdns_exit_reset(cdns
);
1950 dev_err(dev
, "unable to exit bus reset sequence during resume\n");
1955 ret
= intel_shim_sync_go(sdw
);
1957 dev_err(sdw
->cdns
.dev
, "sync go failed during resume\n");
1962 sdw_cdns_check_self_clearing_bits(cdns
, "intel_resume_runtime BUS_RESET",
1963 true, INTEL_MASTER_RESET_ITERATIONS
);
1965 } else if (!clock_stop_quirks
) {
1967 clock_stop0
= sdw_cdns_is_clock_stop(&sdw
->cdns
);
1969 dev_err(dev
, "%s invalid configuration, clock was not stopped", __func__
);
1971 ret
= intel_init(sdw
);
1973 dev_err(dev
, "%s failed: %d\n", __func__
, ret
);
1977 ret
= sdw_cdns_enable_interrupt(cdns
, true);
1979 dev_err(dev
, "cannot enable interrupts during resume\n");
1983 ret
= sdw_cdns_clock_restart(cdns
, false);
1985 dev_err(dev
, "unable to resume master during resume\n");
1989 sdw_cdns_check_self_clearing_bits(cdns
, "intel_resume_runtime no_quirks",
1990 true, INTEL_MASTER_RESET_ITERATIONS
);
1992 dev_err(dev
, "%s clock_stop_quirks %x unsupported\n",
1993 __func__
, clock_stop_quirks
);
2000 static const struct dev_pm_ops intel_pm
= {
2001 .prepare
= intel_pm_prepare
,
2002 SET_SYSTEM_SLEEP_PM_OPS(intel_suspend
, intel_resume
)
2003 SET_RUNTIME_PM_OPS(intel_suspend_runtime
, intel_resume_runtime
, NULL
)
2006 static const struct auxiliary_device_id intel_link_id_table
[] = {
2007 { .name
= "soundwire_intel.link" },
2010 MODULE_DEVICE_TABLE(auxiliary
, intel_link_id_table
);
2012 static struct auxiliary_driver sdw_intel_drv
= {
2013 .probe
= intel_link_probe
,
2014 .remove
= intel_link_remove
,
2016 /* auxiliary_driver_register() sets .name to be the modname */
2019 .id_table
= intel_link_id_table
2021 module_auxiliary_driver(sdw_intel_drv
);
2023 MODULE_LICENSE("Dual BSD/GPL");
2024 MODULE_DESCRIPTION("Intel Soundwire Link Driver");