1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
5 #include <linux/completion.h>
6 #include <linux/interrupt.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
11 #include <linux/of_irq.h>
12 #include <linux/of_device.h>
13 #include <linux/regmap.h>
14 #include <linux/slab.h>
15 #include <linux/slimbus.h>
16 #include <linux/soundwire/sdw.h>
17 #include <linux/soundwire/sdw_registers.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc.h>
22 #define SWRM_COMP_HW_VERSION 0x00
23 #define SWRM_COMP_CFG_ADDR 0x04
24 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
25 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
26 #define SWRM_COMP_PARAMS 0x100
27 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)
28 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
29 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
30 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
31 #define SWRM_INTERRUPT_STATUS 0x200
32 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
33 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
34 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
35 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
36 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3)
37 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4)
38 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5)
39 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6)
40 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
41 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
42 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
43 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
44 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
45 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
46 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
47 #define SWRM_INTERRUPT_MAX 17
48 #define SWRM_INTERRUPT_MASK_ADDR 0x204
49 #define SWRM_INTERRUPT_CLEAR 0x208
50 #define SWRM_INTERRUPT_CPU_EN 0x210
51 #define SWRM_CMD_FIFO_WR_CMD 0x300
52 #define SWRM_CMD_FIFO_RD_CMD 0x304
53 #define SWRM_CMD_FIFO_CMD 0x308
54 #define SWRM_CMD_FIFO_FLUSH 0x1
55 #define SWRM_CMD_FIFO_STATUS 0x30C
56 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
57 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
58 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
59 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
60 #define SWRM_RD_WR_CMD_RETRIES 0x7
61 #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
62 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
63 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
64 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
65 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
66 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
67 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
68 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
69 #define SWRM_MCP_BUS_CTRL 0x1044
70 #define SWRM_MCP_BUS_CLK_START BIT(1)
71 #define SWRM_MCP_CFG_ADDR 0x1048
72 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
73 #define SWRM_DEF_CMD_NO_PINGS 0x1f
74 #define SWRM_MCP_STATUS 0x104C
75 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
76 #define SWRM_MCP_SLV_STATUS 0x1090
77 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
78 #define SWRM_MCP_SLV_STATUS_SZ 2
79 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
80 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
81 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
82 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
83 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
84 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
85 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
87 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
88 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
89 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
90 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
91 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
92 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
93 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
95 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
96 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
98 #define SWRM_SPECIAL_CMD_ID 0xF
99 #define MAX_FREQ_NUM 1
100 #define TIMEOUT_MS (2 * HZ)
101 #define QCOM_SWRM_MAX_RD_LEN 0x1
102 #define QCOM_SDW_MAX_PORTS 14
103 #define DEFAULT_CLK_FREQ 9600000
104 #define SWRM_MAX_DAIS 0xF
105 #define SWR_INVALID_PARAM 0xFF
106 #define SWR_HSTOP_MAX_VAL 0xF
107 #define SWR_HSTART_MIN_VAL 0x0
108 #define SWR_BROADCAST_CMD_ID 0x0F
109 #define SWR_MAX_CMD_ID 14
110 #define MAX_FIFO_RD_RETRY 3
111 #define SWR_OVERFLOW_RETRY_COUNT 30
113 struct qcom_swrm_port_config
{
125 struct qcom_swrm_ctrl
{
128 struct regmap
*regmap
;
130 struct completion broadcast
;
131 struct completion enumeration
;
132 struct work_struct slave_work
;
133 /* Port alloc/free lock */
134 struct mutex port_lock
;
139 unsigned int version
;
144 unsigned long dout_port_mask
;
145 unsigned long din_port_mask
;
149 struct qcom_swrm_port_config pconfig
[QCOM_SDW_MAX_PORTS
];
150 struct sdw_stream_runtime
*sruntime
[SWRM_MAX_DAIS
];
151 enum sdw_slave_status status
[SDW_MAX_DEVICES
];
152 int (*reg_read
)(struct qcom_swrm_ctrl
*ctrl
, int reg
, u32
*val
);
153 int (*reg_write
)(struct qcom_swrm_ctrl
*ctrl
, int reg
, int val
);
159 struct qcom_swrm_data
{
164 static struct qcom_swrm_data swrm_v1_3_data
= {
169 static struct qcom_swrm_data swrm_v1_5_data
= {
174 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
176 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl
*ctrl
, int reg
,
179 struct regmap
*wcd_regmap
= ctrl
->regmap
;
182 /* pg register + offset */
183 ret
= regmap_bulk_write(wcd_regmap
, SWRM_AHB_BRIDGE_RD_ADDR_0
,
188 ret
= regmap_bulk_read(wcd_regmap
, SWRM_AHB_BRIDGE_RD_DATA_0
,
196 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl
*ctrl
,
199 struct regmap
*wcd_regmap
= ctrl
->regmap
;
201 /* pg register + offset */
202 ret
= regmap_bulk_write(wcd_regmap
, SWRM_AHB_BRIDGE_WR_DATA_0
,
207 /* write address register */
208 ret
= regmap_bulk_write(wcd_regmap
, SWRM_AHB_BRIDGE_WR_ADDR_0
,
216 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl
*ctrl
, int reg
,
219 *val
= readl(ctrl
->mmio
+ reg
);
223 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl
*ctrl
, int reg
,
226 writel(val
, ctrl
->mmio
+ reg
);
230 static u32
swrm_get_packed_reg_val(u8
*cmd_id
, u8 cmd_data
,
231 u8 dev_addr
, u16 reg_addr
)
236 if (id
!= SWR_BROADCAST_CMD_ID
) {
237 if (id
< SWR_MAX_CMD_ID
)
243 val
= SWRM_REG_VAL_PACK(cmd_data
, dev_addr
, id
, reg_addr
);
248 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl
*swrm
)
250 u32 fifo_outstanding_data
, value
;
251 int fifo_retry_count
= SWR_OVERFLOW_RETRY_COUNT
;
254 /* Check for fifo underflow during read */
255 swrm
->reg_read(swrm
, SWRM_CMD_FIFO_STATUS
, &value
);
256 fifo_outstanding_data
= FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK
, value
);
258 /* Check if read data is available in read fifo */
259 if (fifo_outstanding_data
> 0)
262 usleep_range(500, 510);
263 } while (fifo_retry_count
--);
265 if (fifo_outstanding_data
== 0) {
266 dev_err_ratelimited(swrm
->dev
, "%s err read underflow\n", __func__
);
273 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl
*swrm
)
275 u32 fifo_outstanding_cmds
, value
;
276 int fifo_retry_count
= SWR_OVERFLOW_RETRY_COUNT
;
279 /* Check for fifo overflow during write */
280 swrm
->reg_read(swrm
, SWRM_CMD_FIFO_STATUS
, &value
);
281 fifo_outstanding_cmds
= FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK
, value
);
283 /* Check for space in write fifo before writing */
284 if (fifo_outstanding_cmds
< swrm
->wr_fifo_depth
)
287 usleep_range(500, 510);
288 } while (fifo_retry_count
--);
290 if (fifo_outstanding_cmds
== swrm
->wr_fifo_depth
) {
291 dev_err_ratelimited(swrm
->dev
, "%s err write overflow\n", __func__
);
298 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl
*swrm
, u8 cmd_data
,
299 u8 dev_addr
, u16 reg_addr
)
306 if (dev_addr
== SDW_BROADCAST_DEV_NUM
) {
307 cmd_id
= SWR_BROADCAST_CMD_ID
;
308 val
= swrm_get_packed_reg_val(&cmd_id
, cmd_data
,
311 val
= swrm_get_packed_reg_val(&swrm
->wcmd_id
, cmd_data
,
315 if (swrm_wait_for_wr_fifo_avail(swrm
))
316 return SDW_CMD_FAIL_OTHER
;
318 /* Its assumed that write is okay as we do not get any status back */
319 swrm
->reg_write(swrm
, SWRM_CMD_FIFO_WR_CMD
, val
);
321 /* version 1.3 or less */
322 if (swrm
->version
<= 0x01030000)
323 usleep_range(150, 155);
325 if (cmd_id
== SWR_BROADCAST_CMD_ID
) {
327 * sleep for 10ms for MSM soundwire variant to allow broadcast
328 * command to complete.
330 ret
= wait_for_completion_timeout(&swrm
->broadcast
,
331 msecs_to_jiffies(TIMEOUT_MS
));
333 ret
= SDW_CMD_IGNORED
;
343 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl
*swrm
,
344 u8 dev_addr
, u16 reg_addr
,
347 u32 cmd_data
, cmd_id
, val
, retry_attempt
= 0;
349 val
= swrm_get_packed_reg_val(&swrm
->rcmd_id
, len
, dev_addr
, reg_addr
);
351 /* wait for FIFO RD to complete to avoid overflow */
352 usleep_range(100, 105);
353 swrm
->reg_write(swrm
, SWRM_CMD_FIFO_RD_CMD
, val
);
354 /* wait for FIFO RD CMD complete to avoid overflow */
355 usleep_range(250, 255);
357 if (swrm_wait_for_rd_fifo_avail(swrm
))
358 return SDW_CMD_FAIL_OTHER
;
361 swrm
->reg_read(swrm
, SWRM_CMD_FIFO_RD_FIFO_ADDR
, &cmd_data
);
362 rval
[0] = cmd_data
& 0xFF;
363 cmd_id
= FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK
, cmd_data
);
365 if (cmd_id
!= swrm
->rcmd_id
) {
366 if (retry_attempt
< (MAX_FIFO_RD_RETRY
- 1)) {
367 /* wait 500 us before retry on fifo read failure */
368 usleep_range(500, 505);
369 swrm
->reg_write(swrm
, SWRM_CMD_FIFO_CMD
,
370 SWRM_CMD_FIFO_FLUSH
);
371 swrm
->reg_write(swrm
, SWRM_CMD_FIFO_RD_CMD
, val
);
378 } while (retry_attempt
< MAX_FIFO_RD_RETRY
);
380 dev_err(swrm
->dev
, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
381 dev_num: 0x%x, cmd_data: 0x%x\n",
382 reg_addr
, swrm
->rcmd_id
, dev_addr
, cmd_data
);
384 return SDW_CMD_IGNORED
;
387 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl
*ctrl
)
392 ctrl
->reg_read(ctrl
, SWRM_MCP_SLV_STATUS
, &val
);
394 for (dev_num
= 0; dev_num
< SDW_MAX_DEVICES
; dev_num
++) {
395 status
= (val
>> (dev_num
* SWRM_MCP_SLV_STATUS_SZ
));
397 if ((status
& SWRM_MCP_SLV_STATUS_MASK
) == SDW_SLAVE_ALERT
) {
398 ctrl
->status
[dev_num
] = status
;
406 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl
*ctrl
)
411 ctrl
->reg_read(ctrl
, SWRM_MCP_SLV_STATUS
, &val
);
412 ctrl
->slave_status
= val
;
414 for (i
= 0; i
< SDW_MAX_DEVICES
; i
++) {
417 s
= (val
>> (i
* 2));
418 s
&= SWRM_MCP_SLV_STATUS_MASK
;
423 static void qcom_swrm_set_slave_dev_num(struct sdw_bus
*bus
,
424 struct sdw_slave
*slave
, int devnum
)
426 struct qcom_swrm_ctrl
*ctrl
= to_qcom_sdw(bus
);
429 ctrl
->reg_read(ctrl
, SWRM_MCP_SLV_STATUS
, &status
);
430 status
= (status
>> (devnum
* SWRM_MCP_SLV_STATUS_SZ
));
431 status
&= SWRM_MCP_SLV_STATUS_MASK
;
433 if (status
== SDW_SLAVE_ATTACHED
) {
435 slave
->dev_num
= devnum
;
436 mutex_lock(&bus
->bus_lock
);
437 set_bit(devnum
, bus
->assigned
);
438 mutex_unlock(&bus
->bus_lock
);
442 static int qcom_swrm_enumerate(struct sdw_bus
*bus
)
444 struct qcom_swrm_ctrl
*ctrl
= to_qcom_sdw(bus
);
445 struct sdw_slave
*slave
, *_s
;
446 struct sdw_slave_id id
;
451 char *buf1
= (char *)&val1
, *buf2
= (char *)&val2
;
453 for (i
= 1; i
<= SDW_MAX_DEVICES
; i
++) {
454 /*SCP_Devid5 - Devid 4*/
455 ctrl
->reg_read(ctrl
, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i
), &val1
);
457 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
458 ctrl
->reg_read(ctrl
, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i
), &val2
);
463 addr
= buf2
[1] | (buf2
[0] << 8) | (buf1
[3] << 16) |
464 ((u64
)buf1
[2] << 24) | ((u64
)buf1
[1] << 32) |
465 ((u64
)buf1
[0] << 40);
467 sdw_extract_slave_id(bus
, addr
, &id
);
469 /* Now compare with entries */
470 list_for_each_entry_safe(slave
, _s
, &bus
->slaves
, node
) {
471 if (sdw_compare_devid(slave
, id
) == 0) {
472 qcom_swrm_set_slave_dev_num(bus
, slave
, i
);
479 qcom_swrm_set_slave_dev_num(bus
, NULL
, i
);
480 sdw_slave_add(bus
, &id
, NULL
);
484 complete(&ctrl
->enumeration
);
488 static irqreturn_t
qcom_swrm_irq_handler(int irq
, void *dev_id
)
490 struct qcom_swrm_ctrl
*swrm
= dev_id
;
491 u32 value
, intr_sts
, intr_sts_masked
, slave_status
;
494 int ret
= IRQ_HANDLED
;
496 swrm
->reg_read(swrm
, SWRM_INTERRUPT_STATUS
, &intr_sts
);
497 intr_sts_masked
= intr_sts
& swrm
->intr_mask
;
500 for (i
= 0; i
< SWRM_INTERRUPT_MAX
; i
++) {
501 value
= intr_sts_masked
& BIT(i
);
506 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ
:
507 devnum
= qcom_swrm_get_alert_slave_dev_num(swrm
);
509 dev_err_ratelimited(swrm
->dev
,
510 "no slave alert found.spurious interrupt\n");
512 sdw_handle_slave_status(&swrm
->bus
, swrm
->status
);
516 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED
:
517 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS
:
518 dev_err_ratelimited(swrm
->dev
, "%s: SWR new slave attached\n",
520 swrm
->reg_read(swrm
, SWRM_MCP_SLV_STATUS
, &slave_status
);
521 if (swrm
->slave_status
== slave_status
) {
522 dev_err(swrm
->dev
, "Slave status not changed %x\n",
525 qcom_swrm_get_device_status(swrm
);
526 qcom_swrm_enumerate(&swrm
->bus
);
527 sdw_handle_slave_status(&swrm
->bus
, swrm
->status
);
530 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET
:
531 dev_err_ratelimited(swrm
->dev
,
532 "%s: SWR bus clsh detected\n",
534 swrm
->intr_mask
&= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET
;
535 swrm
->reg_write(swrm
, SWRM_INTERRUPT_CPU_EN
, swrm
->intr_mask
);
537 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW
:
538 swrm
->reg_read(swrm
, SWRM_CMD_FIFO_STATUS
, &value
);
539 dev_err_ratelimited(swrm
->dev
,
540 "%s: SWR read FIFO overflow fifo status 0x%x\n",
543 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW
:
544 swrm
->reg_read(swrm
, SWRM_CMD_FIFO_STATUS
, &value
);
545 dev_err_ratelimited(swrm
->dev
,
546 "%s: SWR read FIFO underflow fifo status 0x%x\n",
549 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW
:
550 swrm
->reg_read(swrm
, SWRM_CMD_FIFO_STATUS
, &value
);
552 "%s: SWR write FIFO overflow fifo status %x\n",
554 swrm
->reg_write(swrm
, SWRM_CMD_FIFO_CMD
, 0x1);
556 case SWRM_INTERRUPT_STATUS_CMD_ERROR
:
557 swrm
->reg_read(swrm
, SWRM_CMD_FIFO_STATUS
, &value
);
558 dev_err_ratelimited(swrm
->dev
,
559 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
561 swrm
->reg_write(swrm
, SWRM_CMD_FIFO_CMD
, 0x1);
563 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION
:
564 dev_err_ratelimited(swrm
->dev
,
565 "%s: SWR Port collision detected\n",
567 swrm
->intr_mask
&= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION
;
568 swrm
->reg_write(swrm
,
569 SWRM_INTERRUPT_CPU_EN
, swrm
->intr_mask
);
571 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH
:
572 dev_err_ratelimited(swrm
->dev
,
573 "%s: SWR read enable valid mismatch\n",
576 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH
;
577 swrm
->reg_write(swrm
,
578 SWRM_INTERRUPT_CPU_EN
, swrm
->intr_mask
);
580 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED
:
581 complete(&swrm
->broadcast
);
583 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2
:
585 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2
:
587 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP
:
590 dev_err_ratelimited(swrm
->dev
,
591 "%s: SWR unknown interrupt value: %d\n",
597 swrm
->reg_write(swrm
, SWRM_INTERRUPT_CLEAR
, intr_sts
);
598 swrm
->reg_read(swrm
, SWRM_INTERRUPT_STATUS
, &intr_sts
);
599 intr_sts_masked
= intr_sts
& swrm
->intr_mask
;
600 } while (intr_sts_masked
);
605 static int qcom_swrm_init(struct qcom_swrm_ctrl
*ctrl
)
609 /* Clear Rows and Cols */
610 val
= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK
, ctrl
->rows_index
);
611 val
|= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK
, ctrl
->cols_index
);
613 ctrl
->reg_write(ctrl
, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val
);
615 /* Enable Auto enumeration */
616 ctrl
->reg_write(ctrl
, SWRM_ENUMERATOR_CFG_ADDR
, 1);
618 ctrl
->intr_mask
= SWRM_INTERRUPT_STATUS_RMSK
;
619 /* Mask soundwire interrupts */
620 ctrl
->reg_write(ctrl
, SWRM_INTERRUPT_MASK_ADDR
,
621 SWRM_INTERRUPT_STATUS_RMSK
);
623 /* Configure No pings */
624 ctrl
->reg_read(ctrl
, SWRM_MCP_CFG_ADDR
, &val
);
625 u32p_replace_bits(&val
, SWRM_DEF_CMD_NO_PINGS
, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK
);
626 ctrl
->reg_write(ctrl
, SWRM_MCP_CFG_ADDR
, val
);
628 ctrl
->reg_write(ctrl
, SWRM_MCP_BUS_CTRL
, SWRM_MCP_BUS_CLK_START
);
629 /* Configure number of retries of a read/write cmd */
630 if (ctrl
->version
> 0x01050001) {
631 /* Only for versions >= 1.5.1 */
632 ctrl
->reg_write(ctrl
, SWRM_CMD_FIFO_CFG_ADDR
,
633 SWRM_RD_WR_CMD_RETRIES
|
634 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE
);
636 ctrl
->reg_write(ctrl
, SWRM_CMD_FIFO_CFG_ADDR
,
637 SWRM_RD_WR_CMD_RETRIES
);
640 /* Set IRQ to PULSE */
641 ctrl
->reg_write(ctrl
, SWRM_COMP_CFG_ADDR
,
642 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK
|
643 SWRM_COMP_CFG_ENABLE_MSK
);
645 /* enable CPU IRQs */
647 ctrl
->reg_write(ctrl
, SWRM_INTERRUPT_CPU_EN
,
648 SWRM_INTERRUPT_STATUS_RMSK
);
650 ctrl
->slave_status
= 0;
651 ctrl
->reg_read(ctrl
, SWRM_COMP_PARAMS
, &val
);
652 ctrl
->rd_fifo_depth
= FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH
, val
);
653 ctrl
->wr_fifo_depth
= FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH
, val
);
658 static enum sdw_command_response
qcom_swrm_xfer_msg(struct sdw_bus
*bus
,
661 struct qcom_swrm_ctrl
*ctrl
= to_qcom_sdw(bus
);
664 if (msg
->flags
== SDW_MSG_FLAG_READ
) {
665 for (i
= 0; i
< msg
->len
;) {
666 if ((msg
->len
- i
) < QCOM_SWRM_MAX_RD_LEN
)
669 len
= QCOM_SWRM_MAX_RD_LEN
;
671 ret
= qcom_swrm_cmd_fifo_rd_cmd(ctrl
, msg
->dev_num
,
679 } else if (msg
->flags
== SDW_MSG_FLAG_WRITE
) {
680 for (i
= 0; i
< msg
->len
; i
++) {
681 ret
= qcom_swrm_cmd_fifo_wr_cmd(ctrl
, msg
->buf
[i
],
685 return SDW_CMD_IGNORED
;
692 static int qcom_swrm_pre_bank_switch(struct sdw_bus
*bus
)
694 u32 reg
= SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus
->params
.next_bank
);
695 struct qcom_swrm_ctrl
*ctrl
= to_qcom_sdw(bus
);
698 ctrl
->reg_read(ctrl
, reg
, &val
);
700 u32p_replace_bits(&val
, ctrl
->cols_index
, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK
);
701 u32p_replace_bits(&val
, ctrl
->rows_index
, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK
);
703 return ctrl
->reg_write(ctrl
, reg
, val
);
706 static int qcom_swrm_port_params(struct sdw_bus
*bus
,
707 struct sdw_port_params
*p_params
,
710 struct qcom_swrm_ctrl
*ctrl
= to_qcom_sdw(bus
);
712 return ctrl
->reg_write(ctrl
, SWRM_DP_BLOCK_CTRL_1(p_params
->num
),
717 static int qcom_swrm_transport_params(struct sdw_bus
*bus
,
718 struct sdw_transport_params
*params
,
719 enum sdw_reg_bank bank
)
721 struct qcom_swrm_ctrl
*ctrl
= to_qcom_sdw(bus
);
722 struct qcom_swrm_port_config
*pcfg
;
724 int reg
= SWRM_DP_PORT_CTRL_BANK((params
->port_num
), bank
);
727 pcfg
= &ctrl
->pconfig
[params
->port_num
];
729 value
= pcfg
->off1
<< SWRM_DP_PORT_CTRL_OFFSET1_SHFT
;
730 value
|= pcfg
->off2
<< SWRM_DP_PORT_CTRL_OFFSET2_SHFT
;
733 ret
= ctrl
->reg_write(ctrl
, reg
, value
);
737 if (pcfg
->lane_control
!= SWR_INVALID_PARAM
) {
738 reg
= SWRM_DP_PORT_CTRL_2_BANK(params
->port_num
, bank
);
739 value
= pcfg
->lane_control
;
740 ret
= ctrl
->reg_write(ctrl
, reg
, value
);
745 if (pcfg
->blk_group_count
!= SWR_INVALID_PARAM
) {
746 reg
= SWRM_DP_BLOCK_CTRL2_BANK(params
->port_num
, bank
);
747 value
= pcfg
->blk_group_count
;
748 ret
= ctrl
->reg_write(ctrl
, reg
, value
);
753 if (pcfg
->hstart
!= SWR_INVALID_PARAM
754 && pcfg
->hstop
!= SWR_INVALID_PARAM
) {
755 reg
= SWRM_DP_PORT_HCTRL_BANK(params
->port_num
, bank
);
756 value
= (pcfg
->hstop
<< 4) | pcfg
->hstart
;
757 ret
= ctrl
->reg_write(ctrl
, reg
, value
);
759 reg
= SWRM_DP_PORT_HCTRL_BANK(params
->port_num
, bank
);
760 value
= (SWR_HSTOP_MAX_VAL
<< 4) | SWR_HSTART_MIN_VAL
;
761 ret
= ctrl
->reg_write(ctrl
, reg
, value
);
767 if (pcfg
->bp_mode
!= SWR_INVALID_PARAM
) {
768 reg
= SWRM_DP_BLOCK_CTRL3_BANK(params
->port_num
, bank
);
769 ret
= ctrl
->reg_write(ctrl
, reg
, pcfg
->bp_mode
);
776 static int qcom_swrm_port_enable(struct sdw_bus
*bus
,
777 struct sdw_enable_ch
*enable_ch
,
780 u32 reg
= SWRM_DP_PORT_CTRL_BANK(enable_ch
->port_num
, bank
);
781 struct qcom_swrm_ctrl
*ctrl
= to_qcom_sdw(bus
);
784 ctrl
->reg_read(ctrl
, reg
, &val
);
786 if (enable_ch
->enable
)
787 val
|= (enable_ch
->ch_mask
<< SWRM_DP_PORT_CTRL_EN_CHAN_SHFT
);
789 val
&= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT
);
791 return ctrl
->reg_write(ctrl
, reg
, val
);
794 static const struct sdw_master_port_ops qcom_swrm_port_ops
= {
795 .dpn_set_port_params
= qcom_swrm_port_params
,
796 .dpn_set_port_transport_params
= qcom_swrm_transport_params
,
797 .dpn_port_enable_ch
= qcom_swrm_port_enable
,
800 static const struct sdw_master_ops qcom_swrm_ops
= {
801 .xfer_msg
= qcom_swrm_xfer_msg
,
802 .pre_bank_switch
= qcom_swrm_pre_bank_switch
,
805 static int qcom_swrm_compute_params(struct sdw_bus
*bus
)
807 struct qcom_swrm_ctrl
*ctrl
= to_qcom_sdw(bus
);
808 struct sdw_master_runtime
*m_rt
;
809 struct sdw_slave_runtime
*s_rt
;
810 struct sdw_port_runtime
*p_rt
;
811 struct qcom_swrm_port_config
*pcfg
;
812 struct sdw_slave
*slave
;
816 list_for_each_entry(m_rt
, &bus
->m_rt_list
, bus_node
) {
817 list_for_each_entry(p_rt
, &m_rt
->port_list
, port_node
) {
818 pcfg
= &ctrl
->pconfig
[p_rt
->num
];
819 p_rt
->transport_params
.port_num
= p_rt
->num
;
820 if (pcfg
->word_length
!= SWR_INVALID_PARAM
) {
821 sdw_fill_port_params(&p_rt
->port_params
,
822 p_rt
->num
, pcfg
->word_length
+ 1,
823 SDW_PORT_FLOW_MODE_ISOCH
,
824 SDW_PORT_DATA_MODE_NORMAL
);
829 list_for_each_entry(s_rt
, &m_rt
->slave_rt_list
, m_rt_node
) {
831 list_for_each_entry(p_rt
, &s_rt
->port_list
, port_node
) {
832 m_port
= slave
->m_port_map
[p_rt
->num
];
833 /* port config starts at offset 0 so -1 from actual port number */
835 pcfg
= &ctrl
->pconfig
[m_port
];
837 pcfg
= &ctrl
->pconfig
[i
];
838 p_rt
->transport_params
.port_num
= p_rt
->num
;
839 p_rt
->transport_params
.sample_interval
=
841 p_rt
->transport_params
.offset1
= pcfg
->off1
;
842 p_rt
->transport_params
.offset2
= pcfg
->off2
;
843 p_rt
->transport_params
.blk_pkg_mode
= pcfg
->bp_mode
;
844 p_rt
->transport_params
.blk_grp_ctrl
= pcfg
->blk_group_count
;
846 p_rt
->transport_params
.hstart
= pcfg
->hstart
;
847 p_rt
->transport_params
.hstop
= pcfg
->hstop
;
848 p_rt
->transport_params
.lane_ctrl
= pcfg
->lane_control
;
849 if (pcfg
->word_length
!= SWR_INVALID_PARAM
) {
850 sdw_fill_port_params(&p_rt
->port_params
,
852 pcfg
->word_length
+ 1,
853 SDW_PORT_FLOW_MODE_ISOCH
,
854 SDW_PORT_DATA_MODE_NORMAL
);
864 static u32 qcom_swrm_freq_tbl
[MAX_FREQ_NUM
] = {
868 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl
*ctrl
,
869 struct sdw_stream_runtime
*stream
)
871 struct sdw_master_runtime
*m_rt
;
872 struct sdw_port_runtime
*p_rt
;
873 unsigned long *port_mask
;
875 mutex_lock(&ctrl
->port_lock
);
877 list_for_each_entry(m_rt
, &stream
->master_list
, stream_node
) {
878 if (m_rt
->direction
== SDW_DATA_DIR_RX
)
879 port_mask
= &ctrl
->dout_port_mask
;
881 port_mask
= &ctrl
->din_port_mask
;
883 list_for_each_entry(p_rt
, &m_rt
->port_list
, port_node
)
884 clear_bit(p_rt
->num
, port_mask
);
887 mutex_unlock(&ctrl
->port_lock
);
890 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl
*ctrl
,
891 struct sdw_stream_runtime
*stream
,
892 struct snd_pcm_hw_params
*params
,
895 struct sdw_port_config pconfig
[QCOM_SDW_MAX_PORTS
];
896 struct sdw_stream_config sconfig
;
897 struct sdw_master_runtime
*m_rt
;
898 struct sdw_slave_runtime
*s_rt
;
899 struct sdw_port_runtime
*p_rt
;
900 struct sdw_slave
*slave
;
901 unsigned long *port_mask
;
902 int i
, maxport
, pn
, nports
= 0, ret
= 0;
905 mutex_lock(&ctrl
->port_lock
);
906 list_for_each_entry(m_rt
, &stream
->master_list
, stream_node
) {
907 if (m_rt
->direction
== SDW_DATA_DIR_RX
) {
908 maxport
= ctrl
->num_dout_ports
;
909 port_mask
= &ctrl
->dout_port_mask
;
911 maxport
= ctrl
->num_din_ports
;
912 port_mask
= &ctrl
->din_port_mask
;
915 list_for_each_entry(s_rt
, &m_rt
->slave_rt_list
, m_rt_node
) {
917 list_for_each_entry(p_rt
, &s_rt
->port_list
, port_node
) {
918 m_port
= slave
->m_port_map
[p_rt
->num
];
919 /* Port numbers start from 1 - 14*/
923 pn
= find_first_zero_bit(port_mask
, maxport
);
926 dev_err(ctrl
->dev
, "All ports busy\n");
930 set_bit(pn
, port_mask
);
931 pconfig
[nports
].num
= pn
;
932 pconfig
[nports
].ch_mask
= p_rt
->ch_mask
;
938 if (direction
== SNDRV_PCM_STREAM_CAPTURE
)
939 sconfig
.direction
= SDW_DATA_DIR_TX
;
941 sconfig
.direction
= SDW_DATA_DIR_RX
;
943 /* hw parameters wil be ignored as we only support PDM */
944 sconfig
.ch_count
= 1;
945 sconfig
.frame_rate
= params_rate(params
);
946 sconfig
.type
= stream
->type
;
948 sdw_stream_add_master(&ctrl
->bus
, &sconfig
, pconfig
,
952 for (i
= 0; i
< nports
; i
++)
953 clear_bit(pconfig
[i
].num
, port_mask
);
956 mutex_unlock(&ctrl
->port_lock
);
961 static int qcom_swrm_hw_params(struct snd_pcm_substream
*substream
,
962 struct snd_pcm_hw_params
*params
,
963 struct snd_soc_dai
*dai
)
965 struct qcom_swrm_ctrl
*ctrl
= dev_get_drvdata(dai
->dev
);
966 struct sdw_stream_runtime
*sruntime
= ctrl
->sruntime
[dai
->id
];
969 ret
= qcom_swrm_stream_alloc_ports(ctrl
, sruntime
, params
,
972 qcom_swrm_stream_free_ports(ctrl
, sruntime
);
977 static int qcom_swrm_hw_free(struct snd_pcm_substream
*substream
,
978 struct snd_soc_dai
*dai
)
980 struct qcom_swrm_ctrl
*ctrl
= dev_get_drvdata(dai
->dev
);
981 struct sdw_stream_runtime
*sruntime
= ctrl
->sruntime
[dai
->id
];
983 qcom_swrm_stream_free_ports(ctrl
, sruntime
);
984 sdw_stream_remove_master(&ctrl
->bus
, sruntime
);
989 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai
*dai
,
990 void *stream
, int direction
)
992 struct qcom_swrm_ctrl
*ctrl
= dev_get_drvdata(dai
->dev
);
994 ctrl
->sruntime
[dai
->id
] = stream
;
999 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai
*dai
, int direction
)
1001 struct qcom_swrm_ctrl
*ctrl
= dev_get_drvdata(dai
->dev
);
1003 return ctrl
->sruntime
[dai
->id
];
1006 static int qcom_swrm_startup(struct snd_pcm_substream
*substream
,
1007 struct snd_soc_dai
*dai
)
1009 struct qcom_swrm_ctrl
*ctrl
= dev_get_drvdata(dai
->dev
);
1010 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1011 struct sdw_stream_runtime
*sruntime
;
1012 struct snd_soc_dai
*codec_dai
;
1015 sruntime
= sdw_alloc_stream(dai
->name
);
1019 ctrl
->sruntime
[dai
->id
] = sruntime
;
1021 for_each_rtd_codec_dais(rtd
, i
, codec_dai
) {
1022 ret
= snd_soc_dai_set_sdw_stream(codec_dai
, sruntime
,
1024 if (ret
< 0 && ret
!= -ENOTSUPP
) {
1025 dev_err(dai
->dev
, "Failed to set sdw stream on %s\n",
1027 sdw_release_stream(sruntime
);
1035 static void qcom_swrm_shutdown(struct snd_pcm_substream
*substream
,
1036 struct snd_soc_dai
*dai
)
1038 struct qcom_swrm_ctrl
*ctrl
= dev_get_drvdata(dai
->dev
);
1040 sdw_release_stream(ctrl
->sruntime
[dai
->id
]);
1041 ctrl
->sruntime
[dai
->id
] = NULL
;
1044 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops
= {
1045 .hw_params
= qcom_swrm_hw_params
,
1046 .hw_free
= qcom_swrm_hw_free
,
1047 .startup
= qcom_swrm_startup
,
1048 .shutdown
= qcom_swrm_shutdown
,
1049 .set_sdw_stream
= qcom_swrm_set_sdw_stream
,
1050 .get_sdw_stream
= qcom_swrm_get_sdw_stream
,
1053 static const struct snd_soc_component_driver qcom_swrm_dai_component
= {
1054 .name
= "soundwire",
1057 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl
*ctrl
)
1059 int num_dais
= ctrl
->num_dout_ports
+ ctrl
->num_din_ports
;
1060 struct snd_soc_dai_driver
*dais
;
1061 struct snd_soc_pcm_stream
*stream
;
1062 struct device
*dev
= ctrl
->dev
;
1065 /* PDM dais are only tested for now */
1066 dais
= devm_kcalloc(dev
, num_dais
, sizeof(*dais
), GFP_KERNEL
);
1070 for (i
= 0; i
< num_dais
; i
++) {
1071 dais
[i
].name
= devm_kasprintf(dev
, GFP_KERNEL
, "SDW Pin%d", i
);
1075 if (i
< ctrl
->num_dout_ports
)
1076 stream
= &dais
[i
].playback
;
1078 stream
= &dais
[i
].capture
;
1080 stream
->channels_min
= 1;
1081 stream
->channels_max
= 1;
1082 stream
->rates
= SNDRV_PCM_RATE_48000
;
1083 stream
->formats
= SNDRV_PCM_FMTBIT_S16_LE
;
1085 dais
[i
].ops
= &qcom_swrm_pdm_dai_ops
;
1089 return devm_snd_soc_register_component(ctrl
->dev
,
1090 &qcom_swrm_dai_component
,
1094 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl
*ctrl
)
1096 struct device_node
*np
= ctrl
->dev
->of_node
;
1097 u8 off1
[QCOM_SDW_MAX_PORTS
];
1098 u8 off2
[QCOM_SDW_MAX_PORTS
];
1099 u8 si
[QCOM_SDW_MAX_PORTS
];
1100 u8 bp_mode
[QCOM_SDW_MAX_PORTS
] = { 0, };
1101 u8 hstart
[QCOM_SDW_MAX_PORTS
];
1102 u8 hstop
[QCOM_SDW_MAX_PORTS
];
1103 u8 word_length
[QCOM_SDW_MAX_PORTS
];
1104 u8 blk_group_count
[QCOM_SDW_MAX_PORTS
];
1105 u8 lane_control
[QCOM_SDW_MAX_PORTS
];
1106 int i
, ret
, nports
, val
;
1108 ctrl
->reg_read(ctrl
, SWRM_COMP_PARAMS
, &val
);
1110 ctrl
->num_dout_ports
= FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK
, val
);
1111 ctrl
->num_din_ports
= FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK
, val
);
1113 ret
= of_property_read_u32(np
, "qcom,din-ports", &val
);
1117 if (val
> ctrl
->num_din_ports
)
1120 ctrl
->num_din_ports
= val
;
1122 ret
= of_property_read_u32(np
, "qcom,dout-ports", &val
);
1126 if (val
> ctrl
->num_dout_ports
)
1129 ctrl
->num_dout_ports
= val
;
1131 nports
= ctrl
->num_dout_ports
+ ctrl
->num_din_ports
;
1132 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1133 set_bit(0, &ctrl
->dout_port_mask
);
1134 set_bit(0, &ctrl
->din_port_mask
);
1136 ret
= of_property_read_u8_array(np
, "qcom,ports-offset1",
1141 ret
= of_property_read_u8_array(np
, "qcom,ports-offset2",
1146 ret
= of_property_read_u8_array(np
, "qcom,ports-sinterval-low",
1151 ret
= of_property_read_u8_array(np
, "qcom,ports-block-pack-mode",
1156 ctrl
->reg_read(ctrl
, SWRM_COMP_HW_VERSION
, &version
);
1158 if (version
<= 0x01030000)
1159 memset(bp_mode
, SWR_INVALID_PARAM
, QCOM_SDW_MAX_PORTS
);
1164 memset(hstart
, SWR_INVALID_PARAM
, QCOM_SDW_MAX_PORTS
);
1165 of_property_read_u8_array(np
, "qcom,ports-hstart", hstart
, nports
);
1167 memset(hstop
, SWR_INVALID_PARAM
, QCOM_SDW_MAX_PORTS
);
1168 of_property_read_u8_array(np
, "qcom,ports-hstop", hstop
, nports
);
1170 memset(word_length
, SWR_INVALID_PARAM
, QCOM_SDW_MAX_PORTS
);
1171 of_property_read_u8_array(np
, "qcom,ports-word-length", word_length
, nports
);
1173 memset(blk_group_count
, SWR_INVALID_PARAM
, QCOM_SDW_MAX_PORTS
);
1174 of_property_read_u8_array(np
, "qcom,ports-block-group-count", blk_group_count
, nports
);
1176 memset(lane_control
, SWR_INVALID_PARAM
, QCOM_SDW_MAX_PORTS
);
1177 of_property_read_u8_array(np
, "qcom,ports-lane-control", lane_control
, nports
);
1179 for (i
= 0; i
< nports
; i
++) {
1180 /* Valid port number range is from 1-14 */
1181 ctrl
->pconfig
[i
+ 1].si
= si
[i
];
1182 ctrl
->pconfig
[i
+ 1].off1
= off1
[i
];
1183 ctrl
->pconfig
[i
+ 1].off2
= off2
[i
];
1184 ctrl
->pconfig
[i
+ 1].bp_mode
= bp_mode
[i
];
1185 ctrl
->pconfig
[i
+ 1].hstart
= hstart
[i
];
1186 ctrl
->pconfig
[i
+ 1].hstop
= hstop
[i
];
1187 ctrl
->pconfig
[i
+ 1].word_length
= word_length
[i
];
1188 ctrl
->pconfig
[i
+ 1].blk_group_count
= blk_group_count
[i
];
1189 ctrl
->pconfig
[i
+ 1].lane_control
= lane_control
[i
];
1195 static int qcom_swrm_probe(struct platform_device
*pdev
)
1197 struct device
*dev
= &pdev
->dev
;
1198 struct sdw_master_prop
*prop
;
1199 struct sdw_bus_params
*params
;
1200 struct qcom_swrm_ctrl
*ctrl
;
1201 const struct qcom_swrm_data
*data
;
1205 ctrl
= devm_kzalloc(dev
, sizeof(*ctrl
), GFP_KERNEL
);
1209 data
= of_device_get_match_data(dev
);
1210 ctrl
->rows_index
= sdw_find_row_index(data
->default_rows
);
1211 ctrl
->cols_index
= sdw_find_col_index(data
->default_cols
);
1212 #if IS_REACHABLE(CONFIG_SLIMBUS)
1213 if (dev
->parent
->bus
== &slimbus_bus
) {
1217 ctrl
->reg_read
= qcom_swrm_ahb_reg_read
;
1218 ctrl
->reg_write
= qcom_swrm_ahb_reg_write
;
1219 ctrl
->regmap
= dev_get_regmap(dev
->parent
, NULL
);
1223 ctrl
->reg_read
= qcom_swrm_cpu_reg_read
;
1224 ctrl
->reg_write
= qcom_swrm_cpu_reg_write
;
1225 ctrl
->mmio
= devm_platform_ioremap_resource(pdev
, 0);
1226 if (IS_ERR(ctrl
->mmio
))
1227 return PTR_ERR(ctrl
->mmio
);
1230 ctrl
->irq
= of_irq_get(dev
->of_node
, 0);
1231 if (ctrl
->irq
< 0) {
1236 ctrl
->hclk
= devm_clk_get(dev
, "iface");
1237 if (IS_ERR(ctrl
->hclk
)) {
1238 ret
= PTR_ERR(ctrl
->hclk
);
1242 clk_prepare_enable(ctrl
->hclk
);
1245 dev_set_drvdata(&pdev
->dev
, ctrl
);
1246 mutex_init(&ctrl
->port_lock
);
1247 init_completion(&ctrl
->broadcast
);
1248 init_completion(&ctrl
->enumeration
);
1250 ctrl
->bus
.ops
= &qcom_swrm_ops
;
1251 ctrl
->bus
.port_ops
= &qcom_swrm_port_ops
;
1252 ctrl
->bus
.compute_params
= &qcom_swrm_compute_params
;
1254 ret
= qcom_swrm_get_port_config(ctrl
);
1258 params
= &ctrl
->bus
.params
;
1259 params
->max_dr_freq
= DEFAULT_CLK_FREQ
;
1260 params
->curr_dr_freq
= DEFAULT_CLK_FREQ
;
1261 params
->col
= data
->default_cols
;
1262 params
->row
= data
->default_rows
;
1263 ctrl
->reg_read(ctrl
, SWRM_MCP_STATUS
, &val
);
1264 params
->curr_bank
= val
& SWRM_MCP_STATUS_BANK_NUM_MASK
;
1265 params
->next_bank
= !params
->curr_bank
;
1267 prop
= &ctrl
->bus
.prop
;
1268 prop
->max_clk_freq
= DEFAULT_CLK_FREQ
;
1269 prop
->num_clk_gears
= 0;
1270 prop
->num_clk_freq
= MAX_FREQ_NUM
;
1271 prop
->clk_freq
= &qcom_swrm_freq_tbl
[0];
1272 prop
->default_col
= data
->default_cols
;
1273 prop
->default_row
= data
->default_rows
;
1275 ctrl
->reg_read(ctrl
, SWRM_COMP_HW_VERSION
, &ctrl
->version
);
1277 ret
= devm_request_threaded_irq(dev
, ctrl
->irq
, NULL
,
1278 qcom_swrm_irq_handler
,
1279 IRQF_TRIGGER_RISING
|
1283 dev_err(dev
, "Failed to request soundwire irq\n");
1287 ret
= sdw_bus_master_add(&ctrl
->bus
, dev
, dev
->fwnode
);
1289 dev_err(dev
, "Failed to register Soundwire controller (%d)\n",
1294 qcom_swrm_init(ctrl
);
1295 wait_for_completion_timeout(&ctrl
->enumeration
,
1296 msecs_to_jiffies(TIMEOUT_MS
));
1297 ret
= qcom_swrm_register_dais(ctrl
);
1299 goto err_master_add
;
1301 dev_info(dev
, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1302 (ctrl
->version
>> 24) & 0xff, (ctrl
->version
>> 16) & 0xff,
1303 ctrl
->version
& 0xffff);
1308 sdw_bus_master_delete(&ctrl
->bus
);
1310 clk_disable_unprepare(ctrl
->hclk
);
1315 static int qcom_swrm_remove(struct platform_device
*pdev
)
1317 struct qcom_swrm_ctrl
*ctrl
= dev_get_drvdata(&pdev
->dev
);
1319 sdw_bus_master_delete(&ctrl
->bus
);
1320 clk_disable_unprepare(ctrl
->hclk
);
1325 static const struct of_device_id qcom_swrm_of_match
[] = {
1326 { .compatible
= "qcom,soundwire-v1.3.0", .data
= &swrm_v1_3_data
},
1327 { .compatible
= "qcom,soundwire-v1.5.1", .data
= &swrm_v1_5_data
},
1331 MODULE_DEVICE_TABLE(of
, qcom_swrm_of_match
);
1333 static struct platform_driver qcom_swrm_driver
= {
1334 .probe
= &qcom_swrm_probe
,
1335 .remove
= &qcom_swrm_remove
,
1337 .name
= "qcom-soundwire",
1338 .of_match_table
= qcom_swrm_of_match
,
1341 module_platform_driver(qcom_swrm_driver
);
1343 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1344 MODULE_LICENSE("GPL v2");