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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-bionic-kernel.git] / drivers / spi / omap2_mcspi.c
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/io.h>
35
36 #include <linux/spi/spi.h>
37
38 #include <plat/dma.h>
39 #include <plat/clock.h>
40
41
42 #define OMAP2_MCSPI_MAX_FREQ 48000000
43
44 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
45 #define OMAP2_MCSPI_MAX_CTRL 4
46
47 #define OMAP2_MCSPI_REVISION 0x00
48 #define OMAP2_MCSPI_SYSCONFIG 0x10
49 #define OMAP2_MCSPI_SYSSTATUS 0x14
50 #define OMAP2_MCSPI_IRQSTATUS 0x18
51 #define OMAP2_MCSPI_IRQENABLE 0x1c
52 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
53 #define OMAP2_MCSPI_SYST 0x24
54 #define OMAP2_MCSPI_MODULCTRL 0x28
55
56 /* per-channel banks, 0x14 bytes each, first is: */
57 #define OMAP2_MCSPI_CHCONF0 0x2c
58 #define OMAP2_MCSPI_CHSTAT0 0x30
59 #define OMAP2_MCSPI_CHCTRL0 0x34
60 #define OMAP2_MCSPI_TX0 0x38
61 #define OMAP2_MCSPI_RX0 0x3c
62
63 /* per-register bitmasks: */
64
65 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
66 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
67 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
68 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
69
70 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
71
72 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
73 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
74 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
75
76 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
77 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
78 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
79 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
80 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
81 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
82 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
83 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
84 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
85 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
86 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
87 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
88 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
89 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
90 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
91
92 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
93 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
94 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
95
96 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
97
98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
99
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
101 struct omap2_mcspi_dma {
102 int dma_tx_channel;
103 int dma_rx_channel;
104
105 int dma_tx_sync_dev;
106 int dma_rx_sync_dev;
107
108 struct completion dma_tx_completion;
109 struct completion dma_rx_completion;
110 };
111
112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113 * cache operations; better heuristics consider wordsize and bitrate.
114 */
115 #define DMA_MIN_BYTES 8
116
117
118 struct omap2_mcspi {
119 struct work_struct work;
120 /* lock protects queue and registers */
121 spinlock_t lock;
122 struct list_head msg_queue;
123 struct spi_master *master;
124 struct clk *ick;
125 struct clk *fck;
126 /* Virtual base address of the controller */
127 void __iomem *base;
128 unsigned long phys;
129 /* SPI1 has 4 channels, while SPI2 has 2 */
130 struct omap2_mcspi_dma *dma_channels;
131 };
132
133 struct omap2_mcspi_cs {
134 void __iomem *base;
135 unsigned long phys;
136 int word_len;
137 struct list_head node;
138 /* Context save and restore shadow register */
139 u32 chconf0;
140 };
141
142 /* used for context save and restore, structure members to be updated whenever
143 * corresponding registers are modified.
144 */
145 struct omap2_mcspi_regs {
146 u32 sysconfig;
147 u32 modulctrl;
148 u32 wakeupenable;
149 struct list_head cs;
150 };
151
152 static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
153
154 static struct workqueue_struct *omap2_mcspi_wq;
155
156 #define MOD_REG_BIT(val, mask, set) do { \
157 if (set) \
158 val |= mask; \
159 else \
160 val &= ~mask; \
161 } while (0)
162
163 static inline void mcspi_write_reg(struct spi_master *master,
164 int idx, u32 val)
165 {
166 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
167
168 __raw_writel(val, mcspi->base + idx);
169 }
170
171 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
172 {
173 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
174
175 return __raw_readl(mcspi->base + idx);
176 }
177
178 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
179 int idx, u32 val)
180 {
181 struct omap2_mcspi_cs *cs = spi->controller_state;
182
183 __raw_writel(val, cs->base + idx);
184 }
185
186 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
187 {
188 struct omap2_mcspi_cs *cs = spi->controller_state;
189
190 return __raw_readl(cs->base + idx);
191 }
192
193 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
194 {
195 struct omap2_mcspi_cs *cs = spi->controller_state;
196
197 return cs->chconf0;
198 }
199
200 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
201 {
202 struct omap2_mcspi_cs *cs = spi->controller_state;
203
204 cs->chconf0 = val;
205 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
206 }
207
208 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
209 int is_read, int enable)
210 {
211 u32 l, rw;
212
213 l = mcspi_cached_chconf0(spi);
214
215 if (is_read) /* 1 is read, 0 write */
216 rw = OMAP2_MCSPI_CHCONF_DMAR;
217 else
218 rw = OMAP2_MCSPI_CHCONF_DMAW;
219
220 MOD_REG_BIT(l, rw, enable);
221 mcspi_write_chconf0(spi, l);
222 }
223
224 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
225 {
226 u32 l;
227
228 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
229 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
230 }
231
232 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
233 {
234 u32 l;
235
236 l = mcspi_cached_chconf0(spi);
237 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
238 mcspi_write_chconf0(spi, l);
239 }
240
241 static void omap2_mcspi_set_master_mode(struct spi_master *master)
242 {
243 u32 l;
244
245 /* setup when switching from (reset default) slave mode
246 * to single-channel master mode
247 */
248 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
249 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
250 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
251 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
252 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
253
254 omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
255 }
256
257 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
258 {
259 struct spi_master *spi_cntrl;
260 struct omap2_mcspi_cs *cs;
261 spi_cntrl = mcspi->master;
262
263 /* McSPI: context restore */
264 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
265 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
266
267 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
268 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
269
270 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
271 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
272
273 list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
274 node)
275 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
276 }
277 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
278 {
279 clk_disable(mcspi->ick);
280 clk_disable(mcspi->fck);
281 }
282
283 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
284 {
285 if (clk_enable(mcspi->ick))
286 return -ENODEV;
287 if (clk_enable(mcspi->fck))
288 return -ENODEV;
289
290 omap2_mcspi_restore_ctx(mcspi);
291
292 return 0;
293 }
294
295 static unsigned
296 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
297 {
298 struct omap2_mcspi *mcspi;
299 struct omap2_mcspi_cs *cs = spi->controller_state;
300 struct omap2_mcspi_dma *mcspi_dma;
301 unsigned int count, c;
302 unsigned long base, tx_reg, rx_reg;
303 int word_len, data_type, element_count;
304 u8 * rx;
305 const u8 * tx;
306
307 mcspi = spi_master_get_devdata(spi->master);
308 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
309
310 count = xfer->len;
311 c = count;
312 word_len = cs->word_len;
313
314 base = cs->phys;
315 tx_reg = base + OMAP2_MCSPI_TX0;
316 rx_reg = base + OMAP2_MCSPI_RX0;
317 rx = xfer->rx_buf;
318 tx = xfer->tx_buf;
319
320 if (word_len <= 8) {
321 data_type = OMAP_DMA_DATA_TYPE_S8;
322 element_count = count;
323 } else if (word_len <= 16) {
324 data_type = OMAP_DMA_DATA_TYPE_S16;
325 element_count = count >> 1;
326 } else /* word_len <= 32 */ {
327 data_type = OMAP_DMA_DATA_TYPE_S32;
328 element_count = count >> 2;
329 }
330
331 if (tx != NULL) {
332 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
333 data_type, element_count, 1,
334 OMAP_DMA_SYNC_ELEMENT,
335 mcspi_dma->dma_tx_sync_dev, 0);
336
337 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
338 OMAP_DMA_AMODE_CONSTANT,
339 tx_reg, 0, 0);
340
341 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
342 OMAP_DMA_AMODE_POST_INC,
343 xfer->tx_dma, 0, 0);
344 }
345
346 if (rx != NULL) {
347 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
348 data_type, element_count - 1, 1,
349 OMAP_DMA_SYNC_ELEMENT,
350 mcspi_dma->dma_rx_sync_dev, 1);
351
352 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
353 OMAP_DMA_AMODE_CONSTANT,
354 rx_reg, 0, 0);
355
356 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
357 OMAP_DMA_AMODE_POST_INC,
358 xfer->rx_dma, 0, 0);
359 }
360
361 if (tx != NULL) {
362 omap_start_dma(mcspi_dma->dma_tx_channel);
363 omap2_mcspi_set_dma_req(spi, 0, 1);
364 }
365
366 if (rx != NULL) {
367 omap_start_dma(mcspi_dma->dma_rx_channel);
368 omap2_mcspi_set_dma_req(spi, 1, 1);
369 }
370
371 if (tx != NULL) {
372 wait_for_completion(&mcspi_dma->dma_tx_completion);
373 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
374 }
375
376 if (rx != NULL) {
377 wait_for_completion(&mcspi_dma->dma_rx_completion);
378 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
379 omap2_mcspi_set_enable(spi, 0);
380 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
381 & OMAP2_MCSPI_CHSTAT_RXS)) {
382 u32 w;
383
384 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
385 if (word_len <= 8)
386 ((u8 *)xfer->rx_buf)[element_count - 1] = w;
387 else if (word_len <= 16)
388 ((u16 *)xfer->rx_buf)[element_count - 1] = w;
389 else /* word_len <= 32 */
390 ((u32 *)xfer->rx_buf)[element_count - 1] = w;
391 } else {
392 dev_err(&spi->dev, "DMA RX last word empty");
393 count -= (word_len <= 8) ? 1 :
394 (word_len <= 16) ? 2 :
395 /* word_len <= 32 */ 4;
396 }
397 omap2_mcspi_set_enable(spi, 1);
398 }
399 return count;
400 }
401
402 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
403 {
404 unsigned long timeout;
405
406 timeout = jiffies + msecs_to_jiffies(1000);
407 while (!(__raw_readl(reg) & bit)) {
408 if (time_after(jiffies, timeout))
409 return -1;
410 cpu_relax();
411 }
412 return 0;
413 }
414
415 static unsigned
416 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
417 {
418 struct omap2_mcspi *mcspi;
419 struct omap2_mcspi_cs *cs = spi->controller_state;
420 unsigned int count, c;
421 u32 l;
422 void __iomem *base = cs->base;
423 void __iomem *tx_reg;
424 void __iomem *rx_reg;
425 void __iomem *chstat_reg;
426 int word_len;
427
428 mcspi = spi_master_get_devdata(spi->master);
429 count = xfer->len;
430 c = count;
431 word_len = cs->word_len;
432
433 l = mcspi_cached_chconf0(spi);
434 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
435
436 /* We store the pre-calculated register addresses on stack to speed
437 * up the transfer loop. */
438 tx_reg = base + OMAP2_MCSPI_TX0;
439 rx_reg = base + OMAP2_MCSPI_RX0;
440 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
441
442 if (word_len <= 8) {
443 u8 *rx;
444 const u8 *tx;
445
446 rx = xfer->rx_buf;
447 tx = xfer->tx_buf;
448
449 do {
450 c -= 1;
451 if (tx != NULL) {
452 if (mcspi_wait_for_reg_bit(chstat_reg,
453 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
454 dev_err(&spi->dev, "TXS timed out\n");
455 goto out;
456 }
457 #ifdef VERBOSE
458 dev_dbg(&spi->dev, "write-%d %02x\n",
459 word_len, *tx);
460 #endif
461 __raw_writel(*tx++, tx_reg);
462 }
463 if (rx != NULL) {
464 if (mcspi_wait_for_reg_bit(chstat_reg,
465 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
466 dev_err(&spi->dev, "RXS timed out\n");
467 goto out;
468 }
469 /* prevent last RX_ONLY read from triggering
470 * more word i/o: switch to rx+tx
471 */
472 if (c == 0 && tx == NULL)
473 mcspi_write_chconf0(spi, l);
474 *rx++ = __raw_readl(rx_reg);
475 #ifdef VERBOSE
476 dev_dbg(&spi->dev, "read-%d %02x\n",
477 word_len, *(rx - 1));
478 #endif
479 }
480 } while (c);
481 } else if (word_len <= 16) {
482 u16 *rx;
483 const u16 *tx;
484
485 rx = xfer->rx_buf;
486 tx = xfer->tx_buf;
487 do {
488 c -= 2;
489 if (tx != NULL) {
490 if (mcspi_wait_for_reg_bit(chstat_reg,
491 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
492 dev_err(&spi->dev, "TXS timed out\n");
493 goto out;
494 }
495 #ifdef VERBOSE
496 dev_dbg(&spi->dev, "write-%d %04x\n",
497 word_len, *tx);
498 #endif
499 __raw_writel(*tx++, tx_reg);
500 }
501 if (rx != NULL) {
502 if (mcspi_wait_for_reg_bit(chstat_reg,
503 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
504 dev_err(&spi->dev, "RXS timed out\n");
505 goto out;
506 }
507 /* prevent last RX_ONLY read from triggering
508 * more word i/o: switch to rx+tx
509 */
510 if (c == 0 && tx == NULL)
511 mcspi_write_chconf0(spi, l);
512 *rx++ = __raw_readl(rx_reg);
513 #ifdef VERBOSE
514 dev_dbg(&spi->dev, "read-%d %04x\n",
515 word_len, *(rx - 1));
516 #endif
517 }
518 } while (c);
519 } else if (word_len <= 32) {
520 u32 *rx;
521 const u32 *tx;
522
523 rx = xfer->rx_buf;
524 tx = xfer->tx_buf;
525 do {
526 c -= 4;
527 if (tx != NULL) {
528 if (mcspi_wait_for_reg_bit(chstat_reg,
529 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
530 dev_err(&spi->dev, "TXS timed out\n");
531 goto out;
532 }
533 #ifdef VERBOSE
534 dev_dbg(&spi->dev, "write-%d %04x\n",
535 word_len, *tx);
536 #endif
537 __raw_writel(*tx++, tx_reg);
538 }
539 if (rx != NULL) {
540 if (mcspi_wait_for_reg_bit(chstat_reg,
541 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
542 dev_err(&spi->dev, "RXS timed out\n");
543 goto out;
544 }
545 /* prevent last RX_ONLY read from triggering
546 * more word i/o: switch to rx+tx
547 */
548 if (c == 0 && tx == NULL)
549 mcspi_write_chconf0(spi, l);
550 *rx++ = __raw_readl(rx_reg);
551 #ifdef VERBOSE
552 dev_dbg(&spi->dev, "read-%d %04x\n",
553 word_len, *(rx - 1));
554 #endif
555 }
556 } while (c);
557 }
558
559 /* for TX_ONLY mode, be sure all words have shifted out */
560 if (xfer->rx_buf == NULL) {
561 if (mcspi_wait_for_reg_bit(chstat_reg,
562 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
563 dev_err(&spi->dev, "TXS timed out\n");
564 } else if (mcspi_wait_for_reg_bit(chstat_reg,
565 OMAP2_MCSPI_CHSTAT_EOT) < 0)
566 dev_err(&spi->dev, "EOT timed out\n");
567 }
568 out:
569 return count - c;
570 }
571
572 /* called only when no transfer is active to this device */
573 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
574 struct spi_transfer *t)
575 {
576 struct omap2_mcspi_cs *cs = spi->controller_state;
577 struct omap2_mcspi *mcspi;
578 struct spi_master *spi_cntrl;
579 u32 l = 0, div = 0;
580 u8 word_len = spi->bits_per_word;
581 u32 speed_hz = spi->max_speed_hz;
582
583 mcspi = spi_master_get_devdata(spi->master);
584 spi_cntrl = mcspi->master;
585
586 if (t != NULL && t->bits_per_word)
587 word_len = t->bits_per_word;
588
589 cs->word_len = word_len;
590
591 if (t && t->speed_hz)
592 speed_hz = t->speed_hz;
593
594 if (speed_hz) {
595 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
596 > speed_hz)
597 div++;
598 } else
599 div = 15;
600
601 l = mcspi_cached_chconf0(spi);
602
603 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
604 * REVISIT: this controller could support SPI_3WIRE mode.
605 */
606 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
607 l |= OMAP2_MCSPI_CHCONF_DPE0;
608
609 /* wordlength */
610 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
611 l |= (word_len - 1) << 7;
612
613 /* set chipselect polarity; manage with FORCE */
614 if (!(spi->mode & SPI_CS_HIGH))
615 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
616 else
617 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
618
619 /* set clock divisor */
620 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
621 l |= div << 2;
622
623 /* set SPI mode 0..3 */
624 if (spi->mode & SPI_CPOL)
625 l |= OMAP2_MCSPI_CHCONF_POL;
626 else
627 l &= ~OMAP2_MCSPI_CHCONF_POL;
628 if (spi->mode & SPI_CPHA)
629 l |= OMAP2_MCSPI_CHCONF_PHA;
630 else
631 l &= ~OMAP2_MCSPI_CHCONF_PHA;
632
633 mcspi_write_chconf0(spi, l);
634
635 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
636 OMAP2_MCSPI_MAX_FREQ / (1 << div),
637 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
638 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
639
640 return 0;
641 }
642
643 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
644 {
645 struct spi_device *spi = data;
646 struct omap2_mcspi *mcspi;
647 struct omap2_mcspi_dma *mcspi_dma;
648
649 mcspi = spi_master_get_devdata(spi->master);
650 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
651
652 complete(&mcspi_dma->dma_rx_completion);
653
654 /* We must disable the DMA RX request */
655 omap2_mcspi_set_dma_req(spi, 1, 0);
656 }
657
658 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
659 {
660 struct spi_device *spi = data;
661 struct omap2_mcspi *mcspi;
662 struct omap2_mcspi_dma *mcspi_dma;
663
664 mcspi = spi_master_get_devdata(spi->master);
665 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
666
667 complete(&mcspi_dma->dma_tx_completion);
668
669 /* We must disable the DMA TX request */
670 omap2_mcspi_set_dma_req(spi, 0, 0);
671 }
672
673 static int omap2_mcspi_request_dma(struct spi_device *spi)
674 {
675 struct spi_master *master = spi->master;
676 struct omap2_mcspi *mcspi;
677 struct omap2_mcspi_dma *mcspi_dma;
678
679 mcspi = spi_master_get_devdata(master);
680 mcspi_dma = mcspi->dma_channels + spi->chip_select;
681
682 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
683 omap2_mcspi_dma_rx_callback, spi,
684 &mcspi_dma->dma_rx_channel)) {
685 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
686 return -EAGAIN;
687 }
688
689 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
690 omap2_mcspi_dma_tx_callback, spi,
691 &mcspi_dma->dma_tx_channel)) {
692 omap_free_dma(mcspi_dma->dma_rx_channel);
693 mcspi_dma->dma_rx_channel = -1;
694 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
695 return -EAGAIN;
696 }
697
698 init_completion(&mcspi_dma->dma_rx_completion);
699 init_completion(&mcspi_dma->dma_tx_completion);
700
701 return 0;
702 }
703
704 static int omap2_mcspi_setup(struct spi_device *spi)
705 {
706 int ret;
707 struct omap2_mcspi *mcspi;
708 struct omap2_mcspi_dma *mcspi_dma;
709 struct omap2_mcspi_cs *cs = spi->controller_state;
710
711 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
712 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
713 spi->bits_per_word);
714 return -EINVAL;
715 }
716
717 mcspi = spi_master_get_devdata(spi->master);
718 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
719
720 if (!cs) {
721 cs = kzalloc(sizeof *cs, GFP_KERNEL);
722 if (!cs)
723 return -ENOMEM;
724 cs->base = mcspi->base + spi->chip_select * 0x14;
725 cs->phys = mcspi->phys + spi->chip_select * 0x14;
726 cs->chconf0 = 0;
727 spi->controller_state = cs;
728 /* Link this to context save list */
729 list_add_tail(&cs->node,
730 &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
731 }
732
733 if (mcspi_dma->dma_rx_channel == -1
734 || mcspi_dma->dma_tx_channel == -1) {
735 ret = omap2_mcspi_request_dma(spi);
736 if (ret < 0)
737 return ret;
738 }
739
740 if (omap2_mcspi_enable_clocks(mcspi))
741 return -ENODEV;
742
743 ret = omap2_mcspi_setup_transfer(spi, NULL);
744 omap2_mcspi_disable_clocks(mcspi);
745
746 return ret;
747 }
748
749 static void omap2_mcspi_cleanup(struct spi_device *spi)
750 {
751 struct omap2_mcspi *mcspi;
752 struct omap2_mcspi_dma *mcspi_dma;
753 struct omap2_mcspi_cs *cs;
754
755 mcspi = spi_master_get_devdata(spi->master);
756 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
757
758 if (spi->controller_state) {
759 /* Unlink controller state from context save list */
760 cs = spi->controller_state;
761 list_del(&cs->node);
762
763 kfree(spi->controller_state);
764 }
765
766 if (mcspi_dma->dma_rx_channel != -1) {
767 omap_free_dma(mcspi_dma->dma_rx_channel);
768 mcspi_dma->dma_rx_channel = -1;
769 }
770 if (mcspi_dma->dma_tx_channel != -1) {
771 omap_free_dma(mcspi_dma->dma_tx_channel);
772 mcspi_dma->dma_tx_channel = -1;
773 }
774 }
775
776 static void omap2_mcspi_work(struct work_struct *work)
777 {
778 struct omap2_mcspi *mcspi;
779
780 mcspi = container_of(work, struct omap2_mcspi, work);
781 spin_lock_irq(&mcspi->lock);
782
783 if (omap2_mcspi_enable_clocks(mcspi))
784 goto out;
785
786 /* We only enable one channel at a time -- the one whose message is
787 * at the head of the queue -- although this controller would gladly
788 * arbitrate among multiple channels. This corresponds to "single
789 * channel" master mode. As a side effect, we need to manage the
790 * chipselect with the FORCE bit ... CS != channel enable.
791 */
792 while (!list_empty(&mcspi->msg_queue)) {
793 struct spi_message *m;
794 struct spi_device *spi;
795 struct spi_transfer *t = NULL;
796 int cs_active = 0;
797 struct omap2_mcspi_cs *cs;
798 int par_override = 0;
799 int status = 0;
800 u32 chconf;
801
802 m = container_of(mcspi->msg_queue.next, struct spi_message,
803 queue);
804
805 list_del_init(&m->queue);
806 spin_unlock_irq(&mcspi->lock);
807
808 spi = m->spi;
809 cs = spi->controller_state;
810
811 omap2_mcspi_set_enable(spi, 1);
812 list_for_each_entry(t, &m->transfers, transfer_list) {
813 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
814 status = -EINVAL;
815 break;
816 }
817 if (par_override || t->speed_hz || t->bits_per_word) {
818 par_override = 1;
819 status = omap2_mcspi_setup_transfer(spi, t);
820 if (status < 0)
821 break;
822 if (!t->speed_hz && !t->bits_per_word)
823 par_override = 0;
824 }
825
826 if (!cs_active) {
827 omap2_mcspi_force_cs(spi, 1);
828 cs_active = 1;
829 }
830
831 chconf = mcspi_cached_chconf0(spi);
832 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
833 if (t->tx_buf == NULL)
834 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
835 else if (t->rx_buf == NULL)
836 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
837 mcspi_write_chconf0(spi, chconf);
838
839 if (t->len) {
840 unsigned count;
841
842 /* RX_ONLY mode needs dummy data in TX reg */
843 if (t->tx_buf == NULL)
844 __raw_writel(0, cs->base
845 + OMAP2_MCSPI_TX0);
846
847 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
848 count = omap2_mcspi_txrx_dma(spi, t);
849 else
850 count = omap2_mcspi_txrx_pio(spi, t);
851 m->actual_length += count;
852
853 if (count != t->len) {
854 status = -EIO;
855 break;
856 }
857 }
858
859 if (t->delay_usecs)
860 udelay(t->delay_usecs);
861
862 /* ignore the "leave it on after last xfer" hint */
863 if (t->cs_change) {
864 omap2_mcspi_force_cs(spi, 0);
865 cs_active = 0;
866 }
867 }
868
869 /* Restore defaults if they were overriden */
870 if (par_override) {
871 par_override = 0;
872 status = omap2_mcspi_setup_transfer(spi, NULL);
873 }
874
875 if (cs_active)
876 omap2_mcspi_force_cs(spi, 0);
877
878 omap2_mcspi_set_enable(spi, 0);
879
880 m->status = status;
881 m->complete(m->context);
882
883 spin_lock_irq(&mcspi->lock);
884 }
885
886 omap2_mcspi_disable_clocks(mcspi);
887
888 out:
889 spin_unlock_irq(&mcspi->lock);
890 }
891
892 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
893 {
894 struct omap2_mcspi *mcspi;
895 unsigned long flags;
896 struct spi_transfer *t;
897
898 m->actual_length = 0;
899 m->status = 0;
900
901 /* reject invalid messages and transfers */
902 if (list_empty(&m->transfers) || !m->complete)
903 return -EINVAL;
904 list_for_each_entry(t, &m->transfers, transfer_list) {
905 const void *tx_buf = t->tx_buf;
906 void *rx_buf = t->rx_buf;
907 unsigned len = t->len;
908
909 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
910 || (len && !(rx_buf || tx_buf))
911 || (t->bits_per_word &&
912 ( t->bits_per_word < 4
913 || t->bits_per_word > 32))) {
914 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
915 t->speed_hz,
916 len,
917 tx_buf ? "tx" : "",
918 rx_buf ? "rx" : "",
919 t->bits_per_word);
920 return -EINVAL;
921 }
922 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
923 dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
924 t->speed_hz,
925 OMAP2_MCSPI_MAX_FREQ/(1<<16));
926 return -EINVAL;
927 }
928
929 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
930 continue;
931
932 /* Do DMA mapping "early" for better error reporting and
933 * dcache use. Note that if dma_unmap_single() ever starts
934 * to do real work on ARM, we'd need to clean up mappings
935 * for previous transfers on *ALL* exits of this loop...
936 */
937 if (tx_buf != NULL) {
938 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
939 len, DMA_TO_DEVICE);
940 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
941 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
942 'T', len);
943 return -EINVAL;
944 }
945 }
946 if (rx_buf != NULL) {
947 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
948 DMA_FROM_DEVICE);
949 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
950 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
951 'R', len);
952 if (tx_buf != NULL)
953 dma_unmap_single(NULL, t->tx_dma,
954 len, DMA_TO_DEVICE);
955 return -EINVAL;
956 }
957 }
958 }
959
960 mcspi = spi_master_get_devdata(spi->master);
961
962 spin_lock_irqsave(&mcspi->lock, flags);
963 list_add_tail(&m->queue, &mcspi->msg_queue);
964 queue_work(omap2_mcspi_wq, &mcspi->work);
965 spin_unlock_irqrestore(&mcspi->lock, flags);
966
967 return 0;
968 }
969
970 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
971 {
972 struct spi_master *master = mcspi->master;
973 u32 tmp;
974
975 if (omap2_mcspi_enable_clocks(mcspi))
976 return -1;
977
978 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
979 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
980 do {
981 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
982 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
983
984 tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
985 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
986 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
987 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
988 omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
989
990 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
991 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
992 omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
993
994 omap2_mcspi_set_master_mode(master);
995 omap2_mcspi_disable_clocks(mcspi);
996 return 0;
997 }
998
999 static u8 __initdata spi1_rxdma_id [] = {
1000 OMAP24XX_DMA_SPI1_RX0,
1001 OMAP24XX_DMA_SPI1_RX1,
1002 OMAP24XX_DMA_SPI1_RX2,
1003 OMAP24XX_DMA_SPI1_RX3,
1004 };
1005
1006 static u8 __initdata spi1_txdma_id [] = {
1007 OMAP24XX_DMA_SPI1_TX0,
1008 OMAP24XX_DMA_SPI1_TX1,
1009 OMAP24XX_DMA_SPI1_TX2,
1010 OMAP24XX_DMA_SPI1_TX3,
1011 };
1012
1013 static u8 __initdata spi2_rxdma_id[] = {
1014 OMAP24XX_DMA_SPI2_RX0,
1015 OMAP24XX_DMA_SPI2_RX1,
1016 };
1017
1018 static u8 __initdata spi2_txdma_id[] = {
1019 OMAP24XX_DMA_SPI2_TX0,
1020 OMAP24XX_DMA_SPI2_TX1,
1021 };
1022
1023 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1024 || defined(CONFIG_ARCH_OMAP4)
1025 static u8 __initdata spi3_rxdma_id[] = {
1026 OMAP24XX_DMA_SPI3_RX0,
1027 OMAP24XX_DMA_SPI3_RX1,
1028 };
1029
1030 static u8 __initdata spi3_txdma_id[] = {
1031 OMAP24XX_DMA_SPI3_TX0,
1032 OMAP24XX_DMA_SPI3_TX1,
1033 };
1034 #endif
1035
1036 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1037 static u8 __initdata spi4_rxdma_id[] = {
1038 OMAP34XX_DMA_SPI4_RX0,
1039 };
1040
1041 static u8 __initdata spi4_txdma_id[] = {
1042 OMAP34XX_DMA_SPI4_TX0,
1043 };
1044 #endif
1045
1046 static int __init omap2_mcspi_probe(struct platform_device *pdev)
1047 {
1048 struct spi_master *master;
1049 struct omap2_mcspi *mcspi;
1050 struct resource *r;
1051 int status = 0, i;
1052 const u8 *rxdma_id, *txdma_id;
1053 unsigned num_chipselect;
1054
1055 switch (pdev->id) {
1056 case 1:
1057 rxdma_id = spi1_rxdma_id;
1058 txdma_id = spi1_txdma_id;
1059 num_chipselect = 4;
1060 break;
1061 case 2:
1062 rxdma_id = spi2_rxdma_id;
1063 txdma_id = spi2_txdma_id;
1064 num_chipselect = 2;
1065 break;
1066 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1067 || defined(CONFIG_ARCH_OMAP4)
1068 case 3:
1069 rxdma_id = spi3_rxdma_id;
1070 txdma_id = spi3_txdma_id;
1071 num_chipselect = 2;
1072 break;
1073 #endif
1074 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1075 case 4:
1076 rxdma_id = spi4_rxdma_id;
1077 txdma_id = spi4_txdma_id;
1078 num_chipselect = 1;
1079 break;
1080 #endif
1081 default:
1082 return -EINVAL;
1083 }
1084
1085 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1086 if (master == NULL) {
1087 dev_dbg(&pdev->dev, "master allocation failed\n");
1088 return -ENOMEM;
1089 }
1090
1091 /* the spi->mode bits understood by this driver: */
1092 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1093
1094 if (pdev->id != -1)
1095 master->bus_num = pdev->id;
1096
1097 master->setup = omap2_mcspi_setup;
1098 master->transfer = omap2_mcspi_transfer;
1099 master->cleanup = omap2_mcspi_cleanup;
1100 master->num_chipselect = num_chipselect;
1101
1102 dev_set_drvdata(&pdev->dev, master);
1103
1104 mcspi = spi_master_get_devdata(master);
1105 mcspi->master = master;
1106
1107 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108 if (r == NULL) {
1109 status = -ENODEV;
1110 goto err1;
1111 }
1112 if (!request_mem_region(r->start, (r->end - r->start) + 1,
1113 dev_name(&pdev->dev))) {
1114 status = -EBUSY;
1115 goto err1;
1116 }
1117
1118 mcspi->phys = r->start;
1119 mcspi->base = ioremap(r->start, r->end - r->start + 1);
1120 if (!mcspi->base) {
1121 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1122 status = -ENOMEM;
1123 goto err1aa;
1124 }
1125
1126 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1127
1128 spin_lock_init(&mcspi->lock);
1129 INIT_LIST_HEAD(&mcspi->msg_queue);
1130 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1131
1132 mcspi->ick = clk_get(&pdev->dev, "ick");
1133 if (IS_ERR(mcspi->ick)) {
1134 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1135 status = PTR_ERR(mcspi->ick);
1136 goto err1a;
1137 }
1138 mcspi->fck = clk_get(&pdev->dev, "fck");
1139 if (IS_ERR(mcspi->fck)) {
1140 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1141 status = PTR_ERR(mcspi->fck);
1142 goto err2;
1143 }
1144
1145 mcspi->dma_channels = kcalloc(master->num_chipselect,
1146 sizeof(struct omap2_mcspi_dma),
1147 GFP_KERNEL);
1148
1149 if (mcspi->dma_channels == NULL)
1150 goto err3;
1151
1152 for (i = 0; i < num_chipselect; i++) {
1153 mcspi->dma_channels[i].dma_rx_channel = -1;
1154 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1155 mcspi->dma_channels[i].dma_tx_channel = -1;
1156 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1157 }
1158
1159 if (omap2_mcspi_reset(mcspi) < 0)
1160 goto err4;
1161
1162 status = spi_register_master(master);
1163 if (status < 0)
1164 goto err4;
1165
1166 return status;
1167
1168 err4:
1169 kfree(mcspi->dma_channels);
1170 err3:
1171 clk_put(mcspi->fck);
1172 err2:
1173 clk_put(mcspi->ick);
1174 err1a:
1175 iounmap(mcspi->base);
1176 err1aa:
1177 release_mem_region(r->start, (r->end - r->start) + 1);
1178 err1:
1179 spi_master_put(master);
1180 return status;
1181 }
1182
1183 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1184 {
1185 struct spi_master *master;
1186 struct omap2_mcspi *mcspi;
1187 struct omap2_mcspi_dma *dma_channels;
1188 struct resource *r;
1189 void __iomem *base;
1190
1191 master = dev_get_drvdata(&pdev->dev);
1192 mcspi = spi_master_get_devdata(master);
1193 dma_channels = mcspi->dma_channels;
1194
1195 clk_put(mcspi->fck);
1196 clk_put(mcspi->ick);
1197
1198 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1199 release_mem_region(r->start, (r->end - r->start) + 1);
1200
1201 base = mcspi->base;
1202 spi_unregister_master(master);
1203 iounmap(base);
1204 kfree(dma_channels);
1205
1206 return 0;
1207 }
1208
1209 /* work with hotplug and coldplug */
1210 MODULE_ALIAS("platform:omap2_mcspi");
1211
1212 static struct platform_driver omap2_mcspi_driver = {
1213 .driver = {
1214 .name = "omap2_mcspi",
1215 .owner = THIS_MODULE,
1216 },
1217 .remove = __exit_p(omap2_mcspi_remove),
1218 };
1219
1220
1221 static int __init omap2_mcspi_init(void)
1222 {
1223 omap2_mcspi_wq = create_singlethread_workqueue(
1224 omap2_mcspi_driver.driver.name);
1225 if (omap2_mcspi_wq == NULL)
1226 return -1;
1227 return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1228 }
1229 subsys_initcall(omap2_mcspi_init);
1230
1231 static void __exit omap2_mcspi_exit(void)
1232 {
1233 platform_driver_unregister(&omap2_mcspi_driver);
1234
1235 destroy_workqueue(omap2_mcspi_wq);
1236 }
1237 module_exit(omap2_mcspi_exit);
1238
1239 MODULE_LICENSE("GPL");
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