]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/spi/pxa2xx_spi.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
spi/pxa2xx: Add chipselect support for Sodaville
[mirror_ubuntu-bionic-kernel.git] / drivers / spi / pxa2xx_spi.c
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/spi/pxa2xx_spi.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/gpio.h>
32 #include <linux/slab.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/delay.h>
37
38
39 MODULE_AUTHOR("Stephen Street");
40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
41 MODULE_LICENSE("GPL");
42 MODULE_ALIAS("platform:pxa2xx-spi");
43
44 #define MAX_BUSES 3
45
46 #define TIMOUT_DFLT 1000
47
48 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
49 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
50 #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
51 #define MAX_DMA_LEN 8191
52 #define DMA_ALIGNMENT 8
53
54 /*
55 * for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables, the pxa270 developer
57 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
58 * list, but the PXA255 dev man says all bits without really meaning the
59 * service and interrupt enables
60 */
61 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
62 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
63 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
65 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
67
68 #define DEFINE_SSP_REG(reg, off) \
69 static inline u32 read_##reg(void const __iomem *p) \
70 { return __raw_readl(p + (off)); } \
71 \
72 static inline void write_##reg(u32 v, void __iomem *p) \
73 { __raw_writel(v, p + (off)); }
74
75 DEFINE_SSP_REG(SSCR0, 0x00)
76 DEFINE_SSP_REG(SSCR1, 0x04)
77 DEFINE_SSP_REG(SSSR, 0x08)
78 DEFINE_SSP_REG(SSITR, 0x0c)
79 DEFINE_SSP_REG(SSDR, 0x10)
80 DEFINE_SSP_REG(SSTO, 0x28)
81 DEFINE_SSP_REG(SSPSP, 0x2c)
82
83 #define START_STATE ((void*)0)
84 #define RUNNING_STATE ((void*)1)
85 #define DONE_STATE ((void*)2)
86 #define ERROR_STATE ((void*)-1)
87
88 #define QUEUE_RUNNING 0
89 #define QUEUE_STOPPED 1
90
91 struct driver_data {
92 /* Driver model hookup */
93 struct platform_device *pdev;
94
95 /* SSP Info */
96 struct ssp_device *ssp;
97
98 /* SPI framework hookup */
99 enum pxa_ssp_type ssp_type;
100 struct spi_master *master;
101
102 /* PXA hookup */
103 struct pxa2xx_spi_master *master_info;
104
105 /* DMA setup stuff */
106 int rx_channel;
107 int tx_channel;
108 u32 *null_dma_buf;
109
110 /* SSP register addresses */
111 void __iomem *ioaddr;
112 u32 ssdr_physical;
113
114 /* SSP masks*/
115 u32 dma_cr1;
116 u32 int_cr1;
117 u32 clear_sr;
118 u32 mask_sr;
119
120 /* Driver message queue */
121 struct workqueue_struct *workqueue;
122 struct work_struct pump_messages;
123 spinlock_t lock;
124 struct list_head queue;
125 int busy;
126 int run;
127
128 /* Message Transfer pump */
129 struct tasklet_struct pump_transfers;
130
131 /* Current message transfer state info */
132 struct spi_message* cur_msg;
133 struct spi_transfer* cur_transfer;
134 struct chip_data *cur_chip;
135 size_t len;
136 void *tx;
137 void *tx_end;
138 void *rx;
139 void *rx_end;
140 int dma_mapped;
141 dma_addr_t rx_dma;
142 dma_addr_t tx_dma;
143 size_t rx_map_len;
144 size_t tx_map_len;
145 u8 n_bytes;
146 u32 dma_width;
147 int (*write)(struct driver_data *drv_data);
148 int (*read)(struct driver_data *drv_data);
149 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
150 void (*cs_control)(u32 command);
151 };
152
153 struct chip_data {
154 u32 cr0;
155 u32 cr1;
156 u32 psp;
157 u32 timeout;
158 u8 n_bytes;
159 u32 dma_width;
160 u32 dma_burst_size;
161 u32 threshold;
162 u32 dma_threshold;
163 u8 enable_dma;
164 u8 bits_per_word;
165 u32 speed_hz;
166 union {
167 int gpio_cs;
168 unsigned int frm;
169 };
170 int gpio_cs_inverted;
171 int (*write)(struct driver_data *drv_data);
172 int (*read)(struct driver_data *drv_data);
173 void (*cs_control)(u32 command);
174 };
175
176 static void pump_messages(struct work_struct *work);
177
178 static void cs_assert(struct driver_data *drv_data)
179 {
180 struct chip_data *chip = drv_data->cur_chip;
181
182 if (drv_data->ssp_type == CE4100_SSP) {
183 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
184 return;
185 }
186
187 if (chip->cs_control) {
188 chip->cs_control(PXA2XX_CS_ASSERT);
189 return;
190 }
191
192 if (gpio_is_valid(chip->gpio_cs))
193 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
194 }
195
196 static void cs_deassert(struct driver_data *drv_data)
197 {
198 struct chip_data *chip = drv_data->cur_chip;
199
200 if (drv_data->ssp_type == CE4100_SSP)
201 return;
202
203 if (chip->cs_control) {
204 chip->cs_control(PXA2XX_CS_DEASSERT);
205 return;
206 }
207
208 if (gpio_is_valid(chip->gpio_cs))
209 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
210 }
211
212 static void write_SSSR_CS(struct driver_data *drv_data, u32 val)
213 {
214 void __iomem *reg = drv_data->ioaddr;
215
216 if (drv_data->ssp_type == CE4100_SSP)
217 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
218
219 write_SSSR(val, reg);
220 }
221
222 static int pxa25x_ssp_comp(struct driver_data *drv_data)
223 {
224 if (drv_data->ssp_type == PXA25x_SSP)
225 return 1;
226 if (drv_data->ssp_type == CE4100_SSP)
227 return 1;
228 return 0;
229 }
230
231 static int flush(struct driver_data *drv_data)
232 {
233 unsigned long limit = loops_per_jiffy << 1;
234
235 void __iomem *reg = drv_data->ioaddr;
236
237 do {
238 while (read_SSSR(reg) & SSSR_RNE) {
239 read_SSDR(reg);
240 }
241 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
242 write_SSSR_CS(drv_data, SSSR_ROR);
243
244 return limit;
245 }
246
247 static int null_writer(struct driver_data *drv_data)
248 {
249 void __iomem *reg = drv_data->ioaddr;
250 u8 n_bytes = drv_data->n_bytes;
251
252 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
253 || (drv_data->tx == drv_data->tx_end))
254 return 0;
255
256 write_SSDR(0, reg);
257 drv_data->tx += n_bytes;
258
259 return 1;
260 }
261
262 static int null_reader(struct driver_data *drv_data)
263 {
264 void __iomem *reg = drv_data->ioaddr;
265 u8 n_bytes = drv_data->n_bytes;
266
267 while ((read_SSSR(reg) & SSSR_RNE)
268 && (drv_data->rx < drv_data->rx_end)) {
269 read_SSDR(reg);
270 drv_data->rx += n_bytes;
271 }
272
273 return drv_data->rx == drv_data->rx_end;
274 }
275
276 static int u8_writer(struct driver_data *drv_data)
277 {
278 void __iomem *reg = drv_data->ioaddr;
279
280 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
281 || (drv_data->tx == drv_data->tx_end))
282 return 0;
283
284 write_SSDR(*(u8 *)(drv_data->tx), reg);
285 ++drv_data->tx;
286
287 return 1;
288 }
289
290 static int u8_reader(struct driver_data *drv_data)
291 {
292 void __iomem *reg = drv_data->ioaddr;
293
294 while ((read_SSSR(reg) & SSSR_RNE)
295 && (drv_data->rx < drv_data->rx_end)) {
296 *(u8 *)(drv_data->rx) = read_SSDR(reg);
297 ++drv_data->rx;
298 }
299
300 return drv_data->rx == drv_data->rx_end;
301 }
302
303 static int u16_writer(struct driver_data *drv_data)
304 {
305 void __iomem *reg = drv_data->ioaddr;
306
307 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
308 || (drv_data->tx == drv_data->tx_end))
309 return 0;
310
311 write_SSDR(*(u16 *)(drv_data->tx), reg);
312 drv_data->tx += 2;
313
314 return 1;
315 }
316
317 static int u16_reader(struct driver_data *drv_data)
318 {
319 void __iomem *reg = drv_data->ioaddr;
320
321 while ((read_SSSR(reg) & SSSR_RNE)
322 && (drv_data->rx < drv_data->rx_end)) {
323 *(u16 *)(drv_data->rx) = read_SSDR(reg);
324 drv_data->rx += 2;
325 }
326
327 return drv_data->rx == drv_data->rx_end;
328 }
329
330 static int u32_writer(struct driver_data *drv_data)
331 {
332 void __iomem *reg = drv_data->ioaddr;
333
334 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
335 || (drv_data->tx == drv_data->tx_end))
336 return 0;
337
338 write_SSDR(*(u32 *)(drv_data->tx), reg);
339 drv_data->tx += 4;
340
341 return 1;
342 }
343
344 static int u32_reader(struct driver_data *drv_data)
345 {
346 void __iomem *reg = drv_data->ioaddr;
347
348 while ((read_SSSR(reg) & SSSR_RNE)
349 && (drv_data->rx < drv_data->rx_end)) {
350 *(u32 *)(drv_data->rx) = read_SSDR(reg);
351 drv_data->rx += 4;
352 }
353
354 return drv_data->rx == drv_data->rx_end;
355 }
356
357 static void *next_transfer(struct driver_data *drv_data)
358 {
359 struct spi_message *msg = drv_data->cur_msg;
360 struct spi_transfer *trans = drv_data->cur_transfer;
361
362 /* Move to next transfer */
363 if (trans->transfer_list.next != &msg->transfers) {
364 drv_data->cur_transfer =
365 list_entry(trans->transfer_list.next,
366 struct spi_transfer,
367 transfer_list);
368 return RUNNING_STATE;
369 } else
370 return DONE_STATE;
371 }
372
373 static int map_dma_buffers(struct driver_data *drv_data)
374 {
375 struct spi_message *msg = drv_data->cur_msg;
376 struct device *dev = &msg->spi->dev;
377
378 if (!drv_data->cur_chip->enable_dma)
379 return 0;
380
381 if (msg->is_dma_mapped)
382 return drv_data->rx_dma && drv_data->tx_dma;
383
384 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
385 return 0;
386
387 /* Modify setup if rx buffer is null */
388 if (drv_data->rx == NULL) {
389 *drv_data->null_dma_buf = 0;
390 drv_data->rx = drv_data->null_dma_buf;
391 drv_data->rx_map_len = 4;
392 } else
393 drv_data->rx_map_len = drv_data->len;
394
395
396 /* Modify setup if tx buffer is null */
397 if (drv_data->tx == NULL) {
398 *drv_data->null_dma_buf = 0;
399 drv_data->tx = drv_data->null_dma_buf;
400 drv_data->tx_map_len = 4;
401 } else
402 drv_data->tx_map_len = drv_data->len;
403
404 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
405 * so we flush the cache *before* invalidating it, in case
406 * the tx and rx buffers overlap.
407 */
408 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
409 drv_data->tx_map_len, DMA_TO_DEVICE);
410 if (dma_mapping_error(dev, drv_data->tx_dma))
411 return 0;
412
413 /* Stream map the rx buffer */
414 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
415 drv_data->rx_map_len, DMA_FROM_DEVICE);
416 if (dma_mapping_error(dev, drv_data->rx_dma)) {
417 dma_unmap_single(dev, drv_data->tx_dma,
418 drv_data->tx_map_len, DMA_TO_DEVICE);
419 return 0;
420 }
421
422 return 1;
423 }
424
425 static void unmap_dma_buffers(struct driver_data *drv_data)
426 {
427 struct device *dev;
428
429 if (!drv_data->dma_mapped)
430 return;
431
432 if (!drv_data->cur_msg->is_dma_mapped) {
433 dev = &drv_data->cur_msg->spi->dev;
434 dma_unmap_single(dev, drv_data->rx_dma,
435 drv_data->rx_map_len, DMA_FROM_DEVICE);
436 dma_unmap_single(dev, drv_data->tx_dma,
437 drv_data->tx_map_len, DMA_TO_DEVICE);
438 }
439
440 drv_data->dma_mapped = 0;
441 }
442
443 /* caller already set message->status; dma and pio irqs are blocked */
444 static void giveback(struct driver_data *drv_data)
445 {
446 struct spi_transfer* last_transfer;
447 unsigned long flags;
448 struct spi_message *msg;
449
450 spin_lock_irqsave(&drv_data->lock, flags);
451 msg = drv_data->cur_msg;
452 drv_data->cur_msg = NULL;
453 drv_data->cur_transfer = NULL;
454 queue_work(drv_data->workqueue, &drv_data->pump_messages);
455 spin_unlock_irqrestore(&drv_data->lock, flags);
456
457 last_transfer = list_entry(msg->transfers.prev,
458 struct spi_transfer,
459 transfer_list);
460
461 /* Delay if requested before any change in chip select */
462 if (last_transfer->delay_usecs)
463 udelay(last_transfer->delay_usecs);
464
465 /* Drop chip select UNLESS cs_change is true or we are returning
466 * a message with an error, or next message is for another chip
467 */
468 if (!last_transfer->cs_change)
469 cs_deassert(drv_data);
470 else {
471 struct spi_message *next_msg;
472
473 /* Holding of cs was hinted, but we need to make sure
474 * the next message is for the same chip. Don't waste
475 * time with the following tests unless this was hinted.
476 *
477 * We cannot postpone this until pump_messages, because
478 * after calling msg->complete (below) the driver that
479 * sent the current message could be unloaded, which
480 * could invalidate the cs_control() callback...
481 */
482
483 /* get a pointer to the next message, if any */
484 spin_lock_irqsave(&drv_data->lock, flags);
485 if (list_empty(&drv_data->queue))
486 next_msg = NULL;
487 else
488 next_msg = list_entry(drv_data->queue.next,
489 struct spi_message, queue);
490 spin_unlock_irqrestore(&drv_data->lock, flags);
491
492 /* see if the next and current messages point
493 * to the same chip
494 */
495 if (next_msg && next_msg->spi != msg->spi)
496 next_msg = NULL;
497 if (!next_msg || msg->state == ERROR_STATE)
498 cs_deassert(drv_data);
499 }
500
501 msg->state = NULL;
502 if (msg->complete)
503 msg->complete(msg->context);
504
505 drv_data->cur_chip = NULL;
506 }
507
508 static int wait_ssp_rx_stall(void const __iomem *ioaddr)
509 {
510 unsigned long limit = loops_per_jiffy << 1;
511
512 while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
513 cpu_relax();
514
515 return limit;
516 }
517
518 static int wait_dma_channel_stop(int channel)
519 {
520 unsigned long limit = loops_per_jiffy << 1;
521
522 while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
523 cpu_relax();
524
525 return limit;
526 }
527
528 static void dma_error_stop(struct driver_data *drv_data, const char *msg)
529 {
530 void __iomem *reg = drv_data->ioaddr;
531
532 /* Stop and reset */
533 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
534 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
535 write_SSSR_CS(drv_data, drv_data->clear_sr);
536 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
537 if (!pxa25x_ssp_comp(drv_data))
538 write_SSTO(0, reg);
539 flush(drv_data);
540 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
541
542 unmap_dma_buffers(drv_data);
543
544 dev_err(&drv_data->pdev->dev, "%s\n", msg);
545
546 drv_data->cur_msg->state = ERROR_STATE;
547 tasklet_schedule(&drv_data->pump_transfers);
548 }
549
550 static void dma_transfer_complete(struct driver_data *drv_data)
551 {
552 void __iomem *reg = drv_data->ioaddr;
553 struct spi_message *msg = drv_data->cur_msg;
554
555 /* Clear and disable interrupts on SSP and DMA channels*/
556 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
557 write_SSSR_CS(drv_data, drv_data->clear_sr);
558 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
559 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
560
561 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
562 dev_err(&drv_data->pdev->dev,
563 "dma_handler: dma rx channel stop failed\n");
564
565 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
566 dev_err(&drv_data->pdev->dev,
567 "dma_transfer: ssp rx stall failed\n");
568
569 unmap_dma_buffers(drv_data);
570
571 /* update the buffer pointer for the amount completed in dma */
572 drv_data->rx += drv_data->len -
573 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
574
575 /* read trailing data from fifo, it does not matter how many
576 * bytes are in the fifo just read until buffer is full
577 * or fifo is empty, which ever occurs first */
578 drv_data->read(drv_data);
579
580 /* return count of what was actually read */
581 msg->actual_length += drv_data->len -
582 (drv_data->rx_end - drv_data->rx);
583
584 /* Transfer delays and chip select release are
585 * handled in pump_transfers or giveback
586 */
587
588 /* Move to next transfer */
589 msg->state = next_transfer(drv_data);
590
591 /* Schedule transfer tasklet */
592 tasklet_schedule(&drv_data->pump_transfers);
593 }
594
595 static void dma_handler(int channel, void *data)
596 {
597 struct driver_data *drv_data = data;
598 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
599
600 if (irq_status & DCSR_BUSERR) {
601
602 if (channel == drv_data->tx_channel)
603 dma_error_stop(drv_data,
604 "dma_handler: "
605 "bad bus address on tx channel");
606 else
607 dma_error_stop(drv_data,
608 "dma_handler: "
609 "bad bus address on rx channel");
610 return;
611 }
612
613 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
614 if ((channel == drv_data->tx_channel)
615 && (irq_status & DCSR_ENDINTR)
616 && (drv_data->ssp_type == PXA25x_SSP)) {
617
618 /* Wait for rx to stall */
619 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
620 dev_err(&drv_data->pdev->dev,
621 "dma_handler: ssp rx stall failed\n");
622
623 /* finish this transfer, start the next */
624 dma_transfer_complete(drv_data);
625 }
626 }
627
628 static irqreturn_t dma_transfer(struct driver_data *drv_data)
629 {
630 u32 irq_status;
631 void __iomem *reg = drv_data->ioaddr;
632
633 irq_status = read_SSSR(reg) & drv_data->mask_sr;
634 if (irq_status & SSSR_ROR) {
635 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
636 return IRQ_HANDLED;
637 }
638
639 /* Check for false positive timeout */
640 if ((irq_status & SSSR_TINT)
641 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
642 write_SSSR(SSSR_TINT, reg);
643 return IRQ_HANDLED;
644 }
645
646 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
647
648 /* Clear and disable timeout interrupt, do the rest in
649 * dma_transfer_complete */
650 if (!pxa25x_ssp_comp(drv_data))
651 write_SSTO(0, reg);
652
653 /* finish this transfer, start the next */
654 dma_transfer_complete(drv_data);
655
656 return IRQ_HANDLED;
657 }
658
659 /* Opps problem detected */
660 return IRQ_NONE;
661 }
662
663 static void int_error_stop(struct driver_data *drv_data, const char* msg)
664 {
665 void __iomem *reg = drv_data->ioaddr;
666
667 /* Stop and reset SSP */
668 write_SSSR_CS(drv_data, drv_data->clear_sr);
669 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
670 if (!pxa25x_ssp_comp(drv_data))
671 write_SSTO(0, reg);
672 flush(drv_data);
673 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
674
675 dev_err(&drv_data->pdev->dev, "%s\n", msg);
676
677 drv_data->cur_msg->state = ERROR_STATE;
678 tasklet_schedule(&drv_data->pump_transfers);
679 }
680
681 static void int_transfer_complete(struct driver_data *drv_data)
682 {
683 void __iomem *reg = drv_data->ioaddr;
684
685 /* Stop SSP */
686 write_SSSR_CS(drv_data, drv_data->clear_sr);
687 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
688 if (!pxa25x_ssp_comp(drv_data))
689 write_SSTO(0, reg);
690
691 /* Update total byte transfered return count actual bytes read */
692 drv_data->cur_msg->actual_length += drv_data->len -
693 (drv_data->rx_end - drv_data->rx);
694
695 /* Transfer delays and chip select release are
696 * handled in pump_transfers or giveback
697 */
698
699 /* Move to next transfer */
700 drv_data->cur_msg->state = next_transfer(drv_data);
701
702 /* Schedule transfer tasklet */
703 tasklet_schedule(&drv_data->pump_transfers);
704 }
705
706 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
707 {
708 void __iomem *reg = drv_data->ioaddr;
709
710 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
711 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
712
713 u32 irq_status = read_SSSR(reg) & irq_mask;
714
715 if (irq_status & SSSR_ROR) {
716 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
717 return IRQ_HANDLED;
718 }
719
720 if (irq_status & SSSR_TINT) {
721 write_SSSR(SSSR_TINT, reg);
722 if (drv_data->read(drv_data)) {
723 int_transfer_complete(drv_data);
724 return IRQ_HANDLED;
725 }
726 }
727
728 /* Drain rx fifo, Fill tx fifo and prevent overruns */
729 do {
730 if (drv_data->read(drv_data)) {
731 int_transfer_complete(drv_data);
732 return IRQ_HANDLED;
733 }
734 } while (drv_data->write(drv_data));
735
736 if (drv_data->read(drv_data)) {
737 int_transfer_complete(drv_data);
738 return IRQ_HANDLED;
739 }
740
741 if (drv_data->tx == drv_data->tx_end) {
742 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
743 /* PXA25x_SSP has no timeout, read trailing bytes */
744 if (pxa25x_ssp_comp(drv_data)) {
745 if (!wait_ssp_rx_stall(reg))
746 {
747 int_error_stop(drv_data, "interrupt_transfer: "
748 "rx stall failed");
749 return IRQ_HANDLED;
750 }
751 if (!drv_data->read(drv_data))
752 {
753 int_error_stop(drv_data,
754 "interrupt_transfer: "
755 "trailing byte read failed");
756 return IRQ_HANDLED;
757 }
758 int_transfer_complete(drv_data);
759 }
760 }
761
762 /* We did something */
763 return IRQ_HANDLED;
764 }
765
766 static irqreturn_t ssp_int(int irq, void *dev_id)
767 {
768 struct driver_data *drv_data = dev_id;
769 void __iomem *reg = drv_data->ioaddr;
770 u32 sccr1_reg = read_SSCR1(reg);
771 u32 mask = drv_data->mask_sr;
772 u32 status;
773
774 status = read_SSSR(reg);
775
776 /* Ignore possible writes if we don't need to write */
777 if (!(sccr1_reg & SSCR1_TIE))
778 mask &= ~SSSR_TFS;
779
780 if (!(status & mask))
781 return IRQ_NONE;
782
783 if (!drv_data->cur_msg) {
784
785 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
786 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
787 if (!pxa25x_ssp_comp(drv_data))
788 write_SSTO(0, reg);
789 write_SSSR_CS(drv_data, drv_data->clear_sr);
790
791 dev_err(&drv_data->pdev->dev, "bad message state "
792 "in interrupt handler\n");
793
794 /* Never fail */
795 return IRQ_HANDLED;
796 }
797
798 return drv_data->transfer_handler(drv_data);
799 }
800
801 static int set_dma_burst_and_threshold(struct chip_data *chip,
802 struct spi_device *spi,
803 u8 bits_per_word, u32 *burst_code,
804 u32 *threshold)
805 {
806 struct pxa2xx_spi_chip *chip_info =
807 (struct pxa2xx_spi_chip *)spi->controller_data;
808 int bytes_per_word;
809 int burst_bytes;
810 int thresh_words;
811 int req_burst_size;
812 int retval = 0;
813
814 /* Set the threshold (in registers) to equal the same amount of data
815 * as represented by burst size (in bytes). The computation below
816 * is (burst_size rounded up to nearest 8 byte, word or long word)
817 * divided by (bytes/register); the tx threshold is the inverse of
818 * the rx, so that there will always be enough data in the rx fifo
819 * to satisfy a burst, and there will always be enough space in the
820 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
821 * there is not enough space), there must always remain enough empty
822 * space in the rx fifo for any data loaded to the tx fifo.
823 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
824 * will be 8, or half the fifo;
825 * The threshold can only be set to 2, 4 or 8, but not 16, because
826 * to burst 16 to the tx fifo, the fifo would have to be empty;
827 * however, the minimum fifo trigger level is 1, and the tx will
828 * request service when the fifo is at this level, with only 15 spaces.
829 */
830
831 /* find bytes/word */
832 if (bits_per_word <= 8)
833 bytes_per_word = 1;
834 else if (bits_per_word <= 16)
835 bytes_per_word = 2;
836 else
837 bytes_per_word = 4;
838
839 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
840 if (chip_info)
841 req_burst_size = chip_info->dma_burst_size;
842 else {
843 switch (chip->dma_burst_size) {
844 default:
845 /* if the default burst size is not set,
846 * do it now */
847 chip->dma_burst_size = DCMD_BURST8;
848 case DCMD_BURST8:
849 req_burst_size = 8;
850 break;
851 case DCMD_BURST16:
852 req_burst_size = 16;
853 break;
854 case DCMD_BURST32:
855 req_burst_size = 32;
856 break;
857 }
858 }
859 if (req_burst_size <= 8) {
860 *burst_code = DCMD_BURST8;
861 burst_bytes = 8;
862 } else if (req_burst_size <= 16) {
863 if (bytes_per_word == 1) {
864 /* don't burst more than 1/2 the fifo */
865 *burst_code = DCMD_BURST8;
866 burst_bytes = 8;
867 retval = 1;
868 } else {
869 *burst_code = DCMD_BURST16;
870 burst_bytes = 16;
871 }
872 } else {
873 if (bytes_per_word == 1) {
874 /* don't burst more than 1/2 the fifo */
875 *burst_code = DCMD_BURST8;
876 burst_bytes = 8;
877 retval = 1;
878 } else if (bytes_per_word == 2) {
879 /* don't burst more than 1/2 the fifo */
880 *burst_code = DCMD_BURST16;
881 burst_bytes = 16;
882 retval = 1;
883 } else {
884 *burst_code = DCMD_BURST32;
885 burst_bytes = 32;
886 }
887 }
888
889 thresh_words = burst_bytes / bytes_per_word;
890
891 /* thresh_words will be between 2 and 8 */
892 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
893 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
894
895 return retval;
896 }
897
898 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
899 {
900 unsigned long ssp_clk = clk_get_rate(ssp->clk);
901
902 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
903 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
904 else
905 return ((ssp_clk / rate - 1) & 0xfff) << 8;
906 }
907
908 static void pump_transfers(unsigned long data)
909 {
910 struct driver_data *drv_data = (struct driver_data *)data;
911 struct spi_message *message = NULL;
912 struct spi_transfer *transfer = NULL;
913 struct spi_transfer *previous = NULL;
914 struct chip_data *chip = NULL;
915 struct ssp_device *ssp = drv_data->ssp;
916 void __iomem *reg = drv_data->ioaddr;
917 u32 clk_div = 0;
918 u8 bits = 0;
919 u32 speed = 0;
920 u32 cr0;
921 u32 cr1;
922 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
923 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
924
925 /* Get current state information */
926 message = drv_data->cur_msg;
927 transfer = drv_data->cur_transfer;
928 chip = drv_data->cur_chip;
929
930 /* Handle for abort */
931 if (message->state == ERROR_STATE) {
932 message->status = -EIO;
933 giveback(drv_data);
934 return;
935 }
936
937 /* Handle end of message */
938 if (message->state == DONE_STATE) {
939 message->status = 0;
940 giveback(drv_data);
941 return;
942 }
943
944 /* Delay if requested at end of transfer before CS change */
945 if (message->state == RUNNING_STATE) {
946 previous = list_entry(transfer->transfer_list.prev,
947 struct spi_transfer,
948 transfer_list);
949 if (previous->delay_usecs)
950 udelay(previous->delay_usecs);
951
952 /* Drop chip select only if cs_change is requested */
953 if (previous->cs_change)
954 cs_deassert(drv_data);
955 }
956
957 /* Check for transfers that need multiple DMA segments */
958 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
959
960 /* reject already-mapped transfers; PIO won't always work */
961 if (message->is_dma_mapped
962 || transfer->rx_dma || transfer->tx_dma) {
963 dev_err(&drv_data->pdev->dev,
964 "pump_transfers: mapped transfer length "
965 "of %u is greater than %d\n",
966 transfer->len, MAX_DMA_LEN);
967 message->status = -EINVAL;
968 giveback(drv_data);
969 return;
970 }
971
972 /* warn ... we force this to PIO mode */
973 if (printk_ratelimit())
974 dev_warn(&message->spi->dev, "pump_transfers: "
975 "DMA disabled for transfer length %ld "
976 "greater than %d\n",
977 (long)drv_data->len, MAX_DMA_LEN);
978 }
979
980 /* Setup the transfer state based on the type of transfer */
981 if (flush(drv_data) == 0) {
982 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
983 message->status = -EIO;
984 giveback(drv_data);
985 return;
986 }
987 drv_data->n_bytes = chip->n_bytes;
988 drv_data->dma_width = chip->dma_width;
989 drv_data->tx = (void *)transfer->tx_buf;
990 drv_data->tx_end = drv_data->tx + transfer->len;
991 drv_data->rx = transfer->rx_buf;
992 drv_data->rx_end = drv_data->rx + transfer->len;
993 drv_data->rx_dma = transfer->rx_dma;
994 drv_data->tx_dma = transfer->tx_dma;
995 drv_data->len = transfer->len & DCMD_LENGTH;
996 drv_data->write = drv_data->tx ? chip->write : null_writer;
997 drv_data->read = drv_data->rx ? chip->read : null_reader;
998
999 /* Change speed and bit per word on a per transfer */
1000 cr0 = chip->cr0;
1001 if (transfer->speed_hz || transfer->bits_per_word) {
1002
1003 bits = chip->bits_per_word;
1004 speed = chip->speed_hz;
1005
1006 if (transfer->speed_hz)
1007 speed = transfer->speed_hz;
1008
1009 if (transfer->bits_per_word)
1010 bits = transfer->bits_per_word;
1011
1012 clk_div = ssp_get_clk_div(ssp, speed);
1013
1014 if (bits <= 8) {
1015 drv_data->n_bytes = 1;
1016 drv_data->dma_width = DCMD_WIDTH1;
1017 drv_data->read = drv_data->read != null_reader ?
1018 u8_reader : null_reader;
1019 drv_data->write = drv_data->write != null_writer ?
1020 u8_writer : null_writer;
1021 } else if (bits <= 16) {
1022 drv_data->n_bytes = 2;
1023 drv_data->dma_width = DCMD_WIDTH2;
1024 drv_data->read = drv_data->read != null_reader ?
1025 u16_reader : null_reader;
1026 drv_data->write = drv_data->write != null_writer ?
1027 u16_writer : null_writer;
1028 } else if (bits <= 32) {
1029 drv_data->n_bytes = 4;
1030 drv_data->dma_width = DCMD_WIDTH4;
1031 drv_data->read = drv_data->read != null_reader ?
1032 u32_reader : null_reader;
1033 drv_data->write = drv_data->write != null_writer ?
1034 u32_writer : null_writer;
1035 }
1036 /* if bits/word is changed in dma mode, then must check the
1037 * thresholds and burst also */
1038 if (chip->enable_dma) {
1039 if (set_dma_burst_and_threshold(chip, message->spi,
1040 bits, &dma_burst,
1041 &dma_thresh))
1042 if (printk_ratelimit())
1043 dev_warn(&message->spi->dev,
1044 "pump_transfers: "
1045 "DMA burst size reduced to "
1046 "match bits_per_word\n");
1047 }
1048
1049 cr0 = clk_div
1050 | SSCR0_Motorola
1051 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
1052 | SSCR0_SSE
1053 | (bits > 16 ? SSCR0_EDSS : 0);
1054 }
1055
1056 message->state = RUNNING_STATE;
1057
1058 /* Try to map dma buffer and do a dma transfer if successful, but
1059 * only if the length is non-zero and less than MAX_DMA_LEN.
1060 *
1061 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1062 * of PIO instead. Care is needed above because the transfer may
1063 * have have been passed with buffers that are already dma mapped.
1064 * A zero-length transfer in PIO mode will not try to write/read
1065 * to/from the buffers
1066 *
1067 * REVISIT large transfers are exactly where we most want to be
1068 * using DMA. If this happens much, split those transfers into
1069 * multiple DMA segments rather than forcing PIO.
1070 */
1071 drv_data->dma_mapped = 0;
1072 if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1073 drv_data->dma_mapped = map_dma_buffers(drv_data);
1074 if (drv_data->dma_mapped) {
1075
1076 /* Ensure we have the correct interrupt handler */
1077 drv_data->transfer_handler = dma_transfer;
1078
1079 /* Setup rx DMA Channel */
1080 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
1081 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
1082 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
1083 if (drv_data->rx == drv_data->null_dma_buf)
1084 /* No target address increment */
1085 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
1086 | drv_data->dma_width
1087 | dma_burst
1088 | drv_data->len;
1089 else
1090 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
1091 | DCMD_FLOWSRC
1092 | drv_data->dma_width
1093 | dma_burst
1094 | drv_data->len;
1095
1096 /* Setup tx DMA Channel */
1097 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1098 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1099 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1100 if (drv_data->tx == drv_data->null_dma_buf)
1101 /* No source address increment */
1102 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1103 | drv_data->dma_width
1104 | dma_burst
1105 | drv_data->len;
1106 else
1107 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1108 | DCMD_FLOWTRG
1109 | drv_data->dma_width
1110 | dma_burst
1111 | drv_data->len;
1112
1113 /* Enable dma end irqs on SSP to detect end of transfer */
1114 if (drv_data->ssp_type == PXA25x_SSP)
1115 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1116
1117 /* Clear status and start DMA engine */
1118 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1119 write_SSSR(drv_data->clear_sr, reg);
1120 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1121 DCSR(drv_data->tx_channel) |= DCSR_RUN;
1122 } else {
1123 /* Ensure we have the correct interrupt handler */
1124 drv_data->transfer_handler = interrupt_transfer;
1125
1126 /* Clear status */
1127 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1128 write_SSSR_CS(drv_data, drv_data->clear_sr);
1129 }
1130
1131 /* see if we need to reload the config registers */
1132 if ((read_SSCR0(reg) != cr0)
1133 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1134 (cr1 & SSCR1_CHANGE_MASK)) {
1135
1136 /* stop the SSP, and update the other bits */
1137 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1138 if (!pxa25x_ssp_comp(drv_data))
1139 write_SSTO(chip->timeout, reg);
1140 /* first set CR1 without interrupt and service enables */
1141 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1142 /* restart the SSP */
1143 write_SSCR0(cr0, reg);
1144
1145 } else {
1146 if (!pxa25x_ssp_comp(drv_data))
1147 write_SSTO(chip->timeout, reg);
1148 }
1149
1150 cs_assert(drv_data);
1151
1152 /* after chip select, release the data by enabling service
1153 * requests and interrupts, without changing any mode bits */
1154 write_SSCR1(cr1, reg);
1155 }
1156
1157 static void pump_messages(struct work_struct *work)
1158 {
1159 struct driver_data *drv_data =
1160 container_of(work, struct driver_data, pump_messages);
1161 unsigned long flags;
1162
1163 /* Lock queue and check for queue work */
1164 spin_lock_irqsave(&drv_data->lock, flags);
1165 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1166 drv_data->busy = 0;
1167 spin_unlock_irqrestore(&drv_data->lock, flags);
1168 return;
1169 }
1170
1171 /* Make sure we are not already running a message */
1172 if (drv_data->cur_msg) {
1173 spin_unlock_irqrestore(&drv_data->lock, flags);
1174 return;
1175 }
1176
1177 /* Extract head of queue */
1178 drv_data->cur_msg = list_entry(drv_data->queue.next,
1179 struct spi_message, queue);
1180 list_del_init(&drv_data->cur_msg->queue);
1181
1182 /* Initial message state*/
1183 drv_data->cur_msg->state = START_STATE;
1184 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1185 struct spi_transfer,
1186 transfer_list);
1187
1188 /* prepare to setup the SSP, in pump_transfers, using the per
1189 * chip configuration */
1190 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1191
1192 /* Mark as busy and launch transfers */
1193 tasklet_schedule(&drv_data->pump_transfers);
1194
1195 drv_data->busy = 1;
1196 spin_unlock_irqrestore(&drv_data->lock, flags);
1197 }
1198
1199 static int transfer(struct spi_device *spi, struct spi_message *msg)
1200 {
1201 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1202 unsigned long flags;
1203
1204 spin_lock_irqsave(&drv_data->lock, flags);
1205
1206 if (drv_data->run == QUEUE_STOPPED) {
1207 spin_unlock_irqrestore(&drv_data->lock, flags);
1208 return -ESHUTDOWN;
1209 }
1210
1211 msg->actual_length = 0;
1212 msg->status = -EINPROGRESS;
1213 msg->state = START_STATE;
1214
1215 list_add_tail(&msg->queue, &drv_data->queue);
1216
1217 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1218 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1219
1220 spin_unlock_irqrestore(&drv_data->lock, flags);
1221
1222 return 0;
1223 }
1224
1225 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1226 struct pxa2xx_spi_chip *chip_info)
1227 {
1228 int err = 0;
1229
1230 if (chip == NULL || chip_info == NULL)
1231 return 0;
1232
1233 /* NOTE: setup() can be called multiple times, possibly with
1234 * different chip_info, release previously requested GPIO
1235 */
1236 if (gpio_is_valid(chip->gpio_cs))
1237 gpio_free(chip->gpio_cs);
1238
1239 /* If (*cs_control) is provided, ignore GPIO chip select */
1240 if (chip_info->cs_control) {
1241 chip->cs_control = chip_info->cs_control;
1242 return 0;
1243 }
1244
1245 if (gpio_is_valid(chip_info->gpio_cs)) {
1246 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1247 if (err) {
1248 dev_err(&spi->dev, "failed to request chip select "
1249 "GPIO%d\n", chip_info->gpio_cs);
1250 return err;
1251 }
1252
1253 chip->gpio_cs = chip_info->gpio_cs;
1254 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1255
1256 err = gpio_direction_output(chip->gpio_cs,
1257 !chip->gpio_cs_inverted);
1258 }
1259
1260 return err;
1261 }
1262
1263 static int setup(struct spi_device *spi)
1264 {
1265 struct pxa2xx_spi_chip *chip_info = NULL;
1266 struct chip_data *chip;
1267 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1268 struct ssp_device *ssp = drv_data->ssp;
1269 unsigned int clk_div;
1270 uint tx_thres = TX_THRESH_DFLT;
1271 uint rx_thres = RX_THRESH_DFLT;
1272
1273 if (!pxa25x_ssp_comp(drv_data)
1274 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1275 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1276 "b/w not 4-32 for type non-PXA25x_SSP\n",
1277 drv_data->ssp_type, spi->bits_per_word);
1278 return -EINVAL;
1279 } else if (pxa25x_ssp_comp(drv_data)
1280 && (spi->bits_per_word < 4
1281 || spi->bits_per_word > 16)) {
1282 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1283 "b/w not 4-16 for type PXA25x_SSP\n",
1284 drv_data->ssp_type, spi->bits_per_word);
1285 return -EINVAL;
1286 }
1287
1288 /* Only alloc on first setup */
1289 chip = spi_get_ctldata(spi);
1290 if (!chip) {
1291 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1292 if (!chip) {
1293 dev_err(&spi->dev,
1294 "failed setup: can't allocate chip data\n");
1295 return -ENOMEM;
1296 }
1297
1298 if (drv_data->ssp_type == CE4100_SSP) {
1299 if (spi->chip_select > 4) {
1300 dev_err(&spi->dev, "failed setup: "
1301 "cs number must not be > 4.\n");
1302 kfree(chip);
1303 return -EINVAL;
1304 }
1305
1306 chip->frm = spi->chip_select;
1307 } else
1308 chip->gpio_cs = -1;
1309 chip->enable_dma = 0;
1310 chip->timeout = TIMOUT_DFLT;
1311 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1312 DCMD_BURST8 : 0;
1313 }
1314
1315 /* protocol drivers may change the chip settings, so...
1316 * if chip_info exists, use it */
1317 chip_info = spi->controller_data;
1318
1319 /* chip_info isn't always needed */
1320 chip->cr1 = 0;
1321 if (chip_info) {
1322 if (chip_info->timeout)
1323 chip->timeout = chip_info->timeout;
1324 if (chip_info->tx_threshold)
1325 tx_thres = chip_info->tx_threshold;
1326 if (chip_info->rx_threshold)
1327 rx_thres = chip_info->rx_threshold;
1328 chip->enable_dma = drv_data->master_info->enable_dma;
1329 chip->dma_threshold = 0;
1330 if (chip_info->enable_loopback)
1331 chip->cr1 = SSCR1_LBM;
1332 }
1333
1334 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1335 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1336
1337 /* set dma burst and threshold outside of chip_info path so that if
1338 * chip_info goes away after setting chip->enable_dma, the
1339 * burst and threshold can still respond to changes in bits_per_word */
1340 if (chip->enable_dma) {
1341 /* set up legal burst and threshold for dma */
1342 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1343 &chip->dma_burst_size,
1344 &chip->dma_threshold)) {
1345 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1346 "to match bits_per_word\n");
1347 }
1348 }
1349
1350 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1351 chip->speed_hz = spi->max_speed_hz;
1352
1353 chip->cr0 = clk_div
1354 | SSCR0_Motorola
1355 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1356 spi->bits_per_word - 16 : spi->bits_per_word)
1357 | SSCR0_SSE
1358 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1359 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1360 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1361 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1362
1363 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1364 if (!pxa25x_ssp_comp(drv_data))
1365 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1366 clk_get_rate(ssp->clk)
1367 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1368 chip->enable_dma ? "DMA" : "PIO");
1369 else
1370 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1371 clk_get_rate(ssp->clk) / 2
1372 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1373 chip->enable_dma ? "DMA" : "PIO");
1374
1375 if (spi->bits_per_word <= 8) {
1376 chip->n_bytes = 1;
1377 chip->dma_width = DCMD_WIDTH1;
1378 chip->read = u8_reader;
1379 chip->write = u8_writer;
1380 } else if (spi->bits_per_word <= 16) {
1381 chip->n_bytes = 2;
1382 chip->dma_width = DCMD_WIDTH2;
1383 chip->read = u16_reader;
1384 chip->write = u16_writer;
1385 } else if (spi->bits_per_word <= 32) {
1386 chip->cr0 |= SSCR0_EDSS;
1387 chip->n_bytes = 4;
1388 chip->dma_width = DCMD_WIDTH4;
1389 chip->read = u32_reader;
1390 chip->write = u32_writer;
1391 } else {
1392 dev_err(&spi->dev, "invalid wordsize\n");
1393 return -ENODEV;
1394 }
1395 chip->bits_per_word = spi->bits_per_word;
1396
1397 spi_set_ctldata(spi, chip);
1398
1399 if (drv_data->ssp_type == CE4100_SSP)
1400 return 0;
1401
1402 return setup_cs(spi, chip, chip_info);
1403 }
1404
1405 static void cleanup(struct spi_device *spi)
1406 {
1407 struct chip_data *chip = spi_get_ctldata(spi);
1408 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1409
1410 if (!chip)
1411 return;
1412
1413 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1414 gpio_free(chip->gpio_cs);
1415
1416 kfree(chip);
1417 }
1418
1419 static int __devinit init_queue(struct driver_data *drv_data)
1420 {
1421 INIT_LIST_HEAD(&drv_data->queue);
1422 spin_lock_init(&drv_data->lock);
1423
1424 drv_data->run = QUEUE_STOPPED;
1425 drv_data->busy = 0;
1426
1427 tasklet_init(&drv_data->pump_transfers,
1428 pump_transfers, (unsigned long)drv_data);
1429
1430 INIT_WORK(&drv_data->pump_messages, pump_messages);
1431 drv_data->workqueue = create_singlethread_workqueue(
1432 dev_name(drv_data->master->dev.parent));
1433 if (drv_data->workqueue == NULL)
1434 return -EBUSY;
1435
1436 return 0;
1437 }
1438
1439 static int start_queue(struct driver_data *drv_data)
1440 {
1441 unsigned long flags;
1442
1443 spin_lock_irqsave(&drv_data->lock, flags);
1444
1445 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1446 spin_unlock_irqrestore(&drv_data->lock, flags);
1447 return -EBUSY;
1448 }
1449
1450 drv_data->run = QUEUE_RUNNING;
1451 drv_data->cur_msg = NULL;
1452 drv_data->cur_transfer = NULL;
1453 drv_data->cur_chip = NULL;
1454 spin_unlock_irqrestore(&drv_data->lock, flags);
1455
1456 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1457
1458 return 0;
1459 }
1460
1461 static int stop_queue(struct driver_data *drv_data)
1462 {
1463 unsigned long flags;
1464 unsigned limit = 500;
1465 int status = 0;
1466
1467 spin_lock_irqsave(&drv_data->lock, flags);
1468
1469 /* This is a bit lame, but is optimized for the common execution path.
1470 * A wait_queue on the drv_data->busy could be used, but then the common
1471 * execution path (pump_messages) would be required to call wake_up or
1472 * friends on every SPI message. Do this instead */
1473 drv_data->run = QUEUE_STOPPED;
1474 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1475 spin_unlock_irqrestore(&drv_data->lock, flags);
1476 msleep(10);
1477 spin_lock_irqsave(&drv_data->lock, flags);
1478 }
1479
1480 if (!list_empty(&drv_data->queue) || drv_data->busy)
1481 status = -EBUSY;
1482
1483 spin_unlock_irqrestore(&drv_data->lock, flags);
1484
1485 return status;
1486 }
1487
1488 static int destroy_queue(struct driver_data *drv_data)
1489 {
1490 int status;
1491
1492 status = stop_queue(drv_data);
1493 /* we are unloading the module or failing to load (only two calls
1494 * to this routine), and neither call can handle a return value.
1495 * However, destroy_workqueue calls flush_workqueue, and that will
1496 * block until all work is done. If the reason that stop_queue
1497 * timed out is that the work will never finish, then it does no
1498 * good to call destroy_workqueue, so return anyway. */
1499 if (status != 0)
1500 return status;
1501
1502 destroy_workqueue(drv_data->workqueue);
1503
1504 return 0;
1505 }
1506
1507 static int __devinit pxa2xx_spi_probe(struct platform_device *pdev)
1508 {
1509 struct device *dev = &pdev->dev;
1510 struct pxa2xx_spi_master *platform_info;
1511 struct spi_master *master;
1512 struct driver_data *drv_data;
1513 struct ssp_device *ssp;
1514 int status;
1515
1516 platform_info = dev->platform_data;
1517
1518 ssp = pxa_ssp_request(pdev->id, pdev->name);
1519 if (ssp == NULL) {
1520 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1521 return -ENODEV;
1522 }
1523
1524 /* Allocate master with space for drv_data and null dma buffer */
1525 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1526 if (!master) {
1527 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1528 pxa_ssp_free(ssp);
1529 return -ENOMEM;
1530 }
1531 drv_data = spi_master_get_devdata(master);
1532 drv_data->master = master;
1533 drv_data->master_info = platform_info;
1534 drv_data->pdev = pdev;
1535 drv_data->ssp = ssp;
1536
1537 /* the spi->mode bits understood by this driver: */
1538 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1539
1540 master->bus_num = pdev->id;
1541 master->num_chipselect = platform_info->num_chipselect;
1542 master->dma_alignment = DMA_ALIGNMENT;
1543 master->cleanup = cleanup;
1544 master->setup = setup;
1545 master->transfer = transfer;
1546
1547 drv_data->ssp_type = ssp->type;
1548 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1549 sizeof(struct driver_data)), 8);
1550
1551 drv_data->ioaddr = ssp->mmio_base;
1552 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1553 if (pxa25x_ssp_comp(drv_data)) {
1554 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1555 drv_data->dma_cr1 = 0;
1556 drv_data->clear_sr = SSSR_ROR;
1557 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1558 } else {
1559 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1560 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1561 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1562 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1563 }
1564
1565 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1566 drv_data);
1567 if (status < 0) {
1568 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1569 goto out_error_master_alloc;
1570 }
1571
1572 /* Setup DMA if requested */
1573 drv_data->tx_channel = -1;
1574 drv_data->rx_channel = -1;
1575 if (platform_info->enable_dma) {
1576
1577 /* Get two DMA channels (rx and tx) */
1578 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1579 DMA_PRIO_HIGH,
1580 dma_handler,
1581 drv_data);
1582 if (drv_data->rx_channel < 0) {
1583 dev_err(dev, "problem (%d) requesting rx channel\n",
1584 drv_data->rx_channel);
1585 status = -ENODEV;
1586 goto out_error_irq_alloc;
1587 }
1588 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1589 DMA_PRIO_MEDIUM,
1590 dma_handler,
1591 drv_data);
1592 if (drv_data->tx_channel < 0) {
1593 dev_err(dev, "problem (%d) requesting tx channel\n",
1594 drv_data->tx_channel);
1595 status = -ENODEV;
1596 goto out_error_dma_alloc;
1597 }
1598
1599 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1600 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1601 }
1602
1603 /* Enable SOC clock */
1604 clk_enable(ssp->clk);
1605
1606 /* Load default SSP configuration */
1607 write_SSCR0(0, drv_data->ioaddr);
1608 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1609 SSCR1_TxTresh(TX_THRESH_DFLT),
1610 drv_data->ioaddr);
1611 write_SSCR0(SSCR0_SCR(2)
1612 | SSCR0_Motorola
1613 | SSCR0_DataSize(8),
1614 drv_data->ioaddr);
1615 if (!pxa25x_ssp_comp(drv_data))
1616 write_SSTO(0, drv_data->ioaddr);
1617 write_SSPSP(0, drv_data->ioaddr);
1618
1619 /* Initial and start queue */
1620 status = init_queue(drv_data);
1621 if (status != 0) {
1622 dev_err(&pdev->dev, "problem initializing queue\n");
1623 goto out_error_clock_enabled;
1624 }
1625 status = start_queue(drv_data);
1626 if (status != 0) {
1627 dev_err(&pdev->dev, "problem starting queue\n");
1628 goto out_error_clock_enabled;
1629 }
1630
1631 /* Register with the SPI framework */
1632 platform_set_drvdata(pdev, drv_data);
1633 status = spi_register_master(master);
1634 if (status != 0) {
1635 dev_err(&pdev->dev, "problem registering spi master\n");
1636 goto out_error_queue_alloc;
1637 }
1638
1639 return status;
1640
1641 out_error_queue_alloc:
1642 destroy_queue(drv_data);
1643
1644 out_error_clock_enabled:
1645 clk_disable(ssp->clk);
1646
1647 out_error_dma_alloc:
1648 if (drv_data->tx_channel != -1)
1649 pxa_free_dma(drv_data->tx_channel);
1650 if (drv_data->rx_channel != -1)
1651 pxa_free_dma(drv_data->rx_channel);
1652
1653 out_error_irq_alloc:
1654 free_irq(ssp->irq, drv_data);
1655
1656 out_error_master_alloc:
1657 spi_master_put(master);
1658 pxa_ssp_free(ssp);
1659 return status;
1660 }
1661
1662 static int pxa2xx_spi_remove(struct platform_device *pdev)
1663 {
1664 struct driver_data *drv_data = platform_get_drvdata(pdev);
1665 struct ssp_device *ssp;
1666 int status = 0;
1667
1668 if (!drv_data)
1669 return 0;
1670 ssp = drv_data->ssp;
1671
1672 /* Remove the queue */
1673 status = destroy_queue(drv_data);
1674 if (status != 0)
1675 /* the kernel does not check the return status of this
1676 * this routine (mod->exit, within the kernel). Therefore
1677 * nothing is gained by returning from here, the module is
1678 * going away regardless, and we should not leave any more
1679 * resources allocated than necessary. We cannot free the
1680 * message memory in drv_data->queue, but we can release the
1681 * resources below. I think the kernel should honor -EBUSY
1682 * returns but... */
1683 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1684 "complete, message memory not freed\n");
1685
1686 /* Disable the SSP at the peripheral and SOC level */
1687 write_SSCR0(0, drv_data->ioaddr);
1688 clk_disable(ssp->clk);
1689
1690 /* Release DMA */
1691 if (drv_data->master_info->enable_dma) {
1692 DRCMR(ssp->drcmr_rx) = 0;
1693 DRCMR(ssp->drcmr_tx) = 0;
1694 pxa_free_dma(drv_data->tx_channel);
1695 pxa_free_dma(drv_data->rx_channel);
1696 }
1697
1698 /* Release IRQ */
1699 free_irq(ssp->irq, drv_data);
1700
1701 /* Release SSP */
1702 pxa_ssp_free(ssp);
1703
1704 /* Disconnect from the SPI framework */
1705 spi_unregister_master(drv_data->master);
1706
1707 /* Prevent double remove */
1708 platform_set_drvdata(pdev, NULL);
1709
1710 return 0;
1711 }
1712
1713 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1714 {
1715 int status = 0;
1716
1717 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1718 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1719 }
1720
1721 #ifdef CONFIG_PM
1722 static int pxa2xx_spi_suspend(struct device *dev)
1723 {
1724 struct driver_data *drv_data = dev_get_drvdata(dev);
1725 struct ssp_device *ssp = drv_data->ssp;
1726 int status = 0;
1727
1728 status = stop_queue(drv_data);
1729 if (status != 0)
1730 return status;
1731 write_SSCR0(0, drv_data->ioaddr);
1732 clk_disable(ssp->clk);
1733
1734 return 0;
1735 }
1736
1737 static int pxa2xx_spi_resume(struct device *dev)
1738 {
1739 struct driver_data *drv_data = dev_get_drvdata(dev);
1740 struct ssp_device *ssp = drv_data->ssp;
1741 int status = 0;
1742
1743 if (drv_data->rx_channel != -1)
1744 DRCMR(drv_data->ssp->drcmr_rx) =
1745 DRCMR_MAPVLD | drv_data->rx_channel;
1746 if (drv_data->tx_channel != -1)
1747 DRCMR(drv_data->ssp->drcmr_tx) =
1748 DRCMR_MAPVLD | drv_data->tx_channel;
1749
1750 /* Enable the SSP clock */
1751 clk_enable(ssp->clk);
1752
1753 /* Start the queue running */
1754 status = start_queue(drv_data);
1755 if (status != 0) {
1756 dev_err(dev, "problem starting queue (%d)\n", status);
1757 return status;
1758 }
1759
1760 return 0;
1761 }
1762
1763 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1764 .suspend = pxa2xx_spi_suspend,
1765 .resume = pxa2xx_spi_resume,
1766 };
1767 #endif
1768
1769 static struct platform_driver driver = {
1770 .driver = {
1771 .name = "pxa2xx-spi",
1772 .owner = THIS_MODULE,
1773 #ifdef CONFIG_PM
1774 .pm = &pxa2xx_spi_pm_ops,
1775 #endif
1776 },
1777 .probe = pxa2xx_spi_probe,
1778 .remove = pxa2xx_spi_remove,
1779 .shutdown = pxa2xx_spi_shutdown,
1780 };
1781
1782 static int __init pxa2xx_spi_init(void)
1783 {
1784 return platform_driver_register(&driver);
1785 }
1786 subsys_initcall(pxa2xx_spi_init);
1787
1788 static void __exit pxa2xx_spi_exit(void)
1789 {
1790 platform_driver_unregister(&driver);
1791 }
1792 module_exit(pxa2xx_spi_exit);
ubuntu-bionic-kernel mirror