drivers/spi/spi-ath79.c

   1 /*
   2  * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
   3  *
   4  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This driver has been based on the spi-gpio.c:
   7  *      Copyright (C) 2006,2008 David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/delay.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/io.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spi/spi_bitbang.h>
  23 #include <linux/bitops.h>
  24 #include <linux/gpio.h>
  25 #include <linux/clk.h>
  26 #include <linux/err.h>
  27
  28 #include <asm/mach-ath79/ar71xx_regs.h>
  29 #include <asm/mach-ath79/ath79_spi_platform.h>
  30
  31 #define DRV_NAME        "ath79-spi"
  32
  33 #define ATH79_SPI_RRW_DELAY_FACTOR      12000
  34 #define MHZ                             (1000 * 1000)
  35
  36 struct ath79_spi {
  37         struct spi_bitbang      bitbang;
  38         u32                     ioc_base;
  39         u32                     reg_ctrl;
  40         void __iomem            *base;
  41         struct clk              *clk;
  42         unsigned                rrw_delay;
  43 };
  44
  45 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
  46 {
  47         return ioread32(sp->base + reg);
  48 }
  49
  50 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
  51 {
  52         iowrite32(val, sp->base + reg);
  53 }
  54
  55 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
  56 {
  57         return spi_master_get_devdata(spi->master);
  58 }
  59
  60 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
  61 {
  62         if (nsecs > sp->rrw_delay)
  63                 ndelay(nsecs - sp->rrw_delay);
  64 }
  65
  66 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
  67 {
  68         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  69         int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
  70
  71         if (is_active) {
  72                 /* set initial clock polarity */
  73                 if (spi->mode & SPI_CPOL)
  74                         sp->ioc_base |= AR71XX_SPI_IOC_CLK;
  75                 else
  76                         sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
  77
  78                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  79         }
  80
  81         if (gpio_is_valid(spi->cs_gpio)) {
  82                 /* SPI is normally active-low */
  83                 gpio_set_value_cansleep(spi->cs_gpio, cs_high);
  84         } else {
  85                 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
  86
  87                 if (cs_high)
  88                         sp->ioc_base |= cs_bit;
  89                 else
  90                         sp->ioc_base &= ~cs_bit;
  91
  92                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  93         }
  94
  95 }
  96
  97 static void ath79_spi_enable(struct ath79_spi *sp)
  98 {
  99         /* enable GPIO mode */
 100         ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
 101
 102         /* save CTRL register */
 103         sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
 104         sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
 105
 106         /* TODO: setup speed? */
 107         ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
 108 }
 109
 110 static void ath79_spi_disable(struct ath79_spi *sp)
 111 {
 112         /* restore CTRL register */
 113         ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
 114         /* disable GPIO mode */
 115         ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
 116 }
 117
 118 static int ath79_spi_setup_cs(struct spi_device *spi)
 119 {
 120         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
 121         int status;
 122
 123         status = 0;
 124         if (gpio_is_valid(spi->cs_gpio)) {
 125                 unsigned long flags;
 126
 127                 flags = GPIOF_DIR_OUT;
 128                 if (spi->mode & SPI_CS_HIGH)
 129                         flags |= GPIOF_INIT_LOW;
 130                 else
 131                         flags |= GPIOF_INIT_HIGH;
 132
 133                 status = gpio_request_one(spi->cs_gpio, flags,
 134                                           dev_name(&spi->dev));
 135         } else {
 136                 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
 137
 138                 if (spi->mode & SPI_CS_HIGH)
 139                         sp->ioc_base &= ~cs_bit;
 140                 else
 141                         sp->ioc_base |= cs_bit;
 142
 143                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
 144         }
 145
 146         return status;
 147 }
 148
 149 static void ath79_spi_cleanup_cs(struct spi_device *spi)
 150 {
 151         if (gpio_is_valid(spi->cs_gpio)) {
 152                 gpio_free(spi->cs_gpio);
 153         }
 154 }
 155
 156 static int ath79_spi_setup(struct spi_device *spi)
 157 {
 158         int status = 0;
 159
 160         if (!spi->controller_state) {
 161                 status = ath79_spi_setup_cs(spi);
 162                 if (status)
 163                         return status;
 164         }
 165
 166         status = spi_bitbang_setup(spi);
 167         if (status && !spi->controller_state)
 168                 ath79_spi_cleanup_cs(spi);
 169
 170         return status;
 171 }
 172
 173 static void ath79_spi_cleanup(struct spi_device *spi)
 174 {
 175         ath79_spi_cleanup_cs(spi);
 176         spi_bitbang_cleanup(spi);
 177 }
 178
 179 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
 180                                u32 word, u8 bits)
 181 {
 182         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
 183         u32 ioc = sp->ioc_base;
 184
 185         /* clock starts at inactive polarity */
 186         for (word <<= (32 - bits); likely(bits); bits--) {
 187                 u32 out;
 188
 189                 if (word & (1 << 31))
 190                         out = ioc | AR71XX_SPI_IOC_DO;
 191                 else
 192                         out = ioc & ~AR71XX_SPI_IOC_DO;
 193
 194                 /* setup MSB (to slave) on trailing edge */
 195                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
 196                 ath79_spi_delay(sp, nsecs);
 197                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
 198                 ath79_spi_delay(sp, nsecs);
 199                 if (bits == 1)
 200                         ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
 201
 202                 word <<= 1;
 203         }
 204
 205         return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
 206 }
 207
 208 static int ath79_spi_probe(struct platform_device *pdev)
 209 {
 210         struct spi_master *master;
 211         struct ath79_spi *sp;
 212         struct ath79_spi_platform_data *pdata;
 213         struct resource *r;
 214         unsigned long rate;
 215         int ret;
 216
 217         master = spi_alloc_master(&pdev->dev, sizeof(*sp));
 218         if (master == NULL) {
 219                 dev_err(&pdev->dev, "failed to allocate spi master\n");
 220                 return -ENOMEM;
 221         }
 222
 223         sp = spi_master_get_devdata(master);
 224         master->dev.of_node = pdev->dev.of_node;
 225         platform_set_drvdata(pdev, sp);
 226
 227         pdata = dev_get_platdata(&pdev->dev);
 228
 229         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
 230         master->setup = ath79_spi_setup;
 231         master->cleanup = ath79_spi_cleanup;
 232         if (pdata) {
 233                 master->bus_num = pdata->bus_num;
 234                 master->num_chipselect = pdata->num_chipselect;
 235         }
 236
 237         sp->bitbang.master = master;
 238         sp->bitbang.chipselect = ath79_spi_chipselect;
 239         sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
 240         sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
 241         sp->bitbang.flags = SPI_CS_HIGH;
 242
 243         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 244         sp->base = devm_ioremap_resource(&pdev->dev, r);
 245         if (IS_ERR(sp->base)) {
 246                 ret = PTR_ERR(sp->base);
 247                 goto err_put_master;
 248         }
 249
 250         sp->clk = devm_clk_get(&pdev->dev, "ahb");
 251         if (IS_ERR(sp->clk)) {
 252                 ret = PTR_ERR(sp->clk);
 253                 goto err_put_master;
 254         }
 255
 256         ret = clk_prepare_enable(sp->clk);
 257         if (ret)
 258                 goto err_put_master;
 259
 260         rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
 261         if (!rate) {
 262                 ret = -EINVAL;
 263                 goto err_clk_disable;
 264         }
 265
 266         sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
 267         dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
 268                 sp->rrw_delay);
 269
 270         ath79_spi_enable(sp);
 271         ret = spi_bitbang_start(&sp->bitbang);
 272         if (ret)
 273                 goto err_disable;
 274
 275         return 0;
 276
 277 err_disable:
 278         ath79_spi_disable(sp);
 279 err_clk_disable:
 280         clk_disable_unprepare(sp->clk);
 281 err_put_master:
 282         spi_master_put(sp->bitbang.master);
 283
 284         return ret;
 285 }
 286
 287 static int ath79_spi_remove(struct platform_device *pdev)
 288 {
 289         struct ath79_spi *sp = platform_get_drvdata(pdev);
 290
 291         spi_bitbang_stop(&sp->bitbang);
 292         ath79_spi_disable(sp);
 293         clk_disable_unprepare(sp->clk);
 294         spi_master_put(sp->bitbang.master);
 295
 296         return 0;
 297 }
 298
 299 static void ath79_spi_shutdown(struct platform_device *pdev)
 300 {
 301         ath79_spi_remove(pdev);
 302 }
 303
 304 static const struct of_device_id ath79_spi_of_match[] = {
 305         { .compatible = "qca,ar7100-spi", },
 306         { },
 307 };
 308 MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
 309
 310 static struct platform_driver ath79_spi_driver = {
 311         .probe          = ath79_spi_probe,
 312         .remove         = ath79_spi_remove,
 313         .shutdown       = ath79_spi_shutdown,
 314         .driver         = {
 315                 .name   = DRV_NAME,
 316                 .of_match_table = ath79_spi_of_match,
 317         },
 318 };
 319 module_platform_driver(ath79_spi_driver);
 320
 321 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
 322 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 323 MODULE_LICENSE("GPL v2");
 324 MODULE_ALIAS("platform:" DRV_NAME);