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[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-atmel.c
1 /*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/dma-atmel.h>
23 #include <linux/of.h>
24
25 #include <linux/io.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/pm_runtime.h>
30
31 /* SPI register offsets */
32 #define SPI_CR 0x0000
33 #define SPI_MR 0x0004
34 #define SPI_RDR 0x0008
35 #define SPI_TDR 0x000c
36 #define SPI_SR 0x0010
37 #define SPI_IER 0x0014
38 #define SPI_IDR 0x0018
39 #define SPI_IMR 0x001c
40 #define SPI_CSR0 0x0030
41 #define SPI_CSR1 0x0034
42 #define SPI_CSR2 0x0038
43 #define SPI_CSR3 0x003c
44 #define SPI_FMR 0x0040
45 #define SPI_FLR 0x0044
46 #define SPI_VERSION 0x00fc
47 #define SPI_RPR 0x0100
48 #define SPI_RCR 0x0104
49 #define SPI_TPR 0x0108
50 #define SPI_TCR 0x010c
51 #define SPI_RNPR 0x0110
52 #define SPI_RNCR 0x0114
53 #define SPI_TNPR 0x0118
54 #define SPI_TNCR 0x011c
55 #define SPI_PTCR 0x0120
56 #define SPI_PTSR 0x0124
57
58 /* Bitfields in CR */
59 #define SPI_SPIEN_OFFSET 0
60 #define SPI_SPIEN_SIZE 1
61 #define SPI_SPIDIS_OFFSET 1
62 #define SPI_SPIDIS_SIZE 1
63 #define SPI_SWRST_OFFSET 7
64 #define SPI_SWRST_SIZE 1
65 #define SPI_LASTXFER_OFFSET 24
66 #define SPI_LASTXFER_SIZE 1
67 #define SPI_TXFCLR_OFFSET 16
68 #define SPI_TXFCLR_SIZE 1
69 #define SPI_RXFCLR_OFFSET 17
70 #define SPI_RXFCLR_SIZE 1
71 #define SPI_FIFOEN_OFFSET 30
72 #define SPI_FIFOEN_SIZE 1
73 #define SPI_FIFODIS_OFFSET 31
74 #define SPI_FIFODIS_SIZE 1
75
76 /* Bitfields in MR */
77 #define SPI_MSTR_OFFSET 0
78 #define SPI_MSTR_SIZE 1
79 #define SPI_PS_OFFSET 1
80 #define SPI_PS_SIZE 1
81 #define SPI_PCSDEC_OFFSET 2
82 #define SPI_PCSDEC_SIZE 1
83 #define SPI_FDIV_OFFSET 3
84 #define SPI_FDIV_SIZE 1
85 #define SPI_MODFDIS_OFFSET 4
86 #define SPI_MODFDIS_SIZE 1
87 #define SPI_WDRBT_OFFSET 5
88 #define SPI_WDRBT_SIZE 1
89 #define SPI_LLB_OFFSET 7
90 #define SPI_LLB_SIZE 1
91 #define SPI_PCS_OFFSET 16
92 #define SPI_PCS_SIZE 4
93 #define SPI_DLYBCS_OFFSET 24
94 #define SPI_DLYBCS_SIZE 8
95
96 /* Bitfields in RDR */
97 #define SPI_RD_OFFSET 0
98 #define SPI_RD_SIZE 16
99
100 /* Bitfields in TDR */
101 #define SPI_TD_OFFSET 0
102 #define SPI_TD_SIZE 16
103
104 /* Bitfields in SR */
105 #define SPI_RDRF_OFFSET 0
106 #define SPI_RDRF_SIZE 1
107 #define SPI_TDRE_OFFSET 1
108 #define SPI_TDRE_SIZE 1
109 #define SPI_MODF_OFFSET 2
110 #define SPI_MODF_SIZE 1
111 #define SPI_OVRES_OFFSET 3
112 #define SPI_OVRES_SIZE 1
113 #define SPI_ENDRX_OFFSET 4
114 #define SPI_ENDRX_SIZE 1
115 #define SPI_ENDTX_OFFSET 5
116 #define SPI_ENDTX_SIZE 1
117 #define SPI_RXBUFF_OFFSET 6
118 #define SPI_RXBUFF_SIZE 1
119 #define SPI_TXBUFE_OFFSET 7
120 #define SPI_TXBUFE_SIZE 1
121 #define SPI_NSSR_OFFSET 8
122 #define SPI_NSSR_SIZE 1
123 #define SPI_TXEMPTY_OFFSET 9
124 #define SPI_TXEMPTY_SIZE 1
125 #define SPI_SPIENS_OFFSET 16
126 #define SPI_SPIENS_SIZE 1
127 #define SPI_TXFEF_OFFSET 24
128 #define SPI_TXFEF_SIZE 1
129 #define SPI_TXFFF_OFFSET 25
130 #define SPI_TXFFF_SIZE 1
131 #define SPI_TXFTHF_OFFSET 26
132 #define SPI_TXFTHF_SIZE 1
133 #define SPI_RXFEF_OFFSET 27
134 #define SPI_RXFEF_SIZE 1
135 #define SPI_RXFFF_OFFSET 28
136 #define SPI_RXFFF_SIZE 1
137 #define SPI_RXFTHF_OFFSET 29
138 #define SPI_RXFTHF_SIZE 1
139 #define SPI_TXFPTEF_OFFSET 30
140 #define SPI_TXFPTEF_SIZE 1
141 #define SPI_RXFPTEF_OFFSET 31
142 #define SPI_RXFPTEF_SIZE 1
143
144 /* Bitfields in CSR0 */
145 #define SPI_CPOL_OFFSET 0
146 #define SPI_CPOL_SIZE 1
147 #define SPI_NCPHA_OFFSET 1
148 #define SPI_NCPHA_SIZE 1
149 #define SPI_CSAAT_OFFSET 3
150 #define SPI_CSAAT_SIZE 1
151 #define SPI_BITS_OFFSET 4
152 #define SPI_BITS_SIZE 4
153 #define SPI_SCBR_OFFSET 8
154 #define SPI_SCBR_SIZE 8
155 #define SPI_DLYBS_OFFSET 16
156 #define SPI_DLYBS_SIZE 8
157 #define SPI_DLYBCT_OFFSET 24
158 #define SPI_DLYBCT_SIZE 8
159
160 /* Bitfields in RCR */
161 #define SPI_RXCTR_OFFSET 0
162 #define SPI_RXCTR_SIZE 16
163
164 /* Bitfields in TCR */
165 #define SPI_TXCTR_OFFSET 0
166 #define SPI_TXCTR_SIZE 16
167
168 /* Bitfields in RNCR */
169 #define SPI_RXNCR_OFFSET 0
170 #define SPI_RXNCR_SIZE 16
171
172 /* Bitfields in TNCR */
173 #define SPI_TXNCR_OFFSET 0
174 #define SPI_TXNCR_SIZE 16
175
176 /* Bitfields in PTCR */
177 #define SPI_RXTEN_OFFSET 0
178 #define SPI_RXTEN_SIZE 1
179 #define SPI_RXTDIS_OFFSET 1
180 #define SPI_RXTDIS_SIZE 1
181 #define SPI_TXTEN_OFFSET 8
182 #define SPI_TXTEN_SIZE 1
183 #define SPI_TXTDIS_OFFSET 9
184 #define SPI_TXTDIS_SIZE 1
185
186 /* Bitfields in FMR */
187 #define SPI_TXRDYM_OFFSET 0
188 #define SPI_TXRDYM_SIZE 2
189 #define SPI_RXRDYM_OFFSET 4
190 #define SPI_RXRDYM_SIZE 2
191 #define SPI_TXFTHRES_OFFSET 16
192 #define SPI_TXFTHRES_SIZE 6
193 #define SPI_RXFTHRES_OFFSET 24
194 #define SPI_RXFTHRES_SIZE 6
195
196 /* Bitfields in FLR */
197 #define SPI_TXFL_OFFSET 0
198 #define SPI_TXFL_SIZE 6
199 #define SPI_RXFL_OFFSET 16
200 #define SPI_RXFL_SIZE 6
201
202 /* Constants for BITS */
203 #define SPI_BITS_8_BPT 0
204 #define SPI_BITS_9_BPT 1
205 #define SPI_BITS_10_BPT 2
206 #define SPI_BITS_11_BPT 3
207 #define SPI_BITS_12_BPT 4
208 #define SPI_BITS_13_BPT 5
209 #define SPI_BITS_14_BPT 6
210 #define SPI_BITS_15_BPT 7
211 #define SPI_BITS_16_BPT 8
212 #define SPI_ONE_DATA 0
213 #define SPI_TWO_DATA 1
214 #define SPI_FOUR_DATA 2
215
216 /* Bit manipulation macros */
217 #define SPI_BIT(name) \
218 (1 << SPI_##name##_OFFSET)
219 #define SPI_BF(name, value) \
220 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
221 #define SPI_BFEXT(name, value) \
222 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
223 #define SPI_BFINS(name, value, old) \
224 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
225 | SPI_BF(name, value))
226
227 /* Register access macros */
228 #ifdef CONFIG_AVR32
229 #define spi_readl(port, reg) \
230 __raw_readl((port)->regs + SPI_##reg)
231 #define spi_writel(port, reg, value) \
232 __raw_writel((value), (port)->regs + SPI_##reg)
233
234 #define spi_readw(port, reg) \
235 __raw_readw((port)->regs + SPI_##reg)
236 #define spi_writew(port, reg, value) \
237 __raw_writew((value), (port)->regs + SPI_##reg)
238
239 #define spi_readb(port, reg) \
240 __raw_readb((port)->regs + SPI_##reg)
241 #define spi_writeb(port, reg, value) \
242 __raw_writeb((value), (port)->regs + SPI_##reg)
243 #else
244 #define spi_readl(port, reg) \
245 readl_relaxed((port)->regs + SPI_##reg)
246 #define spi_writel(port, reg, value) \
247 writel_relaxed((value), (port)->regs + SPI_##reg)
248
249 #define spi_readw(port, reg) \
250 readw_relaxed((port)->regs + SPI_##reg)
251 #define spi_writew(port, reg, value) \
252 writew_relaxed((value), (port)->regs + SPI_##reg)
253
254 #define spi_readb(port, reg) \
255 readb_relaxed((port)->regs + SPI_##reg)
256 #define spi_writeb(port, reg, value) \
257 writeb_relaxed((value), (port)->regs + SPI_##reg)
258 #endif
259 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
260 * cache operations; better heuristics consider wordsize and bitrate.
261 */
262 #define DMA_MIN_BYTES 16
263
264 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
265
266 #define AUTOSUSPEND_TIMEOUT 2000
267
268 struct atmel_spi_caps {
269 bool is_spi2;
270 bool has_wdrbt;
271 bool has_dma_support;
272 bool has_pdc_support;
273 };
274
275 /*
276 * The core SPI transfer engine just talks to a register bank to set up
277 * DMA transfers; transfer queue progress is driven by IRQs. The clock
278 * framework provides the base clock, subdivided for each spi_device.
279 */
280 struct atmel_spi {
281 spinlock_t lock;
282 unsigned long flags;
283
284 phys_addr_t phybase;
285 void __iomem *regs;
286 int irq;
287 struct clk *clk;
288 struct platform_device *pdev;
289 unsigned long spi_clk;
290
291 struct spi_transfer *current_transfer;
292 int current_remaining_bytes;
293 int done_status;
294
295 struct completion xfer_completion;
296
297 struct atmel_spi_caps caps;
298
299 bool use_dma;
300 bool use_pdc;
301 bool use_cs_gpios;
302
303 bool keep_cs;
304 bool cs_active;
305
306 u32 fifo_size;
307 };
308
309 /* Controller-specific per-slave state */
310 struct atmel_spi_device {
311 unsigned int npcs_pin;
312 u32 csr;
313 };
314
315 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
316 #define INVALID_DMA_ADDRESS 0xffffffff
317
318 /*
319 * Version 2 of the SPI controller has
320 * - CR.LASTXFER
321 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
322 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
323 * - SPI_CSRx.CSAAT
324 * - SPI_CSRx.SBCR allows faster clocking
325 */
326 static bool atmel_spi_is_v2(struct atmel_spi *as)
327 {
328 return as->caps.is_spi2;
329 }
330
331 /*
332 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
333 * they assume that spi slave device state will not change on deselect, so
334 * that automagic deselection is OK. ("NPCSx rises if no data is to be
335 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
336 * controllers have CSAAT and friends.
337 *
338 * Since the CSAAT functionality is a bit weird on newer controllers as
339 * well, we use GPIO to control nCSx pins on all controllers, updating
340 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
341 * support active-high chipselects despite the controller's belief that
342 * only active-low devices/systems exists.
343 *
344 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
345 * right when driven with GPIO. ("Mode Fault does not allow more than one
346 * Master on Chip Select 0.") No workaround exists for that ... so for
347 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
348 * and (c) will trigger that first erratum in some cases.
349 */
350
351 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
352 {
353 struct atmel_spi_device *asd = spi->controller_state;
354 unsigned active = spi->mode & SPI_CS_HIGH;
355 u32 mr;
356
357 if (atmel_spi_is_v2(as)) {
358 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
359 /* For the low SPI version, there is a issue that PDC transfer
360 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
361 */
362 spi_writel(as, CSR0, asd->csr);
363 if (as->caps.has_wdrbt) {
364 spi_writel(as, MR,
365 SPI_BF(PCS, ~(0x01 << spi->chip_select))
366 | SPI_BIT(WDRBT)
367 | SPI_BIT(MODFDIS)
368 | SPI_BIT(MSTR));
369 } else {
370 spi_writel(as, MR,
371 SPI_BF(PCS, ~(0x01 << spi->chip_select))
372 | SPI_BIT(MODFDIS)
373 | SPI_BIT(MSTR));
374 }
375
376 mr = spi_readl(as, MR);
377 if (as->use_cs_gpios)
378 gpio_set_value(asd->npcs_pin, active);
379 } else {
380 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
381 int i;
382 u32 csr;
383
384 /* Make sure clock polarity is correct */
385 for (i = 0; i < spi->master->num_chipselect; i++) {
386 csr = spi_readl(as, CSR0 + 4 * i);
387 if ((csr ^ cpol) & SPI_BIT(CPOL))
388 spi_writel(as, CSR0 + 4 * i,
389 csr ^ SPI_BIT(CPOL));
390 }
391
392 mr = spi_readl(as, MR);
393 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
394 if (as->use_cs_gpios && spi->chip_select != 0)
395 gpio_set_value(asd->npcs_pin, active);
396 spi_writel(as, MR, mr);
397 }
398
399 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
400 asd->npcs_pin, active ? " (high)" : "",
401 mr);
402 }
403
404 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
405 {
406 struct atmel_spi_device *asd = spi->controller_state;
407 unsigned active = spi->mode & SPI_CS_HIGH;
408 u32 mr;
409
410 /* only deactivate *this* device; sometimes transfers to
411 * another device may be active when this routine is called.
412 */
413 mr = spi_readl(as, MR);
414 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
415 mr = SPI_BFINS(PCS, 0xf, mr);
416 spi_writel(as, MR, mr);
417 }
418
419 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
420 asd->npcs_pin, active ? " (low)" : "",
421 mr);
422
423 if (!as->use_cs_gpios)
424 spi_writel(as, CR, SPI_BIT(LASTXFER));
425 else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
426 gpio_set_value(asd->npcs_pin, !active);
427 }
428
429 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
430 {
431 spin_lock_irqsave(&as->lock, as->flags);
432 }
433
434 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
435 {
436 spin_unlock_irqrestore(&as->lock, as->flags);
437 }
438
439 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
440 struct spi_transfer *xfer)
441 {
442 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
443 }
444
445 static bool atmel_spi_can_dma(struct spi_master *master,
446 struct spi_device *spi,
447 struct spi_transfer *xfer)
448 {
449 struct atmel_spi *as = spi_master_get_devdata(master);
450
451 return atmel_spi_use_dma(as, xfer);
452 }
453
454 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
455 struct dma_slave_config *slave_config,
456 u8 bits_per_word)
457 {
458 struct spi_master *master = platform_get_drvdata(as->pdev);
459 int err = 0;
460
461 if (bits_per_word > 8) {
462 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
463 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
464 } else {
465 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
466 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
467 }
468
469 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
470 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
471 slave_config->src_maxburst = 1;
472 slave_config->dst_maxburst = 1;
473 slave_config->device_fc = false;
474
475 /*
476 * This driver uses fixed peripheral select mode (PS bit set to '0' in
477 * the Mode Register).
478 * So according to the datasheet, when FIFOs are available (and
479 * enabled), the Transmit FIFO operates in Multiple Data Mode.
480 * In this mode, up to 2 data, not 4, can be written into the Transmit
481 * Data Register in a single access.
482 * However, the first data has to be written into the lowest 16 bits and
483 * the second data into the highest 16 bits of the Transmit
484 * Data Register. For 8bit data (the most frequent case), it would
485 * require to rework tx_buf so each data would actualy fit 16 bits.
486 * So we'd rather write only one data at the time. Hence the transmit
487 * path works the same whether FIFOs are available (and enabled) or not.
488 */
489 slave_config->direction = DMA_MEM_TO_DEV;
490 if (dmaengine_slave_config(master->dma_tx, slave_config)) {
491 dev_err(&as->pdev->dev,
492 "failed to configure tx dma channel\n");
493 err = -EINVAL;
494 }
495
496 /*
497 * This driver configures the spi controller for master mode (MSTR bit
498 * set to '1' in the Mode Register).
499 * So according to the datasheet, when FIFOs are available (and
500 * enabled), the Receive FIFO operates in Single Data Mode.
501 * So the receive path works the same whether FIFOs are available (and
502 * enabled) or not.
503 */
504 slave_config->direction = DMA_DEV_TO_MEM;
505 if (dmaengine_slave_config(master->dma_rx, slave_config)) {
506 dev_err(&as->pdev->dev,
507 "failed to configure rx dma channel\n");
508 err = -EINVAL;
509 }
510
511 return err;
512 }
513
514 static int atmel_spi_configure_dma(struct spi_master *master,
515 struct atmel_spi *as)
516 {
517 struct dma_slave_config slave_config;
518 struct device *dev = &as->pdev->dev;
519 int err;
520
521 dma_cap_mask_t mask;
522 dma_cap_zero(mask);
523 dma_cap_set(DMA_SLAVE, mask);
524
525 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
526 if (IS_ERR(master->dma_tx)) {
527 err = PTR_ERR(master->dma_tx);
528 if (err == -EPROBE_DEFER) {
529 dev_warn(dev, "no DMA channel available at the moment\n");
530 goto error_clear;
531 }
532 dev_err(dev,
533 "DMA TX channel not available, SPI unable to use DMA\n");
534 err = -EBUSY;
535 goto error_clear;
536 }
537
538 /*
539 * No reason to check EPROBE_DEFER here since we have already requested
540 * tx channel. If it fails here, it's for another reason.
541 */
542 master->dma_rx = dma_request_slave_channel(dev, "rx");
543
544 if (!master->dma_rx) {
545 dev_err(dev,
546 "DMA RX channel not available, SPI unable to use DMA\n");
547 err = -EBUSY;
548 goto error;
549 }
550
551 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
552 if (err)
553 goto error;
554
555 dev_info(&as->pdev->dev,
556 "Using %s (tx) and %s (rx) for DMA transfers\n",
557 dma_chan_name(master->dma_tx),
558 dma_chan_name(master->dma_rx));
559
560 return 0;
561 error:
562 if (master->dma_rx)
563 dma_release_channel(master->dma_rx);
564 if (!IS_ERR(master->dma_tx))
565 dma_release_channel(master->dma_tx);
566 error_clear:
567 master->dma_tx = master->dma_rx = NULL;
568 return err;
569 }
570
571 static void atmel_spi_stop_dma(struct spi_master *master)
572 {
573 if (master->dma_rx)
574 dmaengine_terminate_all(master->dma_rx);
575 if (master->dma_tx)
576 dmaengine_terminate_all(master->dma_tx);
577 }
578
579 static void atmel_spi_release_dma(struct spi_master *master)
580 {
581 if (master->dma_rx) {
582 dma_release_channel(master->dma_rx);
583 master->dma_rx = NULL;
584 }
585 if (master->dma_tx) {
586 dma_release_channel(master->dma_tx);
587 master->dma_tx = NULL;
588 }
589 }
590
591 /* This function is called by the DMA driver from tasklet context */
592 static void dma_callback(void *data)
593 {
594 struct spi_master *master = data;
595 struct atmel_spi *as = spi_master_get_devdata(master);
596
597 complete(&as->xfer_completion);
598 }
599
600 /*
601 * Next transfer using PIO without FIFO.
602 */
603 static void atmel_spi_next_xfer_single(struct spi_master *master,
604 struct spi_transfer *xfer)
605 {
606 struct atmel_spi *as = spi_master_get_devdata(master);
607 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
608
609 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
610
611 /* Make sure data is not remaining in RDR */
612 spi_readl(as, RDR);
613 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
614 spi_readl(as, RDR);
615 cpu_relax();
616 }
617
618 if (xfer->bits_per_word > 8)
619 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
620 else
621 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
622
623 dev_dbg(master->dev.parent,
624 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
625 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
626 xfer->bits_per_word);
627
628 /* Enable relevant interrupts */
629 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
630 }
631
632 /*
633 * Next transfer using PIO with FIFO.
634 */
635 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
636 struct spi_transfer *xfer)
637 {
638 struct atmel_spi *as = spi_master_get_devdata(master);
639 u32 current_remaining_data, num_data;
640 u32 offset = xfer->len - as->current_remaining_bytes;
641 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
642 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
643 u16 td0, td1;
644 u32 fifomr;
645
646 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
647
648 /* Compute the number of data to transfer in the current iteration */
649 current_remaining_data = ((xfer->bits_per_word > 8) ?
650 ((u32)as->current_remaining_bytes >> 1) :
651 (u32)as->current_remaining_bytes);
652 num_data = min(current_remaining_data, as->fifo_size);
653
654 /* Flush RX and TX FIFOs */
655 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
656 while (spi_readl(as, FLR))
657 cpu_relax();
658
659 /* Set RX FIFO Threshold to the number of data to transfer */
660 fifomr = spi_readl(as, FMR);
661 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
662
663 /* Clear FIFO flags in the Status Register, especially RXFTHF */
664 (void)spi_readl(as, SR);
665
666 /* Fill TX FIFO */
667 while (num_data >= 2) {
668 if (xfer->bits_per_word > 8) {
669 td0 = *words++;
670 td1 = *words++;
671 } else {
672 td0 = *bytes++;
673 td1 = *bytes++;
674 }
675
676 spi_writel(as, TDR, (td1 << 16) | td0);
677 num_data -= 2;
678 }
679
680 if (num_data) {
681 if (xfer->bits_per_word > 8)
682 td0 = *words++;
683 else
684 td0 = *bytes++;
685
686 spi_writew(as, TDR, td0);
687 num_data--;
688 }
689
690 dev_dbg(master->dev.parent,
691 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
692 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
693 xfer->bits_per_word);
694
695 /*
696 * Enable RX FIFO Threshold Flag interrupt to be notified about
697 * transfer completion.
698 */
699 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
700 }
701
702 /*
703 * Next transfer using PIO.
704 */
705 static void atmel_spi_next_xfer_pio(struct spi_master *master,
706 struct spi_transfer *xfer)
707 {
708 struct atmel_spi *as = spi_master_get_devdata(master);
709
710 if (as->fifo_size)
711 atmel_spi_next_xfer_fifo(master, xfer);
712 else
713 atmel_spi_next_xfer_single(master, xfer);
714 }
715
716 /*
717 * Submit next transfer for DMA.
718 */
719 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
720 struct spi_transfer *xfer,
721 u32 *plen)
722 {
723 struct atmel_spi *as = spi_master_get_devdata(master);
724 struct dma_chan *rxchan = master->dma_rx;
725 struct dma_chan *txchan = master->dma_tx;
726 struct dma_async_tx_descriptor *rxdesc;
727 struct dma_async_tx_descriptor *txdesc;
728 struct dma_slave_config slave_config;
729 dma_cookie_t cookie;
730
731 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
732
733 /* Check that the channels are available */
734 if (!rxchan || !txchan)
735 return -ENODEV;
736
737 /* release lock for DMA operations */
738 atmel_spi_unlock(as);
739
740 *plen = xfer->len;
741
742 if (atmel_spi_dma_slave_config(as, &slave_config,
743 xfer->bits_per_word))
744 goto err_exit;
745
746 /* Send both scatterlists */
747 rxdesc = dmaengine_prep_slave_sg(rxchan,
748 xfer->rx_sg.sgl, xfer->rx_sg.nents,
749 DMA_FROM_DEVICE,
750 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
751 if (!rxdesc)
752 goto err_dma;
753
754 txdesc = dmaengine_prep_slave_sg(txchan,
755 xfer->tx_sg.sgl, xfer->tx_sg.nents,
756 DMA_TO_DEVICE,
757 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
758 if (!txdesc)
759 goto err_dma;
760
761 dev_dbg(master->dev.parent,
762 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
763 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
764 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
765
766 /* Enable relevant interrupts */
767 spi_writel(as, IER, SPI_BIT(OVRES));
768
769 /* Put the callback on the RX transfer only, that should finish last */
770 rxdesc->callback = dma_callback;
771 rxdesc->callback_param = master;
772
773 /* Submit and fire RX and TX with TX last so we're ready to read! */
774 cookie = rxdesc->tx_submit(rxdesc);
775 if (dma_submit_error(cookie))
776 goto err_dma;
777 cookie = txdesc->tx_submit(txdesc);
778 if (dma_submit_error(cookie))
779 goto err_dma;
780 rxchan->device->device_issue_pending(rxchan);
781 txchan->device->device_issue_pending(txchan);
782
783 /* take back lock */
784 atmel_spi_lock(as);
785 return 0;
786
787 err_dma:
788 spi_writel(as, IDR, SPI_BIT(OVRES));
789 atmel_spi_stop_dma(master);
790 err_exit:
791 atmel_spi_lock(as);
792 return -ENOMEM;
793 }
794
795 static void atmel_spi_next_xfer_data(struct spi_master *master,
796 struct spi_transfer *xfer,
797 dma_addr_t *tx_dma,
798 dma_addr_t *rx_dma,
799 u32 *plen)
800 {
801 *rx_dma = xfer->rx_dma + xfer->len - *plen;
802 *tx_dma = xfer->tx_dma + xfer->len - *plen;
803 if (*plen > master->max_dma_len)
804 *plen = master->max_dma_len;
805 }
806
807 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
808 struct spi_device *spi,
809 struct spi_transfer *xfer)
810 {
811 u32 scbr, csr;
812 unsigned long bus_hz;
813
814 /* v1 chips start out at half the peripheral bus speed. */
815 bus_hz = as->spi_clk;
816 if (!atmel_spi_is_v2(as))
817 bus_hz /= 2;
818
819 /*
820 * Calculate the lowest divider that satisfies the
821 * constraint, assuming div32/fdiv/mbz == 0.
822 */
823 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
824
825 /*
826 * If the resulting divider doesn't fit into the
827 * register bitfield, we can't satisfy the constraint.
828 */
829 if (scbr >= (1 << SPI_SCBR_SIZE)) {
830 dev_err(&spi->dev,
831 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
832 xfer->speed_hz, scbr, bus_hz/255);
833 return -EINVAL;
834 }
835 if (scbr == 0) {
836 dev_err(&spi->dev,
837 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
838 xfer->speed_hz, scbr, bus_hz);
839 return -EINVAL;
840 }
841 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
842 csr = SPI_BFINS(SCBR, scbr, csr);
843 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
844
845 return 0;
846 }
847
848 /*
849 * Submit next transfer for PDC.
850 * lock is held, spi irq is blocked
851 */
852 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
853 struct spi_message *msg,
854 struct spi_transfer *xfer)
855 {
856 struct atmel_spi *as = spi_master_get_devdata(master);
857 u32 len;
858 dma_addr_t tx_dma, rx_dma;
859
860 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
861
862 len = as->current_remaining_bytes;
863 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
864 as->current_remaining_bytes -= len;
865
866 spi_writel(as, RPR, rx_dma);
867 spi_writel(as, TPR, tx_dma);
868
869 if (msg->spi->bits_per_word > 8)
870 len >>= 1;
871 spi_writel(as, RCR, len);
872 spi_writel(as, TCR, len);
873
874 dev_dbg(&msg->spi->dev,
875 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
876 xfer, xfer->len, xfer->tx_buf,
877 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
878 (unsigned long long)xfer->rx_dma);
879
880 if (as->current_remaining_bytes) {
881 len = as->current_remaining_bytes;
882 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
883 as->current_remaining_bytes -= len;
884
885 spi_writel(as, RNPR, rx_dma);
886 spi_writel(as, TNPR, tx_dma);
887
888 if (msg->spi->bits_per_word > 8)
889 len >>= 1;
890 spi_writel(as, RNCR, len);
891 spi_writel(as, TNCR, len);
892
893 dev_dbg(&msg->spi->dev,
894 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
895 xfer, xfer->len, xfer->tx_buf,
896 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
897 (unsigned long long)xfer->rx_dma);
898 }
899
900 /* REVISIT: We're waiting for RXBUFF before we start the next
901 * transfer because we need to handle some difficult timing
902 * issues otherwise. If we wait for TXBUFE in one transfer and
903 * then starts waiting for RXBUFF in the next, it's difficult
904 * to tell the difference between the RXBUFF interrupt we're
905 * actually waiting for and the RXBUFF interrupt of the
906 * previous transfer.
907 *
908 * It should be doable, though. Just not now...
909 */
910 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
911 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
912 }
913
914 /*
915 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
916 * - The buffer is either valid for CPU access, else NULL
917 * - If the buffer is valid, so is its DMA address
918 *
919 * This driver manages the dma address unless message->is_dma_mapped.
920 */
921 static int
922 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
923 {
924 struct device *dev = &as->pdev->dev;
925
926 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
927 if (xfer->tx_buf) {
928 /* tx_buf is a const void* where we need a void * for the dma
929 * mapping */
930 void *nonconst_tx = (void *)xfer->tx_buf;
931
932 xfer->tx_dma = dma_map_single(dev,
933 nonconst_tx, xfer->len,
934 DMA_TO_DEVICE);
935 if (dma_mapping_error(dev, xfer->tx_dma))
936 return -ENOMEM;
937 }
938 if (xfer->rx_buf) {
939 xfer->rx_dma = dma_map_single(dev,
940 xfer->rx_buf, xfer->len,
941 DMA_FROM_DEVICE);
942 if (dma_mapping_error(dev, xfer->rx_dma)) {
943 if (xfer->tx_buf)
944 dma_unmap_single(dev,
945 xfer->tx_dma, xfer->len,
946 DMA_TO_DEVICE);
947 return -ENOMEM;
948 }
949 }
950 return 0;
951 }
952
953 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
954 struct spi_transfer *xfer)
955 {
956 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
957 dma_unmap_single(master->dev.parent, xfer->tx_dma,
958 xfer->len, DMA_TO_DEVICE);
959 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
960 dma_unmap_single(master->dev.parent, xfer->rx_dma,
961 xfer->len, DMA_FROM_DEVICE);
962 }
963
964 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
965 {
966 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
967 }
968
969 static void
970 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
971 {
972 u8 *rxp;
973 u16 *rxp16;
974 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
975
976 if (xfer->bits_per_word > 8) {
977 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
978 *rxp16 = spi_readl(as, RDR);
979 } else {
980 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
981 *rxp = spi_readl(as, RDR);
982 }
983 if (xfer->bits_per_word > 8) {
984 if (as->current_remaining_bytes > 2)
985 as->current_remaining_bytes -= 2;
986 else
987 as->current_remaining_bytes = 0;
988 } else {
989 as->current_remaining_bytes--;
990 }
991 }
992
993 static void
994 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
995 {
996 u32 fifolr = spi_readl(as, FLR);
997 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
998 u32 offset = xfer->len - as->current_remaining_bytes;
999 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1000 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1001 u16 rd; /* RD field is the lowest 16 bits of RDR */
1002
1003 /* Update the number of remaining bytes to transfer */
1004 num_bytes = ((xfer->bits_per_word > 8) ?
1005 (num_data << 1) :
1006 num_data);
1007
1008 if (as->current_remaining_bytes > num_bytes)
1009 as->current_remaining_bytes -= num_bytes;
1010 else
1011 as->current_remaining_bytes = 0;
1012
1013 /* Handle odd number of bytes when data are more than 8bit width */
1014 if (xfer->bits_per_word > 8)
1015 as->current_remaining_bytes &= ~0x1;
1016
1017 /* Read data */
1018 while (num_data) {
1019 rd = spi_readl(as, RDR);
1020 if (xfer->bits_per_word > 8)
1021 *words++ = rd;
1022 else
1023 *bytes++ = rd;
1024 num_data--;
1025 }
1026 }
1027
1028 /* Called from IRQ
1029 *
1030 * Must update "current_remaining_bytes" to keep track of data
1031 * to transfer.
1032 */
1033 static void
1034 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1035 {
1036 if (as->fifo_size)
1037 atmel_spi_pump_fifo_data(as, xfer);
1038 else
1039 atmel_spi_pump_single_data(as, xfer);
1040 }
1041
1042 /* Interrupt
1043 *
1044 * No need for locking in this Interrupt handler: done_status is the
1045 * only information modified.
1046 */
1047 static irqreturn_t
1048 atmel_spi_pio_interrupt(int irq, void *dev_id)
1049 {
1050 struct spi_master *master = dev_id;
1051 struct atmel_spi *as = spi_master_get_devdata(master);
1052 u32 status, pending, imr;
1053 struct spi_transfer *xfer;
1054 int ret = IRQ_NONE;
1055
1056 imr = spi_readl(as, IMR);
1057 status = spi_readl(as, SR);
1058 pending = status & imr;
1059
1060 if (pending & SPI_BIT(OVRES)) {
1061 ret = IRQ_HANDLED;
1062 spi_writel(as, IDR, SPI_BIT(OVRES));
1063 dev_warn(master->dev.parent, "overrun\n");
1064
1065 /*
1066 * When we get an overrun, we disregard the current
1067 * transfer. Data will not be copied back from any
1068 * bounce buffer and msg->actual_len will not be
1069 * updated with the last xfer.
1070 *
1071 * We will also not process any remaning transfers in
1072 * the message.
1073 */
1074 as->done_status = -EIO;
1075 smp_wmb();
1076
1077 /* Clear any overrun happening while cleaning up */
1078 spi_readl(as, SR);
1079
1080 complete(&as->xfer_completion);
1081
1082 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1083 atmel_spi_lock(as);
1084
1085 if (as->current_remaining_bytes) {
1086 ret = IRQ_HANDLED;
1087 xfer = as->current_transfer;
1088 atmel_spi_pump_pio_data(as, xfer);
1089 if (!as->current_remaining_bytes)
1090 spi_writel(as, IDR, pending);
1091
1092 complete(&as->xfer_completion);
1093 }
1094
1095 atmel_spi_unlock(as);
1096 } else {
1097 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1098 ret = IRQ_HANDLED;
1099 spi_writel(as, IDR, pending);
1100 }
1101
1102 return ret;
1103 }
1104
1105 static irqreturn_t
1106 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1107 {
1108 struct spi_master *master = dev_id;
1109 struct atmel_spi *as = spi_master_get_devdata(master);
1110 u32 status, pending, imr;
1111 int ret = IRQ_NONE;
1112
1113 imr = spi_readl(as, IMR);
1114 status = spi_readl(as, SR);
1115 pending = status & imr;
1116
1117 if (pending & SPI_BIT(OVRES)) {
1118
1119 ret = IRQ_HANDLED;
1120
1121 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1122 | SPI_BIT(OVRES)));
1123
1124 /* Clear any overrun happening while cleaning up */
1125 spi_readl(as, SR);
1126
1127 as->done_status = -EIO;
1128
1129 complete(&as->xfer_completion);
1130
1131 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1132 ret = IRQ_HANDLED;
1133
1134 spi_writel(as, IDR, pending);
1135
1136 complete(&as->xfer_completion);
1137 }
1138
1139 return ret;
1140 }
1141
1142 static int atmel_spi_setup(struct spi_device *spi)
1143 {
1144 struct atmel_spi *as;
1145 struct atmel_spi_device *asd;
1146 u32 csr;
1147 unsigned int bits = spi->bits_per_word;
1148 unsigned int npcs_pin;
1149
1150 as = spi_master_get_devdata(spi->master);
1151
1152 /* see notes above re chipselect */
1153 if (!atmel_spi_is_v2(as)
1154 && spi->chip_select == 0
1155 && (spi->mode & SPI_CS_HIGH)) {
1156 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1157 return -EINVAL;
1158 }
1159
1160 csr = SPI_BF(BITS, bits - 8);
1161 if (spi->mode & SPI_CPOL)
1162 csr |= SPI_BIT(CPOL);
1163 if (!(spi->mode & SPI_CPHA))
1164 csr |= SPI_BIT(NCPHA);
1165 if (!as->use_cs_gpios)
1166 csr |= SPI_BIT(CSAAT);
1167
1168 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1169 *
1170 * DLYBCT would add delays between words, slowing down transfers.
1171 * It could potentially be useful to cope with DMA bottlenecks, but
1172 * in those cases it's probably best to just use a lower bitrate.
1173 */
1174 csr |= SPI_BF(DLYBS, 0);
1175 csr |= SPI_BF(DLYBCT, 0);
1176
1177 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1178 npcs_pin = (unsigned long)spi->controller_data;
1179
1180 if (!as->use_cs_gpios)
1181 npcs_pin = spi->chip_select;
1182 else if (gpio_is_valid(spi->cs_gpio))
1183 npcs_pin = spi->cs_gpio;
1184
1185 asd = spi->controller_state;
1186 if (!asd) {
1187 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1188 if (!asd)
1189 return -ENOMEM;
1190
1191 if (as->use_cs_gpios)
1192 gpio_direction_output(npcs_pin,
1193 !(spi->mode & SPI_CS_HIGH));
1194
1195 asd->npcs_pin = npcs_pin;
1196 spi->controller_state = asd;
1197 }
1198
1199 asd->csr = csr;
1200
1201 dev_dbg(&spi->dev,
1202 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1203 bits, spi->mode, spi->chip_select, csr);
1204
1205 if (!atmel_spi_is_v2(as))
1206 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1207
1208 return 0;
1209 }
1210
1211 static int atmel_spi_one_transfer(struct spi_master *master,
1212 struct spi_message *msg,
1213 struct spi_transfer *xfer)
1214 {
1215 struct atmel_spi *as;
1216 struct spi_device *spi = msg->spi;
1217 u8 bits;
1218 u32 len;
1219 struct atmel_spi_device *asd;
1220 int timeout;
1221 int ret;
1222 unsigned long dma_timeout;
1223
1224 as = spi_master_get_devdata(master);
1225
1226 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1227 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1228 return -EINVAL;
1229 }
1230
1231 asd = spi->controller_state;
1232 bits = (asd->csr >> 4) & 0xf;
1233 if (bits != xfer->bits_per_word - 8) {
1234 dev_dbg(&spi->dev,
1235 "you can't yet change bits_per_word in transfers\n");
1236 return -ENOPROTOOPT;
1237 }
1238
1239 /*
1240 * DMA map early, for performance (empties dcache ASAP) and
1241 * better fault reporting.
1242 */
1243 if ((!msg->is_dma_mapped)
1244 && as->use_pdc) {
1245 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1246 return -ENOMEM;
1247 }
1248
1249 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1250
1251 as->done_status = 0;
1252 as->current_transfer = xfer;
1253 as->current_remaining_bytes = xfer->len;
1254 while (as->current_remaining_bytes) {
1255 reinit_completion(&as->xfer_completion);
1256
1257 if (as->use_pdc) {
1258 atmel_spi_pdc_next_xfer(master, msg, xfer);
1259 } else if (atmel_spi_use_dma(as, xfer)) {
1260 len = as->current_remaining_bytes;
1261 ret = atmel_spi_next_xfer_dma_submit(master,
1262 xfer, &len);
1263 if (ret) {
1264 dev_err(&spi->dev,
1265 "unable to use DMA, fallback to PIO\n");
1266 atmel_spi_next_xfer_pio(master, xfer);
1267 } else {
1268 as->current_remaining_bytes -= len;
1269 if (as->current_remaining_bytes < 0)
1270 as->current_remaining_bytes = 0;
1271 }
1272 } else {
1273 atmel_spi_next_xfer_pio(master, xfer);
1274 }
1275
1276 /* interrupts are disabled, so free the lock for schedule */
1277 atmel_spi_unlock(as);
1278 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1279 SPI_DMA_TIMEOUT);
1280 atmel_spi_lock(as);
1281 if (WARN_ON(dma_timeout == 0)) {
1282 dev_err(&spi->dev, "spi transfer timeout\n");
1283 as->done_status = -EIO;
1284 }
1285
1286 if (as->done_status)
1287 break;
1288 }
1289
1290 if (as->done_status) {
1291 if (as->use_pdc) {
1292 dev_warn(master->dev.parent,
1293 "overrun (%u/%u remaining)\n",
1294 spi_readl(as, TCR), spi_readl(as, RCR));
1295
1296 /*
1297 * Clean up DMA registers and make sure the data
1298 * registers are empty.
1299 */
1300 spi_writel(as, RNCR, 0);
1301 spi_writel(as, TNCR, 0);
1302 spi_writel(as, RCR, 0);
1303 spi_writel(as, TCR, 0);
1304 for (timeout = 1000; timeout; timeout--)
1305 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1306 break;
1307 if (!timeout)
1308 dev_warn(master->dev.parent,
1309 "timeout waiting for TXEMPTY");
1310 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1311 spi_readl(as, RDR);
1312
1313 /* Clear any overrun happening while cleaning up */
1314 spi_readl(as, SR);
1315
1316 } else if (atmel_spi_use_dma(as, xfer)) {
1317 atmel_spi_stop_dma(master);
1318 }
1319
1320 if (!msg->is_dma_mapped
1321 && as->use_pdc)
1322 atmel_spi_dma_unmap_xfer(master, xfer);
1323
1324 return 0;
1325
1326 } else {
1327 /* only update length if no error */
1328 msg->actual_length += xfer->len;
1329 }
1330
1331 if (!msg->is_dma_mapped
1332 && as->use_pdc)
1333 atmel_spi_dma_unmap_xfer(master, xfer);
1334
1335 if (xfer->delay_usecs)
1336 udelay(xfer->delay_usecs);
1337
1338 if (xfer->cs_change) {
1339 if (list_is_last(&xfer->transfer_list,
1340 &msg->transfers)) {
1341 as->keep_cs = true;
1342 } else {
1343 as->cs_active = !as->cs_active;
1344 if (as->cs_active)
1345 cs_activate(as, msg->spi);
1346 else
1347 cs_deactivate(as, msg->spi);
1348 }
1349 }
1350
1351 return 0;
1352 }
1353
1354 static int atmel_spi_transfer_one_message(struct spi_master *master,
1355 struct spi_message *msg)
1356 {
1357 struct atmel_spi *as;
1358 struct spi_transfer *xfer;
1359 struct spi_device *spi = msg->spi;
1360 int ret = 0;
1361
1362 as = spi_master_get_devdata(master);
1363
1364 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1365 msg, dev_name(&spi->dev));
1366
1367 atmel_spi_lock(as);
1368 cs_activate(as, spi);
1369
1370 as->cs_active = true;
1371 as->keep_cs = false;
1372
1373 msg->status = 0;
1374 msg->actual_length = 0;
1375
1376 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1377 ret = atmel_spi_one_transfer(master, msg, xfer);
1378 if (ret)
1379 goto msg_done;
1380 }
1381
1382 if (as->use_pdc)
1383 atmel_spi_disable_pdc_transfer(as);
1384
1385 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1386 dev_dbg(&spi->dev,
1387 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1388 xfer, xfer->len,
1389 xfer->tx_buf, &xfer->tx_dma,
1390 xfer->rx_buf, &xfer->rx_dma);
1391 }
1392
1393 msg_done:
1394 if (!as->keep_cs)
1395 cs_deactivate(as, msg->spi);
1396
1397 atmel_spi_unlock(as);
1398
1399 msg->status = as->done_status;
1400 spi_finalize_current_message(spi->master);
1401
1402 return ret;
1403 }
1404
1405 static void atmel_spi_cleanup(struct spi_device *spi)
1406 {
1407 struct atmel_spi_device *asd = spi->controller_state;
1408
1409 if (!asd)
1410 return;
1411
1412 spi->controller_state = NULL;
1413 kfree(asd);
1414 }
1415
1416 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1417 {
1418 return spi_readl(as, VERSION) & 0x00000fff;
1419 }
1420
1421 static void atmel_get_caps(struct atmel_spi *as)
1422 {
1423 unsigned int version;
1424
1425 version = atmel_get_version(as);
1426
1427 as->caps.is_spi2 = version > 0x121;
1428 as->caps.has_wdrbt = version >= 0x210;
1429 #ifdef CONFIG_SOC_SAM_V4_V5
1430 /*
1431 * Atmel SoCs based on ARM9 (SAM9x) cores should not use spi_map_buf()
1432 * since this later function tries to map buffers with dma_map_sg()
1433 * even if they have not been allocated inside DMA-safe areas.
1434 * On SoCs based on Cortex A5 (SAMA5Dx), it works anyway because for
1435 * those ARM cores, the data cache follows the PIPT model.
1436 * Also the L2 cache controller of SAMA5D2 uses the PIPT model too.
1437 * In case of PIPT caches, there cannot be cache aliases.
1438 * However on ARM9 cores, the data cache follows the VIVT model, hence
1439 * the cache aliases issue can occur when buffers are allocated from
1440 * DMA-unsafe areas, by vmalloc() for instance, where cache coherency is
1441 * not taken into account or at least not handled completely (cache
1442 * lines of aliases are not invalidated).
1443 * This is not a theorical issue: it was reproduced when trying to mount
1444 * a UBI file-system on a at91sam9g35ek board.
1445 */
1446 as->caps.has_dma_support = false;
1447 #else
1448 as->caps.has_dma_support = version >= 0x212;
1449 #endif
1450 as->caps.has_pdc_support = version < 0x212;
1451 }
1452
1453 /*-------------------------------------------------------------------------*/
1454 static int atmel_spi_gpio_cs(struct platform_device *pdev)
1455 {
1456 struct spi_master *master = platform_get_drvdata(pdev);
1457 struct atmel_spi *as = spi_master_get_devdata(master);
1458 struct device_node *np = master->dev.of_node;
1459 int i;
1460 int ret = 0;
1461 int nb = 0;
1462
1463 if (!as->use_cs_gpios)
1464 return 0;
1465
1466 if (!np)
1467 return 0;
1468
1469 nb = of_gpio_named_count(np, "cs-gpios");
1470 for (i = 0; i < nb; i++) {
1471 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1472 "cs-gpios", i);
1473
1474 if (cs_gpio == -EPROBE_DEFER)
1475 return cs_gpio;
1476
1477 if (gpio_is_valid(cs_gpio)) {
1478 ret = devm_gpio_request(&pdev->dev, cs_gpio,
1479 dev_name(&pdev->dev));
1480 if (ret)
1481 return ret;
1482 }
1483 }
1484
1485 return 0;
1486 }
1487
1488 static void atmel_spi_init(struct atmel_spi *as)
1489 {
1490 spi_writel(as, CR, SPI_BIT(SWRST));
1491 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1492 if (as->caps.has_wdrbt) {
1493 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1494 | SPI_BIT(MSTR));
1495 } else {
1496 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1497 }
1498
1499 if (as->use_pdc)
1500 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1501 spi_writel(as, CR, SPI_BIT(SPIEN));
1502
1503 if (as->fifo_size)
1504 spi_writel(as, CR, SPI_BIT(FIFOEN));
1505 }
1506
1507 static int atmel_spi_probe(struct platform_device *pdev)
1508 {
1509 struct resource *regs;
1510 int irq;
1511 struct clk *clk;
1512 int ret;
1513 struct spi_master *master;
1514 struct atmel_spi *as;
1515
1516 /* Select default pin state */
1517 pinctrl_pm_select_default_state(&pdev->dev);
1518
1519 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1520 if (!regs)
1521 return -ENXIO;
1522
1523 irq = platform_get_irq(pdev, 0);
1524 if (irq < 0)
1525 return irq;
1526
1527 clk = devm_clk_get(&pdev->dev, "spi_clk");
1528 if (IS_ERR(clk))
1529 return PTR_ERR(clk);
1530
1531 /* setup spi core then atmel-specific driver state */
1532 ret = -ENOMEM;
1533 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1534 if (!master)
1535 goto out_free;
1536
1537 /* the spi->mode bits understood by this driver: */
1538 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1539 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1540 master->dev.of_node = pdev->dev.of_node;
1541 master->bus_num = pdev->id;
1542 master->num_chipselect = master->dev.of_node ? 0 : 4;
1543 master->setup = atmel_spi_setup;
1544 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1545 master->transfer_one_message = atmel_spi_transfer_one_message;
1546 master->cleanup = atmel_spi_cleanup;
1547 master->auto_runtime_pm = true;
1548 master->max_dma_len = SPI_MAX_DMA_XFER;
1549 master->can_dma = atmel_spi_can_dma;
1550 platform_set_drvdata(pdev, master);
1551
1552 as = spi_master_get_devdata(master);
1553
1554 spin_lock_init(&as->lock);
1555
1556 as->pdev = pdev;
1557 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1558 if (IS_ERR(as->regs)) {
1559 ret = PTR_ERR(as->regs);
1560 goto out_unmap_regs;
1561 }
1562 as->phybase = regs->start;
1563 as->irq = irq;
1564 as->clk = clk;
1565
1566 init_completion(&as->xfer_completion);
1567
1568 atmel_get_caps(as);
1569
1570 as->use_cs_gpios = true;
1571 if (atmel_spi_is_v2(as) &&
1572 pdev->dev.of_node &&
1573 !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1574 as->use_cs_gpios = false;
1575 master->num_chipselect = 4;
1576 }
1577
1578 ret = atmel_spi_gpio_cs(pdev);
1579 if (ret)
1580 goto out_unmap_regs;
1581
1582 as->use_dma = false;
1583 as->use_pdc = false;
1584 if (as->caps.has_dma_support) {
1585 ret = atmel_spi_configure_dma(master, as);
1586 if (ret == 0) {
1587 as->use_dma = true;
1588 } else if (ret == -EPROBE_DEFER) {
1589 return ret;
1590 }
1591 } else if (as->caps.has_pdc_support) {
1592 as->use_pdc = true;
1593 }
1594
1595 if (as->caps.has_dma_support && !as->use_dma)
1596 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1597
1598 if (as->use_pdc) {
1599 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1600 0, dev_name(&pdev->dev), master);
1601 } else {
1602 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1603 0, dev_name(&pdev->dev), master);
1604 }
1605 if (ret)
1606 goto out_unmap_regs;
1607
1608 /* Initialize the hardware */
1609 ret = clk_prepare_enable(clk);
1610 if (ret)
1611 goto out_free_irq;
1612
1613 as->spi_clk = clk_get_rate(clk);
1614
1615 as->fifo_size = 0;
1616 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1617 &as->fifo_size)) {
1618 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1619 }
1620
1621 atmel_spi_init(as);
1622
1623 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1624 pm_runtime_use_autosuspend(&pdev->dev);
1625 pm_runtime_set_active(&pdev->dev);
1626 pm_runtime_enable(&pdev->dev);
1627
1628 ret = devm_spi_register_master(&pdev->dev, master);
1629 if (ret)
1630 goto out_free_dma;
1631
1632 /* go! */
1633 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1634 atmel_get_version(as), (unsigned long)regs->start,
1635 irq);
1636
1637 return 0;
1638
1639 out_free_dma:
1640 pm_runtime_disable(&pdev->dev);
1641 pm_runtime_set_suspended(&pdev->dev);
1642
1643 if (as->use_dma)
1644 atmel_spi_release_dma(master);
1645
1646 spi_writel(as, CR, SPI_BIT(SWRST));
1647 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1648 clk_disable_unprepare(clk);
1649 out_free_irq:
1650 out_unmap_regs:
1651 out_free:
1652 spi_master_put(master);
1653 return ret;
1654 }
1655
1656 static int atmel_spi_remove(struct platform_device *pdev)
1657 {
1658 struct spi_master *master = platform_get_drvdata(pdev);
1659 struct atmel_spi *as = spi_master_get_devdata(master);
1660
1661 pm_runtime_get_sync(&pdev->dev);
1662
1663 /* reset the hardware and block queue progress */
1664 if (as->use_dma) {
1665 atmel_spi_stop_dma(master);
1666 atmel_spi_release_dma(master);
1667 }
1668
1669 spin_lock_irq(&as->lock);
1670 spi_writel(as, CR, SPI_BIT(SWRST));
1671 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1672 spi_readl(as, SR);
1673 spin_unlock_irq(&as->lock);
1674
1675 clk_disable_unprepare(as->clk);
1676
1677 pm_runtime_put_noidle(&pdev->dev);
1678 pm_runtime_disable(&pdev->dev);
1679
1680 return 0;
1681 }
1682
1683 #ifdef CONFIG_PM
1684 static int atmel_spi_runtime_suspend(struct device *dev)
1685 {
1686 struct spi_master *master = dev_get_drvdata(dev);
1687 struct atmel_spi *as = spi_master_get_devdata(master);
1688
1689 clk_disable_unprepare(as->clk);
1690 pinctrl_pm_select_sleep_state(dev);
1691
1692 return 0;
1693 }
1694
1695 static int atmel_spi_runtime_resume(struct device *dev)
1696 {
1697 struct spi_master *master = dev_get_drvdata(dev);
1698 struct atmel_spi *as = spi_master_get_devdata(master);
1699
1700 pinctrl_pm_select_default_state(dev);
1701
1702 return clk_prepare_enable(as->clk);
1703 }
1704
1705 #ifdef CONFIG_PM_SLEEP
1706 static int atmel_spi_suspend(struct device *dev)
1707 {
1708 struct spi_master *master = dev_get_drvdata(dev);
1709 int ret;
1710
1711 /* Stop the queue running */
1712 ret = spi_master_suspend(master);
1713 if (ret) {
1714 dev_warn(dev, "cannot suspend master\n");
1715 return ret;
1716 }
1717
1718 if (!pm_runtime_suspended(dev))
1719 atmel_spi_runtime_suspend(dev);
1720
1721 return 0;
1722 }
1723
1724 static int atmel_spi_resume(struct device *dev)
1725 {
1726 struct spi_master *master = dev_get_drvdata(dev);
1727 struct atmel_spi *as = spi_master_get_devdata(master);
1728 int ret;
1729
1730 ret = clk_prepare_enable(as->clk);
1731 if (ret)
1732 return ret;
1733
1734 atmel_spi_init(as);
1735
1736 clk_disable_unprepare(as->clk);
1737
1738 if (!pm_runtime_suspended(dev)) {
1739 ret = atmel_spi_runtime_resume(dev);
1740 if (ret)
1741 return ret;
1742 }
1743
1744 /* Start the queue running */
1745 ret = spi_master_resume(master);
1746 if (ret)
1747 dev_err(dev, "problem starting queue (%d)\n", ret);
1748
1749 return ret;
1750 }
1751 #endif
1752
1753 static const struct dev_pm_ops atmel_spi_pm_ops = {
1754 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1755 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1756 atmel_spi_runtime_resume, NULL)
1757 };
1758 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1759 #else
1760 #define ATMEL_SPI_PM_OPS NULL
1761 #endif
1762
1763 #if defined(CONFIG_OF)
1764 static const struct of_device_id atmel_spi_dt_ids[] = {
1765 { .compatible = "atmel,at91rm9200-spi" },
1766 { /* sentinel */ }
1767 };
1768
1769 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1770 #endif
1771
1772 static struct platform_driver atmel_spi_driver = {
1773 .driver = {
1774 .name = "atmel_spi",
1775 .pm = ATMEL_SPI_PM_OPS,
1776 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1777 },
1778 .probe = atmel_spi_probe,
1779 .remove = atmel_spi_remove,
1780 };
1781 module_platform_driver(atmel_spi_driver);
1782
1783 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1784 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1785 MODULE_LICENSE("GPL");
1786 MODULE_ALIAS("platform:atmel_spi");
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