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spi: davinci: use spi_device.cs_gpio to store gpio cs per spi device
[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-atmel.c
1 /*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/atmel.h>
23 #include <linux/platform_data/dma-atmel.h>
24 #include <linux/of.h>
25
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/pinctrl/consumer.h>
29
30 /* SPI register offsets */
31 #define SPI_CR 0x0000
32 #define SPI_MR 0x0004
33 #define SPI_RDR 0x0008
34 #define SPI_TDR 0x000c
35 #define SPI_SR 0x0010
36 #define SPI_IER 0x0014
37 #define SPI_IDR 0x0018
38 #define SPI_IMR 0x001c
39 #define SPI_CSR0 0x0030
40 #define SPI_CSR1 0x0034
41 #define SPI_CSR2 0x0038
42 #define SPI_CSR3 0x003c
43 #define SPI_VERSION 0x00fc
44 #define SPI_RPR 0x0100
45 #define SPI_RCR 0x0104
46 #define SPI_TPR 0x0108
47 #define SPI_TCR 0x010c
48 #define SPI_RNPR 0x0110
49 #define SPI_RNCR 0x0114
50 #define SPI_TNPR 0x0118
51 #define SPI_TNCR 0x011c
52 #define SPI_PTCR 0x0120
53 #define SPI_PTSR 0x0124
54
55 /* Bitfields in CR */
56 #define SPI_SPIEN_OFFSET 0
57 #define SPI_SPIEN_SIZE 1
58 #define SPI_SPIDIS_OFFSET 1
59 #define SPI_SPIDIS_SIZE 1
60 #define SPI_SWRST_OFFSET 7
61 #define SPI_SWRST_SIZE 1
62 #define SPI_LASTXFER_OFFSET 24
63 #define SPI_LASTXFER_SIZE 1
64
65 /* Bitfields in MR */
66 #define SPI_MSTR_OFFSET 0
67 #define SPI_MSTR_SIZE 1
68 #define SPI_PS_OFFSET 1
69 #define SPI_PS_SIZE 1
70 #define SPI_PCSDEC_OFFSET 2
71 #define SPI_PCSDEC_SIZE 1
72 #define SPI_FDIV_OFFSET 3
73 #define SPI_FDIV_SIZE 1
74 #define SPI_MODFDIS_OFFSET 4
75 #define SPI_MODFDIS_SIZE 1
76 #define SPI_WDRBT_OFFSET 5
77 #define SPI_WDRBT_SIZE 1
78 #define SPI_LLB_OFFSET 7
79 #define SPI_LLB_SIZE 1
80 #define SPI_PCS_OFFSET 16
81 #define SPI_PCS_SIZE 4
82 #define SPI_DLYBCS_OFFSET 24
83 #define SPI_DLYBCS_SIZE 8
84
85 /* Bitfields in RDR */
86 #define SPI_RD_OFFSET 0
87 #define SPI_RD_SIZE 16
88
89 /* Bitfields in TDR */
90 #define SPI_TD_OFFSET 0
91 #define SPI_TD_SIZE 16
92
93 /* Bitfields in SR */
94 #define SPI_RDRF_OFFSET 0
95 #define SPI_RDRF_SIZE 1
96 #define SPI_TDRE_OFFSET 1
97 #define SPI_TDRE_SIZE 1
98 #define SPI_MODF_OFFSET 2
99 #define SPI_MODF_SIZE 1
100 #define SPI_OVRES_OFFSET 3
101 #define SPI_OVRES_SIZE 1
102 #define SPI_ENDRX_OFFSET 4
103 #define SPI_ENDRX_SIZE 1
104 #define SPI_ENDTX_OFFSET 5
105 #define SPI_ENDTX_SIZE 1
106 #define SPI_RXBUFF_OFFSET 6
107 #define SPI_RXBUFF_SIZE 1
108 #define SPI_TXBUFE_OFFSET 7
109 #define SPI_TXBUFE_SIZE 1
110 #define SPI_NSSR_OFFSET 8
111 #define SPI_NSSR_SIZE 1
112 #define SPI_TXEMPTY_OFFSET 9
113 #define SPI_TXEMPTY_SIZE 1
114 #define SPI_SPIENS_OFFSET 16
115 #define SPI_SPIENS_SIZE 1
116
117 /* Bitfields in CSR0 */
118 #define SPI_CPOL_OFFSET 0
119 #define SPI_CPOL_SIZE 1
120 #define SPI_NCPHA_OFFSET 1
121 #define SPI_NCPHA_SIZE 1
122 #define SPI_CSAAT_OFFSET 3
123 #define SPI_CSAAT_SIZE 1
124 #define SPI_BITS_OFFSET 4
125 #define SPI_BITS_SIZE 4
126 #define SPI_SCBR_OFFSET 8
127 #define SPI_SCBR_SIZE 8
128 #define SPI_DLYBS_OFFSET 16
129 #define SPI_DLYBS_SIZE 8
130 #define SPI_DLYBCT_OFFSET 24
131 #define SPI_DLYBCT_SIZE 8
132
133 /* Bitfields in RCR */
134 #define SPI_RXCTR_OFFSET 0
135 #define SPI_RXCTR_SIZE 16
136
137 /* Bitfields in TCR */
138 #define SPI_TXCTR_OFFSET 0
139 #define SPI_TXCTR_SIZE 16
140
141 /* Bitfields in RNCR */
142 #define SPI_RXNCR_OFFSET 0
143 #define SPI_RXNCR_SIZE 16
144
145 /* Bitfields in TNCR */
146 #define SPI_TXNCR_OFFSET 0
147 #define SPI_TXNCR_SIZE 16
148
149 /* Bitfields in PTCR */
150 #define SPI_RXTEN_OFFSET 0
151 #define SPI_RXTEN_SIZE 1
152 #define SPI_RXTDIS_OFFSET 1
153 #define SPI_RXTDIS_SIZE 1
154 #define SPI_TXTEN_OFFSET 8
155 #define SPI_TXTEN_SIZE 1
156 #define SPI_TXTDIS_OFFSET 9
157 #define SPI_TXTDIS_SIZE 1
158
159 /* Constants for BITS */
160 #define SPI_BITS_8_BPT 0
161 #define SPI_BITS_9_BPT 1
162 #define SPI_BITS_10_BPT 2
163 #define SPI_BITS_11_BPT 3
164 #define SPI_BITS_12_BPT 4
165 #define SPI_BITS_13_BPT 5
166 #define SPI_BITS_14_BPT 6
167 #define SPI_BITS_15_BPT 7
168 #define SPI_BITS_16_BPT 8
169
170 /* Bit manipulation macros */
171 #define SPI_BIT(name) \
172 (1 << SPI_##name##_OFFSET)
173 #define SPI_BF(name, value) \
174 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
175 #define SPI_BFEXT(name, value) \
176 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
177 #define SPI_BFINS(name, value, old) \
178 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
179 | SPI_BF(name, value))
180
181 /* Register access macros */
182 #define spi_readl(port, reg) \
183 __raw_readl((port)->regs + SPI_##reg)
184 #define spi_writel(port, reg, value) \
185 __raw_writel((value), (port)->regs + SPI_##reg)
186
187 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
188 * cache operations; better heuristics consider wordsize and bitrate.
189 */
190 #define DMA_MIN_BYTES 16
191
192 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
193
194 struct atmel_spi_dma {
195 struct dma_chan *chan_rx;
196 struct dma_chan *chan_tx;
197 struct scatterlist sgrx;
198 struct scatterlist sgtx;
199 struct dma_async_tx_descriptor *data_desc_rx;
200 struct dma_async_tx_descriptor *data_desc_tx;
201
202 struct at_dma_slave dma_slave;
203 };
204
205 struct atmel_spi_caps {
206 bool is_spi2;
207 bool has_wdrbt;
208 bool has_dma_support;
209 };
210
211 /*
212 * The core SPI transfer engine just talks to a register bank to set up
213 * DMA transfers; transfer queue progress is driven by IRQs. The clock
214 * framework provides the base clock, subdivided for each spi_device.
215 */
216 struct atmel_spi {
217 spinlock_t lock;
218 unsigned long flags;
219
220 phys_addr_t phybase;
221 void __iomem *regs;
222 int irq;
223 struct clk *clk;
224 struct platform_device *pdev;
225
226 struct spi_transfer *current_transfer;
227 int current_remaining_bytes;
228 int done_status;
229
230 struct completion xfer_completion;
231
232 /* scratch buffer */
233 void *buffer;
234 dma_addr_t buffer_dma;
235
236 struct atmel_spi_caps caps;
237
238 bool use_dma;
239 bool use_pdc;
240 /* dmaengine data */
241 struct atmel_spi_dma dma;
242
243 bool keep_cs;
244 bool cs_active;
245 };
246
247 /* Controller-specific per-slave state */
248 struct atmel_spi_device {
249 unsigned int npcs_pin;
250 u32 csr;
251 };
252
253 #define BUFFER_SIZE PAGE_SIZE
254 #define INVALID_DMA_ADDRESS 0xffffffff
255
256 /*
257 * Version 2 of the SPI controller has
258 * - CR.LASTXFER
259 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
260 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
261 * - SPI_CSRx.CSAAT
262 * - SPI_CSRx.SBCR allows faster clocking
263 */
264 static bool atmel_spi_is_v2(struct atmel_spi *as)
265 {
266 return as->caps.is_spi2;
267 }
268
269 /*
270 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
271 * they assume that spi slave device state will not change on deselect, so
272 * that automagic deselection is OK. ("NPCSx rises if no data is to be
273 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
274 * controllers have CSAAT and friends.
275 *
276 * Since the CSAAT functionality is a bit weird on newer controllers as
277 * well, we use GPIO to control nCSx pins on all controllers, updating
278 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
279 * support active-high chipselects despite the controller's belief that
280 * only active-low devices/systems exists.
281 *
282 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
283 * right when driven with GPIO. ("Mode Fault does not allow more than one
284 * Master on Chip Select 0.") No workaround exists for that ... so for
285 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
286 * and (c) will trigger that first erratum in some cases.
287 */
288
289 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
290 {
291 struct atmel_spi_device *asd = spi->controller_state;
292 unsigned active = spi->mode & SPI_CS_HIGH;
293 u32 mr;
294
295 if (atmel_spi_is_v2(as)) {
296 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
297 /* For the low SPI version, there is a issue that PDC transfer
298 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
299 */
300 spi_writel(as, CSR0, asd->csr);
301 if (as->caps.has_wdrbt) {
302 spi_writel(as, MR,
303 SPI_BF(PCS, ~(0x01 << spi->chip_select))
304 | SPI_BIT(WDRBT)
305 | SPI_BIT(MODFDIS)
306 | SPI_BIT(MSTR));
307 } else {
308 spi_writel(as, MR,
309 SPI_BF(PCS, ~(0x01 << spi->chip_select))
310 | SPI_BIT(MODFDIS)
311 | SPI_BIT(MSTR));
312 }
313
314 mr = spi_readl(as, MR);
315 gpio_set_value(asd->npcs_pin, active);
316 } else {
317 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
318 int i;
319 u32 csr;
320
321 /* Make sure clock polarity is correct */
322 for (i = 0; i < spi->master->num_chipselect; i++) {
323 csr = spi_readl(as, CSR0 + 4 * i);
324 if ((csr ^ cpol) & SPI_BIT(CPOL))
325 spi_writel(as, CSR0 + 4 * i,
326 csr ^ SPI_BIT(CPOL));
327 }
328
329 mr = spi_readl(as, MR);
330 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
331 if (spi->chip_select != 0)
332 gpio_set_value(asd->npcs_pin, active);
333 spi_writel(as, MR, mr);
334 }
335
336 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
337 asd->npcs_pin, active ? " (high)" : "",
338 mr);
339 }
340
341 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
342 {
343 struct atmel_spi_device *asd = spi->controller_state;
344 unsigned active = spi->mode & SPI_CS_HIGH;
345 u32 mr;
346
347 /* only deactivate *this* device; sometimes transfers to
348 * another device may be active when this routine is called.
349 */
350 mr = spi_readl(as, MR);
351 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
352 mr = SPI_BFINS(PCS, 0xf, mr);
353 spi_writel(as, MR, mr);
354 }
355
356 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
357 asd->npcs_pin, active ? " (low)" : "",
358 mr);
359
360 if (atmel_spi_is_v2(as) || spi->chip_select != 0)
361 gpio_set_value(asd->npcs_pin, !active);
362 }
363
364 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
365 {
366 spin_lock_irqsave(&as->lock, as->flags);
367 }
368
369 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
370 {
371 spin_unlock_irqrestore(&as->lock, as->flags);
372 }
373
374 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
375 struct spi_transfer *xfer)
376 {
377 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
378 }
379
380 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
381 struct dma_slave_config *slave_config,
382 u8 bits_per_word)
383 {
384 int err = 0;
385
386 if (bits_per_word > 8) {
387 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
388 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
389 } else {
390 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
391 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
392 }
393
394 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
395 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
396 slave_config->src_maxburst = 1;
397 slave_config->dst_maxburst = 1;
398 slave_config->device_fc = false;
399
400 slave_config->direction = DMA_MEM_TO_DEV;
401 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
402 dev_err(&as->pdev->dev,
403 "failed to configure tx dma channel\n");
404 err = -EINVAL;
405 }
406
407 slave_config->direction = DMA_DEV_TO_MEM;
408 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
409 dev_err(&as->pdev->dev,
410 "failed to configure rx dma channel\n");
411 err = -EINVAL;
412 }
413
414 return err;
415 }
416
417 static bool filter(struct dma_chan *chan, void *pdata)
418 {
419 struct atmel_spi_dma *sl_pdata = pdata;
420 struct at_dma_slave *sl;
421
422 if (!sl_pdata)
423 return false;
424
425 sl = &sl_pdata->dma_slave;
426 if (sl->dma_dev == chan->device->dev) {
427 chan->private = sl;
428 return true;
429 } else {
430 return false;
431 }
432 }
433
434 static int atmel_spi_configure_dma(struct atmel_spi *as)
435 {
436 struct dma_slave_config slave_config;
437 struct device *dev = &as->pdev->dev;
438 int err;
439
440 dma_cap_mask_t mask;
441 dma_cap_zero(mask);
442 dma_cap_set(DMA_SLAVE, mask);
443
444 as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
445 &as->dma,
446 dev, "tx");
447 if (!as->dma.chan_tx) {
448 dev_err(dev,
449 "DMA TX channel not available, SPI unable to use DMA\n");
450 err = -EBUSY;
451 goto error;
452 }
453
454 as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
455 &as->dma,
456 dev, "rx");
457
458 if (!as->dma.chan_rx) {
459 dev_err(dev,
460 "DMA RX channel not available, SPI unable to use DMA\n");
461 err = -EBUSY;
462 goto error;
463 }
464
465 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
466 if (err)
467 goto error;
468
469 dev_info(&as->pdev->dev,
470 "Using %s (tx) and %s (rx) for DMA transfers\n",
471 dma_chan_name(as->dma.chan_tx),
472 dma_chan_name(as->dma.chan_rx));
473 return 0;
474 error:
475 if (as->dma.chan_rx)
476 dma_release_channel(as->dma.chan_rx);
477 if (as->dma.chan_tx)
478 dma_release_channel(as->dma.chan_tx);
479 return err;
480 }
481
482 static void atmel_spi_stop_dma(struct atmel_spi *as)
483 {
484 if (as->dma.chan_rx)
485 as->dma.chan_rx->device->device_control(as->dma.chan_rx,
486 DMA_TERMINATE_ALL, 0);
487 if (as->dma.chan_tx)
488 as->dma.chan_tx->device->device_control(as->dma.chan_tx,
489 DMA_TERMINATE_ALL, 0);
490 }
491
492 static void atmel_spi_release_dma(struct atmel_spi *as)
493 {
494 if (as->dma.chan_rx)
495 dma_release_channel(as->dma.chan_rx);
496 if (as->dma.chan_tx)
497 dma_release_channel(as->dma.chan_tx);
498 }
499
500 /* This function is called by the DMA driver from tasklet context */
501 static void dma_callback(void *data)
502 {
503 struct spi_master *master = data;
504 struct atmel_spi *as = spi_master_get_devdata(master);
505
506 complete(&as->xfer_completion);
507 }
508
509 /*
510 * Next transfer using PIO.
511 */
512 static void atmel_spi_next_xfer_pio(struct spi_master *master,
513 struct spi_transfer *xfer)
514 {
515 struct atmel_spi *as = spi_master_get_devdata(master);
516 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
517
518 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
519
520 /* Make sure data is not remaining in RDR */
521 spi_readl(as, RDR);
522 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
523 spi_readl(as, RDR);
524 cpu_relax();
525 }
526
527 if (xfer->tx_buf) {
528 if (xfer->bits_per_word > 8)
529 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
530 else
531 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
532 } else {
533 spi_writel(as, TDR, 0);
534 }
535
536 dev_dbg(master->dev.parent,
537 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
538 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
539 xfer->bits_per_word);
540
541 /* Enable relevant interrupts */
542 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
543 }
544
545 /*
546 * Submit next transfer for DMA.
547 */
548 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
549 struct spi_transfer *xfer,
550 u32 *plen)
551 {
552 struct atmel_spi *as = spi_master_get_devdata(master);
553 struct dma_chan *rxchan = as->dma.chan_rx;
554 struct dma_chan *txchan = as->dma.chan_tx;
555 struct dma_async_tx_descriptor *rxdesc;
556 struct dma_async_tx_descriptor *txdesc;
557 struct dma_slave_config slave_config;
558 dma_cookie_t cookie;
559 u32 len = *plen;
560
561 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
562
563 /* Check that the channels are available */
564 if (!rxchan || !txchan)
565 return -ENODEV;
566
567 /* release lock for DMA operations */
568 atmel_spi_unlock(as);
569
570 /* prepare the RX dma transfer */
571 sg_init_table(&as->dma.sgrx, 1);
572 if (xfer->rx_buf) {
573 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
574 } else {
575 as->dma.sgrx.dma_address = as->buffer_dma;
576 if (len > BUFFER_SIZE)
577 len = BUFFER_SIZE;
578 }
579
580 /* prepare the TX dma transfer */
581 sg_init_table(&as->dma.sgtx, 1);
582 if (xfer->tx_buf) {
583 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
584 } else {
585 as->dma.sgtx.dma_address = as->buffer_dma;
586 if (len > BUFFER_SIZE)
587 len = BUFFER_SIZE;
588 memset(as->buffer, 0, len);
589 }
590
591 sg_dma_len(&as->dma.sgtx) = len;
592 sg_dma_len(&as->dma.sgrx) = len;
593
594 *plen = len;
595
596 if (atmel_spi_dma_slave_config(as, &slave_config, 8))
597 goto err_exit;
598
599 /* Send both scatterlists */
600 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
601 &as->dma.sgrx,
602 1,
603 DMA_FROM_DEVICE,
604 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
605 NULL);
606 if (!rxdesc)
607 goto err_dma;
608
609 txdesc = txchan->device->device_prep_slave_sg(txchan,
610 &as->dma.sgtx,
611 1,
612 DMA_TO_DEVICE,
613 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
614 NULL);
615 if (!txdesc)
616 goto err_dma;
617
618 dev_dbg(master->dev.parent,
619 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
620 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
621 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
622
623 /* Enable relevant interrupts */
624 spi_writel(as, IER, SPI_BIT(OVRES));
625
626 /* Put the callback on the RX transfer only, that should finish last */
627 rxdesc->callback = dma_callback;
628 rxdesc->callback_param = master;
629
630 /* Submit and fire RX and TX with TX last so we're ready to read! */
631 cookie = rxdesc->tx_submit(rxdesc);
632 if (dma_submit_error(cookie))
633 goto err_dma;
634 cookie = txdesc->tx_submit(txdesc);
635 if (dma_submit_error(cookie))
636 goto err_dma;
637 rxchan->device->device_issue_pending(rxchan);
638 txchan->device->device_issue_pending(txchan);
639
640 /* take back lock */
641 atmel_spi_lock(as);
642 return 0;
643
644 err_dma:
645 spi_writel(as, IDR, SPI_BIT(OVRES));
646 atmel_spi_stop_dma(as);
647 err_exit:
648 atmel_spi_lock(as);
649 return -ENOMEM;
650 }
651
652 static void atmel_spi_next_xfer_data(struct spi_master *master,
653 struct spi_transfer *xfer,
654 dma_addr_t *tx_dma,
655 dma_addr_t *rx_dma,
656 u32 *plen)
657 {
658 struct atmel_spi *as = spi_master_get_devdata(master);
659 u32 len = *plen;
660
661 /* use scratch buffer only when rx or tx data is unspecified */
662 if (xfer->rx_buf)
663 *rx_dma = xfer->rx_dma + xfer->len - *plen;
664 else {
665 *rx_dma = as->buffer_dma;
666 if (len > BUFFER_SIZE)
667 len = BUFFER_SIZE;
668 }
669
670 if (xfer->tx_buf)
671 *tx_dma = xfer->tx_dma + xfer->len - *plen;
672 else {
673 *tx_dma = as->buffer_dma;
674 if (len > BUFFER_SIZE)
675 len = BUFFER_SIZE;
676 memset(as->buffer, 0, len);
677 dma_sync_single_for_device(&as->pdev->dev,
678 as->buffer_dma, len, DMA_TO_DEVICE);
679 }
680
681 *plen = len;
682 }
683
684 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
685 struct spi_device *spi,
686 struct spi_transfer *xfer)
687 {
688 u32 scbr, csr;
689 unsigned long bus_hz;
690
691 /* v1 chips start out at half the peripheral bus speed. */
692 bus_hz = clk_get_rate(as->clk);
693 if (!atmel_spi_is_v2(as))
694 bus_hz /= 2;
695
696 /*
697 * Calculate the lowest divider that satisfies the
698 * constraint, assuming div32/fdiv/mbz == 0.
699 */
700 if (xfer->speed_hz)
701 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
702 else
703 /*
704 * This can happend if max_speed is null.
705 * In this case, we set the lowest possible speed
706 */
707 scbr = 0xff;
708
709 /*
710 * If the resulting divider doesn't fit into the
711 * register bitfield, we can't satisfy the constraint.
712 */
713 if (scbr >= (1 << SPI_SCBR_SIZE)) {
714 dev_err(&spi->dev,
715 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
716 xfer->speed_hz, scbr, bus_hz/255);
717 return -EINVAL;
718 }
719 if (scbr == 0) {
720 dev_err(&spi->dev,
721 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
722 xfer->speed_hz, scbr, bus_hz);
723 return -EINVAL;
724 }
725 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
726 csr = SPI_BFINS(SCBR, scbr, csr);
727 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
728
729 return 0;
730 }
731
732 /*
733 * Submit next transfer for PDC.
734 * lock is held, spi irq is blocked
735 */
736 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
737 struct spi_message *msg,
738 struct spi_transfer *xfer)
739 {
740 struct atmel_spi *as = spi_master_get_devdata(master);
741 u32 len;
742 dma_addr_t tx_dma, rx_dma;
743
744 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
745
746 len = as->current_remaining_bytes;
747 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
748 as->current_remaining_bytes -= len;
749
750 spi_writel(as, RPR, rx_dma);
751 spi_writel(as, TPR, tx_dma);
752
753 if (msg->spi->bits_per_word > 8)
754 len >>= 1;
755 spi_writel(as, RCR, len);
756 spi_writel(as, TCR, len);
757
758 dev_dbg(&msg->spi->dev,
759 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
760 xfer, xfer->len, xfer->tx_buf,
761 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
762 (unsigned long long)xfer->rx_dma);
763
764 if (as->current_remaining_bytes) {
765 len = as->current_remaining_bytes;
766 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
767 as->current_remaining_bytes -= len;
768
769 spi_writel(as, RNPR, rx_dma);
770 spi_writel(as, TNPR, tx_dma);
771
772 if (msg->spi->bits_per_word > 8)
773 len >>= 1;
774 spi_writel(as, RNCR, len);
775 spi_writel(as, TNCR, len);
776
777 dev_dbg(&msg->spi->dev,
778 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
779 xfer, xfer->len, xfer->tx_buf,
780 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
781 (unsigned long long)xfer->rx_dma);
782 }
783
784 /* REVISIT: We're waiting for ENDRX before we start the next
785 * transfer because we need to handle some difficult timing
786 * issues otherwise. If we wait for ENDTX in one transfer and
787 * then starts waiting for ENDRX in the next, it's difficult
788 * to tell the difference between the ENDRX interrupt we're
789 * actually waiting for and the ENDRX interrupt of the
790 * previous transfer.
791 *
792 * It should be doable, though. Just not now...
793 */
794 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
795 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
796 }
797
798 /*
799 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
800 * - The buffer is either valid for CPU access, else NULL
801 * - If the buffer is valid, so is its DMA address
802 *
803 * This driver manages the dma address unless message->is_dma_mapped.
804 */
805 static int
806 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
807 {
808 struct device *dev = &as->pdev->dev;
809
810 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
811 if (xfer->tx_buf) {
812 /* tx_buf is a const void* where we need a void * for the dma
813 * mapping */
814 void *nonconst_tx = (void *)xfer->tx_buf;
815
816 xfer->tx_dma = dma_map_single(dev,
817 nonconst_tx, xfer->len,
818 DMA_TO_DEVICE);
819 if (dma_mapping_error(dev, xfer->tx_dma))
820 return -ENOMEM;
821 }
822 if (xfer->rx_buf) {
823 xfer->rx_dma = dma_map_single(dev,
824 xfer->rx_buf, xfer->len,
825 DMA_FROM_DEVICE);
826 if (dma_mapping_error(dev, xfer->rx_dma)) {
827 if (xfer->tx_buf)
828 dma_unmap_single(dev,
829 xfer->tx_dma, xfer->len,
830 DMA_TO_DEVICE);
831 return -ENOMEM;
832 }
833 }
834 return 0;
835 }
836
837 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
838 struct spi_transfer *xfer)
839 {
840 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
841 dma_unmap_single(master->dev.parent, xfer->tx_dma,
842 xfer->len, DMA_TO_DEVICE);
843 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
844 dma_unmap_single(master->dev.parent, xfer->rx_dma,
845 xfer->len, DMA_FROM_DEVICE);
846 }
847
848 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
849 {
850 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
851 }
852
853 /* Called from IRQ
854 *
855 * Must update "current_remaining_bytes" to keep track of data
856 * to transfer.
857 */
858 static void
859 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
860 {
861 u8 *rxp;
862 u16 *rxp16;
863 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
864
865 if (xfer->rx_buf) {
866 if (xfer->bits_per_word > 8) {
867 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
868 *rxp16 = spi_readl(as, RDR);
869 } else {
870 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
871 *rxp = spi_readl(as, RDR);
872 }
873 } else {
874 spi_readl(as, RDR);
875 }
876 if (xfer->bits_per_word > 8) {
877 if (as->current_remaining_bytes > 2)
878 as->current_remaining_bytes -= 2;
879 else
880 as->current_remaining_bytes = 0;
881 } else {
882 as->current_remaining_bytes--;
883 }
884 }
885
886 /* Interrupt
887 *
888 * No need for locking in this Interrupt handler: done_status is the
889 * only information modified.
890 */
891 static irqreturn_t
892 atmel_spi_pio_interrupt(int irq, void *dev_id)
893 {
894 struct spi_master *master = dev_id;
895 struct atmel_spi *as = spi_master_get_devdata(master);
896 u32 status, pending, imr;
897 struct spi_transfer *xfer;
898 int ret = IRQ_NONE;
899
900 imr = spi_readl(as, IMR);
901 status = spi_readl(as, SR);
902 pending = status & imr;
903
904 if (pending & SPI_BIT(OVRES)) {
905 ret = IRQ_HANDLED;
906 spi_writel(as, IDR, SPI_BIT(OVRES));
907 dev_warn(master->dev.parent, "overrun\n");
908
909 /*
910 * When we get an overrun, we disregard the current
911 * transfer. Data will not be copied back from any
912 * bounce buffer and msg->actual_len will not be
913 * updated with the last xfer.
914 *
915 * We will also not process any remaning transfers in
916 * the message.
917 */
918 as->done_status = -EIO;
919 smp_wmb();
920
921 /* Clear any overrun happening while cleaning up */
922 spi_readl(as, SR);
923
924 complete(&as->xfer_completion);
925
926 } else if (pending & SPI_BIT(RDRF)) {
927 atmel_spi_lock(as);
928
929 if (as->current_remaining_bytes) {
930 ret = IRQ_HANDLED;
931 xfer = as->current_transfer;
932 atmel_spi_pump_pio_data(as, xfer);
933 if (!as->current_remaining_bytes)
934 spi_writel(as, IDR, pending);
935
936 complete(&as->xfer_completion);
937 }
938
939 atmel_spi_unlock(as);
940 } else {
941 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
942 ret = IRQ_HANDLED;
943 spi_writel(as, IDR, pending);
944 }
945
946 return ret;
947 }
948
949 static irqreturn_t
950 atmel_spi_pdc_interrupt(int irq, void *dev_id)
951 {
952 struct spi_master *master = dev_id;
953 struct atmel_spi *as = spi_master_get_devdata(master);
954 u32 status, pending, imr;
955 int ret = IRQ_NONE;
956
957 imr = spi_readl(as, IMR);
958 status = spi_readl(as, SR);
959 pending = status & imr;
960
961 if (pending & SPI_BIT(OVRES)) {
962
963 ret = IRQ_HANDLED;
964
965 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
966 | SPI_BIT(OVRES)));
967
968 /* Clear any overrun happening while cleaning up */
969 spi_readl(as, SR);
970
971 as->done_status = -EIO;
972
973 complete(&as->xfer_completion);
974
975 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
976 ret = IRQ_HANDLED;
977
978 spi_writel(as, IDR, pending);
979
980 complete(&as->xfer_completion);
981 }
982
983 return ret;
984 }
985
986 static int atmel_spi_setup(struct spi_device *spi)
987 {
988 struct atmel_spi *as;
989 struct atmel_spi_device *asd;
990 u32 csr;
991 unsigned int bits = spi->bits_per_word;
992 unsigned int npcs_pin;
993 int ret;
994
995 as = spi_master_get_devdata(spi->master);
996
997 /* see notes above re chipselect */
998 if (!atmel_spi_is_v2(as)
999 && spi->chip_select == 0
1000 && (spi->mode & SPI_CS_HIGH)) {
1001 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1002 return -EINVAL;
1003 }
1004
1005 csr = SPI_BF(BITS, bits - 8);
1006 if (spi->mode & SPI_CPOL)
1007 csr |= SPI_BIT(CPOL);
1008 if (!(spi->mode & SPI_CPHA))
1009 csr |= SPI_BIT(NCPHA);
1010
1011 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1012 *
1013 * DLYBCT would add delays between words, slowing down transfers.
1014 * It could potentially be useful to cope with DMA bottlenecks, but
1015 * in those cases it's probably best to just use a lower bitrate.
1016 */
1017 csr |= SPI_BF(DLYBS, 0);
1018 csr |= SPI_BF(DLYBCT, 0);
1019
1020 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1021 npcs_pin = (unsigned int)spi->controller_data;
1022
1023 if (gpio_is_valid(spi->cs_gpio))
1024 npcs_pin = spi->cs_gpio;
1025
1026 asd = spi->controller_state;
1027 if (!asd) {
1028 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1029 if (!asd)
1030 return -ENOMEM;
1031
1032 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1033 if (ret) {
1034 kfree(asd);
1035 return ret;
1036 }
1037
1038 asd->npcs_pin = npcs_pin;
1039 spi->controller_state = asd;
1040 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1041 }
1042
1043 asd->csr = csr;
1044
1045 dev_dbg(&spi->dev,
1046 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1047 bits, spi->mode, spi->chip_select, csr);
1048
1049 if (!atmel_spi_is_v2(as))
1050 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1051
1052 return 0;
1053 }
1054
1055 static int atmel_spi_one_transfer(struct spi_master *master,
1056 struct spi_message *msg,
1057 struct spi_transfer *xfer)
1058 {
1059 struct atmel_spi *as;
1060 struct spi_device *spi = msg->spi;
1061 u8 bits;
1062 u32 len;
1063 struct atmel_spi_device *asd;
1064 int timeout;
1065 int ret;
1066
1067 as = spi_master_get_devdata(master);
1068
1069 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1070 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1071 return -EINVAL;
1072 }
1073
1074 if (xfer->bits_per_word) {
1075 asd = spi->controller_state;
1076 bits = (asd->csr >> 4) & 0xf;
1077 if (bits != xfer->bits_per_word - 8) {
1078 dev_dbg(&spi->dev,
1079 "you can't yet change bits_per_word in transfers\n");
1080 return -ENOPROTOOPT;
1081 }
1082 }
1083
1084 /*
1085 * DMA map early, for performance (empties dcache ASAP) and
1086 * better fault reporting.
1087 */
1088 if ((!msg->is_dma_mapped)
1089 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1090 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1091 return -ENOMEM;
1092 }
1093
1094 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1095
1096 as->done_status = 0;
1097 as->current_transfer = xfer;
1098 as->current_remaining_bytes = xfer->len;
1099 while (as->current_remaining_bytes) {
1100 reinit_completion(&as->xfer_completion);
1101
1102 if (as->use_pdc) {
1103 atmel_spi_pdc_next_xfer(master, msg, xfer);
1104 } else if (atmel_spi_use_dma(as, xfer)) {
1105 len = as->current_remaining_bytes;
1106 ret = atmel_spi_next_xfer_dma_submit(master,
1107 xfer, &len);
1108 if (ret) {
1109 dev_err(&spi->dev,
1110 "unable to use DMA, fallback to PIO\n");
1111 atmel_spi_next_xfer_pio(master, xfer);
1112 } else {
1113 as->current_remaining_bytes -= len;
1114 if (as->current_remaining_bytes < 0)
1115 as->current_remaining_bytes = 0;
1116 }
1117 } else {
1118 atmel_spi_next_xfer_pio(master, xfer);
1119 }
1120
1121 /* interrupts are disabled, so free the lock for schedule */
1122 atmel_spi_unlock(as);
1123 ret = wait_for_completion_timeout(&as->xfer_completion,
1124 SPI_DMA_TIMEOUT);
1125 atmel_spi_lock(as);
1126 if (WARN_ON(ret == 0)) {
1127 dev_err(&spi->dev,
1128 "spi trasfer timeout, err %d\n", ret);
1129 as->done_status = -EIO;
1130 } else {
1131 ret = 0;
1132 }
1133
1134 if (as->done_status)
1135 break;
1136 }
1137
1138 if (as->done_status) {
1139 if (as->use_pdc) {
1140 dev_warn(master->dev.parent,
1141 "overrun (%u/%u remaining)\n",
1142 spi_readl(as, TCR), spi_readl(as, RCR));
1143
1144 /*
1145 * Clean up DMA registers and make sure the data
1146 * registers are empty.
1147 */
1148 spi_writel(as, RNCR, 0);
1149 spi_writel(as, TNCR, 0);
1150 spi_writel(as, RCR, 0);
1151 spi_writel(as, TCR, 0);
1152 for (timeout = 1000; timeout; timeout--)
1153 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1154 break;
1155 if (!timeout)
1156 dev_warn(master->dev.parent,
1157 "timeout waiting for TXEMPTY");
1158 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1159 spi_readl(as, RDR);
1160
1161 /* Clear any overrun happening while cleaning up */
1162 spi_readl(as, SR);
1163
1164 } else if (atmel_spi_use_dma(as, xfer)) {
1165 atmel_spi_stop_dma(as);
1166 }
1167
1168 if (!msg->is_dma_mapped
1169 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1170 atmel_spi_dma_unmap_xfer(master, xfer);
1171
1172 return 0;
1173
1174 } else {
1175 /* only update length if no error */
1176 msg->actual_length += xfer->len;
1177 }
1178
1179 if (!msg->is_dma_mapped
1180 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1181 atmel_spi_dma_unmap_xfer(master, xfer);
1182
1183 if (xfer->delay_usecs)
1184 udelay(xfer->delay_usecs);
1185
1186 if (xfer->cs_change) {
1187 if (list_is_last(&xfer->transfer_list,
1188 &msg->transfers)) {
1189 as->keep_cs = true;
1190 } else {
1191 as->cs_active = !as->cs_active;
1192 if (as->cs_active)
1193 cs_activate(as, msg->spi);
1194 else
1195 cs_deactivate(as, msg->spi);
1196 }
1197 }
1198
1199 return 0;
1200 }
1201
1202 static int atmel_spi_transfer_one_message(struct spi_master *master,
1203 struct spi_message *msg)
1204 {
1205 struct atmel_spi *as;
1206 struct spi_transfer *xfer;
1207 struct spi_device *spi = msg->spi;
1208 int ret = 0;
1209
1210 as = spi_master_get_devdata(master);
1211
1212 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1213 msg, dev_name(&spi->dev));
1214
1215 atmel_spi_lock(as);
1216 cs_activate(as, spi);
1217
1218 as->cs_active = true;
1219 as->keep_cs = false;
1220
1221 msg->status = 0;
1222 msg->actual_length = 0;
1223
1224 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1225 ret = atmel_spi_one_transfer(master, msg, xfer);
1226 if (ret)
1227 goto msg_done;
1228 }
1229
1230 if (as->use_pdc)
1231 atmel_spi_disable_pdc_transfer(as);
1232
1233 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1234 dev_dbg(&spi->dev,
1235 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1236 xfer, xfer->len,
1237 xfer->tx_buf, &xfer->tx_dma,
1238 xfer->rx_buf, &xfer->rx_dma);
1239 }
1240
1241 msg_done:
1242 if (!as->keep_cs)
1243 cs_deactivate(as, msg->spi);
1244
1245 atmel_spi_unlock(as);
1246
1247 msg->status = as->done_status;
1248 spi_finalize_current_message(spi->master);
1249
1250 return ret;
1251 }
1252
1253 static void atmel_spi_cleanup(struct spi_device *spi)
1254 {
1255 struct atmel_spi_device *asd = spi->controller_state;
1256 unsigned gpio = (unsigned) spi->controller_data;
1257
1258 if (!asd)
1259 return;
1260
1261 spi->controller_state = NULL;
1262 gpio_free(gpio);
1263 kfree(asd);
1264 }
1265
1266 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1267 {
1268 return spi_readl(as, VERSION) & 0x00000fff;
1269 }
1270
1271 static void atmel_get_caps(struct atmel_spi *as)
1272 {
1273 unsigned int version;
1274
1275 version = atmel_get_version(as);
1276 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1277
1278 as->caps.is_spi2 = version > 0x121;
1279 as->caps.has_wdrbt = version >= 0x210;
1280 as->caps.has_dma_support = version >= 0x212;
1281 }
1282
1283 /*-------------------------------------------------------------------------*/
1284
1285 static int atmel_spi_probe(struct platform_device *pdev)
1286 {
1287 struct resource *regs;
1288 int irq;
1289 struct clk *clk;
1290 int ret;
1291 struct spi_master *master;
1292 struct atmel_spi *as;
1293
1294 /* Select default pin state */
1295 pinctrl_pm_select_default_state(&pdev->dev);
1296
1297 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1298 if (!regs)
1299 return -ENXIO;
1300
1301 irq = platform_get_irq(pdev, 0);
1302 if (irq < 0)
1303 return irq;
1304
1305 clk = devm_clk_get(&pdev->dev, "spi_clk");
1306 if (IS_ERR(clk))
1307 return PTR_ERR(clk);
1308
1309 /* setup spi core then atmel-specific driver state */
1310 ret = -ENOMEM;
1311 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1312 if (!master)
1313 goto out_free;
1314
1315 /* the spi->mode bits understood by this driver: */
1316 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1317 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1318 master->dev.of_node = pdev->dev.of_node;
1319 master->bus_num = pdev->id;
1320 master->num_chipselect = master->dev.of_node ? 0 : 4;
1321 master->setup = atmel_spi_setup;
1322 master->transfer_one_message = atmel_spi_transfer_one_message;
1323 master->cleanup = atmel_spi_cleanup;
1324 platform_set_drvdata(pdev, master);
1325
1326 as = spi_master_get_devdata(master);
1327
1328 /*
1329 * Scratch buffer is used for throwaway rx and tx data.
1330 * It's coherent to minimize dcache pollution.
1331 */
1332 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1333 &as->buffer_dma, GFP_KERNEL);
1334 if (!as->buffer)
1335 goto out_free;
1336
1337 spin_lock_init(&as->lock);
1338
1339 as->pdev = pdev;
1340 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1341 if (IS_ERR(as->regs)) {
1342 ret = PTR_ERR(as->regs);
1343 goto out_free_buffer;
1344 }
1345 as->phybase = regs->start;
1346 as->irq = irq;
1347 as->clk = clk;
1348
1349 init_completion(&as->xfer_completion);
1350
1351 atmel_get_caps(as);
1352
1353 as->use_dma = false;
1354 as->use_pdc = false;
1355 if (as->caps.has_dma_support) {
1356 if (atmel_spi_configure_dma(as) == 0)
1357 as->use_dma = true;
1358 } else {
1359 as->use_pdc = true;
1360 }
1361
1362 if (as->caps.has_dma_support && !as->use_dma)
1363 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1364
1365 if (as->use_pdc) {
1366 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1367 0, dev_name(&pdev->dev), master);
1368 } else {
1369 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1370 0, dev_name(&pdev->dev), master);
1371 }
1372 if (ret)
1373 goto out_unmap_regs;
1374
1375 /* Initialize the hardware */
1376 ret = clk_prepare_enable(clk);
1377 if (ret)
1378 goto out_free_irq;
1379 spi_writel(as, CR, SPI_BIT(SWRST));
1380 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1381 if (as->caps.has_wdrbt) {
1382 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1383 | SPI_BIT(MSTR));
1384 } else {
1385 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1386 }
1387
1388 if (as->use_pdc)
1389 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1390 spi_writel(as, CR, SPI_BIT(SPIEN));
1391
1392 /* go! */
1393 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1394 (unsigned long)regs->start, irq);
1395
1396 ret = devm_spi_register_master(&pdev->dev, master);
1397 if (ret)
1398 goto out_free_dma;
1399
1400 return 0;
1401
1402 out_free_dma:
1403 if (as->use_dma)
1404 atmel_spi_release_dma(as);
1405
1406 spi_writel(as, CR, SPI_BIT(SWRST));
1407 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1408 clk_disable_unprepare(clk);
1409 out_free_irq:
1410 out_unmap_regs:
1411 out_free_buffer:
1412 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1413 as->buffer_dma);
1414 out_free:
1415 spi_master_put(master);
1416 return ret;
1417 }
1418
1419 static int atmel_spi_remove(struct platform_device *pdev)
1420 {
1421 struct spi_master *master = platform_get_drvdata(pdev);
1422 struct atmel_spi *as = spi_master_get_devdata(master);
1423
1424 /* reset the hardware and block queue progress */
1425 spin_lock_irq(&as->lock);
1426 if (as->use_dma) {
1427 atmel_spi_stop_dma(as);
1428 atmel_spi_release_dma(as);
1429 }
1430
1431 spi_writel(as, CR, SPI_BIT(SWRST));
1432 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1433 spi_readl(as, SR);
1434 spin_unlock_irq(&as->lock);
1435
1436 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1437 as->buffer_dma);
1438
1439 clk_disable_unprepare(as->clk);
1440
1441 return 0;
1442 }
1443
1444 #ifdef CONFIG_PM_SLEEP
1445 static int atmel_spi_suspend(struct device *dev)
1446 {
1447 struct spi_master *master = dev_get_drvdata(dev);
1448 struct atmel_spi *as = spi_master_get_devdata(master);
1449 int ret;
1450
1451 /* Stop the queue running */
1452 ret = spi_master_suspend(master);
1453 if (ret) {
1454 dev_warn(dev, "cannot suspend master\n");
1455 return ret;
1456 }
1457
1458 clk_disable_unprepare(as->clk);
1459
1460 pinctrl_pm_select_sleep_state(dev);
1461
1462 return 0;
1463 }
1464
1465 static int atmel_spi_resume(struct device *dev)
1466 {
1467 struct spi_master *master = dev_get_drvdata(dev);
1468 struct atmel_spi *as = spi_master_get_devdata(master);
1469 int ret;
1470
1471 pinctrl_pm_select_default_state(dev);
1472
1473 clk_prepare_enable(as->clk);
1474
1475 /* Start the queue running */
1476 ret = spi_master_resume(master);
1477 if (ret)
1478 dev_err(dev, "problem starting queue (%d)\n", ret);
1479
1480 return ret;
1481 }
1482
1483 static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume);
1484
1485 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1486 #else
1487 #define ATMEL_SPI_PM_OPS NULL
1488 #endif
1489
1490 #if defined(CONFIG_OF)
1491 static const struct of_device_id atmel_spi_dt_ids[] = {
1492 { .compatible = "atmel,at91rm9200-spi" },
1493 { /* sentinel */ }
1494 };
1495
1496 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1497 #endif
1498
1499 static struct platform_driver atmel_spi_driver = {
1500 .driver = {
1501 .name = "atmel_spi",
1502 .owner = THIS_MODULE,
1503 .pm = ATMEL_SPI_PM_OPS,
1504 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1505 },
1506 .probe = atmel_spi_probe,
1507 .remove = atmel_spi_remove,
1508 };
1509 module_platform_driver(atmel_spi_driver);
1510
1511 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1512 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1513 MODULE_LICENSE("GPL");
1514 MODULE_ALIAS("platform:atmel_spi");
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