drivers/spi/spi-bcm-qspi.c

   1 /*
   2  * Driver for Broadcom BRCMSTB, NSP,  NS2, Cygnus SPI Controllers
   3  *
   4  * Copyright 2016 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License, version 2, as
   8  * published by the Free Software Foundation (the "GPL").
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License version 2 (GPLv2) for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * version 2 (GPLv2) along with this source code.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/device.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/ioport.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/of.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/slab.h>
  32 #include <linux/spi/spi.h>
  33 #include <linux/sysfs.h>
  34 #include <linux/types.h>
  35 #include "spi-bcm-qspi.h"
  36
  37 #define DRIVER_NAME "bcm_qspi"
  38
  39
  40 /* BSPI register offsets */
  41 #define BSPI_REVISION_ID                        0x000
  42 #define BSPI_SCRATCH                            0x004
  43 #define BSPI_MAST_N_BOOT_CTRL                   0x008
  44 #define BSPI_BUSY_STATUS                        0x00c
  45 #define BSPI_INTR_STATUS                        0x010
  46 #define BSPI_B0_STATUS                          0x014
  47 #define BSPI_B0_CTRL                            0x018
  48 #define BSPI_B1_STATUS                          0x01c
  49 #define BSPI_B1_CTRL                            0x020
  50 #define BSPI_STRAP_OVERRIDE_CTRL                0x024
  51 #define BSPI_FLEX_MODE_ENABLE                   0x028
  52 #define BSPI_BITS_PER_CYCLE                     0x02c
  53 #define BSPI_BITS_PER_PHASE                     0x030
  54 #define BSPI_CMD_AND_MODE_BYTE                  0x034
  55 #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
  56 #define BSPI_BSPI_XOR_VALUE                     0x03c
  57 #define BSPI_BSPI_XOR_ENABLE                    0x040
  58 #define BSPI_BSPI_PIO_MODE_ENABLE               0x044
  59 #define BSPI_BSPI_PIO_IODIR                     0x048
  60 #define BSPI_BSPI_PIO_DATA                      0x04c
  61
  62 /* RAF register offsets */
  63 #define BSPI_RAF_START_ADDR                     0x100
  64 #define BSPI_RAF_NUM_WORDS                      0x104
  65 #define BSPI_RAF_CTRL                           0x108
  66 #define BSPI_RAF_FULLNESS                       0x10c
  67 #define BSPI_RAF_WATERMARK                      0x110
  68 #define BSPI_RAF_STATUS                 0x114
  69 #define BSPI_RAF_READ_DATA                      0x118
  70 #define BSPI_RAF_WORD_CNT                       0x11c
  71 #define BSPI_RAF_CURR_ADDR                      0x120
  72
  73 /* Override mode masks */
  74 #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE       BIT(0)
  75 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL      BIT(1)
  76 #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE     BIT(2)
  77 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD      BIT(3)
  78 #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE    BIT(4)
  79
  80 #define BSPI_ADDRLEN_3BYTES                     3
  81 #define BSPI_ADDRLEN_4BYTES                     4
  82
  83 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
  84
  85 #define BSPI_RAF_CTRL_START_MASK                BIT(0)
  86 #define BSPI_RAF_CTRL_CLEAR_MASK                BIT(1)
  87
  88 #define BSPI_BPP_MODE_SELECT_MASK               BIT(8)
  89 #define BSPI_BPP_ADDR_SELECT_MASK               BIT(16)
  90
  91 #define BSPI_READ_LENGTH                        512
  92
  93 /* MSPI register offsets */
  94 #define MSPI_SPCR0_LSB                          0x000
  95 #define MSPI_SPCR0_MSB                          0x004
  96 #define MSPI_SPCR1_LSB                          0x008
  97 #define MSPI_SPCR1_MSB                          0x00c
  98 #define MSPI_NEWQP                              0x010
  99 #define MSPI_ENDQP                              0x014
 100 #define MSPI_SPCR2                              0x018
 101 #define MSPI_MSPI_STATUS                        0x020
 102 #define MSPI_CPTQP                              0x024
 103 #define MSPI_SPCR3                              0x028
 104 #define MSPI_TXRAM                              0x040
 105 #define MSPI_RXRAM                              0x0c0
 106 #define MSPI_CDRAM                              0x140
 107 #define MSPI_WRITE_LOCK                 0x180
 108
 109 #define MSPI_MASTER_BIT                 BIT(7)
 110
 111 #define MSPI_NUM_CDRAM                          16
 112 #define MSPI_CDRAM_CONT_BIT                     BIT(7)
 113 #define MSPI_CDRAM_BITSE_BIT                    BIT(6)
 114 #define MSPI_CDRAM_PCS                          0xf
 115
 116 #define MSPI_SPCR2_SPE                          BIT(6)
 117 #define MSPI_SPCR2_CONT_AFTER_CMD               BIT(7)
 118
 119 #define MSPI_MSPI_STATUS_SPIF                   BIT(0)
 120
 121 #define INTR_BASE_BIT_SHIFT                     0x02
 122 #define INTR_COUNT                              0x07
 123
 124 #define NUM_CHIPSELECT                          4
 125 #define QSPI_SPBR_MIN                           8U
 126 #define QSPI_SPBR_MAX                           255U
 127
 128 #define OPCODE_DIOR                             0xBB
 129 #define OPCODE_QIOR                             0xEB
 130 #define OPCODE_DIOR_4B                          0xBC
 131 #define OPCODE_QIOR_4B                          0xEC
 132
 133 #define MAX_CMD_SIZE                            6
 134
 135 #define ADDR_4MB_MASK                           GENMASK(22, 0)
 136
 137 /* stop at end of transfer, no other reason */
 138 #define TRANS_STATUS_BREAK_NONE         0
 139 /* stop at end of spi_message */
 140 #define TRANS_STATUS_BREAK_EOM                  1
 141 /* stop at end of spi_transfer if delay */
 142 #define TRANS_STATUS_BREAK_DELAY                2
 143 /* stop at end of spi_transfer if cs_change */
 144 #define TRANS_STATUS_BREAK_CS_CHANGE            4
 145 /* stop if we run out of bytes */
 146 #define TRANS_STATUS_BREAK_NO_BYTES             8
 147
 148 /* events that make us stop filling TX slots */
 149 #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM |         \
 150                                TRANS_STATUS_BREAK_DELAY |               \
 151                                TRANS_STATUS_BREAK_CS_CHANGE)
 152
 153 /* events that make us deassert CS */
 154 #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM |           \
 155                                      TRANS_STATUS_BREAK_CS_CHANGE)
 156
 157 struct bcm_qspi_parms {
 158         u32 speed_hz;
 159         u8 mode;
 160         u8 bits_per_word;
 161 };
 162
 163 struct bcm_xfer_mode {
 164         bool flex_mode;
 165         unsigned int width;
 166         unsigned int addrlen;
 167         unsigned int hp;
 168 };
 169
 170 enum base_type {
 171         MSPI,
 172         BSPI,
 173         CHIP_SELECT,
 174         BASEMAX,
 175 };
 176
 177 enum irq_source {
 178         SINGLE_L2,
 179         MUXED_L1,
 180 };
 181
 182 struct bcm_qspi_irq {
 183         const char *irq_name;
 184         const irq_handler_t irq_handler;
 185         int irq_source;
 186         u32 mask;
 187 };
 188
 189 struct bcm_qspi_dev_id {
 190         const struct bcm_qspi_irq *irqp;
 191         void *dev;
 192 };
 193
 194
 195 struct qspi_trans {
 196         struct spi_transfer *trans;
 197         int byte;
 198         bool mspi_last_trans;
 199 };
 200
 201 struct bcm_qspi {
 202         struct platform_device *pdev;
 203         struct spi_master *master;
 204         struct clk *clk;
 205         u32 base_clk;
 206         u32 max_speed_hz;
 207         void __iomem *base[BASEMAX];
 208
 209         /* Some SoCs provide custom interrupt status register(s) */
 210         struct bcm_qspi_soc_intc        *soc_intc;
 211
 212         struct bcm_qspi_parms last_parms;
 213         struct qspi_trans  trans_pos;
 214         int curr_cs;
 215         int bspi_maj_rev;
 216         int bspi_min_rev;
 217         int bspi_enabled;
 218         struct spi_flash_read_message *bspi_rf_msg;
 219         u32 bspi_rf_msg_idx;
 220         u32 bspi_rf_msg_len;
 221         u32 bspi_rf_msg_status;
 222         struct bcm_xfer_mode xfer_mode;
 223         u32 s3_strap_override_ctrl;
 224         bool bspi_mode;
 225         bool big_endian;
 226         int num_irqs;
 227         struct bcm_qspi_dev_id *dev_ids;
 228         struct completion mspi_done;
 229         struct completion bspi_done;
 230 };
 231
 232 static inline bool has_bspi(struct bcm_qspi *qspi)
 233 {
 234         return qspi->bspi_mode;
 235 }
 236
 237 /* Read qspi controller register*/
 238 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
 239                                 unsigned int offset)
 240 {
 241         return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
 242 }
 243
 244 /* Write qspi controller register*/
 245 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
 246                                   unsigned int offset, unsigned int data)
 247 {
 248         bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
 249 }
 250
 251 /* BSPI helpers */
 252 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
 253 {
 254         int i;
 255
 256         /* this should normally finish within 10us */
 257         for (i = 0; i < 1000; i++) {
 258                 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
 259                         return 0;
 260                 udelay(1);
 261         }
 262         dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
 263         return -EIO;
 264 }
 265
 266 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
 267 {
 268         if (qspi->bspi_maj_rev < 4)
 269                 return true;
 270         return false;
 271 }
 272
 273 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
 274 {
 275         bcm_qspi_bspi_busy_poll(qspi);
 276         /* Force rising edge for the b0/b1 'flush' field */
 277         bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
 278         bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
 279         bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
 280         bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
 281 }
 282
 283 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
 284 {
 285         return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
 286                                 BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
 287 }
 288
 289 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
 290 {
 291         u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
 292
 293         /* BSPI v3 LR is LE only, convert data to host endianness */
 294         if (bcm_qspi_bspi_ver_three(qspi))
 295                 data = le32_to_cpu(data);
 296
 297         return data;
 298 }
 299
 300 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
 301 {
 302         bcm_qspi_bspi_busy_poll(qspi);
 303         bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
 304                        BSPI_RAF_CTRL_START_MASK);
 305 }
 306
 307 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
 308 {
 309         bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
 310                        BSPI_RAF_CTRL_CLEAR_MASK);
 311         bcm_qspi_bspi_flush_prefetch_buffers(qspi);
 312 }
 313
 314 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
 315 {
 316         u32 *buf = (u32 *)qspi->bspi_rf_msg->buf;
 317         u32 data = 0;
 318
 319         dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_msg,
 320                 qspi->bspi_rf_msg->buf, qspi->bspi_rf_msg_len);
 321         while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
 322                 data = bcm_qspi_bspi_lr_read_fifo(qspi);
 323                 if (likely(qspi->bspi_rf_msg_len >= 4) &&
 324                     IS_ALIGNED((uintptr_t)buf, 4)) {
 325                         buf[qspi->bspi_rf_msg_idx++] = data;
 326                         qspi->bspi_rf_msg_len -= 4;
 327                 } else {
 328                         /* Read out remaining bytes, make sure*/
 329                         u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_msg_idx];
 330
 331                         data = cpu_to_le32(data);
 332                         while (qspi->bspi_rf_msg_len) {
 333                                 *cbuf++ = (u8)data;
 334                                 data >>= 8;
 335                                 qspi->bspi_rf_msg_len--;
 336                         }
 337                 }
 338         }
 339 }
 340
 341 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
 342                                           int bpp, int bpc, int flex_mode)
 343 {
 344         bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
 345         bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
 346         bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
 347         bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
 348         bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
 349 }
 350
 351 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
 352                                        struct spi_flash_read_message *msg,
 353                                        int hp)
 354 {
 355         int bpc = 0, bpp = 0;
 356         u8 command = msg->read_opcode;
 357         int width  = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
 358         int addrlen = msg->addr_width;
 359         int addr_nbits = msg->addr_nbits ? msg->addr_nbits : SPI_NBITS_SINGLE;
 360         int flex_mode = 1;
 361
 362         dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
 363                 width, addrlen, hp);
 364
 365         if (addrlen == BSPI_ADDRLEN_4BYTES)
 366                 bpp = BSPI_BPP_ADDR_SELECT_MASK;
 367
 368         bpp |= msg->dummy_bytes * (8/addr_nbits);
 369
 370         switch (width) {
 371         case SPI_NBITS_SINGLE:
 372                 if (addrlen == BSPI_ADDRLEN_3BYTES)
 373                         /* default mode, does not need flex_cmd */
 374                         flex_mode = 0;
 375                 break;
 376         case SPI_NBITS_DUAL:
 377                 bpc = 0x00000001;
 378                 if (hp) {
 379                         bpc |= 0x00010100; /* address and mode are 2-bit */
 380                         bpp = BSPI_BPP_MODE_SELECT_MASK;
 381                 }
 382                 break;
 383         case SPI_NBITS_QUAD:
 384                 bpc = 0x00000002;
 385                 if (hp) {
 386                         bpc |= 0x00020200; /* address and mode are 4-bit */
 387                         bpp |= BSPI_BPP_MODE_SELECT_MASK;
 388                 }
 389                 break;
 390         default:
 391                 return -EINVAL;
 392         }
 393
 394         bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
 395
 396         return 0;
 397 }
 398
 399 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
 400                                       struct spi_flash_read_message *msg,
 401                                       int hp)
 402 {
 403         int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
 404         int addrlen = msg->addr_width;
 405         u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
 406
 407         dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
 408                 width, addrlen, hp);
 409
 410         switch (width) {
 411         case SPI_NBITS_SINGLE:
 412                 /* clear quad/dual mode */
 413                 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
 414                           BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
 415                 break;
 416         case SPI_NBITS_QUAD:
 417                 /* clear dual mode and set quad mode */
 418                 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
 419                 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
 420                 break;
 421         case SPI_NBITS_DUAL:
 422                 /* clear quad mode set dual mode */
 423                 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
 424                 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
 425                 break;
 426         default:
 427                 return -EINVAL;
 428         }
 429
 430         if (addrlen == BSPI_ADDRLEN_4BYTES)
 431                 /* set 4byte mode*/
 432                 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
 433         else
 434                 /* clear 4 byte mode */
 435                 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
 436
 437         /* set the override mode */
 438         data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
 439         bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
 440         bcm_qspi_bspi_set_xfer_params(qspi, msg->read_opcode, 0, 0, 0);
 441
 442         return 0;
 443 }
 444
 445 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
 446                                   struct spi_flash_read_message *msg, int hp)
 447 {
 448         int error = 0;
 449         int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
 450         int addrlen = msg->addr_width;
 451
 452         /* default mode */
 453         qspi->xfer_mode.flex_mode = true;
 454
 455         if (!bcm_qspi_bspi_ver_three(qspi)) {
 456                 u32 val, mask;
 457
 458                 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
 459                 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
 460                 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
 461                         qspi->xfer_mode.flex_mode = false;
 462                         bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
 463                         error = bcm_qspi_bspi_set_override(qspi, msg, hp);
 464                 }
 465         }
 466
 467         if (qspi->xfer_mode.flex_mode)
 468                 error = bcm_qspi_bspi_set_flex_mode(qspi, msg, hp);
 469
 470         if (error) {
 471                 dev_warn(&qspi->pdev->dev,
 472                          "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
 473                          width, addrlen, hp);
 474         } else if (qspi->xfer_mode.width != width ||
 475                    qspi->xfer_mode.addrlen != addrlen ||
 476                    qspi->xfer_mode.hp != hp) {
 477                 qspi->xfer_mode.width = width;
 478                 qspi->xfer_mode.addrlen = addrlen;
 479                 qspi->xfer_mode.hp = hp;
 480                 dev_dbg(&qspi->pdev->dev,
 481                         "cs:%d %d-lane output, %d-byte address%s\n",
 482                         qspi->curr_cs,
 483                         qspi->xfer_mode.width,
 484                         qspi->xfer_mode.addrlen,
 485                         qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
 486         }
 487
 488         return error;
 489 }
 490
 491 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
 492 {
 493         if (!has_bspi(qspi))
 494                 return;
 495
 496         qspi->bspi_enabled = 1;
 497         if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
 498                 return;
 499
 500         bcm_qspi_bspi_flush_prefetch_buffers(qspi);
 501         udelay(1);
 502         bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
 503         udelay(1);
 504 }
 505
 506 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
 507 {
 508         if (!has_bspi(qspi))
 509                 return;
 510
 511         qspi->bspi_enabled = 0;
 512         if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
 513                 return;
 514
 515         bcm_qspi_bspi_busy_poll(qspi);
 516         bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
 517         udelay(1);
 518 }
 519
 520 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
 521 {
 522         u32 rd = 0;
 523         u32 wr = 0;
 524
 525         if (qspi->base[CHIP_SELECT]) {
 526                 rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
 527                 wr = (rd & ~0xff) | (1 << cs);
 528                 if (rd == wr)
 529                         return;
 530                 bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
 531                 usleep_range(10, 20);
 532         }
 533
 534         dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
 535         qspi->curr_cs = cs;
 536 }
 537
 538 /* MSPI helpers */
 539 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
 540                                   const struct bcm_qspi_parms *xp)
 541 {
 542         u32 spcr, spbr = 0;
 543
 544         if (xp->speed_hz)
 545                 spbr = qspi->base_clk / (2 * xp->speed_hz);
 546
 547         spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
 548         bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
 549
 550         spcr = MSPI_MASTER_BIT;
 551         /* for 16 bit the data should be zero */
 552         if (xp->bits_per_word != 16)
 553                 spcr |= xp->bits_per_word << 2;
 554         spcr |= xp->mode & 3;
 555         bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
 556
 557         qspi->last_parms = *xp;
 558 }
 559
 560 static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
 561                                   struct spi_device *spi,
 562                                   struct spi_transfer *trans)
 563 {
 564         struct bcm_qspi_parms xp;
 565
 566         xp.speed_hz = trans->speed_hz;
 567         xp.bits_per_word = trans->bits_per_word;
 568         xp.mode = spi->mode;
 569
 570         bcm_qspi_hw_set_parms(qspi, &xp);
 571 }
 572
 573 static int bcm_qspi_setup(struct spi_device *spi)
 574 {
 575         struct bcm_qspi_parms *xp;
 576
 577         if (spi->bits_per_word > 16)
 578                 return -EINVAL;
 579
 580         xp = spi_get_ctldata(spi);
 581         if (!xp) {
 582                 xp = kzalloc(sizeof(*xp), GFP_KERNEL);
 583                 if (!xp)
 584                         return -ENOMEM;
 585                 spi_set_ctldata(spi, xp);
 586         }
 587         xp->speed_hz = spi->max_speed_hz;
 588         xp->mode = spi->mode;
 589
 590         if (spi->bits_per_word)
 591                 xp->bits_per_word = spi->bits_per_word;
 592         else
 593                 xp->bits_per_word = 8;
 594
 595         return 0;
 596 }
 597
 598 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
 599                                            struct qspi_trans *qt)
 600 {
 601         if (qt->mspi_last_trans &&
 602             spi_transfer_is_last(qspi->master, qt->trans))
 603                 return true;
 604         else
 605                 return false;
 606 }
 607
 608 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
 609                                         struct qspi_trans *qt, int flags)
 610 {
 611         int ret = TRANS_STATUS_BREAK_NONE;
 612
 613         /* count the last transferred bytes */
 614         if (qt->trans->bits_per_word <= 8)
 615                 qt->byte++;
 616         else
 617                 qt->byte += 2;
 618
 619         if (qt->byte >= qt->trans->len) {
 620                 /* we're at the end of the spi_transfer */
 621                 /* in TX mode, need to pause for a delay or CS change */
 622                 if (qt->trans->delay_usecs &&
 623                     (flags & TRANS_STATUS_BREAK_DELAY))
 624                         ret |= TRANS_STATUS_BREAK_DELAY;
 625                 if (qt->trans->cs_change &&
 626                     (flags & TRANS_STATUS_BREAK_CS_CHANGE))
 627                         ret |= TRANS_STATUS_BREAK_CS_CHANGE;
 628                 if (ret)
 629                         goto done;
 630
 631                 dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
 632                 if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
 633                         ret = TRANS_STATUS_BREAK_EOM;
 634                 else
 635                         ret = TRANS_STATUS_BREAK_NO_BYTES;
 636
 637                 qt->trans = NULL;
 638         }
 639
 640 done:
 641         dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
 642                 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
 643         return ret;
 644 }
 645
 646 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
 647 {
 648         u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
 649
 650         /* mask out reserved bits */
 651         return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
 652 }
 653
 654 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
 655 {
 656         u32 reg_offset = MSPI_RXRAM;
 657         u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
 658         u32 msb_offset = reg_offset + (slot << 3);
 659
 660         return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
 661                 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
 662 }
 663
 664 static void read_from_hw(struct bcm_qspi *qspi, int slots)
 665 {
 666         struct qspi_trans tp;
 667         int slot;
 668
 669         bcm_qspi_disable_bspi(qspi);
 670
 671         if (slots > MSPI_NUM_CDRAM) {
 672                 /* should never happen */
 673                 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
 674                 return;
 675         }
 676
 677         tp = qspi->trans_pos;
 678
 679         for (slot = 0; slot < slots; slot++) {
 680                 if (tp.trans->bits_per_word <= 8) {
 681                         u8 *buf = tp.trans->rx_buf;
 682
 683                         if (buf)
 684                                 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
 685                         dev_dbg(&qspi->pdev->dev, "RD %02x\n",
 686                                 buf ? buf[tp.byte] : 0xff);
 687                 } else {
 688                         u16 *buf = tp.trans->rx_buf;
 689
 690                         if (buf)
 691                                 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
 692                                                                       slot);
 693                         dev_dbg(&qspi->pdev->dev, "RD %04x\n",
 694                                 buf ? buf[tp.byte] : 0xffff);
 695                 }
 696
 697                 update_qspi_trans_byte_count(qspi, &tp,
 698                                              TRANS_STATUS_BREAK_NONE);
 699         }
 700
 701         qspi->trans_pos = tp;
 702 }
 703
 704 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
 705                                        u8 val)
 706 {
 707         u32 reg_offset = MSPI_TXRAM + (slot << 3);
 708
 709         /* mask out reserved bits */
 710         bcm_qspi_write(qspi, MSPI, reg_offset, val);
 711 }
 712
 713 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
 714                                         u16 val)
 715 {
 716         u32 reg_offset = MSPI_TXRAM;
 717         u32 msb_offset = reg_offset + (slot << 3);
 718         u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
 719
 720         bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
 721         bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
 722 }
 723
 724 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
 725 {
 726         return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
 727 }
 728
 729 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
 730 {
 731         bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
 732 }
 733
 734 /* Return number of slots written */
 735 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
 736 {
 737         struct qspi_trans tp;
 738         int slot = 0, tstatus = 0;
 739         u32 mspi_cdram = 0;
 740
 741         bcm_qspi_disable_bspi(qspi);
 742         tp = qspi->trans_pos;
 743         bcm_qspi_update_parms(qspi, spi, tp.trans);
 744
 745         /* Run until end of transfer or reached the max data */
 746         while (!tstatus && slot < MSPI_NUM_CDRAM) {
 747                 if (tp.trans->bits_per_word <= 8) {
 748                         const u8 *buf = tp.trans->tx_buf;
 749                         u8 val = buf ? buf[tp.byte] : 0xff;
 750
 751                         write_txram_slot_u8(qspi, slot, val);
 752                         dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
 753                 } else {
 754                         const u16 *buf = tp.trans->tx_buf;
 755                         u16 val = buf ? buf[tp.byte / 2] : 0xffff;
 756
 757                         write_txram_slot_u16(qspi, slot, val);
 758                         dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
 759                 }
 760                 mspi_cdram = MSPI_CDRAM_CONT_BIT;
 761
 762                 if (has_bspi(qspi))
 763                         mspi_cdram &= ~1;
 764                 else
 765                         mspi_cdram |= (~(1 << spi->chip_select) &
 766                                        MSPI_CDRAM_PCS);
 767
 768                 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
 769                                 MSPI_CDRAM_BITSE_BIT);
 770
 771                 write_cdram_slot(qspi, slot, mspi_cdram);
 772
 773                 tstatus = update_qspi_trans_byte_count(qspi, &tp,
 774                                                        TRANS_STATUS_BREAK_TX);
 775                 slot++;
 776         }
 777
 778         if (!slot) {
 779                 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
 780                 goto done;
 781         }
 782
 783         dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
 784         bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
 785         bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
 786
 787         if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
 788                 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
 789                         ~MSPI_CDRAM_CONT_BIT;
 790                 write_cdram_slot(qspi, slot - 1, mspi_cdram);
 791         }
 792
 793         if (has_bspi(qspi))
 794                 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
 795
 796         /* Must flush previous writes before starting MSPI operation */
 797         mb();
 798         /* Set cont | spe | spifie */
 799         bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
 800
 801 done:
 802         return slot;
 803 }
 804
 805 static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
 806                                     struct spi_flash_read_message *msg)
 807 {
 808         struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
 809         u32 addr = 0, len, rdlen, len_words;
 810         int ret = 0;
 811         unsigned long timeo = msecs_to_jiffies(100);
 812         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
 813
 814         if (bcm_qspi_bspi_ver_three(qspi))
 815                 if (msg->addr_width == BSPI_ADDRLEN_4BYTES)
 816                         return -EIO;
 817
 818         bcm_qspi_chip_select(qspi, spi->chip_select);
 819         bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
 820
 821         /*
 822          * when using flex mode we need to send
 823          * the upper address byte to bspi
 824          */
 825         if (bcm_qspi_bspi_ver_three(qspi) == false) {
 826                 addr = msg->from & 0xff000000;
 827                 bcm_qspi_write(qspi, BSPI,
 828                                BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
 829         }
 830
 831         if (!qspi->xfer_mode.flex_mode)
 832                 addr = msg->from;
 833         else
 834                 addr = msg->from & 0x00ffffff;
 835
 836         if (bcm_qspi_bspi_ver_three(qspi) == true)
 837                 addr = (addr + 0xc00000) & 0xffffff;
 838
 839         /*
 840          * read into the entire buffer by breaking the reads
 841          * into RAF buffer read lengths
 842          */
 843         len = msg->len;
 844         qspi->bspi_rf_msg_idx = 0;
 845
 846         do {
 847                 if (len > BSPI_READ_LENGTH)
 848                         rdlen = BSPI_READ_LENGTH;
 849                 else
 850                         rdlen = len;
 851
 852                 reinit_completion(&qspi->bspi_done);
 853                 bcm_qspi_enable_bspi(qspi);
 854                 len_words = (rdlen + 3) >> 2;
 855                 qspi->bspi_rf_msg = msg;
 856                 qspi->bspi_rf_msg_status = 0;
 857                 qspi->bspi_rf_msg_len = rdlen;
 858                 dev_dbg(&qspi->pdev->dev,
 859                         "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
 860                 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
 861                 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
 862                 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
 863                 if (qspi->soc_intc) {
 864                         /*
 865                          * clear soc MSPI and BSPI interrupts and enable
 866                          * BSPI interrupts.
 867                          */
 868                         soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
 869                         soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
 870                 }
 871
 872                 /* Must flush previous writes before starting BSPI operation */
 873                 mb();
 874                 bcm_qspi_bspi_lr_start(qspi);
 875                 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
 876                         dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
 877                         ret = -ETIMEDOUT;
 878                         break;
 879                 }
 880
 881                 /* set msg return length */
 882                 msg->retlen += rdlen;
 883                 addr += rdlen;
 884                 len -= rdlen;
 885         } while (len);
 886
 887         return ret;
 888 }
 889
 890 static int bcm_qspi_transfer_one(struct spi_master *master,
 891                                  struct spi_device *spi,
 892                                  struct spi_transfer *trans)
 893 {
 894         struct bcm_qspi *qspi = spi_master_get_devdata(master);
 895         int slots;
 896         unsigned long timeo = msecs_to_jiffies(100);
 897
 898         bcm_qspi_chip_select(qspi, spi->chip_select);
 899         qspi->trans_pos.trans = trans;
 900         qspi->trans_pos.byte = 0;
 901
 902         while (qspi->trans_pos.byte < trans->len) {
 903                 reinit_completion(&qspi->mspi_done);
 904
 905                 slots = write_to_hw(qspi, spi);
 906                 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
 907                         dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
 908                         return -ETIMEDOUT;
 909                 }
 910
 911                 read_from_hw(qspi, slots);
 912         }
 913
 914         return 0;
 915 }
 916
 917 static int bcm_qspi_mspi_flash_read(struct spi_device *spi,
 918                                     struct spi_flash_read_message *msg)
 919 {
 920         struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
 921         struct spi_transfer t[2];
 922         u8 cmd[6];
 923         int ret;
 924
 925         memset(cmd, 0, sizeof(cmd));
 926         memset(t, 0, sizeof(t));
 927
 928         /* tx */
 929         /* opcode is in cmd[0] */
 930         cmd[0] = msg->read_opcode;
 931         cmd[1] = msg->from >> (msg->addr_width * 8 -  8);
 932         cmd[2] = msg->from >> (msg->addr_width * 8 - 16);
 933         cmd[3] = msg->from >> (msg->addr_width * 8 - 24);
 934         cmd[4] = msg->from >> (msg->addr_width * 8 - 32);
 935         t[0].tx_buf = cmd;
 936         t[0].len = msg->addr_width + msg->dummy_bytes + 1;
 937         t[0].bits_per_word = spi->bits_per_word;
 938         t[0].tx_nbits = msg->opcode_nbits;
 939         /* lets mspi know that this is not last transfer */
 940         qspi->trans_pos.mspi_last_trans = false;
 941         ret = bcm_qspi_transfer_one(spi->master, spi, &t[0]);
 942
 943         /* rx */
 944         qspi->trans_pos.mspi_last_trans = true;
 945         if (!ret) {
 946                 /* rx */
 947                 t[1].rx_buf = msg->buf;
 948                 t[1].len = msg->len;
 949                 t[1].rx_nbits =  msg->data_nbits;
 950                 t[1].bits_per_word = spi->bits_per_word;
 951                 ret = bcm_qspi_transfer_one(spi->master, spi, &t[1]);
 952         }
 953
 954         if (!ret)
 955                 msg->retlen = msg->len;
 956
 957         return ret;
 958 }
 959
 960 static int bcm_qspi_flash_read(struct spi_device *spi,
 961                                struct spi_flash_read_message *msg)
 962 {
 963         struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
 964         int ret = 0;
 965         bool mspi_read = false;
 966         u32 addr, len;
 967         u_char *buf;
 968
 969         buf = msg->buf;
 970         addr = msg->from;
 971         len = msg->len;
 972
 973         if (bcm_qspi_bspi_ver_three(qspi) == true) {
 974                 /*
 975                  * The address coming into this function is a raw flash offset.
 976                  * But for BSPI <= V3, we need to convert it to a remapped BSPI
 977                  * address. If it crosses a 4MB boundary, just revert back to
 978                  * using MSPI.
 979                  */
 980                 addr = (addr + 0xc00000) & 0xffffff;
 981
 982                 if ((~ADDR_4MB_MASK & addr) ^
 983                     (~ADDR_4MB_MASK & (addr + len - 1)))
 984                         mspi_read = true;
 985         }
 986
 987         /* non-aligned and very short transfers are handled by MSPI */
 988         if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
 989             len < 4)
 990                 mspi_read = true;
 991
 992         if (mspi_read)
 993                 return bcm_qspi_mspi_flash_read(spi, msg);
 994
 995         ret = bcm_qspi_bspi_set_mode(qspi, msg, -1);
 996
 997         if (!ret)
 998                 ret = bcm_qspi_bspi_flash_read(spi, msg);
 999
1000         return ret;
1001 }
1002
1003 static void bcm_qspi_cleanup(struct spi_device *spi)
1004 {
1005         struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
1006
1007         kfree(xp);
1008 }
1009
1010 static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
1011 {
1012         struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1013         struct bcm_qspi *qspi = qspi_dev_id->dev;
1014         u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1015
1016         if (status & MSPI_MSPI_STATUS_SPIF) {
1017                 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1018                 /* clear interrupt */
1019                 status &= ~MSPI_MSPI_STATUS_SPIF;
1020                 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1021                 if (qspi->soc_intc)
1022                         soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
1023                 complete(&qspi->mspi_done);
1024                 return IRQ_HANDLED;
1025         }
1026
1027         return IRQ_NONE;
1028 }
1029
1030 static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
1031 {
1032         struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1033         struct bcm_qspi *qspi = qspi_dev_id->dev;
1034         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1035         u32 status = qspi_dev_id->irqp->mask;
1036
1037         if (qspi->bspi_enabled && qspi->bspi_rf_msg) {
1038                 bcm_qspi_bspi_lr_data_read(qspi);
1039                 if (qspi->bspi_rf_msg_len == 0) {
1040                         qspi->bspi_rf_msg = NULL;
1041                         if (qspi->soc_intc) {
1042                                 /* disable soc BSPI interrupt */
1043                                 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
1044                                                            false);
1045                                 /* indicate done */
1046                                 status = INTR_BSPI_LR_SESSION_DONE_MASK;
1047                         }
1048
1049                         if (qspi->bspi_rf_msg_status)
1050                                 bcm_qspi_bspi_lr_clear(qspi);
1051                         else
1052                                 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1053                 }
1054
1055                 if (qspi->soc_intc)
1056                         /* clear soc BSPI interrupt */
1057                         soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
1058         }
1059
1060         status &= INTR_BSPI_LR_SESSION_DONE_MASK;
1061         if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0)
1062                 complete(&qspi->bspi_done);
1063
1064         return IRQ_HANDLED;
1065 }
1066
1067 static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
1068 {
1069         struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1070         struct bcm_qspi *qspi = qspi_dev_id->dev;
1071         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1072
1073         dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1074         qspi->bspi_rf_msg_status = -EIO;
1075         if (qspi->soc_intc)
1076                 /* clear soc interrupt */
1077                 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
1078
1079         complete(&qspi->bspi_done);
1080         return IRQ_HANDLED;
1081 }
1082
1083 static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
1084 {
1085         struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1086         struct bcm_qspi *qspi = qspi_dev_id->dev;
1087         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1088         irqreturn_t ret = IRQ_NONE;
1089
1090         if (soc_intc) {
1091                 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
1092
1093                 if (status & MSPI_DONE)
1094                         ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
1095                 else if (status & BSPI_DONE)
1096                         ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
1097                 else if (status & BSPI_ERR)
1098                         ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
1099         }
1100
1101         return ret;
1102 }
1103
1104 static const struct bcm_qspi_irq qspi_irq_tab[] = {
1105         {
1106                 .irq_name = "spi_lr_fullness_reached",
1107                 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1108                 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
1109         },
1110         {
1111                 .irq_name = "spi_lr_session_aborted",
1112                 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1113                 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
1114         },
1115         {
1116                 .irq_name = "spi_lr_impatient",
1117                 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1118                 .mask = INTR_BSPI_LR_IMPATIENT_MASK,
1119         },
1120         {
1121                 .irq_name = "spi_lr_session_done",
1122                 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1123                 .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
1124         },
1125 #ifdef QSPI_INT_DEBUG
1126         /* this interrupt is for debug purposes only, dont request irq */
1127         {
1128                 .irq_name = "spi_lr_overread",
1129                 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1130                 .mask = INTR_BSPI_LR_OVERREAD_MASK,
1131         },
1132 #endif
1133         {
1134                 .irq_name = "mspi_done",
1135                 .irq_handler = bcm_qspi_mspi_l2_isr,
1136                 .mask = INTR_MSPI_DONE_MASK,
1137         },
1138         {
1139                 .irq_name = "mspi_halted",
1140                 .irq_handler = bcm_qspi_mspi_l2_isr,
1141                 .mask = INTR_MSPI_HALTED_MASK,
1142         },
1143         {
1144                 /* single muxed L1 interrupt source */
1145                 .irq_name = "spi_l1_intr",
1146                 .irq_handler = bcm_qspi_l1_isr,
1147                 .irq_source = MUXED_L1,
1148                 .mask = QSPI_INTERRUPTS_ALL,
1149         },
1150 };
1151
1152 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1153 {
1154         u32 val = 0;
1155
1156         val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1157         qspi->bspi_maj_rev = (val >> 8) & 0xff;
1158         qspi->bspi_min_rev = val & 0xff;
1159         if (!(bcm_qspi_bspi_ver_three(qspi))) {
1160                 /* Force mapping of BSPI address -> flash offset */
1161                 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1162                 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1163         }
1164         qspi->bspi_enabled = 1;
1165         bcm_qspi_disable_bspi(qspi);
1166         bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1167         bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1168 }
1169
1170 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1171 {
1172         struct bcm_qspi_parms parms;
1173
1174         bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1175         bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1176         bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1177         bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1178         bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1179
1180         parms.mode = SPI_MODE_3;
1181         parms.bits_per_word = 8;
1182         parms.speed_hz = qspi->max_speed_hz;
1183         bcm_qspi_hw_set_parms(qspi, &parms);
1184
1185         if (has_bspi(qspi))
1186                 bcm_qspi_bspi_init(qspi);
1187 }
1188
1189 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1190 {
1191         bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1192         if (has_bspi(qspi))
1193                 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1194
1195 }
1196
1197 static const struct of_device_id bcm_qspi_of_match[] = {
1198         { .compatible = "brcm,spi-bcm-qspi" },
1199         {},
1200 };
1201 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
1202
1203 int bcm_qspi_probe(struct platform_device *pdev,
1204                    struct bcm_qspi_soc_intc *soc_intc)
1205 {
1206         struct device *dev = &pdev->dev;
1207         struct bcm_qspi *qspi;
1208         struct spi_master *master;
1209         struct resource *res;
1210         int irq, ret = 0, num_ints = 0;
1211         u32 val;
1212         const char *name = NULL;
1213         int num_irqs = ARRAY_SIZE(qspi_irq_tab);
1214
1215         /* We only support device-tree instantiation */
1216         if (!dev->of_node)
1217                 return -ENODEV;
1218
1219         if (!of_match_node(bcm_qspi_of_match, dev->of_node))
1220                 return -ENODEV;
1221
1222         master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
1223         if (!master) {
1224                 dev_err(dev, "error allocating spi_master\n");
1225                 return -ENOMEM;
1226         }
1227
1228         qspi = spi_master_get_devdata(master);
1229         qspi->pdev = pdev;
1230         qspi->trans_pos.trans = NULL;
1231         qspi->trans_pos.byte = 0;
1232         qspi->trans_pos.mspi_last_trans = true;
1233         qspi->master = master;
1234
1235         master->bus_num = -1;
1236         master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
1237         master->setup = bcm_qspi_setup;
1238         master->transfer_one = bcm_qspi_transfer_one;
1239         master->spi_flash_read = bcm_qspi_flash_read;
1240         master->cleanup = bcm_qspi_cleanup;
1241         master->dev.of_node = dev->of_node;
1242         master->num_chipselect = NUM_CHIPSELECT;
1243
1244         qspi->big_endian = of_device_is_big_endian(dev->of_node);
1245
1246         if (!of_property_read_u32(dev->of_node, "num-cs", &val))
1247                 master->num_chipselect = val;
1248
1249         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
1250         if (!res)
1251                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1252                                                    "mspi");
1253
1254         if (res) {
1255                 qspi->base[MSPI]  = devm_ioremap_resource(dev, res);
1256                 if (IS_ERR(qspi->base[MSPI])) {
1257                         ret = PTR_ERR(qspi->base[MSPI]);
1258                         goto qspi_resource_err;
1259                 }
1260         } else {
1261                 goto qspi_resource_err;
1262         }
1263
1264         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
1265         if (res) {
1266                 qspi->base[BSPI]  = devm_ioremap_resource(dev, res);
1267                 if (IS_ERR(qspi->base[BSPI])) {
1268                         ret = PTR_ERR(qspi->base[BSPI]);
1269                         goto qspi_resource_err;
1270                 }
1271                 qspi->bspi_mode = true;
1272         } else {
1273                 qspi->bspi_mode = false;
1274         }
1275
1276         dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1277
1278         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
1279         if (res) {
1280                 qspi->base[CHIP_SELECT]  = devm_ioremap_resource(dev, res);
1281                 if (IS_ERR(qspi->base[CHIP_SELECT])) {
1282                         ret = PTR_ERR(qspi->base[CHIP_SELECT]);
1283                         goto qspi_resource_err;
1284                 }
1285         }
1286
1287         qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1288                                 GFP_KERNEL);
1289         if (!qspi->dev_ids) {
1290                 ret = -ENOMEM;
1291                 goto qspi_resource_err;
1292         }
1293
1294         for (val = 0; val < num_irqs; val++) {
1295                 irq = -1;
1296                 name = qspi_irq_tab[val].irq_name;
1297                 if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
1298                         /* get the l2 interrupts */
1299                         irq = platform_get_irq_byname(pdev, name);
1300                 } else if (!num_ints && soc_intc) {
1301                         /* all mspi, bspi intrs muxed to one L1 intr */
1302                         irq = platform_get_irq(pdev, 0);
1303                 }
1304
1305                 if (irq  >= 0) {
1306                         ret = devm_request_irq(&pdev->dev, irq,
1307                                                qspi_irq_tab[val].irq_handler, 0,
1308                                                name,
1309                                                &qspi->dev_ids[val]);
1310                         if (ret < 0) {
1311                                 dev_err(&pdev->dev, "IRQ %s not found\n", name);
1312                                 goto qspi_probe_err;
1313                         }
1314
1315                         qspi->dev_ids[val].dev = qspi;
1316                         qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1317                         num_ints++;
1318                         dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
1319                                 qspi_irq_tab[val].irq_name,
1320                                 irq);
1321                 }
1322         }
1323
1324         if (!num_ints) {
1325                 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
1326                 ret = -EINVAL;
1327                 goto qspi_probe_err;
1328         }
1329
1330         /*
1331          * Some SoCs integrate spi controller (e.g., its interrupt bits)
1332          * in specific ways
1333          */
1334         if (soc_intc) {
1335                 qspi->soc_intc = soc_intc;
1336                 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1337         } else {
1338                 qspi->soc_intc = NULL;
1339         }
1340
1341         qspi->clk = devm_clk_get(&pdev->dev, NULL);
1342         if (IS_ERR(qspi->clk)) {
1343                 dev_warn(dev, "unable to get clock\n");
1344                 ret = PTR_ERR(qspi->clk);
1345                 goto qspi_probe_err;
1346         }
1347
1348         ret = clk_prepare_enable(qspi->clk);
1349         if (ret) {
1350                 dev_err(dev, "failed to prepare clock\n");
1351                 goto qspi_probe_err;
1352         }
1353
1354         qspi->base_clk = clk_get_rate(qspi->clk);
1355         qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
1356
1357         bcm_qspi_hw_init(qspi);
1358         init_completion(&qspi->mspi_done);
1359         init_completion(&qspi->bspi_done);
1360         qspi->curr_cs = -1;
1361
1362         platform_set_drvdata(pdev, qspi);
1363
1364         qspi->xfer_mode.width = -1;
1365         qspi->xfer_mode.addrlen = -1;
1366         qspi->xfer_mode.hp = -1;
1367
1368         ret = devm_spi_register_master(&pdev->dev, master);
1369         if (ret < 0) {
1370                 dev_err(dev, "can't register master\n");
1371                 goto qspi_reg_err;
1372         }
1373
1374         return 0;
1375
1376 qspi_reg_err:
1377         bcm_qspi_hw_uninit(qspi);
1378         clk_disable_unprepare(qspi->clk);
1379 qspi_probe_err:
1380         kfree(qspi->dev_ids);
1381 qspi_resource_err:
1382         spi_master_put(master);
1383         return ret;
1384 }
1385 /* probe function to be called by SoC specific platform driver probe */
1386 EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1387
1388 int bcm_qspi_remove(struct platform_device *pdev)
1389 {
1390         struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1391
1392         bcm_qspi_hw_uninit(qspi);
1393         clk_disable_unprepare(qspi->clk);
1394         kfree(qspi->dev_ids);
1395         spi_unregister_master(qspi->master);
1396
1397         return 0;
1398 }
1399 /* function to be called by SoC specific platform driver remove() */
1400 EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1401
1402 static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1403 {
1404         struct bcm_qspi *qspi = dev_get_drvdata(dev);
1405
1406         /* store the override strap value */
1407         if (!bcm_qspi_bspi_ver_three(qspi))
1408                 qspi->s3_strap_override_ctrl =
1409                         bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
1410
1411         spi_master_suspend(qspi->master);
1412         clk_disable(qspi->clk);
1413         bcm_qspi_hw_uninit(qspi);
1414
1415         return 0;
1416 };
1417
1418 static int __maybe_unused bcm_qspi_resume(struct device *dev)
1419 {
1420         struct bcm_qspi *qspi = dev_get_drvdata(dev);
1421         int ret = 0;
1422
1423         bcm_qspi_hw_init(qspi);
1424         bcm_qspi_chip_select(qspi, qspi->curr_cs);
1425         if (qspi->soc_intc)
1426                 /* enable MSPI interrupt */
1427                 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1428                                                  true);
1429
1430         ret = clk_enable(qspi->clk);
1431         if (!ret)
1432                 spi_master_resume(qspi->master);
1433
1434         return ret;
1435 }
1436
1437 SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
1438
1439 /* pm_ops to be called by SoC specific platform driver */
1440 EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
1441
1442 MODULE_AUTHOR("Kamal Dasu");
1443 MODULE_DESCRIPTION("Broadcom QSPI driver");
1444 MODULE_LICENSE("GPL v2");
1445 MODULE_ALIAS("platform:" DRIVER_NAME);