2 * Driver for Broadcom BCM2835 SPI Controllers
4 * Copyright (C) 2012 Chris Boot
5 * Copyright (C) 2013 Stephen Warren
6 * Copyright (C) 2015 Martin Sperl
8 * This driver is inspired by:
9 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
10 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 #include <linux/clk.h>
25 #include <linux/completion.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmaengine.h>
29 #include <linux/err.h>
30 #include <linux/interrupt.h>
32 #include <linux/kernel.h>
33 #include <linux/module.h>
35 #include <linux/of_address.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/of_irq.h>
39 #include <linux/spi/spi.h>
41 /* SPI register offsets */
42 #define BCM2835_SPI_CS 0x00
43 #define BCM2835_SPI_FIFO 0x04
44 #define BCM2835_SPI_CLK 0x08
45 #define BCM2835_SPI_DLEN 0x0c
46 #define BCM2835_SPI_LTOH 0x10
47 #define BCM2835_SPI_DC 0x14
50 #define BCM2835_SPI_CS_LEN_LONG 0x02000000
51 #define BCM2835_SPI_CS_DMA_LEN 0x01000000
52 #define BCM2835_SPI_CS_CSPOL2 0x00800000
53 #define BCM2835_SPI_CS_CSPOL1 0x00400000
54 #define BCM2835_SPI_CS_CSPOL0 0x00200000
55 #define BCM2835_SPI_CS_RXF 0x00100000
56 #define BCM2835_SPI_CS_RXR 0x00080000
57 #define BCM2835_SPI_CS_TXD 0x00040000
58 #define BCM2835_SPI_CS_RXD 0x00020000
59 #define BCM2835_SPI_CS_DONE 0x00010000
60 #define BCM2835_SPI_CS_LEN 0x00002000
61 #define BCM2835_SPI_CS_REN 0x00001000
62 #define BCM2835_SPI_CS_ADCS 0x00000800
63 #define BCM2835_SPI_CS_INTR 0x00000400
64 #define BCM2835_SPI_CS_INTD 0x00000200
65 #define BCM2835_SPI_CS_DMAEN 0x00000100
66 #define BCM2835_SPI_CS_TA 0x00000080
67 #define BCM2835_SPI_CS_CSPOL 0x00000040
68 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020
69 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010
70 #define BCM2835_SPI_CS_CPOL 0x00000008
71 #define BCM2835_SPI_CS_CPHA 0x00000004
72 #define BCM2835_SPI_CS_CS_10 0x00000002
73 #define BCM2835_SPI_CS_CS_01 0x00000001
75 #define BCM2835_SPI_POLLING_LIMIT_US 30
76 #define BCM2835_SPI_POLLING_JIFFIES 2
77 #define BCM2835_SPI_DMA_MIN_LENGTH 96
78 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
79 | SPI_NO_CS | SPI_3WIRE)
81 #define DRV_NAME "spi-bcm2835"
94 static inline u32
bcm2835_rd(struct bcm2835_spi
*bs
, unsigned reg
)
96 return readl(bs
->regs
+ reg
);
99 static inline void bcm2835_wr(struct bcm2835_spi
*bs
, unsigned reg
, u32 val
)
101 writel(val
, bs
->regs
+ reg
);
104 static inline void bcm2835_rd_fifo(struct bcm2835_spi
*bs
)
108 while ((bs
->rx_len
) &&
109 (bcm2835_rd(bs
, BCM2835_SPI_CS
) & BCM2835_SPI_CS_RXD
)) {
110 byte
= bcm2835_rd(bs
, BCM2835_SPI_FIFO
);
112 *bs
->rx_buf
++ = byte
;
117 static inline void bcm2835_wr_fifo(struct bcm2835_spi
*bs
)
121 while ((bs
->tx_len
) &&
122 (bcm2835_rd(bs
, BCM2835_SPI_CS
) & BCM2835_SPI_CS_TXD
)) {
123 byte
= bs
->tx_buf
? *bs
->tx_buf
++ : 0;
124 bcm2835_wr(bs
, BCM2835_SPI_FIFO
, byte
);
129 static void bcm2835_spi_reset_hw(struct spi_master
*master
)
131 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
132 u32 cs
= bcm2835_rd(bs
, BCM2835_SPI_CS
);
134 /* Disable SPI interrupts and transfer */
135 cs
&= ~(BCM2835_SPI_CS_INTR
|
136 BCM2835_SPI_CS_INTD
|
137 BCM2835_SPI_CS_DMAEN
|
139 /* and reset RX/TX FIFOS */
140 cs
|= BCM2835_SPI_CS_CLEAR_RX
| BCM2835_SPI_CS_CLEAR_TX
;
142 /* and reset the SPI_HW */
143 bcm2835_wr(bs
, BCM2835_SPI_CS
, cs
);
144 /* as well as DLEN */
145 bcm2835_wr(bs
, BCM2835_SPI_DLEN
, 0);
148 static irqreturn_t
bcm2835_spi_interrupt(int irq
, void *dev_id
)
150 struct spi_master
*master
= dev_id
;
151 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
153 /* Read as many bytes as possible from FIFO */
155 /* Write as many bytes as possible to FIFO */
159 /* Transfer complete - reset SPI HW */
160 bcm2835_spi_reset_hw(master
);
161 /* wake up the framework */
162 complete(&master
->xfer_completion
);
168 static int bcm2835_spi_transfer_one_irq(struct spi_master
*master
,
169 struct spi_device
*spi
,
170 struct spi_transfer
*tfr
,
173 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
175 /* fill in fifo if we have gpio-cs
176 * note that there have been rare events where the native-CS
177 * flapped for <1us which may change the behaviour
178 * with gpio-cs this does not happen, so it is implemented
181 if (gpio_is_valid(spi
->cs_gpio
)) {
182 /* enable HW block, but without interrupts enabled
183 * this would triggern an immediate interrupt
185 bcm2835_wr(bs
, BCM2835_SPI_CS
,
186 cs
| BCM2835_SPI_CS_TA
);
187 /* fill in tx fifo as much as possible */
192 * Enable the HW block. This will immediately trigger a DONE (TX
193 * empty) interrupt, upon which we will fill the TX FIFO with the
194 * first TX bytes. Pre-filling the TX FIFO here to avoid the
195 * interrupt doesn't work:-(
197 cs
|= BCM2835_SPI_CS_INTR
| BCM2835_SPI_CS_INTD
| BCM2835_SPI_CS_TA
;
198 bcm2835_wr(bs
, BCM2835_SPI_CS
, cs
);
200 /* signal that we need to wait for completion */
207 * this implementation has currently a few issues in so far as it does
208 * not work arrount limitations of the HW.
210 * the main one being that DMA transfers are limited to 16 bit
211 * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN
213 * also we currently assume that the scatter-gather fragments are
214 * all multiple of 4 (except the last) - otherwise we would need
215 * to reset the FIFO before subsequent transfers...
216 * this also means that tx/rx transfers sg's need to be of equal size!
218 * there may be a few more border-cases we may need to address as well
219 * but unfortunately this would mean splitting up the scatter-gather
220 * list making it slightly unpractical...
222 static void bcm2835_spi_dma_done(void *data
)
224 struct spi_master
*master
= data
;
225 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
227 /* reset fifo and HW */
228 bcm2835_spi_reset_hw(master
);
230 /* and terminate tx-dma as we do not have an irq for it
231 * because when the rx dma will terminate and this callback
232 * is called the tx-dma must have finished - can't get to this
233 * situation otherwise...
235 if (cmpxchg(&bs
->dma_pending
, true, false)) {
236 dmaengine_terminate_all(master
->dma_tx
);
239 /* and mark as completed */;
240 complete(&master
->xfer_completion
);
243 static int bcm2835_spi_prepare_sg(struct spi_master
*master
,
244 struct spi_transfer
*tfr
,
247 struct dma_chan
*chan
;
248 struct scatterlist
*sgl
;
250 enum dma_transfer_direction dir
;
253 struct dma_async_tx_descriptor
*desc
;
257 dir
= DMA_MEM_TO_DEV
;
258 chan
= master
->dma_tx
;
259 nents
= tfr
->tx_sg
.nents
;
260 sgl
= tfr
->tx_sg
.sgl
;
261 flags
= 0 /* no tx interrupt */;
264 dir
= DMA_DEV_TO_MEM
;
265 chan
= master
->dma_rx
;
266 nents
= tfr
->rx_sg
.nents
;
267 sgl
= tfr
->rx_sg
.sgl
;
268 flags
= DMA_PREP_INTERRUPT
;
270 /* prepare the channel */
271 desc
= dmaengine_prep_slave_sg(chan
, sgl
, nents
, dir
, flags
);
275 /* set callback for rx */
277 desc
->callback
= bcm2835_spi_dma_done
;
278 desc
->callback_param
= master
;
281 /* submit it to DMA-engine */
282 cookie
= dmaengine_submit(desc
);
284 return dma_submit_error(cookie
);
287 static inline int bcm2835_check_sg_length(struct sg_table
*sgt
)
290 struct scatterlist
*sgl
;
292 /* check that the sg entries are word-sized (except for last) */
293 for_each_sg(sgt
->sgl
, sgl
, (int)sgt
->nents
- 1, i
) {
294 if (sg_dma_len(sgl
) % 4)
301 static int bcm2835_spi_transfer_one_dma(struct spi_master
*master
,
302 struct spi_device
*spi
,
303 struct spi_transfer
*tfr
,
306 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
309 /* check that the scatter gather segments are all a multiple of 4 */
310 if (bcm2835_check_sg_length(&tfr
->tx_sg
) ||
311 bcm2835_check_sg_length(&tfr
->rx_sg
)) {
312 dev_warn_once(&spi
->dev
,
313 "scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n");
314 return bcm2835_spi_transfer_one_irq(master
, spi
, tfr
, cs
);
318 ret
= bcm2835_spi_prepare_sg(master
, tfr
, true);
323 dma_async_issue_pending(master
->dma_tx
);
325 /* mark as dma pending */
328 /* set the DMA length */
329 bcm2835_wr(bs
, BCM2835_SPI_DLEN
, tfr
->len
);
332 bcm2835_wr(bs
, BCM2835_SPI_CS
,
333 cs
| BCM2835_SPI_CS_TA
| BCM2835_SPI_CS_DMAEN
);
335 /* setup rx-DMA late - to run transfers while
336 * mapping of the rx buffers still takes place
337 * this saves 10us or more.
339 ret
= bcm2835_spi_prepare_sg(master
, tfr
, false);
341 /* need to reset on errors */
342 dmaengine_terminate_all(master
->dma_tx
);
343 bs
->dma_pending
= false;
344 bcm2835_spi_reset_hw(master
);
348 /* start rx dma late */
349 dma_async_issue_pending(master
->dma_rx
);
351 /* wait for wakeup in framework */
355 static bool bcm2835_spi_can_dma(struct spi_master
*master
,
356 struct spi_device
*spi
,
357 struct spi_transfer
*tfr
)
359 /* only run for gpio_cs */
360 if (!gpio_is_valid(spi
->cs_gpio
))
363 /* we start DMA efforts only on bigger transfers */
364 if (tfr
->len
< BCM2835_SPI_DMA_MIN_LENGTH
)
367 /* BCM2835_SPI_DLEN has defined a max transfer size as
368 * 16 bit, so max is 65535
369 * we can revisit this by using an alternative transfer
370 * method - ideally this would get done without any more
373 if (tfr
->len
> 65535) {
374 dev_warn_once(&spi
->dev
,
375 "transfer size of %d too big for dma-transfer\n",
380 /* if we run rx/tx_buf with word aligned addresses then we are OK */
381 if ((((size_t)tfr
->rx_buf
& 3) == 0) &&
382 (((size_t)tfr
->tx_buf
& 3) == 0))
385 /* otherwise we only allow transfers within the same page
386 * to avoid wasting time on dma_mapping when it is not practical
388 if (((size_t)tfr
->tx_buf
& (PAGE_SIZE
- 1)) + tfr
->len
> PAGE_SIZE
) {
389 dev_warn_once(&spi
->dev
,
390 "Unaligned spi tx-transfer bridging page\n");
393 if (((size_t)tfr
->rx_buf
& (PAGE_SIZE
- 1)) + tfr
->len
> PAGE_SIZE
) {
394 dev_warn_once(&spi
->dev
,
395 "Unaligned spi rx-transfer bridging page\n");
403 static void bcm2835_dma_release(struct spi_master
*master
)
405 if (master
->dma_tx
) {
406 dmaengine_terminate_all(master
->dma_tx
);
407 dma_release_channel(master
->dma_tx
);
408 master
->dma_tx
= NULL
;
410 if (master
->dma_rx
) {
411 dmaengine_terminate_all(master
->dma_rx
);
412 dma_release_channel(master
->dma_rx
);
413 master
->dma_rx
= NULL
;
417 static void bcm2835_dma_init(struct spi_master
*master
, struct device
*dev
)
419 struct dma_slave_config slave_config
;
421 dma_addr_t dma_reg_base
;
424 /* base address in dma-space */
425 addr
= of_get_address(master
->dev
.of_node
, 0, NULL
, NULL
);
427 dev_err(dev
, "could not get DMA-register address - not using dma mode\n");
430 dma_reg_base
= be32_to_cpup(addr
);
433 master
->dma_tx
= dma_request_slave_channel(dev
, "tx");
434 if (!master
->dma_tx
) {
435 dev_err(dev
, "no tx-dma configuration found - not using dma mode\n");
438 master
->dma_rx
= dma_request_slave_channel(dev
, "rx");
439 if (!master
->dma_rx
) {
440 dev_err(dev
, "no rx-dma configuration found - not using dma mode\n");
445 slave_config
.direction
= DMA_MEM_TO_DEV
;
446 slave_config
.dst_addr
= (u32
)(dma_reg_base
+ BCM2835_SPI_FIFO
);
447 slave_config
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
449 ret
= dmaengine_slave_config(master
->dma_tx
, &slave_config
);
453 slave_config
.direction
= DMA_DEV_TO_MEM
;
454 slave_config
.src_addr
= (u32
)(dma_reg_base
+ BCM2835_SPI_FIFO
);
455 slave_config
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
457 ret
= dmaengine_slave_config(master
->dma_rx
, &slave_config
);
461 /* all went well, so set can_dma */
462 master
->can_dma
= bcm2835_spi_can_dma
;
463 master
->max_dma_len
= 65535; /* limitation by BCM2835_SPI_DLEN */
464 /* need to do TX AND RX DMA, so we need dummy buffers */
465 master
->flags
= SPI_MASTER_MUST_RX
| SPI_MASTER_MUST_TX
;
470 dev_err(dev
, "issue configuring dma: %d - not using DMA mode\n",
473 bcm2835_dma_release(master
);
478 static int bcm2835_spi_transfer_one_poll(struct spi_master
*master
,
479 struct spi_device
*spi
,
480 struct spi_transfer
*tfr
,
482 unsigned long long xfer_time_us
)
484 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
485 unsigned long timeout
;
487 /* enable HW block without interrupts */
488 bcm2835_wr(bs
, BCM2835_SPI_CS
, cs
| BCM2835_SPI_CS_TA
);
490 /* fill in the fifo before timeout calculations
491 * if we are interrupted here, then the data is
492 * getting transferred by the HW while we are interrupted
496 /* set the timeout */
497 timeout
= jiffies
+ BCM2835_SPI_POLLING_JIFFIES
;
499 /* loop until finished the transfer */
501 /* fill in tx fifo with remaining data */
504 /* read from fifo as much as possible */
507 /* if there is still data pending to read
508 * then check the timeout
510 if (bs
->rx_len
&& time_after(jiffies
, timeout
)) {
511 dev_dbg_ratelimited(&spi
->dev
,
512 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
514 bs
->tx_len
, bs
->rx_len
);
515 /* fall back to interrupt mode */
516 return bcm2835_spi_transfer_one_irq(master
, spi
,
521 /* Transfer complete - reset SPI HW */
522 bcm2835_spi_reset_hw(master
);
523 /* and return without waiting for completion */
527 static int bcm2835_spi_transfer_one(struct spi_master
*master
,
528 struct spi_device
*spi
,
529 struct spi_transfer
*tfr
)
531 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
532 unsigned long spi_hz
, clk_hz
, cdiv
;
533 unsigned long spi_used_hz
;
534 unsigned long long xfer_time_us
;
535 u32 cs
= bcm2835_rd(bs
, BCM2835_SPI_CS
);
538 spi_hz
= tfr
->speed_hz
;
539 clk_hz
= clk_get_rate(bs
->clk
);
541 if (spi_hz
>= clk_hz
/ 2) {
542 cdiv
= 2; /* clk_hz/2 is the fastest we can go */
544 /* CDIV must be a multiple of two */
545 cdiv
= DIV_ROUND_UP(clk_hz
, spi_hz
);
549 cdiv
= 0; /* 0 is the slowest we can go */
551 cdiv
= 0; /* 0 is the slowest we can go */
553 spi_used_hz
= cdiv
? (clk_hz
/ cdiv
) : (clk_hz
/ 65536);
554 bcm2835_wr(bs
, BCM2835_SPI_CLK
, cdiv
);
556 /* handle all the 3-wire mode */
557 if ((spi
->mode
& SPI_3WIRE
) && (tfr
->rx_buf
))
558 cs
|= BCM2835_SPI_CS_REN
;
560 cs
&= ~BCM2835_SPI_CS_REN
;
562 /* for gpio_cs set dummy CS so that no HW-CS get changed
563 * we can not run this in bcm2835_spi_set_cs, as it does
564 * not get called for cs_gpio cases, so we need to do it here
566 if (gpio_is_valid(spi
->cs_gpio
) || (spi
->mode
& SPI_NO_CS
))
567 cs
|= BCM2835_SPI_CS_CS_10
| BCM2835_SPI_CS_CS_01
;
569 /* set transmit buffers and length */
570 bs
->tx_buf
= tfr
->tx_buf
;
571 bs
->rx_buf
= tfr
->rx_buf
;
572 bs
->tx_len
= tfr
->len
;
573 bs
->rx_len
= tfr
->len
;
575 /* calculate the estimated time in us the transfer runs */
576 xfer_time_us
= (unsigned long long)tfr
->len
577 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
579 do_div(xfer_time_us
, spi_used_hz
);
581 /* for short requests run polling*/
582 if (xfer_time_us
<= BCM2835_SPI_POLLING_LIMIT_US
)
583 return bcm2835_spi_transfer_one_poll(master
, spi
, tfr
,
586 /* run in dma mode if conditions are right */
587 if (master
->can_dma
&& bcm2835_spi_can_dma(master
, spi
, tfr
))
588 return bcm2835_spi_transfer_one_dma(master
, spi
, tfr
, cs
);
590 /* run in interrupt-mode */
591 return bcm2835_spi_transfer_one_irq(master
, spi
, tfr
, cs
);
594 static int bcm2835_spi_prepare_message(struct spi_master
*master
,
595 struct spi_message
*msg
)
597 struct spi_device
*spi
= msg
->spi
;
598 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
599 u32 cs
= bcm2835_rd(bs
, BCM2835_SPI_CS
);
601 cs
&= ~(BCM2835_SPI_CS_CPOL
| BCM2835_SPI_CS_CPHA
);
603 if (spi
->mode
& SPI_CPOL
)
604 cs
|= BCM2835_SPI_CS_CPOL
;
605 if (spi
->mode
& SPI_CPHA
)
606 cs
|= BCM2835_SPI_CS_CPHA
;
608 bcm2835_wr(bs
, BCM2835_SPI_CS
, cs
);
613 static void bcm2835_spi_handle_err(struct spi_master
*master
,
614 struct spi_message
*msg
)
616 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
618 /* if an error occurred and we have an active dma, then terminate */
619 if (cmpxchg(&bs
->dma_pending
, true, false)) {
620 dmaengine_terminate_all(master
->dma_tx
);
621 dmaengine_terminate_all(master
->dma_rx
);
624 bcm2835_spi_reset_hw(master
);
627 static void bcm2835_spi_set_cs(struct spi_device
*spi
, bool gpio_level
)
630 * we can assume that we are "native" as per spi_set_cs
631 * calling us ONLY when cs_gpio is not set
632 * we can also assume that we are CS < 3 as per bcm2835_spi_setup
633 * we would not get called because of error handling there.
634 * the level passed is the electrical level not enabled/disabled
635 * so it has to get translated back to enable/disable
636 * see spi_set_cs in spi.c for the implementation
639 struct spi_master
*master
= spi
->master
;
640 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
641 u32 cs
= bcm2835_rd(bs
, BCM2835_SPI_CS
);
644 /* calculate the enable flag from the passed gpio_level */
645 enable
= (spi
->mode
& SPI_CS_HIGH
) ? gpio_level
: !gpio_level
;
647 /* set flags for "reverse" polarity in the registers */
648 if (spi
->mode
& SPI_CS_HIGH
) {
649 /* set the correct CS-bits */
650 cs
|= BCM2835_SPI_CS_CSPOL
;
651 cs
|= BCM2835_SPI_CS_CSPOL0
<< spi
->chip_select
;
653 /* clean the CS-bits */
654 cs
&= ~BCM2835_SPI_CS_CSPOL
;
655 cs
&= ~(BCM2835_SPI_CS_CSPOL0
<< spi
->chip_select
);
658 /* select the correct chip_select depending on disabled/enabled */
660 /* set cs correctly */
661 if (spi
->mode
& SPI_NO_CS
) {
662 /* use the "undefined" chip-select */
663 cs
|= BCM2835_SPI_CS_CS_10
| BCM2835_SPI_CS_CS_01
;
665 /* set the chip select */
666 cs
&= ~(BCM2835_SPI_CS_CS_10
| BCM2835_SPI_CS_CS_01
);
667 cs
|= spi
->chip_select
;
670 /* disable CSPOL which puts HW-CS into deselected state */
671 cs
&= ~BCM2835_SPI_CS_CSPOL
;
672 /* use the "undefined" chip-select as precaution */
673 cs
|= BCM2835_SPI_CS_CS_10
| BCM2835_SPI_CS_CS_01
;
676 /* finally set the calculated flags in SPI_CS */
677 bcm2835_wr(bs
, BCM2835_SPI_CS
, cs
);
680 static int chip_match_name(struct gpio_chip
*chip
, void *data
)
682 return !strcmp(chip
->label
, data
);
685 static int bcm2835_spi_setup(struct spi_device
*spi
)
688 struct gpio_chip
*chip
;
690 * sanity checking the native-chipselects
692 if (spi
->mode
& SPI_NO_CS
)
694 if (gpio_is_valid(spi
->cs_gpio
))
696 if (spi
->chip_select
> 1) {
697 /* error in the case of native CS requested with CS > 1
698 * officially there is a CS2, but it is not documented
699 * which GPIO is connected with that...
702 "setup: only two native chip-selects are supported\n");
705 /* now translate native cs to GPIO */
707 /* get the gpio chip for the base */
708 chip
= gpiochip_find("pinctrl-bcm2835", chip_match_name
);
712 /* and calculate the real CS */
713 spi
->cs_gpio
= chip
->base
+ 8 - spi
->chip_select
;
715 /* and set up the "mode" and level */
716 dev_info(&spi
->dev
, "setting up native-CS%i as GPIO %i\n",
717 spi
->chip_select
, spi
->cs_gpio
);
719 /* set up GPIO as output and pull to the correct level */
720 err
= gpio_direction_output(spi
->cs_gpio
,
721 (spi
->mode
& SPI_CS_HIGH
) ? 0 : 1);
724 "could not set CS%i gpio %i as output: %i",
725 spi
->chip_select
, spi
->cs_gpio
, err
);
732 static int bcm2835_spi_probe(struct platform_device
*pdev
)
734 struct spi_master
*master
;
735 struct bcm2835_spi
*bs
;
736 struct resource
*res
;
739 master
= spi_alloc_master(&pdev
->dev
, sizeof(*bs
));
741 dev_err(&pdev
->dev
, "spi_alloc_master() failed\n");
745 platform_set_drvdata(pdev
, master
);
747 master
->mode_bits
= BCM2835_SPI_MODE_BITS
;
748 master
->bits_per_word_mask
= SPI_BPW_MASK(8);
749 master
->num_chipselect
= 3;
750 master
->setup
= bcm2835_spi_setup
;
751 master
->set_cs
= bcm2835_spi_set_cs
;
752 master
->transfer_one
= bcm2835_spi_transfer_one
;
753 master
->handle_err
= bcm2835_spi_handle_err
;
754 master
->prepare_message
= bcm2835_spi_prepare_message
;
755 master
->dev
.of_node
= pdev
->dev
.of_node
;
757 bs
= spi_master_get_devdata(master
);
759 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
760 bs
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
761 if (IS_ERR(bs
->regs
)) {
762 err
= PTR_ERR(bs
->regs
);
766 bs
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
767 if (IS_ERR(bs
->clk
)) {
768 err
= PTR_ERR(bs
->clk
);
769 dev_err(&pdev
->dev
, "could not get clk: %d\n", err
);
773 bs
->irq
= platform_get_irq(pdev
, 0);
775 dev_err(&pdev
->dev
, "could not get IRQ: %d\n", bs
->irq
);
776 err
= bs
->irq
? bs
->irq
: -ENODEV
;
780 clk_prepare_enable(bs
->clk
);
782 bcm2835_dma_init(master
, &pdev
->dev
);
784 /* initialise the hardware with the default polarities */
785 bcm2835_wr(bs
, BCM2835_SPI_CS
,
786 BCM2835_SPI_CS_CLEAR_RX
| BCM2835_SPI_CS_CLEAR_TX
);
788 err
= devm_request_irq(&pdev
->dev
, bs
->irq
, bcm2835_spi_interrupt
, 0,
789 dev_name(&pdev
->dev
), master
);
791 dev_err(&pdev
->dev
, "could not request IRQ: %d\n", err
);
792 goto out_clk_disable
;
795 err
= devm_spi_register_master(&pdev
->dev
, master
);
797 dev_err(&pdev
->dev
, "could not register SPI master: %d\n", err
);
798 goto out_clk_disable
;
804 clk_disable_unprepare(bs
->clk
);
806 spi_master_put(master
);
810 static int bcm2835_spi_remove(struct platform_device
*pdev
)
812 struct spi_master
*master
= platform_get_drvdata(pdev
);
813 struct bcm2835_spi
*bs
= spi_master_get_devdata(master
);
815 /* Clear FIFOs, and disable the HW block */
816 bcm2835_wr(bs
, BCM2835_SPI_CS
,
817 BCM2835_SPI_CS_CLEAR_RX
| BCM2835_SPI_CS_CLEAR_TX
);
819 clk_disable_unprepare(bs
->clk
);
821 bcm2835_dma_release(master
);
826 static const struct of_device_id bcm2835_spi_match
[] = {
827 { .compatible
= "brcm,bcm2835-spi", },
830 MODULE_DEVICE_TABLE(of
, bcm2835_spi_match
);
832 static struct platform_driver bcm2835_spi_driver
= {
835 .of_match_table
= bcm2835_spi_match
,
837 .probe
= bcm2835_spi_probe
,
838 .remove
= bcm2835_spi_remove
,
840 module_platform_driver(bcm2835_spi_driver
);
842 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
843 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
844 MODULE_LICENSE("GPL");