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[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-bfin5xx.c
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/slab.h>
17 #include <linux/io.h>
18 #include <linux/ioport.h>
19 #include <linux/irq.h>
20 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/spi/spi.h>
25 #include <linux/workqueue.h>
26
27 #include <asm/dma.h>
28 #include <asm/portmux.h>
29 #include <asm/bfin5xx_spi.h>
30 #include <asm/cacheflush.h>
31
32 #define DRV_NAME "bfin-spi"
33 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
34 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
35 #define DRV_VERSION "1.0"
36
37 MODULE_AUTHOR(DRV_AUTHOR);
38 MODULE_DESCRIPTION(DRV_DESC);
39 MODULE_LICENSE("GPL");
40
41 #define START_STATE ((void *)0)
42 #define RUNNING_STATE ((void *)1)
43 #define DONE_STATE ((void *)2)
44 #define ERROR_STATE ((void *)-1)
45
46 struct bfin_spi_master_data;
47
48 struct bfin_spi_transfer_ops {
49 void (*write) (struct bfin_spi_master_data *);
50 void (*read) (struct bfin_spi_master_data *);
51 void (*duplex) (struct bfin_spi_master_data *);
52 };
53
54 struct bfin_spi_master_data {
55 /* Driver model hookup */
56 struct platform_device *pdev;
57
58 /* SPI framework hookup */
59 struct spi_master *master;
60
61 /* Regs base of SPI controller */
62 struct bfin_spi_regs __iomem *regs;
63
64 /* Pin request list */
65 u16 *pin_req;
66
67 /* BFIN hookup */
68 struct bfin5xx_spi_master *master_info;
69
70 struct work_struct pump_messages;
71 spinlock_t lock;
72 struct list_head queue;
73 int busy;
74 bool running;
75
76 /* Message Transfer pump */
77 struct tasklet_struct pump_transfers;
78
79 /* Current message transfer state info */
80 struct spi_message *cur_msg;
81 struct spi_transfer *cur_transfer;
82 struct bfin_spi_slave_data *cur_chip;
83 size_t len_in_bytes;
84 size_t len;
85 void *tx;
86 void *tx_end;
87 void *rx;
88 void *rx_end;
89
90 /* DMA stuffs */
91 int dma_channel;
92 int dma_mapped;
93 int dma_requested;
94 dma_addr_t rx_dma;
95 dma_addr_t tx_dma;
96
97 int irq_requested;
98 int spi_irq;
99
100 size_t rx_map_len;
101 size_t tx_map_len;
102 u8 n_bytes;
103 u16 ctrl_reg;
104 u16 flag_reg;
105
106 int cs_change;
107 const struct bfin_spi_transfer_ops *ops;
108 };
109
110 struct bfin_spi_slave_data {
111 u16 ctl_reg;
112 u16 baud;
113 u16 flag;
114
115 u8 chip_select_num;
116 u8 enable_dma;
117 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
118 u32 cs_gpio;
119 u16 idle_tx_val;
120 u8 pio_interrupt; /* use spi data irq */
121 const struct bfin_spi_transfer_ops *ops;
122 };
123
124 static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
125 {
126 bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
127 }
128
129 static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
130 {
131 bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
132 }
133
134 /* Caculate the SPI_BAUD register value based on input HZ */
135 static u16 hz_to_spi_baud(u32 speed_hz)
136 {
137 u_long sclk = get_sclk();
138 u16 spi_baud = (sclk / (2 * speed_hz));
139
140 if ((sclk % (2 * speed_hz)) > 0)
141 spi_baud++;
142
143 if (spi_baud < MIN_SPI_BAUD_VAL)
144 spi_baud = MIN_SPI_BAUD_VAL;
145
146 return spi_baud;
147 }
148
149 static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
150 {
151 unsigned long limit = loops_per_jiffy << 1;
152
153 /* wait for stop and clear stat */
154 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
155 cpu_relax();
156
157 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
158
159 return limit;
160 }
161
162 /* Chip select operation functions for cs_change flag */
163 static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
164 {
165 if (likely(chip->chip_select_num < MAX_CTRL_CS))
166 bfin_write_and(&drv_data->regs->flg, ~chip->flag);
167 else
168 gpio_set_value(chip->cs_gpio, 0);
169 }
170
171 static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
172 struct bfin_spi_slave_data *chip)
173 {
174 if (likely(chip->chip_select_num < MAX_CTRL_CS))
175 bfin_write_or(&drv_data->regs->flg, chip->flag);
176 else
177 gpio_set_value(chip->cs_gpio, 1);
178
179 /* Move delay here for consistency */
180 if (chip->cs_chg_udelay)
181 udelay(chip->cs_chg_udelay);
182 }
183
184 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
185 static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
186 struct bfin_spi_slave_data *chip)
187 {
188 if (chip->chip_select_num < MAX_CTRL_CS)
189 bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
190 }
191
192 static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
193 struct bfin_spi_slave_data *chip)
194 {
195 if (chip->chip_select_num < MAX_CTRL_CS)
196 bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
197 }
198
199 /* stop controller and re-config current chip*/
200 static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
201 {
202 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
203
204 /* Clear status and disable clock */
205 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
206 bfin_spi_disable(drv_data);
207 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
208
209 SSYNC();
210
211 /* Load the registers */
212 bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
213 bfin_write(&drv_data->regs->baud, chip->baud);
214
215 bfin_spi_enable(drv_data);
216 bfin_spi_cs_active(drv_data, chip);
217 }
218
219 /* used to kick off transfer in rx mode and read unwanted RX data */
220 static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
221 {
222 (void) bfin_read(&drv_data->regs->rdbr);
223 }
224
225 static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
226 {
227 /* clear RXS (we check for RXS inside the loop) */
228 bfin_spi_dummy_read(drv_data);
229
230 while (drv_data->tx < drv_data->tx_end) {
231 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
232 /* wait until transfer finished.
233 checking SPIF or TXS may not guarantee transfer completion */
234 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
235 cpu_relax();
236 /* discard RX data and clear RXS */
237 bfin_spi_dummy_read(drv_data);
238 }
239 }
240
241 static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
242 {
243 u16 tx_val = drv_data->cur_chip->idle_tx_val;
244
245 /* discard old RX data and clear RXS */
246 bfin_spi_dummy_read(drv_data);
247
248 while (drv_data->rx < drv_data->rx_end) {
249 bfin_write(&drv_data->regs->tdbr, tx_val);
250 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
251 cpu_relax();
252 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
253 }
254 }
255
256 static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
257 {
258 /* discard old RX data and clear RXS */
259 bfin_spi_dummy_read(drv_data);
260
261 while (drv_data->rx < drv_data->rx_end) {
262 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
263 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
264 cpu_relax();
265 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
266 }
267 }
268
269 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
270 .write = bfin_spi_u8_writer,
271 .read = bfin_spi_u8_reader,
272 .duplex = bfin_spi_u8_duplex,
273 };
274
275 static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
276 {
277 /* clear RXS (we check for RXS inside the loop) */
278 bfin_spi_dummy_read(drv_data);
279
280 while (drv_data->tx < drv_data->tx_end) {
281 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
282 drv_data->tx += 2;
283 /* wait until transfer finished.
284 checking SPIF or TXS may not guarantee transfer completion */
285 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
286 cpu_relax();
287 /* discard RX data and clear RXS */
288 bfin_spi_dummy_read(drv_data);
289 }
290 }
291
292 static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
293 {
294 u16 tx_val = drv_data->cur_chip->idle_tx_val;
295
296 /* discard old RX data and clear RXS */
297 bfin_spi_dummy_read(drv_data);
298
299 while (drv_data->rx < drv_data->rx_end) {
300 bfin_write(&drv_data->regs->tdbr, tx_val);
301 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
302 cpu_relax();
303 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
304 drv_data->rx += 2;
305 }
306 }
307
308 static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
309 {
310 /* discard old RX data and clear RXS */
311 bfin_spi_dummy_read(drv_data);
312
313 while (drv_data->rx < drv_data->rx_end) {
314 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
315 drv_data->tx += 2;
316 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
317 cpu_relax();
318 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
319 drv_data->rx += 2;
320 }
321 }
322
323 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
324 .write = bfin_spi_u16_writer,
325 .read = bfin_spi_u16_reader,
326 .duplex = bfin_spi_u16_duplex,
327 };
328
329 /* test if there is more transfer to be done */
330 static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
331 {
332 struct spi_message *msg = drv_data->cur_msg;
333 struct spi_transfer *trans = drv_data->cur_transfer;
334
335 /* Move to next transfer */
336 if (trans->transfer_list.next != &msg->transfers) {
337 drv_data->cur_transfer =
338 list_entry(trans->transfer_list.next,
339 struct spi_transfer, transfer_list);
340 return RUNNING_STATE;
341 } else
342 return DONE_STATE;
343 }
344
345 /*
346 * caller already set message->status;
347 * dma and pio irqs are blocked give finished message back
348 */
349 static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
350 {
351 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
352 unsigned long flags;
353 struct spi_message *msg;
354
355 spin_lock_irqsave(&drv_data->lock, flags);
356 msg = drv_data->cur_msg;
357 drv_data->cur_msg = NULL;
358 drv_data->cur_transfer = NULL;
359 drv_data->cur_chip = NULL;
360 schedule_work(&drv_data->pump_messages);
361 spin_unlock_irqrestore(&drv_data->lock, flags);
362
363 msg->state = NULL;
364
365 if (!drv_data->cs_change)
366 bfin_spi_cs_deactive(drv_data, chip);
367
368 /* Not stop spi in autobuffer mode */
369 if (drv_data->tx_dma != 0xFFFF)
370 bfin_spi_disable(drv_data);
371
372 if (msg->complete)
373 msg->complete(msg->context);
374 }
375
376 /* spi data irq handler */
377 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
378 {
379 struct bfin_spi_master_data *drv_data = dev_id;
380 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
381 struct spi_message *msg = drv_data->cur_msg;
382 int n_bytes = drv_data->n_bytes;
383 int loop = 0;
384
385 /* wait until transfer finished. */
386 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
387 cpu_relax();
388
389 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
390 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
391 /* last read */
392 if (drv_data->rx) {
393 dev_dbg(&drv_data->pdev->dev, "last read\n");
394 if (!(n_bytes % 2)) {
395 u16 *buf = (u16 *)drv_data->rx;
396 for (loop = 0; loop < n_bytes / 2; loop++)
397 *buf++ = bfin_read(&drv_data->regs->rdbr);
398 } else {
399 u8 *buf = (u8 *)drv_data->rx;
400 for (loop = 0; loop < n_bytes; loop++)
401 *buf++ = bfin_read(&drv_data->regs->rdbr);
402 }
403 drv_data->rx += n_bytes;
404 }
405
406 msg->actual_length += drv_data->len_in_bytes;
407 if (drv_data->cs_change)
408 bfin_spi_cs_deactive(drv_data, chip);
409 /* Move to next transfer */
410 msg->state = bfin_spi_next_transfer(drv_data);
411
412 disable_irq_nosync(drv_data->spi_irq);
413
414 /* Schedule transfer tasklet */
415 tasklet_schedule(&drv_data->pump_transfers);
416 return IRQ_HANDLED;
417 }
418
419 if (drv_data->rx && drv_data->tx) {
420 /* duplex */
421 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
422 if (!(n_bytes % 2)) {
423 u16 *buf = (u16 *)drv_data->rx;
424 u16 *buf2 = (u16 *)drv_data->tx;
425 for (loop = 0; loop < n_bytes / 2; loop++) {
426 *buf++ = bfin_read(&drv_data->regs->rdbr);
427 bfin_write(&drv_data->regs->tdbr, *buf2++);
428 }
429 } else {
430 u8 *buf = (u8 *)drv_data->rx;
431 u8 *buf2 = (u8 *)drv_data->tx;
432 for (loop = 0; loop < n_bytes; loop++) {
433 *buf++ = bfin_read(&drv_data->regs->rdbr);
434 bfin_write(&drv_data->regs->tdbr, *buf2++);
435 }
436 }
437 } else if (drv_data->rx) {
438 /* read */
439 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
440 if (!(n_bytes % 2)) {
441 u16 *buf = (u16 *)drv_data->rx;
442 for (loop = 0; loop < n_bytes / 2; loop++) {
443 *buf++ = bfin_read(&drv_data->regs->rdbr);
444 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
445 }
446 } else {
447 u8 *buf = (u8 *)drv_data->rx;
448 for (loop = 0; loop < n_bytes; loop++) {
449 *buf++ = bfin_read(&drv_data->regs->rdbr);
450 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
451 }
452 }
453 } else if (drv_data->tx) {
454 /* write */
455 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
456 if (!(n_bytes % 2)) {
457 u16 *buf = (u16 *)drv_data->tx;
458 for (loop = 0; loop < n_bytes / 2; loop++) {
459 bfin_read(&drv_data->regs->rdbr);
460 bfin_write(&drv_data->regs->tdbr, *buf++);
461 }
462 } else {
463 u8 *buf = (u8 *)drv_data->tx;
464 for (loop = 0; loop < n_bytes; loop++) {
465 bfin_read(&drv_data->regs->rdbr);
466 bfin_write(&drv_data->regs->tdbr, *buf++);
467 }
468 }
469 }
470
471 if (drv_data->tx)
472 drv_data->tx += n_bytes;
473 if (drv_data->rx)
474 drv_data->rx += n_bytes;
475
476 return IRQ_HANDLED;
477 }
478
479 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
480 {
481 struct bfin_spi_master_data *drv_data = dev_id;
482 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
483 struct spi_message *msg = drv_data->cur_msg;
484 unsigned long timeout;
485 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
486 u16 spistat = bfin_read(&drv_data->regs->stat);
487
488 dev_dbg(&drv_data->pdev->dev,
489 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
490 dmastat, spistat);
491
492 if (drv_data->rx != NULL) {
493 u16 cr = bfin_read(&drv_data->regs->ctl);
494 /* discard old RX data and clear RXS */
495 bfin_spi_dummy_read(drv_data);
496 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
497 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
498 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
499 }
500
501 clear_dma_irqstat(drv_data->dma_channel);
502
503 /*
504 * wait for the last transaction shifted out. HRM states:
505 * at this point there may still be data in the SPI DMA FIFO waiting
506 * to be transmitted ... software needs to poll TXS in the SPI_STAT
507 * register until it goes low for 2 successive reads
508 */
509 if (drv_data->tx != NULL) {
510 while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
511 (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
512 cpu_relax();
513 }
514
515 dev_dbg(&drv_data->pdev->dev,
516 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
517 dmastat, bfin_read(&drv_data->regs->stat));
518
519 timeout = jiffies + HZ;
520 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
521 if (!time_before(jiffies, timeout)) {
522 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF\n");
523 break;
524 } else
525 cpu_relax();
526
527 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
528 msg->state = ERROR_STATE;
529 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
530 } else {
531 msg->actual_length += drv_data->len_in_bytes;
532
533 if (drv_data->cs_change)
534 bfin_spi_cs_deactive(drv_data, chip);
535
536 /* Move to next transfer */
537 msg->state = bfin_spi_next_transfer(drv_data);
538 }
539
540 /* Schedule transfer tasklet */
541 tasklet_schedule(&drv_data->pump_transfers);
542
543 /* free the irq handler before next transfer */
544 dev_dbg(&drv_data->pdev->dev,
545 "disable dma channel irq%d\n",
546 drv_data->dma_channel);
547 dma_disable_irq_nosync(drv_data->dma_channel);
548
549 return IRQ_HANDLED;
550 }
551
552 static void bfin_spi_pump_transfers(unsigned long data)
553 {
554 struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
555 struct spi_message *message = NULL;
556 struct spi_transfer *transfer = NULL;
557 struct spi_transfer *previous = NULL;
558 struct bfin_spi_slave_data *chip = NULL;
559 unsigned int bits_per_word;
560 u16 cr, cr_width = 0, dma_width, dma_config;
561 u32 tranf_success = 1;
562 u8 full_duplex = 0;
563
564 /* Get current state information */
565 message = drv_data->cur_msg;
566 transfer = drv_data->cur_transfer;
567 chip = drv_data->cur_chip;
568
569 /*
570 * if msg is error or done, report it back using complete() callback
571 */
572
573 /* Handle for abort */
574 if (message->state == ERROR_STATE) {
575 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
576 message->status = -EIO;
577 bfin_spi_giveback(drv_data);
578 return;
579 }
580
581 /* Handle end of message */
582 if (message->state == DONE_STATE) {
583 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
584 message->status = 0;
585 bfin_spi_flush(drv_data);
586 bfin_spi_giveback(drv_data);
587 return;
588 }
589
590 /* Delay if requested at end of transfer */
591 if (message->state == RUNNING_STATE) {
592 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
593 previous = list_entry(transfer->transfer_list.prev,
594 struct spi_transfer, transfer_list);
595 if (previous->delay_usecs)
596 udelay(previous->delay_usecs);
597 }
598
599 /* Flush any existing transfers that may be sitting in the hardware */
600 if (bfin_spi_flush(drv_data) == 0) {
601 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
602 message->status = -EIO;
603 bfin_spi_giveback(drv_data);
604 return;
605 }
606
607 if (transfer->len == 0) {
608 /* Move to next transfer of this msg */
609 message->state = bfin_spi_next_transfer(drv_data);
610 /* Schedule next transfer tasklet */
611 tasklet_schedule(&drv_data->pump_transfers);
612 return;
613 }
614
615 if (transfer->tx_buf != NULL) {
616 drv_data->tx = (void *)transfer->tx_buf;
617 drv_data->tx_end = drv_data->tx + transfer->len;
618 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
619 transfer->tx_buf, drv_data->tx_end);
620 } else {
621 drv_data->tx = NULL;
622 }
623
624 if (transfer->rx_buf != NULL) {
625 full_duplex = transfer->tx_buf != NULL;
626 drv_data->rx = transfer->rx_buf;
627 drv_data->rx_end = drv_data->rx + transfer->len;
628 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
629 transfer->rx_buf, drv_data->rx_end);
630 } else {
631 drv_data->rx = NULL;
632 }
633
634 drv_data->rx_dma = transfer->rx_dma;
635 drv_data->tx_dma = transfer->tx_dma;
636 drv_data->len_in_bytes = transfer->len;
637 drv_data->cs_change = transfer->cs_change;
638
639 /* Bits per word setup */
640 bits_per_word = transfer->bits_per_word;
641 if (bits_per_word == 16) {
642 drv_data->n_bytes = bits_per_word/8;
643 drv_data->len = (transfer->len) >> 1;
644 cr_width = BIT_CTL_WORDSIZE;
645 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
646 } else if (bits_per_word == 8) {
647 drv_data->n_bytes = bits_per_word/8;
648 drv_data->len = transfer->len;
649 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
650 }
651 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
652 cr |= cr_width;
653 bfin_write(&drv_data->regs->ctl, cr);
654
655 dev_dbg(&drv_data->pdev->dev,
656 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
657 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
658
659 message->state = RUNNING_STATE;
660 dma_config = 0;
661
662 bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
663
664 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
665 bfin_spi_cs_active(drv_data, chip);
666
667 dev_dbg(&drv_data->pdev->dev,
668 "now pumping a transfer: width is %d, len is %d\n",
669 cr_width, transfer->len);
670
671 /*
672 * Try to map dma buffer and do a dma transfer. If successful use,
673 * different way to r/w according to the enable_dma settings and if
674 * we are not doing a full duplex transfer (since the hardware does
675 * not support full duplex DMA transfers).
676 */
677 if (!full_duplex && drv_data->cur_chip->enable_dma
678 && drv_data->len > 6) {
679
680 unsigned long dma_start_addr, flags;
681
682 disable_dma(drv_data->dma_channel);
683 clear_dma_irqstat(drv_data->dma_channel);
684
685 /* config dma channel */
686 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
687 set_dma_x_count(drv_data->dma_channel, drv_data->len);
688 if (cr_width == BIT_CTL_WORDSIZE) {
689 set_dma_x_modify(drv_data->dma_channel, 2);
690 dma_width = WDSIZE_16;
691 } else {
692 set_dma_x_modify(drv_data->dma_channel, 1);
693 dma_width = WDSIZE_8;
694 }
695
696 /* poll for SPI completion before start */
697 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
698 cpu_relax();
699
700 /* dirty hack for autobuffer DMA mode */
701 if (drv_data->tx_dma == 0xFFFF) {
702 dev_dbg(&drv_data->pdev->dev,
703 "doing autobuffer DMA out.\n");
704
705 /* no irq in autobuffer mode */
706 dma_config =
707 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
708 set_dma_config(drv_data->dma_channel, dma_config);
709 set_dma_start_addr(drv_data->dma_channel,
710 (unsigned long)drv_data->tx);
711 enable_dma(drv_data->dma_channel);
712
713 /* start SPI transfer */
714 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
715
716 /* just return here, there can only be one transfer
717 * in this mode
718 */
719 message->status = 0;
720 bfin_spi_giveback(drv_data);
721 return;
722 }
723
724 /* In dma mode, rx or tx must be NULL in one transfer */
725 dma_config = (RESTART | dma_width | DI_EN);
726 if (drv_data->rx != NULL) {
727 /* set transfer mode, and enable SPI */
728 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
729 drv_data->rx, drv_data->len_in_bytes);
730
731 /* invalidate caches, if needed */
732 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
733 invalidate_dcache_range((unsigned long) drv_data->rx,
734 (unsigned long) (drv_data->rx +
735 drv_data->len_in_bytes));
736
737 dma_config |= WNR;
738 dma_start_addr = (unsigned long)drv_data->rx;
739 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
740
741 } else if (drv_data->tx != NULL) {
742 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
743
744 /* flush caches, if needed */
745 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
746 flush_dcache_range((unsigned long) drv_data->tx,
747 (unsigned long) (drv_data->tx +
748 drv_data->len_in_bytes));
749
750 dma_start_addr = (unsigned long)drv_data->tx;
751 cr |= BIT_CTL_TIMOD_DMA_TX;
752
753 } else
754 BUG();
755
756 /* oh man, here there be monsters ... and i dont mean the
757 * fluffy cute ones from pixar, i mean the kind that'll eat
758 * your data, kick your dog, and love it all. do *not* try
759 * and change these lines unless you (1) heavily test DMA
760 * with SPI flashes on a loaded system (e.g. ping floods),
761 * (2) know just how broken the DMA engine interaction with
762 * the SPI peripheral is, and (3) have someone else to blame
763 * when you screw it all up anyways.
764 */
765 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
766 set_dma_config(drv_data->dma_channel, dma_config);
767 local_irq_save(flags);
768 SSYNC();
769 bfin_write(&drv_data->regs->ctl, cr);
770 enable_dma(drv_data->dma_channel);
771 dma_enable_irq(drv_data->dma_channel);
772 local_irq_restore(flags);
773
774 return;
775 }
776
777 /*
778 * We always use SPI_WRITE mode (transfer starts with TDBR write).
779 * SPI_READ mode (transfer starts with RDBR read) seems to have
780 * problems with setting up the output value in TDBR prior to the
781 * start of the transfer.
782 */
783 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
784
785 if (chip->pio_interrupt) {
786 /* SPI irq should have been disabled by now */
787
788 /* discard old RX data and clear RXS */
789 bfin_spi_dummy_read(drv_data);
790
791 /* start transfer */
792 if (drv_data->tx == NULL)
793 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
794 else {
795 int loop;
796 if (bits_per_word == 16) {
797 u16 *buf = (u16 *)drv_data->tx;
798 for (loop = 0; loop < bits_per_word / 16;
799 loop++) {
800 bfin_write(&drv_data->regs->tdbr, *buf++);
801 }
802 } else if (bits_per_word == 8) {
803 u8 *buf = (u8 *)drv_data->tx;
804 for (loop = 0; loop < bits_per_word / 8; loop++)
805 bfin_write(&drv_data->regs->tdbr, *buf++);
806 }
807
808 drv_data->tx += drv_data->n_bytes;
809 }
810
811 /* once TDBR is empty, interrupt is triggered */
812 enable_irq(drv_data->spi_irq);
813 return;
814 }
815
816 /* IO mode */
817 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
818
819 if (full_duplex) {
820 /* full duplex mode */
821 BUG_ON((drv_data->tx_end - drv_data->tx) !=
822 (drv_data->rx_end - drv_data->rx));
823 dev_dbg(&drv_data->pdev->dev,
824 "IO duplex: cr is 0x%x\n", cr);
825
826 drv_data->ops->duplex(drv_data);
827
828 if (drv_data->tx != drv_data->tx_end)
829 tranf_success = 0;
830 } else if (drv_data->tx != NULL) {
831 /* write only half duplex */
832 dev_dbg(&drv_data->pdev->dev,
833 "IO write: cr is 0x%x\n", cr);
834
835 drv_data->ops->write(drv_data);
836
837 if (drv_data->tx != drv_data->tx_end)
838 tranf_success = 0;
839 } else if (drv_data->rx != NULL) {
840 /* read only half duplex */
841 dev_dbg(&drv_data->pdev->dev,
842 "IO read: cr is 0x%x\n", cr);
843
844 drv_data->ops->read(drv_data);
845 if (drv_data->rx != drv_data->rx_end)
846 tranf_success = 0;
847 }
848
849 if (!tranf_success) {
850 dev_dbg(&drv_data->pdev->dev,
851 "IO write error!\n");
852 message->state = ERROR_STATE;
853 } else {
854 /* Update total byte transferred */
855 message->actual_length += drv_data->len_in_bytes;
856 /* Move to next transfer of this msg */
857 message->state = bfin_spi_next_transfer(drv_data);
858 if (drv_data->cs_change && message->state != DONE_STATE) {
859 bfin_spi_flush(drv_data);
860 bfin_spi_cs_deactive(drv_data, chip);
861 }
862 }
863
864 /* Schedule next transfer tasklet */
865 tasklet_schedule(&drv_data->pump_transfers);
866 }
867
868 /* pop a msg from queue and kick off real transfer */
869 static void bfin_spi_pump_messages(struct work_struct *work)
870 {
871 struct bfin_spi_master_data *drv_data;
872 unsigned long flags;
873
874 drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
875
876 /* Lock queue and check for queue work */
877 spin_lock_irqsave(&drv_data->lock, flags);
878 if (list_empty(&drv_data->queue) || !drv_data->running) {
879 /* pumper kicked off but no work to do */
880 drv_data->busy = 0;
881 spin_unlock_irqrestore(&drv_data->lock, flags);
882 return;
883 }
884
885 /* Make sure we are not already running a message */
886 if (drv_data->cur_msg) {
887 spin_unlock_irqrestore(&drv_data->lock, flags);
888 return;
889 }
890
891 /* Extract head of queue */
892 drv_data->cur_msg = list_entry(drv_data->queue.next,
893 struct spi_message, queue);
894
895 /* Setup the SSP using the per chip configuration */
896 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
897 bfin_spi_restore_state(drv_data);
898
899 list_del_init(&drv_data->cur_msg->queue);
900
901 /* Initial message state */
902 drv_data->cur_msg->state = START_STATE;
903 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
904 struct spi_transfer, transfer_list);
905
906 dev_dbg(&drv_data->pdev->dev,
907 "got a message to pump, state is set to: baud "
908 "%d, flag 0x%x, ctl 0x%x\n",
909 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
910 drv_data->cur_chip->ctl_reg);
911
912 dev_dbg(&drv_data->pdev->dev,
913 "the first transfer len is %d\n",
914 drv_data->cur_transfer->len);
915
916 /* Mark as busy and launch transfers */
917 tasklet_schedule(&drv_data->pump_transfers);
918
919 drv_data->busy = 1;
920 spin_unlock_irqrestore(&drv_data->lock, flags);
921 }
922
923 /*
924 * got a msg to transfer, queue it in drv_data->queue.
925 * And kick off message pumper
926 */
927 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
928 {
929 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
930 unsigned long flags;
931
932 spin_lock_irqsave(&drv_data->lock, flags);
933
934 if (!drv_data->running) {
935 spin_unlock_irqrestore(&drv_data->lock, flags);
936 return -ESHUTDOWN;
937 }
938
939 msg->actual_length = 0;
940 msg->status = -EINPROGRESS;
941 msg->state = START_STATE;
942
943 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
944 list_add_tail(&msg->queue, &drv_data->queue);
945
946 if (drv_data->running && !drv_data->busy)
947 schedule_work(&drv_data->pump_messages);
948
949 spin_unlock_irqrestore(&drv_data->lock, flags);
950
951 return 0;
952 }
953
954 #define MAX_SPI_SSEL 7
955
956 static const u16 ssel[][MAX_SPI_SSEL] = {
957 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
958 P_SPI0_SSEL4, P_SPI0_SSEL5,
959 P_SPI0_SSEL6, P_SPI0_SSEL7},
960
961 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
962 P_SPI1_SSEL4, P_SPI1_SSEL5,
963 P_SPI1_SSEL6, P_SPI1_SSEL7},
964
965 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
966 P_SPI2_SSEL4, P_SPI2_SSEL5,
967 P_SPI2_SSEL6, P_SPI2_SSEL7},
968 };
969
970 /* setup for devices (may be called multiple times -- not just first setup) */
971 static int bfin_spi_setup(struct spi_device *spi)
972 {
973 struct bfin5xx_spi_chip *chip_info;
974 struct bfin_spi_slave_data *chip = NULL;
975 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
976 u16 bfin_ctl_reg;
977 int ret = -EINVAL;
978
979 /* Only alloc (or use chip_info) on first setup */
980 chip_info = NULL;
981 chip = spi_get_ctldata(spi);
982 if (chip == NULL) {
983 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
984 if (!chip) {
985 dev_err(&spi->dev, "cannot allocate chip data\n");
986 ret = -ENOMEM;
987 goto error;
988 }
989
990 chip->enable_dma = 0;
991 chip_info = spi->controller_data;
992 }
993
994 /* Let people set non-standard bits directly */
995 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
996 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
997
998 /* chip_info isn't always needed */
999 if (chip_info) {
1000 /* Make sure people stop trying to set fields via ctl_reg
1001 * when they should actually be using common SPI framework.
1002 * Currently we let through: WOM EMISO PSSE GM SZ.
1003 * Not sure if a user actually needs/uses any of these,
1004 * but let's assume (for now) they do.
1005 */
1006 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1007 dev_err(&spi->dev,
1008 "do not set bits in ctl_reg that the SPI framework manages\n");
1009 goto error;
1010 }
1011 chip->enable_dma = chip_info->enable_dma != 0
1012 && drv_data->master_info->enable_dma;
1013 chip->ctl_reg = chip_info->ctl_reg;
1014 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1015 chip->idle_tx_val = chip_info->idle_tx_val;
1016 chip->pio_interrupt = chip_info->pio_interrupt;
1017 } else {
1018 /* force a default base state */
1019 chip->ctl_reg &= bfin_ctl_reg;
1020 }
1021
1022 /* translate common spi framework into our register */
1023 if (spi->mode & SPI_CPOL)
1024 chip->ctl_reg |= BIT_CTL_CPOL;
1025 if (spi->mode & SPI_CPHA)
1026 chip->ctl_reg |= BIT_CTL_CPHA;
1027 if (spi->mode & SPI_LSB_FIRST)
1028 chip->ctl_reg |= BIT_CTL_LSBF;
1029 /* we dont support running in slave mode (yet?) */
1030 chip->ctl_reg |= BIT_CTL_MASTER;
1031
1032 /*
1033 * Notice: for blackfin, the speed_hz is the value of register
1034 * SPI_BAUD, not the real baudrate
1035 */
1036 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1037 chip->chip_select_num = spi->chip_select;
1038 if (chip->chip_select_num < MAX_CTRL_CS) {
1039 if (!(spi->mode & SPI_CPHA))
1040 dev_warn(&spi->dev,
1041 "Warning: SPI CPHA not set: Slave Select not under software control!\n"
1042 "See Documentation/blackfin/bfin-spi-notes.txt\n");
1043
1044 chip->flag = (1 << spi->chip_select) << 8;
1045 } else
1046 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1047
1048 if (chip->enable_dma && chip->pio_interrupt) {
1049 dev_err(&spi->dev,
1050 "enable_dma is set, do not set pio_interrupt\n");
1051 goto error;
1052 }
1053 /*
1054 * if any one SPI chip is registered and wants DMA, request the
1055 * DMA channel for it
1056 */
1057 if (chip->enable_dma && !drv_data->dma_requested) {
1058 /* register dma irq handler */
1059 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1060 if (ret) {
1061 dev_err(&spi->dev,
1062 "Unable to request BlackFin SPI DMA channel\n");
1063 goto error;
1064 }
1065 drv_data->dma_requested = 1;
1066
1067 ret = set_dma_callback(drv_data->dma_channel,
1068 bfin_spi_dma_irq_handler, drv_data);
1069 if (ret) {
1070 dev_err(&spi->dev, "Unable to set dma callback\n");
1071 goto error;
1072 }
1073 dma_disable_irq(drv_data->dma_channel);
1074 }
1075
1076 if (chip->pio_interrupt && !drv_data->irq_requested) {
1077 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1078 0, "BFIN_SPI", drv_data);
1079 if (ret) {
1080 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1081 goto error;
1082 }
1083 drv_data->irq_requested = 1;
1084 /* we use write mode, spi irq has to be disabled here */
1085 disable_irq(drv_data->spi_irq);
1086 }
1087
1088 if (chip->chip_select_num >= MAX_CTRL_CS) {
1089 /* Only request on first setup */
1090 if (spi_get_ctldata(spi) == NULL) {
1091 ret = gpio_request(chip->cs_gpio, spi->modalias);
1092 if (ret) {
1093 dev_err(&spi->dev, "gpio_request() error\n");
1094 goto pin_error;
1095 }
1096 gpio_direction_output(chip->cs_gpio, 1);
1097 }
1098 }
1099
1100 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1101 spi->modalias, spi->bits_per_word, chip->enable_dma);
1102 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1103 chip->ctl_reg, chip->flag);
1104
1105 spi_set_ctldata(spi, chip);
1106
1107 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1108 if (chip->chip_select_num < MAX_CTRL_CS) {
1109 ret = peripheral_request(ssel[spi->master->bus_num]
1110 [chip->chip_select_num-1], spi->modalias);
1111 if (ret) {
1112 dev_err(&spi->dev, "peripheral_request() error\n");
1113 goto pin_error;
1114 }
1115 }
1116
1117 bfin_spi_cs_enable(drv_data, chip);
1118 bfin_spi_cs_deactive(drv_data, chip);
1119
1120 return 0;
1121
1122 pin_error:
1123 if (chip->chip_select_num >= MAX_CTRL_CS)
1124 gpio_free(chip->cs_gpio);
1125 else
1126 peripheral_free(ssel[spi->master->bus_num]
1127 [chip->chip_select_num - 1]);
1128 error:
1129 if (chip) {
1130 if (drv_data->dma_requested)
1131 free_dma(drv_data->dma_channel);
1132 drv_data->dma_requested = 0;
1133
1134 kfree(chip);
1135 /* prevent free 'chip' twice */
1136 spi_set_ctldata(spi, NULL);
1137 }
1138
1139 return ret;
1140 }
1141
1142 /*
1143 * callback for spi framework.
1144 * clean driver specific data
1145 */
1146 static void bfin_spi_cleanup(struct spi_device *spi)
1147 {
1148 struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1149 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1150
1151 if (!chip)
1152 return;
1153
1154 if (chip->chip_select_num < MAX_CTRL_CS) {
1155 peripheral_free(ssel[spi->master->bus_num]
1156 [chip->chip_select_num-1]);
1157 bfin_spi_cs_disable(drv_data, chip);
1158 } else
1159 gpio_free(chip->cs_gpio);
1160
1161 kfree(chip);
1162 /* prevent free 'chip' twice */
1163 spi_set_ctldata(spi, NULL);
1164 }
1165
1166 static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1167 {
1168 INIT_LIST_HEAD(&drv_data->queue);
1169 spin_lock_init(&drv_data->lock);
1170
1171 drv_data->running = false;
1172 drv_data->busy = 0;
1173
1174 /* init transfer tasklet */
1175 tasklet_init(&drv_data->pump_transfers,
1176 bfin_spi_pump_transfers, (unsigned long)drv_data);
1177
1178 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1179
1180 return 0;
1181 }
1182
1183 static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1184 {
1185 unsigned long flags;
1186
1187 spin_lock_irqsave(&drv_data->lock, flags);
1188
1189 if (drv_data->running || drv_data->busy) {
1190 spin_unlock_irqrestore(&drv_data->lock, flags);
1191 return -EBUSY;
1192 }
1193
1194 drv_data->running = true;
1195 drv_data->cur_msg = NULL;
1196 drv_data->cur_transfer = NULL;
1197 drv_data->cur_chip = NULL;
1198 spin_unlock_irqrestore(&drv_data->lock, flags);
1199
1200 schedule_work(&drv_data->pump_messages);
1201
1202 return 0;
1203 }
1204
1205 static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1206 {
1207 unsigned long flags;
1208 unsigned limit = 500;
1209 int status = 0;
1210
1211 spin_lock_irqsave(&drv_data->lock, flags);
1212
1213 /*
1214 * This is a bit lame, but is optimized for the common execution path.
1215 * A wait_queue on the drv_data->busy could be used, but then the common
1216 * execution path (pump_messages) would be required to call wake_up or
1217 * friends on every SPI message. Do this instead
1218 */
1219 drv_data->running = false;
1220 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1221 spin_unlock_irqrestore(&drv_data->lock, flags);
1222 msleep(10);
1223 spin_lock_irqsave(&drv_data->lock, flags);
1224 }
1225
1226 if (!list_empty(&drv_data->queue) || drv_data->busy)
1227 status = -EBUSY;
1228
1229 spin_unlock_irqrestore(&drv_data->lock, flags);
1230
1231 return status;
1232 }
1233
1234 static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1235 {
1236 int status;
1237
1238 status = bfin_spi_stop_queue(drv_data);
1239 if (status != 0)
1240 return status;
1241
1242 flush_work(&drv_data->pump_messages);
1243
1244 return 0;
1245 }
1246
1247 static int bfin_spi_probe(struct platform_device *pdev)
1248 {
1249 struct device *dev = &pdev->dev;
1250 struct bfin5xx_spi_master *platform_info;
1251 struct spi_master *master;
1252 struct bfin_spi_master_data *drv_data;
1253 struct resource *res;
1254 int status = 0;
1255
1256 platform_info = dev_get_platdata(dev);
1257
1258 /* Allocate master with space for drv_data */
1259 master = spi_alloc_master(dev, sizeof(*drv_data));
1260 if (!master) {
1261 dev_err(&pdev->dev, "can not alloc spi_master\n");
1262 return -ENOMEM;
1263 }
1264
1265 drv_data = spi_master_get_devdata(master);
1266 drv_data->master = master;
1267 drv_data->master_info = platform_info;
1268 drv_data->pdev = pdev;
1269 drv_data->pin_req = platform_info->pin_req;
1270
1271 /* the spi->mode bits supported by this driver: */
1272 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1273 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1274 master->bus_num = pdev->id;
1275 master->num_chipselect = platform_info->num_chipselect;
1276 master->cleanup = bfin_spi_cleanup;
1277 master->setup = bfin_spi_setup;
1278 master->transfer = bfin_spi_transfer;
1279
1280 /* Find and map our resources */
1281 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1282 if (res == NULL) {
1283 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1284 status = -ENOENT;
1285 goto out_error_get_res;
1286 }
1287
1288 drv_data->regs = ioremap(res->start, resource_size(res));
1289 if (drv_data->regs == NULL) {
1290 dev_err(dev, "Cannot map IO\n");
1291 status = -ENXIO;
1292 goto out_error_ioremap;
1293 }
1294
1295 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1296 if (res == NULL) {
1297 dev_err(dev, "No DMA channel specified\n");
1298 status = -ENOENT;
1299 goto out_error_free_io;
1300 }
1301 drv_data->dma_channel = res->start;
1302
1303 drv_data->spi_irq = platform_get_irq(pdev, 0);
1304 if (drv_data->spi_irq < 0) {
1305 dev_err(dev, "No spi pio irq specified\n");
1306 status = -ENOENT;
1307 goto out_error_free_io;
1308 }
1309
1310 /* Initial and start queue */
1311 status = bfin_spi_init_queue(drv_data);
1312 if (status != 0) {
1313 dev_err(dev, "problem initializing queue\n");
1314 goto out_error_queue_alloc;
1315 }
1316
1317 status = bfin_spi_start_queue(drv_data);
1318 if (status != 0) {
1319 dev_err(dev, "problem starting queue\n");
1320 goto out_error_queue_alloc;
1321 }
1322
1323 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1324 if (status != 0) {
1325 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1326 goto out_error_queue_alloc;
1327 }
1328
1329 /* Reset SPI registers. If these registers were used by the boot loader,
1330 * the sky may fall on your head if you enable the dma controller.
1331 */
1332 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1333 bfin_write(&drv_data->regs->flg, 0xFF00);
1334
1335 /* Register with the SPI framework */
1336 platform_set_drvdata(pdev, drv_data);
1337 status = spi_register_master(master);
1338 if (status != 0) {
1339 dev_err(dev, "problem registering spi master\n");
1340 goto out_error_queue_alloc;
1341 }
1342
1343 dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
1344 DRV_DESC, DRV_VERSION, drv_data->regs,
1345 drv_data->dma_channel);
1346 return status;
1347
1348 out_error_queue_alloc:
1349 bfin_spi_destroy_queue(drv_data);
1350 out_error_free_io:
1351 iounmap(drv_data->regs);
1352 out_error_ioremap:
1353 out_error_get_res:
1354 spi_master_put(master);
1355
1356 return status;
1357 }
1358
1359 /* stop hardware and remove the driver */
1360 static int bfin_spi_remove(struct platform_device *pdev)
1361 {
1362 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1363 int status = 0;
1364
1365 if (!drv_data)
1366 return 0;
1367
1368 /* Remove the queue */
1369 status = bfin_spi_destroy_queue(drv_data);
1370 if (status != 0)
1371 return status;
1372
1373 /* Disable the SSP at the peripheral and SOC level */
1374 bfin_spi_disable(drv_data);
1375
1376 /* Release DMA */
1377 if (drv_data->master_info->enable_dma) {
1378 if (dma_channel_active(drv_data->dma_channel))
1379 free_dma(drv_data->dma_channel);
1380 }
1381
1382 if (drv_data->irq_requested) {
1383 free_irq(drv_data->spi_irq, drv_data);
1384 drv_data->irq_requested = 0;
1385 }
1386
1387 /* Disconnect from the SPI framework */
1388 spi_unregister_master(drv_data->master);
1389
1390 peripheral_free_list(drv_data->pin_req);
1391
1392 return 0;
1393 }
1394
1395 #ifdef CONFIG_PM_SLEEP
1396 static int bfin_spi_suspend(struct device *dev)
1397 {
1398 struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
1399 int status = 0;
1400
1401 status = bfin_spi_stop_queue(drv_data);
1402 if (status != 0)
1403 return status;
1404
1405 drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
1406 drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
1407
1408 /*
1409 * reset SPI_CTL and SPI_FLG registers
1410 */
1411 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1412 bfin_write(&drv_data->regs->flg, 0xFF00);
1413
1414 return 0;
1415 }
1416
1417 static int bfin_spi_resume(struct device *dev)
1418 {
1419 struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
1420 int status = 0;
1421
1422 bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
1423 bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
1424
1425 /* Start the queue running */
1426 status = bfin_spi_start_queue(drv_data);
1427 if (status != 0) {
1428 dev_err(dev, "problem starting queue (%d)\n", status);
1429 return status;
1430 }
1431
1432 return 0;
1433 }
1434
1435 static SIMPLE_DEV_PM_OPS(bfin_spi_pm_ops, bfin_spi_suspend, bfin_spi_resume);
1436
1437 #define BFIN_SPI_PM_OPS (&bfin_spi_pm_ops)
1438 #else
1439 #define BFIN_SPI_PM_OPS NULL
1440 #endif
1441
1442 MODULE_ALIAS("platform:bfin-spi");
1443 static struct platform_driver bfin_spi_driver = {
1444 .driver = {
1445 .name = DRV_NAME,
1446 .pm = BFIN_SPI_PM_OPS,
1447 },
1448 .probe = bfin_spi_probe,
1449 .remove = bfin_spi_remove,
1450 };
1451
1452 static int __init bfin_spi_init(void)
1453 {
1454 return platform_driver_register(&bfin_spi_driver);
1455 }
1456 subsys_initcall(bfin_spi_init);
1457
1458 static void __exit bfin_spi_exit(void)
1459 {
1460 platform_driver_unregister(&bfin_spi_driver);
1461 }
1462 module_exit(bfin_spi_exit);
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