2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/interrupt.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/edma.h>
28 #include <linux/of_device.h>
29 #include <linux/of_gpio.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/slab.h>
34 #include <linux/platform_data/spi-davinci.h>
36 #define SPI_NO_RESOURCE ((resource_size_t)-1)
38 #define CS_DEFAULT 0xFF
40 #define SPIFMT_PHASE_MASK BIT(16)
41 #define SPIFMT_POLARITY_MASK BIT(17)
42 #define SPIFMT_DISTIMER_MASK BIT(18)
43 #define SPIFMT_SHIFTDIR_MASK BIT(20)
44 #define SPIFMT_WAITENA_MASK BIT(21)
45 #define SPIFMT_PARITYENA_MASK BIT(22)
46 #define SPIFMT_ODD_PARITY_MASK BIT(23)
47 #define SPIFMT_WDELAY_MASK 0x3f000000u
48 #define SPIFMT_WDELAY_SHIFT 24
49 #define SPIFMT_PRESCALE_SHIFT 8
52 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
53 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
54 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
55 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
57 #define SPIINT_MASKALL 0x0101035F
58 #define SPIINT_MASKINT 0x0000015F
59 #define SPI_INTLVL_1 0x000001FF
60 #define SPI_INTLVL_0 0x00000000
62 /* SPIDAT1 (upper 16 bit defines) */
63 #define SPIDAT1_CSHOLD_MASK BIT(12)
64 #define SPIDAT1_WDEL BIT(10)
67 #define SPIGCR1_CLKMOD_MASK BIT(1)
68 #define SPIGCR1_MASTER_MASK BIT(0)
69 #define SPIGCR1_POWERDOWN_MASK BIT(8)
70 #define SPIGCR1_LOOPBACK_MASK BIT(16)
71 #define SPIGCR1_SPIENA_MASK BIT(24)
74 #define SPIBUF_TXFULL_MASK BIT(29)
75 #define SPIBUF_RXEMPTY_MASK BIT(31)
78 #define SPIDELAY_C2TDELAY_SHIFT 24
79 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
80 #define SPIDELAY_T2CDELAY_SHIFT 16
81 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
82 #define SPIDELAY_T2EDELAY_SHIFT 8
83 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
84 #define SPIDELAY_C2EDELAY_SHIFT 0
85 #define SPIDELAY_C2EDELAY_MASK 0xFF
88 #define SPIFLG_DLEN_ERR_MASK BIT(0)
89 #define SPIFLG_TIMEOUT_MASK BIT(1)
90 #define SPIFLG_PARERR_MASK BIT(2)
91 #define SPIFLG_DESYNC_MASK BIT(3)
92 #define SPIFLG_BITERR_MASK BIT(4)
93 #define SPIFLG_OVRRUN_MASK BIT(6)
94 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
95 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
96 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
97 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
100 #define SPIINT_DMA_REQ_EN BIT(16)
102 /* SPI Controller registers */
111 #define SPIDELAY 0x48
115 /* SPI Controller driver's private data. */
117 struct spi_bitbang bitbang
;
121 resource_size_t pbase
;
124 struct completion done
;
131 struct dma_chan
*dma_rx
;
132 struct dma_chan
*dma_tx
;
136 struct davinci_spi_platform_data pdata
;
138 void (*get_rx
)(u32 rx_data
, struct davinci_spi
*);
139 u32 (*get_tx
)(struct davinci_spi
*);
146 static struct davinci_spi_config davinci_spi_default_cfg
;
148 static void davinci_spi_rx_buf_u8(u32 data
, struct davinci_spi
*dspi
)
157 static void davinci_spi_rx_buf_u16(u32 data
, struct davinci_spi
*dspi
)
166 static u32
davinci_spi_tx_buf_u8(struct davinci_spi
*dspi
)
171 const u8
*tx
= dspi
->tx
;
179 static u32
davinci_spi_tx_buf_u16(struct davinci_spi
*dspi
)
184 const u16
*tx
= dspi
->tx
;
192 static inline void set_io_bits(void __iomem
*addr
, u32 bits
)
194 u32 v
= ioread32(addr
);
200 static inline void clear_io_bits(void __iomem
*addr
, u32 bits
)
202 u32 v
= ioread32(addr
);
209 * Interface to control the chip select signal
211 static void davinci_spi_chipselect(struct spi_device
*spi
, int value
)
213 struct davinci_spi
*dspi
;
214 struct davinci_spi_platform_data
*pdata
;
215 struct davinci_spi_config
*spicfg
= spi
->controller_data
;
216 u8 chip_sel
= spi
->chip_select
;
217 u16 spidat1
= CS_DEFAULT
;
218 bool gpio_chipsel
= false;
221 dspi
= spi_master_get_devdata(spi
->master
);
222 pdata
= &dspi
->pdata
;
224 if (spi
->cs_gpio
>= 0) {
225 /* SPI core parse and update master->cs_gpio */
230 /* program delay transfers if tx_delay is non zero */
232 spidat1
|= SPIDAT1_WDEL
;
235 * Board specific chip select logic decides the polarity and cs
236 * line for the controller
239 if (value
== BITBANG_CS_ACTIVE
)
240 gpio_set_value(gpio
, spi
->mode
& SPI_CS_HIGH
);
242 gpio_set_value(gpio
, !(spi
->mode
& SPI_CS_HIGH
));
244 if (value
== BITBANG_CS_ACTIVE
) {
245 spidat1
|= SPIDAT1_CSHOLD_MASK
;
246 spidat1
&= ~(0x1 << chip_sel
);
250 iowrite16(spidat1
, dspi
->base
+ SPIDAT1
+ 2);
254 * davinci_spi_get_prescale - Calculates the correct prescale value
255 * @maxspeed_hz: the maximum rate the SPI clock can run at
257 * This function calculates the prescale value that generates a clock rate
258 * less than or equal to the specified maximum.
260 * Returns: calculated prescale value for easy programming into SPI registers
261 * or negative error number if valid prescalar cannot be updated.
263 static inline int davinci_spi_get_prescale(struct davinci_spi
*dspi
,
268 /* Subtract 1 to match what will be programmed into SPI register. */
269 ret
= DIV_ROUND_UP(clk_get_rate(dspi
->clk
), max_speed_hz
) - 1;
271 if (ret
< dspi
->prescaler_limit
|| ret
> 255)
278 * davinci_spi_setup_transfer - This functions will determine transfer method
279 * @spi: spi device on which data transfer to be done
280 * @t: spi transfer in which transfer info is filled
282 * This function determines data transfer method (8/16/32 bit transfer).
283 * It will also set the SPI Clock Control register according to
284 * SPI slave device freq.
286 static int davinci_spi_setup_transfer(struct spi_device
*spi
,
287 struct spi_transfer
*t
)
290 struct davinci_spi
*dspi
;
291 struct davinci_spi_config
*spicfg
;
292 u8 bits_per_word
= 0;
293 u32 hz
= 0, spifmt
= 0;
296 dspi
= spi_master_get_devdata(spi
->master
);
297 spicfg
= spi
->controller_data
;
299 spicfg
= &davinci_spi_default_cfg
;
302 bits_per_word
= t
->bits_per_word
;
306 /* if bits_per_word is not set then set it default */
308 bits_per_word
= spi
->bits_per_word
;
311 * Assign function pointer to appropriate transfer method
312 * 8bit, 16bit or 32bit transfer
314 if (bits_per_word
<= 8) {
315 dspi
->get_rx
= davinci_spi_rx_buf_u8
;
316 dspi
->get_tx
= davinci_spi_tx_buf_u8
;
317 dspi
->bytes_per_word
[spi
->chip_select
] = 1;
319 dspi
->get_rx
= davinci_spi_rx_buf_u16
;
320 dspi
->get_tx
= davinci_spi_tx_buf_u16
;
321 dspi
->bytes_per_word
[spi
->chip_select
] = 2;
325 hz
= spi
->max_speed_hz
;
327 /* Set up SPIFMTn register, unique to this chipselect. */
329 prescale
= davinci_spi_get_prescale(dspi
, hz
);
333 spifmt
= (prescale
<< SPIFMT_PRESCALE_SHIFT
) | (bits_per_word
& 0x1f);
335 if (spi
->mode
& SPI_LSB_FIRST
)
336 spifmt
|= SPIFMT_SHIFTDIR_MASK
;
338 if (spi
->mode
& SPI_CPOL
)
339 spifmt
|= SPIFMT_POLARITY_MASK
;
341 if (!(spi
->mode
& SPI_CPHA
))
342 spifmt
|= SPIFMT_PHASE_MASK
;
345 * Assume wdelay is used only on SPI peripherals that has this field
346 * in SPIFMTn register and when it's configured from board file or DT.
349 spifmt
|= ((spicfg
->wdelay
<< SPIFMT_WDELAY_SHIFT
)
350 & SPIFMT_WDELAY_MASK
);
353 * Version 1 hardware supports two basic SPI modes:
354 * - Standard SPI mode uses 4 pins, with chipselect
355 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
356 * (distinct from SPI_3WIRE, with just one data wire;
357 * or similar variants without MOSI or without MISO)
359 * Version 2 hardware supports an optional handshaking signal,
360 * so it can support two more modes:
361 * - 5 pin SPI variant is standard SPI plus SPI_READY
362 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
365 if (dspi
->version
== SPI_VERSION_2
) {
369 if (spicfg
->odd_parity
)
370 spifmt
|= SPIFMT_ODD_PARITY_MASK
;
372 if (spicfg
->parity_enable
)
373 spifmt
|= SPIFMT_PARITYENA_MASK
;
375 if (spicfg
->timer_disable
) {
376 spifmt
|= SPIFMT_DISTIMER_MASK
;
378 delay
|= (spicfg
->c2tdelay
<< SPIDELAY_C2TDELAY_SHIFT
)
379 & SPIDELAY_C2TDELAY_MASK
;
380 delay
|= (spicfg
->t2cdelay
<< SPIDELAY_T2CDELAY_SHIFT
)
381 & SPIDELAY_T2CDELAY_MASK
;
384 if (spi
->mode
& SPI_READY
) {
385 spifmt
|= SPIFMT_WAITENA_MASK
;
386 delay
|= (spicfg
->t2edelay
<< SPIDELAY_T2EDELAY_SHIFT
)
387 & SPIDELAY_T2EDELAY_MASK
;
388 delay
|= (spicfg
->c2edelay
<< SPIDELAY_C2EDELAY_SHIFT
)
389 & SPIDELAY_C2EDELAY_MASK
;
392 iowrite32(delay
, dspi
->base
+ SPIDELAY
);
395 iowrite32(spifmt
, dspi
->base
+ SPIFMT0
);
400 static int davinci_spi_of_setup(struct spi_device
*spi
)
402 struct davinci_spi_config
*spicfg
= spi
->controller_data
;
403 struct device_node
*np
= spi
->dev
.of_node
;
406 if (spicfg
== NULL
&& np
) {
407 spicfg
= kzalloc(sizeof(*spicfg
), GFP_KERNEL
);
410 *spicfg
= davinci_spi_default_cfg
;
411 /* override with dt configured values */
412 if (!of_property_read_u32(np
, "ti,spi-wdelay", &prop
))
413 spicfg
->wdelay
= (u8
)prop
;
414 spi
->controller_data
= spicfg
;
421 * davinci_spi_setup - This functions will set default transfer method
422 * @spi: spi device on which data transfer to be done
424 * This functions sets the default transfer method.
426 static int davinci_spi_setup(struct spi_device
*spi
)
429 struct davinci_spi
*dspi
;
430 struct davinci_spi_platform_data
*pdata
;
431 struct spi_master
*master
= spi
->master
;
432 struct device_node
*np
= spi
->dev
.of_node
;
433 bool internal_cs
= true;
435 dspi
= spi_master_get_devdata(spi
->master
);
436 pdata
= &dspi
->pdata
;
438 if (!(spi
->mode
& SPI_NO_CS
)) {
439 if (np
&& (master
->cs_gpios
!= NULL
) && (spi
->cs_gpio
>= 0)) {
440 retval
= gpio_direction_output(
441 spi
->cs_gpio
, !(spi
->mode
& SPI_CS_HIGH
));
443 } else if (pdata
->chip_sel
&&
444 spi
->chip_select
< pdata
->num_chipselect
&&
445 pdata
->chip_sel
[spi
->chip_select
] != SPI_INTERN_CS
) {
446 spi
->cs_gpio
= pdata
->chip_sel
[spi
->chip_select
];
447 retval
= gpio_direction_output(
448 spi
->cs_gpio
, !(spi
->mode
& SPI_CS_HIGH
));
453 dev_err(&spi
->dev
, "GPIO %d setup failed (%d)\n",
454 spi
->cs_gpio
, retval
);
459 set_io_bits(dspi
->base
+ SPIPC0
, 1 << spi
->chip_select
);
462 if (spi
->mode
& SPI_READY
)
463 set_io_bits(dspi
->base
+ SPIPC0
, SPIPC0_SPIENA_MASK
);
465 if (spi
->mode
& SPI_LOOP
)
466 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_LOOPBACK_MASK
);
468 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_LOOPBACK_MASK
);
470 return davinci_spi_of_setup(spi
);
473 static void davinci_spi_cleanup(struct spi_device
*spi
)
475 struct davinci_spi_config
*spicfg
= spi
->controller_data
;
477 spi
->controller_data
= NULL
;
478 if (spi
->dev
.of_node
)
482 static int davinci_spi_check_error(struct davinci_spi
*dspi
, int int_status
)
484 struct device
*sdev
= dspi
->bitbang
.master
->dev
.parent
;
486 if (int_status
& SPIFLG_TIMEOUT_MASK
) {
487 dev_dbg(sdev
, "SPI Time-out Error\n");
490 if (int_status
& SPIFLG_DESYNC_MASK
) {
491 dev_dbg(sdev
, "SPI Desynchronization Error\n");
494 if (int_status
& SPIFLG_BITERR_MASK
) {
495 dev_dbg(sdev
, "SPI Bit error\n");
499 if (dspi
->version
== SPI_VERSION_2
) {
500 if (int_status
& SPIFLG_DLEN_ERR_MASK
) {
501 dev_dbg(sdev
, "SPI Data Length Error\n");
504 if (int_status
& SPIFLG_PARERR_MASK
) {
505 dev_dbg(sdev
, "SPI Parity Error\n");
508 if (int_status
& SPIFLG_OVRRUN_MASK
) {
509 dev_dbg(sdev
, "SPI Data Overrun error\n");
512 if (int_status
& SPIFLG_BUF_INIT_ACTIVE_MASK
) {
513 dev_dbg(sdev
, "SPI Buffer Init Active\n");
522 * davinci_spi_process_events - check for and handle any SPI controller events
523 * @dspi: the controller data
525 * This function will check the SPIFLG register and handle any events that are
528 static int davinci_spi_process_events(struct davinci_spi
*dspi
)
530 u32 buf
, status
, errors
= 0, spidat1
;
532 buf
= ioread32(dspi
->base
+ SPIBUF
);
534 if (dspi
->rcount
> 0 && !(buf
& SPIBUF_RXEMPTY_MASK
)) {
535 dspi
->get_rx(buf
& 0xFFFF, dspi
);
539 status
= ioread32(dspi
->base
+ SPIFLG
);
541 if (unlikely(status
& SPIFLG_ERROR_MASK
)) {
542 errors
= status
& SPIFLG_ERROR_MASK
;
546 if (dspi
->wcount
> 0 && !(buf
& SPIBUF_TXFULL_MASK
)) {
547 spidat1
= ioread32(dspi
->base
+ SPIDAT1
);
550 spidat1
|= 0xFFFF & dspi
->get_tx(dspi
);
551 iowrite32(spidat1
, dspi
->base
+ SPIDAT1
);
558 static void davinci_spi_dma_rx_callback(void *data
)
560 struct davinci_spi
*dspi
= (struct davinci_spi
*)data
;
564 if (!dspi
->wcount
&& !dspi
->rcount
)
565 complete(&dspi
->done
);
568 static void davinci_spi_dma_tx_callback(void *data
)
570 struct davinci_spi
*dspi
= (struct davinci_spi
*)data
;
574 if (!dspi
->wcount
&& !dspi
->rcount
)
575 complete(&dspi
->done
);
579 * davinci_spi_bufs - functions which will handle transfer data
580 * @spi: spi device on which data transfer to be done
581 * @t: spi transfer in which transfer info is filled
583 * This function will put data to be transferred into data register
584 * of SPI controller and then wait until the completion will be marked
585 * by the IRQ Handler.
587 static int davinci_spi_bufs(struct spi_device
*spi
, struct spi_transfer
*t
)
589 struct davinci_spi
*dspi
;
590 int data_type
, ret
= -ENOMEM
;
591 u32 tx_data
, spidat1
;
593 struct davinci_spi_config
*spicfg
;
594 struct davinci_spi_platform_data
*pdata
;
595 unsigned uninitialized_var(rx_buf_count
);
596 void *dummy_buf
= NULL
;
597 struct scatterlist sg_rx
, sg_tx
;
599 dspi
= spi_master_get_devdata(spi
->master
);
600 pdata
= &dspi
->pdata
;
601 spicfg
= (struct davinci_spi_config
*)spi
->controller_data
;
603 spicfg
= &davinci_spi_default_cfg
;
605 /* convert len to words based on bits_per_word */
606 data_type
= dspi
->bytes_per_word
[spi
->chip_select
];
608 dspi
->tx
= t
->tx_buf
;
609 dspi
->rx
= t
->rx_buf
;
610 dspi
->wcount
= t
->len
/ data_type
;
611 dspi
->rcount
= dspi
->wcount
;
613 spidat1
= ioread32(dspi
->base
+ SPIDAT1
);
615 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
616 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_SPIENA_MASK
);
618 reinit_completion(&dspi
->done
);
620 if (spicfg
->io_type
== SPI_IO_TYPE_INTR
)
621 set_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKINT
);
623 if (spicfg
->io_type
!= SPI_IO_TYPE_DMA
) {
624 /* start the transfer */
626 tx_data
= dspi
->get_tx(dspi
);
627 spidat1
&= 0xFFFF0000;
628 spidat1
|= tx_data
& 0xFFFF;
629 iowrite32(spidat1
, dspi
->base
+ SPIDAT1
);
631 struct dma_slave_config dma_rx_conf
= {
632 .direction
= DMA_DEV_TO_MEM
,
633 .src_addr
= (unsigned long)dspi
->pbase
+ SPIBUF
,
634 .src_addr_width
= data_type
,
637 struct dma_slave_config dma_tx_conf
= {
638 .direction
= DMA_MEM_TO_DEV
,
639 .dst_addr
= (unsigned long)dspi
->pbase
+ SPIDAT1
,
640 .dst_addr_width
= data_type
,
643 struct dma_async_tx_descriptor
*rxdesc
;
644 struct dma_async_tx_descriptor
*txdesc
;
647 dummy_buf
= kzalloc(t
->len
, GFP_KERNEL
);
649 goto err_alloc_dummy_buf
;
651 dmaengine_slave_config(dspi
->dma_rx
, &dma_rx_conf
);
652 dmaengine_slave_config(dspi
->dma_tx
, &dma_tx_conf
);
654 sg_init_table(&sg_rx
, 1);
659 t
->rx_dma
= dma_map_single(&spi
->dev
, buf
,
660 t
->len
, DMA_FROM_DEVICE
);
665 sg_dma_address(&sg_rx
) = t
->rx_dma
;
666 sg_dma_len(&sg_rx
) = t
->len
;
668 sg_init_table(&sg_tx
, 1);
672 buf
= (void *)t
->tx_buf
;
673 t
->tx_dma
= dma_map_single(&spi
->dev
, buf
,
674 t
->len
, DMA_TO_DEVICE
);
679 sg_dma_address(&sg_tx
) = t
->tx_dma
;
680 sg_dma_len(&sg_tx
) = t
->len
;
682 rxdesc
= dmaengine_prep_slave_sg(dspi
->dma_rx
,
683 &sg_rx
, 1, DMA_DEV_TO_MEM
,
684 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
688 txdesc
= dmaengine_prep_slave_sg(dspi
->dma_tx
,
689 &sg_tx
, 1, DMA_MEM_TO_DEV
,
690 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
694 rxdesc
->callback
= davinci_spi_dma_rx_callback
;
695 rxdesc
->callback_param
= (void *)dspi
;
696 txdesc
->callback
= davinci_spi_dma_tx_callback
;
697 txdesc
->callback_param
= (void *)dspi
;
699 if (pdata
->cshold_bug
)
700 iowrite16(spidat1
>> 16, dspi
->base
+ SPIDAT1
+ 2);
702 dmaengine_submit(rxdesc
);
703 dmaengine_submit(txdesc
);
705 dma_async_issue_pending(dspi
->dma_rx
);
706 dma_async_issue_pending(dspi
->dma_tx
);
708 set_io_bits(dspi
->base
+ SPIINT
, SPIINT_DMA_REQ_EN
);
711 /* Wait for the transfer to complete */
712 if (spicfg
->io_type
!= SPI_IO_TYPE_POLL
) {
713 wait_for_completion_interruptible(&(dspi
->done
));
715 while (dspi
->rcount
> 0 || dspi
->wcount
> 0) {
716 errors
= davinci_spi_process_events(dspi
);
723 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKALL
);
724 if (spicfg
->io_type
== SPI_IO_TYPE_DMA
) {
725 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_DMA_REQ_EN
);
727 dma_unmap_single(&spi
->dev
, t
->rx_dma
,
728 t
->len
, DMA_FROM_DEVICE
);
729 dma_unmap_single(&spi
->dev
, t
->tx_dma
,
730 t
->len
, DMA_TO_DEVICE
);
734 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_SPIENA_MASK
);
735 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
738 * Check for bit error, desync error,parity error,timeout error and
739 * receive overflow errors
742 ret
= davinci_spi_check_error(dspi
, errors
);
743 WARN(!ret
, "%s: error reported but no error found!\n",
744 dev_name(&spi
->dev
));
748 if (dspi
->rcount
!= 0 || dspi
->wcount
!= 0) {
749 dev_err(&spi
->dev
, "SPI data transfer error\n");
756 dma_unmap_single(&spi
->dev
, t
->tx_dma
, t
->len
, DMA_TO_DEVICE
);
758 dma_unmap_single(&spi
->dev
, t
->rx_dma
, t
->len
, DMA_FROM_DEVICE
);
766 * dummy_thread_fn - dummy thread function
767 * @irq: IRQ number for this SPI Master
768 * @context_data: structure for SPI Master controller davinci_spi
770 * This is to satisfy the request_threaded_irq() API so that the irq
771 * handler is called in interrupt context.
773 static irqreturn_t
dummy_thread_fn(s32 irq
, void *data
)
779 * davinci_spi_irq - Interrupt handler for SPI Master Controller
780 * @irq: IRQ number for this SPI Master
781 * @context_data: structure for SPI Master controller davinci_spi
783 * ISR will determine that interrupt arrives either for READ or WRITE command.
784 * According to command it will do the appropriate action. It will check
785 * transfer length and if it is not zero then dispatch transfer command again.
786 * If transfer length is zero then it will indicate the COMPLETION so that
787 * davinci_spi_bufs function can go ahead.
789 static irqreturn_t
davinci_spi_irq(s32 irq
, void *data
)
791 struct davinci_spi
*dspi
= data
;
794 status
= davinci_spi_process_events(dspi
);
795 if (unlikely(status
!= 0))
796 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKINT
);
798 if ((!dspi
->rcount
&& !dspi
->wcount
) || status
)
799 complete(&dspi
->done
);
804 static int davinci_spi_request_dma(struct davinci_spi
*dspi
)
807 struct device
*sdev
= dspi
->bitbang
.master
->dev
.parent
;
811 dma_cap_set(DMA_SLAVE
, mask
);
813 dspi
->dma_rx
= dma_request_channel(mask
, edma_filter_fn
,
814 &dspi
->dma_rx_chnum
);
816 dev_err(sdev
, "request RX DMA channel failed\n");
821 dspi
->dma_tx
= dma_request_channel(mask
, edma_filter_fn
,
822 &dspi
->dma_tx_chnum
);
824 dev_err(sdev
, "request TX DMA channel failed\n");
832 dma_release_channel(dspi
->dma_rx
);
837 #if defined(CONFIG_OF)
839 /* OF SPI data structure */
840 struct davinci_spi_of_data
{
845 static const struct davinci_spi_of_data dm6441_spi_data
= {
846 .version
= SPI_VERSION_1
,
847 .prescaler_limit
= 2,
850 static const struct davinci_spi_of_data da830_spi_data
= {
851 .version
= SPI_VERSION_2
,
852 .prescaler_limit
= 2,
855 static const struct davinci_spi_of_data keystone_spi_data
= {
856 .version
= SPI_VERSION_1
,
857 .prescaler_limit
= 0,
860 static const struct of_device_id davinci_spi_of_match
[] = {
862 .compatible
= "ti,dm6441-spi",
863 .data
= &dm6441_spi_data
,
866 .compatible
= "ti,da830-spi",
867 .data
= &da830_spi_data
,
870 .compatible
= "ti,keystone-spi",
871 .data
= &keystone_spi_data
,
875 MODULE_DEVICE_TABLE(of
, davinci_spi_of_match
);
878 * spi_davinci_get_pdata - Get platform data from DTS binding
879 * @pdev: ptr to platform data
880 * @dspi: ptr to driver data
882 * Parses and populates pdata in dspi from device tree bindings.
884 * NOTE: Not all platform data params are supported currently.
886 static int spi_davinci_get_pdata(struct platform_device
*pdev
,
887 struct davinci_spi
*dspi
)
889 struct device_node
*node
= pdev
->dev
.of_node
;
890 struct davinci_spi_of_data
*spi_data
;
891 struct davinci_spi_platform_data
*pdata
;
892 unsigned int num_cs
, intr_line
= 0;
893 const struct of_device_id
*match
;
895 pdata
= &dspi
->pdata
;
897 match
= of_match_device(davinci_spi_of_match
, &pdev
->dev
);
901 spi_data
= (struct davinci_spi_of_data
*)match
->data
;
903 pdata
->version
= spi_data
->version
;
904 pdata
->prescaler_limit
= spi_data
->prescaler_limit
;
906 * default num_cs is 1 and all chipsel are internal to the chip
907 * indicated by chip_sel being NULL or cs_gpios being NULL or
908 * set to -ENOENT. num-cs includes internal as well as gpios.
909 * indicated by chip_sel being NULL. GPIO based CS is not
910 * supported yet in DT bindings.
913 of_property_read_u32(node
, "num-cs", &num_cs
);
914 pdata
->num_chipselect
= num_cs
;
915 of_property_read_u32(node
, "ti,davinci-spi-intr-line", &intr_line
);
916 pdata
->intr_line
= intr_line
;
920 static struct davinci_spi_platform_data
921 *spi_davinci_get_pdata(struct platform_device
*pdev
,
922 struct davinci_spi
*dspi
)
929 * davinci_spi_probe - probe function for SPI Master Controller
930 * @pdev: platform_device structure which contains plateform specific data
932 * According to Linux Device Model this function will be invoked by Linux
933 * with platform_device struct which contains the device specific info.
934 * This function will map the SPI controller's memory, register IRQ,
935 * Reset SPI controller and setting its registers to default value.
936 * It will invoke spi_bitbang_start to create work queue so that client driver
937 * can register transfer method to work queue.
939 static int davinci_spi_probe(struct platform_device
*pdev
)
941 struct spi_master
*master
;
942 struct davinci_spi
*dspi
;
943 struct davinci_spi_platform_data
*pdata
;
945 resource_size_t dma_rx_chan
= SPI_NO_RESOURCE
;
946 resource_size_t dma_tx_chan
= SPI_NO_RESOURCE
;
950 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct davinci_spi
));
951 if (master
== NULL
) {
956 platform_set_drvdata(pdev
, master
);
958 dspi
= spi_master_get_devdata(master
);
960 if (dev_get_platdata(&pdev
->dev
)) {
961 pdata
= dev_get_platdata(&pdev
->dev
);
962 dspi
->pdata
= *pdata
;
964 /* update dspi pdata with that from the DT */
965 ret
= spi_davinci_get_pdata(pdev
, dspi
);
970 /* pdata in dspi is now updated and point pdata to that */
971 pdata
= &dspi
->pdata
;
973 dspi
->bytes_per_word
= devm_kzalloc(&pdev
->dev
,
974 sizeof(*dspi
->bytes_per_word
) *
975 pdata
->num_chipselect
, GFP_KERNEL
);
976 if (dspi
->bytes_per_word
== NULL
) {
981 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
987 dspi
->pbase
= r
->start
;
989 dspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
990 if (IS_ERR(dspi
->base
)) {
991 ret
= PTR_ERR(dspi
->base
);
995 ret
= platform_get_irq(pdev
, 0);
1002 ret
= devm_request_threaded_irq(&pdev
->dev
, dspi
->irq
, davinci_spi_irq
,
1003 dummy_thread_fn
, 0, dev_name(&pdev
->dev
), dspi
);
1007 dspi
->bitbang
.master
= master
;
1009 dspi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1010 if (IS_ERR(dspi
->clk
)) {
1014 clk_prepare_enable(dspi
->clk
);
1016 master
->dev
.of_node
= pdev
->dev
.of_node
;
1017 master
->bus_num
= pdev
->id
;
1018 master
->num_chipselect
= pdata
->num_chipselect
;
1019 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(2, 16);
1020 master
->setup
= davinci_spi_setup
;
1021 master
->cleanup
= davinci_spi_cleanup
;
1023 dspi
->bitbang
.chipselect
= davinci_spi_chipselect
;
1024 dspi
->bitbang
.setup_transfer
= davinci_spi_setup_transfer
;
1025 dspi
->prescaler_limit
= pdata
->prescaler_limit
;
1026 dspi
->version
= pdata
->version
;
1028 dspi
->bitbang
.flags
= SPI_NO_CS
| SPI_LSB_FIRST
| SPI_LOOP
;
1029 if (dspi
->version
== SPI_VERSION_2
)
1030 dspi
->bitbang
.flags
|= SPI_READY
;
1032 if (pdev
->dev
.of_node
) {
1035 for (i
= 0; i
< pdata
->num_chipselect
; i
++) {
1036 int cs_gpio
= of_get_named_gpio(pdev
->dev
.of_node
,
1039 if (cs_gpio
== -EPROBE_DEFER
) {
1044 if (gpio_is_valid(cs_gpio
)) {
1045 ret
= devm_gpio_request(&pdev
->dev
, cs_gpio
,
1046 dev_name(&pdev
->dev
));
1053 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1055 dma_rx_chan
= r
->start
;
1056 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
1058 dma_tx_chan
= r
->start
;
1060 dspi
->bitbang
.txrx_bufs
= davinci_spi_bufs
;
1061 if (dma_rx_chan
!= SPI_NO_RESOURCE
&&
1062 dma_tx_chan
!= SPI_NO_RESOURCE
) {
1063 dspi
->dma_rx_chnum
= dma_rx_chan
;
1064 dspi
->dma_tx_chnum
= dma_tx_chan
;
1066 ret
= davinci_spi_request_dma(dspi
);
1070 dev_info(&pdev
->dev
, "DMA: supported\n");
1071 dev_info(&pdev
->dev
, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n",
1072 &dma_rx_chan
, &dma_tx_chan
,
1073 pdata
->dma_event_q
);
1076 dspi
->get_rx
= davinci_spi_rx_buf_u8
;
1077 dspi
->get_tx
= davinci_spi_tx_buf_u8
;
1079 init_completion(&dspi
->done
);
1081 /* Reset In/OUT SPI module */
1082 iowrite32(0, dspi
->base
+ SPIGCR0
);
1084 iowrite32(1, dspi
->base
+ SPIGCR0
);
1086 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
1087 spipc0
= SPIPC0_DIFUN_MASK
| SPIPC0_DOFUN_MASK
| SPIPC0_CLKFUN_MASK
;
1088 iowrite32(spipc0
, dspi
->base
+ SPIPC0
);
1090 if (pdata
->intr_line
)
1091 iowrite32(SPI_INTLVL_1
, dspi
->base
+ SPILVL
);
1093 iowrite32(SPI_INTLVL_0
, dspi
->base
+ SPILVL
);
1095 iowrite32(CS_DEFAULT
, dspi
->base
+ SPIDEF
);
1097 /* master mode default */
1098 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_CLKMOD_MASK
);
1099 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_MASTER_MASK
);
1100 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
1102 ret
= spi_bitbang_start(&dspi
->bitbang
);
1106 dev_info(&pdev
->dev
, "Controller at 0x%p\n", dspi
->base
);
1111 dma_release_channel(dspi
->dma_rx
);
1112 dma_release_channel(dspi
->dma_tx
);
1114 clk_disable_unprepare(dspi
->clk
);
1116 spi_master_put(master
);
1122 * davinci_spi_remove - remove function for SPI Master Controller
1123 * @pdev: platform_device structure which contains plateform specific data
1125 * This function will do the reverse action of davinci_spi_probe function
1126 * It will free the IRQ and SPI controller's memory region.
1127 * It will also call spi_bitbang_stop to destroy the work queue which was
1128 * created by spi_bitbang_start.
1130 static int davinci_spi_remove(struct platform_device
*pdev
)
1132 struct davinci_spi
*dspi
;
1133 struct spi_master
*master
;
1135 master
= platform_get_drvdata(pdev
);
1136 dspi
= spi_master_get_devdata(master
);
1138 spi_bitbang_stop(&dspi
->bitbang
);
1140 clk_disable_unprepare(dspi
->clk
);
1141 spi_master_put(master
);
1146 static struct platform_driver davinci_spi_driver
= {
1148 .name
= "spi_davinci",
1149 .of_match_table
= of_match_ptr(davinci_spi_of_match
),
1151 .probe
= davinci_spi_probe
,
1152 .remove
= davinci_spi_remove
,
1154 module_platform_driver(davinci_spi_driver
);
1156 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1157 MODULE_LICENSE("GPL");