drivers/spi/spi-dw-mid.c

   1 /*
   2  * Special handling for DW core on Intel MID platform
   3  *
   4  * Copyright (c) 2009, 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/types.h>
  22
  23 #include "spi-dw.h"
  24
  25 #ifdef CONFIG_SPI_DW_MID_DMA
  26 #include <linux/intel_mid_dma.h>
  27 #include <linux/pci.h>
  28
  29 #define RX_BUSY         0
  30 #define TX_BUSY         1
  31
  32 struct mid_dma {
  33         struct intel_mid_dma_slave      dmas_tx;
  34         struct intel_mid_dma_slave      dmas_rx;
  35 };
  36
  37 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  38 {
  39         struct dw_spi *dws = param;
  40
  41         return dws->dma_dev == chan->device->dev;
  42 }
  43
  44 static int mid_spi_dma_init(struct dw_spi *dws)
  45 {
  46         struct mid_dma *dw_dma = dws->dma_priv;
  47         struct pci_dev *dma_dev;
  48         struct intel_mid_dma_slave *rxs, *txs;
  49         dma_cap_mask_t mask;
  50
  51         /*
  52          * Get pci device for DMA controller, currently it could only
  53          * be the DMA controller of Medfield
  54          */
  55         dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  56         if (!dma_dev)
  57                 return -ENODEV;
  58
  59         dws->dma_dev = &dma_dev->dev;
  60
  61         dma_cap_zero(mask);
  62         dma_cap_set(DMA_SLAVE, mask);
  63
  64         /* 1. Init rx channel */
  65         dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  66         if (!dws->rxchan)
  67                 goto err_exit;
  68         rxs = &dw_dma->dmas_rx;
  69         rxs->hs_mode = LNW_DMA_HW_HS;
  70         rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
  71         dws->rxchan->private = rxs;
  72
  73         /* 2. Init tx channel */
  74         dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  75         if (!dws->txchan)
  76                 goto free_rxchan;
  77         txs = &dw_dma->dmas_tx;
  78         txs->hs_mode = LNW_DMA_HW_HS;
  79         txs->cfg_mode = LNW_DMA_MEM_TO_PER;
  80         dws->txchan->private = txs;
  81
  82         dws->dma_inited = 1;
  83         return 0;
  84
  85 free_rxchan:
  86         dma_release_channel(dws->rxchan);
  87 err_exit:
  88         return -EBUSY;
  89 }
  90
  91 static void mid_spi_dma_exit(struct dw_spi *dws)
  92 {
  93         if (!dws->dma_inited)
  94                 return;
  95
  96         dmaengine_terminate_all(dws->txchan);
  97         dma_release_channel(dws->txchan);
  98
  99         dmaengine_terminate_all(dws->rxchan);
 100         dma_release_channel(dws->rxchan);
 101 }
 102
 103 /*
 104  * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 105  * channel will clear a corresponding bit.
 106  */
 107 static void dw_spi_dma_tx_done(void *arg)
 108 {
 109         struct dw_spi *dws = arg;
 110
 111         if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
 112                 return;
 113         dw_spi_xfer_done(dws);
 114 }
 115
 116 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
 117 {
 118         struct dma_slave_config txconf;
 119         struct dma_async_tx_descriptor *txdesc;
 120
 121         if (!dws->tx_dma)
 122                 return NULL;
 123
 124         txconf.direction = DMA_MEM_TO_DEV;
 125         txconf.dst_addr = dws->dma_addr;
 126         txconf.dst_maxburst = LNW_DMA_MSIZE_16;
 127         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 128         txconf.dst_addr_width = dws->dma_width;
 129         txconf.device_fc = false;
 130
 131         dmaengine_slave_config(dws->txchan, &txconf);
 132
 133         memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
 134         dws->tx_sgl.dma_address = dws->tx_dma;
 135         dws->tx_sgl.length = dws->len;
 136
 137         txdesc = dmaengine_prep_slave_sg(dws->txchan,
 138                                 &dws->tx_sgl,
 139                                 1,
 140                                 DMA_MEM_TO_DEV,
 141                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 142         txdesc->callback = dw_spi_dma_tx_done;
 143         txdesc->callback_param = dws;
 144
 145         return txdesc;
 146 }
 147
 148 /*
 149  * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 150  * channel will clear a corresponding bit.
 151  */
 152 static void dw_spi_dma_rx_done(void *arg)
 153 {
 154         struct dw_spi *dws = arg;
 155
 156         if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
 157                 return;
 158         dw_spi_xfer_done(dws);
 159 }
 160
 161 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
 162 {
 163         struct dma_slave_config rxconf;
 164         struct dma_async_tx_descriptor *rxdesc;
 165
 166         if (!dws->rx_dma)
 167                 return NULL;
 168
 169         rxconf.direction = DMA_DEV_TO_MEM;
 170         rxconf.src_addr = dws->dma_addr;
 171         rxconf.src_maxburst = LNW_DMA_MSIZE_16;
 172         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 173         rxconf.src_addr_width = dws->dma_width;
 174         rxconf.device_fc = false;
 175
 176         dmaengine_slave_config(dws->rxchan, &rxconf);
 177
 178         memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
 179         dws->rx_sgl.dma_address = dws->rx_dma;
 180         dws->rx_sgl.length = dws->len;
 181
 182         rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
 183                                 &dws->rx_sgl,
 184                                 1,
 185                                 DMA_DEV_TO_MEM,
 186                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 187         rxdesc->callback = dw_spi_dma_rx_done;
 188         rxdesc->callback_param = dws;
 189
 190         return rxdesc;
 191 }
 192
 193 static void dw_spi_dma_setup(struct dw_spi *dws)
 194 {
 195         u16 dma_ctrl = 0;
 196
 197         spi_enable_chip(dws, 0);
 198
 199         dw_writew(dws, DW_SPI_DMARDLR, 0xf);
 200         dw_writew(dws, DW_SPI_DMATDLR, 0x10);
 201
 202         if (dws->tx_dma)
 203                 dma_ctrl |= SPI_DMA_TDMAE;
 204         if (dws->rx_dma)
 205                 dma_ctrl |= SPI_DMA_RDMAE;
 206         dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
 207
 208         spi_enable_chip(dws, 1);
 209 }
 210
 211 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
 212 {
 213         struct dma_async_tx_descriptor *txdesc, *rxdesc;
 214
 215         /* 1. setup DMA related registers */
 216         if (cs_change)
 217                 dw_spi_dma_setup(dws);
 218
 219         /* 2. Prepare the TX dma transfer */
 220         txdesc = dw_spi_dma_prepare_tx(dws);
 221
 222         /* 3. Prepare the RX dma transfer */
 223         rxdesc = dw_spi_dma_prepare_rx(dws);
 224
 225         /* rx must be started before tx due to spi instinct */
 226         if (rxdesc) {
 227                 set_bit(RX_BUSY, &dws->dma_chan_busy);
 228                 dmaengine_submit(rxdesc);
 229                 dma_async_issue_pending(dws->rxchan);
 230         }
 231
 232         if (txdesc) {
 233                 set_bit(TX_BUSY, &dws->dma_chan_busy);
 234                 dmaengine_submit(txdesc);
 235                 dma_async_issue_pending(dws->txchan);
 236         }
 237
 238         return 0;
 239 }
 240
 241 static struct dw_spi_dma_ops mid_dma_ops = {
 242         .dma_init       = mid_spi_dma_init,
 243         .dma_exit       = mid_spi_dma_exit,
 244         .dma_transfer   = mid_spi_dma_transfer,
 245 };
 246 #endif
 247
 248 /* Some specific info for SPI0 controller on Intel MID */
 249
 250 /* HW info for MRST CLk Control Unit, one 32b reg */
 251 #define MRST_SPI_CLK_BASE       100000000       /* 100m */
 252 #define MRST_CLK_SPI0_REG       0xff11d86c
 253 #define CLK_SPI_BDIV_OFFSET     0
 254 #define CLK_SPI_BDIV_MASK       0x00000007
 255 #define CLK_SPI_CDIV_OFFSET     9
 256 #define CLK_SPI_CDIV_MASK       0x00000e00
 257 #define CLK_SPI_DISABLE_OFFSET  8
 258
 259 int dw_spi_mid_init(struct dw_spi *dws)
 260 {
 261         void __iomem *clk_reg;
 262         u32 clk_cdiv;
 263
 264         clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
 265         if (!clk_reg)
 266                 return -ENOMEM;
 267
 268         /* get SPI controller operating freq info */
 269         clk_cdiv  = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
 270         dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 271         iounmap(clk_reg);
 272
 273         dws->num_cs = 16;
 274         dws->fifo_len = 40;     /* FIFO has 40 words buffer */
 275
 276 #ifdef CONFIG_SPI_DW_MID_DMA
 277         dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
 278         if (!dws->dma_priv)
 279                 return -ENOMEM;
 280         dws->dma_ops = &mid_dma_ops;
 281 #endif
 282         return 0;
 283 }