drivers/spi/spi-fsl-dspi.c

   1 /*
   2  * drivers/spi/spi-fsl-dspi.c
   3  *
   4  * Copyright 2013 Freescale Semiconductor, Inc.
   5  *
   6  * Freescale DSPI driver
   7  * This file contains a driver for the Freescale DSPI
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/errno.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/math64.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/regmap.h>
  31 #include <linux/sched.h>
  32 #include <linux/spi/spi.h>
  33 #include <linux/spi/spi_bitbang.h>
  34 #include <linux/time.h>
  35
  36 #define DRIVER_NAME "fsl-dspi"
  37
  38 #define TRAN_STATE_RX_VOID              0x01
  39 #define TRAN_STATE_TX_VOID              0x02
  40 #define TRAN_STATE_WORD_ODD_NUM 0x04
  41
  42 #define DSPI_FIFO_SIZE                  4
  43
  44 #define SPI_MCR         0x00
  45 #define SPI_MCR_MASTER          (1 << 31)
  46 #define SPI_MCR_PCSIS           (0x3F << 16)
  47 #define SPI_MCR_CLR_TXF (1 << 11)
  48 #define SPI_MCR_CLR_RXF (1 << 10)
  49
  50 #define SPI_TCR                 0x08
  51 #define SPI_TCR_GET_TCNT(x)     (((x) & 0xffff0000) >> 16)
  52
  53 #define SPI_CTAR(x)             (0x0c + (((x) & 0x3) * 4))
  54 #define SPI_CTAR_FMSZ(x)        (((x) & 0x0000000f) << 27)
  55 #define SPI_CTAR_CPOL(x)        ((x) << 26)
  56 #define SPI_CTAR_CPHA(x)        ((x) << 25)
  57 #define SPI_CTAR_LSBFE(x)       ((x) << 24)
  58 #define SPI_CTAR_PCSSCK(x)      (((x) & 0x00000003) << 22)
  59 #define SPI_CTAR_PASC(x)        (((x) & 0x00000003) << 20)
  60 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
  61 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
  62 #define SPI_CTAR_CSSCK(x)       (((x) & 0x0000000f) << 12)
  63 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
  64 #define SPI_CTAR_DT(x)          (((x) & 0x0000000f) << 4)
  65 #define SPI_CTAR_BR(x)          ((x) & 0x0000000f)
  66 #define SPI_CTAR_SCALE_BITS     0xf
  67
  68 #define SPI_CTAR0_SLAVE 0x0c
  69
  70 #define SPI_SR                  0x2c
  71 #define SPI_SR_EOQF             0x10000000
  72 #define SPI_SR_TCFQF            0x80000000
  73 #define SPI_SR_CLEAR            0xdaad0000
  74
  75 #define SPI_RSER                0x30
  76 #define SPI_RSER_EOQFE          0x10000000
  77 #define SPI_RSER_TCFQE          0x80000000
  78
  79 #define SPI_PUSHR               0x34
  80 #define SPI_PUSHR_CONT          (1 << 31)
  81 #define SPI_PUSHR_CTAS(x)       (((x) & 0x00000003) << 28)
  82 #define SPI_PUSHR_EOQ           (1 << 27)
  83 #define SPI_PUSHR_CTCNT (1 << 26)
  84 #define SPI_PUSHR_PCS(x)        (((1 << x) & 0x0000003f) << 16)
  85 #define SPI_PUSHR_TXDATA(x)     ((x) & 0x0000ffff)
  86
  87 #define SPI_PUSHR_SLAVE 0x34
  88
  89 #define SPI_POPR                0x38
  90 #define SPI_POPR_RXDATA(x)      ((x) & 0x0000ffff)
  91
  92 #define SPI_TXFR0               0x3c
  93 #define SPI_TXFR1               0x40
  94 #define SPI_TXFR2               0x44
  95 #define SPI_TXFR3               0x48
  96 #define SPI_RXFR0               0x7c
  97 #define SPI_RXFR1               0x80
  98 #define SPI_RXFR2               0x84
  99 #define SPI_RXFR3               0x88
 100
 101 #define SPI_FRAME_BITS(bits)    SPI_CTAR_FMSZ((bits) - 1)
 102 #define SPI_FRAME_BITS_MASK     SPI_CTAR_FMSZ(0xf)
 103 #define SPI_FRAME_BITS_16       SPI_CTAR_FMSZ(0xf)
 104 #define SPI_FRAME_BITS_8        SPI_CTAR_FMSZ(0x7)
 105
 106 #define SPI_CS_INIT             0x01
 107 #define SPI_CS_ASSERT           0x02
 108 #define SPI_CS_DROP             0x04
 109
 110 #define SPI_TCR_TCNT_MAX        0x10000
 111
 112 struct chip_data {
 113         u32 mcr_val;
 114         u32 ctar_val;
 115         u16 void_write_data;
 116 };
 117
 118 enum dspi_trans_mode {
 119         DSPI_EOQ_MODE = 0,
 120         DSPI_TCFQ_MODE,
 121 };
 122
 123 struct fsl_dspi_devtype_data {
 124         enum dspi_trans_mode trans_mode;
 125         u8 max_clock_factor;
 126 };
 127
 128 static const struct fsl_dspi_devtype_data vf610_data = {
 129         .trans_mode = DSPI_EOQ_MODE,
 130         .max_clock_factor = 2,
 131 };
 132
 133 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
 134         .trans_mode = DSPI_TCFQ_MODE,
 135         .max_clock_factor = 8,
 136 };
 137
 138 static const struct fsl_dspi_devtype_data ls2085a_data = {
 139         .trans_mode = DSPI_TCFQ_MODE,
 140         .max_clock_factor = 8,
 141 };
 142
 143 struct fsl_dspi {
 144         struct spi_master       *master;
 145         struct platform_device  *pdev;
 146
 147         struct regmap           *regmap;
 148         int                     irq;
 149         struct clk              *clk;
 150
 151         struct spi_transfer     *cur_transfer;
 152         struct spi_message      *cur_msg;
 153         struct chip_data        *cur_chip;
 154         size_t                  len;
 155         void                    *tx;
 156         void                    *tx_end;
 157         void                    *rx;
 158         void                    *rx_end;
 159         char                    dataflags;
 160         u8                      cs;
 161         u16                     void_write_data;
 162         u32                     cs_change;
 163         const struct fsl_dspi_devtype_data *devtype_data;
 164
 165         wait_queue_head_t       waitq;
 166         u32                     waitflags;
 167
 168         u32                     spi_tcnt;
 169 };
 170
 171 static inline int is_double_byte_mode(struct fsl_dspi *dspi)
 172 {
 173         unsigned int val;
 174
 175         regmap_read(dspi->regmap, SPI_CTAR(0), &val);
 176
 177         return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
 178 }
 179
 180 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
 181                 unsigned long clkrate)
 182 {
 183         /* Valid baud rate pre-scaler values */
 184         int pbr_tbl[4] = {2, 3, 5, 7};
 185         int brs[16] = { 2,      4,      6,      8,
 186                 16,     32,     64,     128,
 187                 256,    512,    1024,   2048,
 188                 4096,   8192,   16384,  32768 };
 189         int scale_needed, scale, minscale = INT_MAX;
 190         int i, j;
 191
 192         scale_needed = clkrate / speed_hz;
 193         if (clkrate % speed_hz)
 194                 scale_needed++;
 195
 196         for (i = 0; i < ARRAY_SIZE(brs); i++)
 197                 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
 198                         scale = brs[i] * pbr_tbl[j];
 199                         if (scale >= scale_needed) {
 200                                 if (scale < minscale) {
 201                                         minscale = scale;
 202                                         *br = i;
 203                                         *pbr = j;
 204                                 }
 205                                 break;
 206                         }
 207                 }
 208
 209         if (minscale == INT_MAX) {
 210                 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
 211                         speed_hz, clkrate);
 212                 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
 213                 *br =  ARRAY_SIZE(brs) - 1;
 214         }
 215 }
 216
 217 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
 218                 unsigned long clkrate)
 219 {
 220         int pscale_tbl[4] = {1, 3, 5, 7};
 221         int scale_needed, scale, minscale = INT_MAX;
 222         int i, j;
 223         u32 remainder;
 224
 225         scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
 226                         &remainder);
 227         if (remainder)
 228                 scale_needed++;
 229
 230         for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
 231                 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
 232                         scale = pscale_tbl[i] * (2 << j);
 233                         if (scale >= scale_needed) {
 234                                 if (scale < minscale) {
 235                                         minscale = scale;
 236                                         *psc = i;
 237                                         *sc = j;
 238                                 }
 239                                 break;
 240                         }
 241                 }
 242
 243         if (minscale == INT_MAX) {
 244                 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
 245                         delay_ns, clkrate);
 246                 *psc = ARRAY_SIZE(pscale_tbl) - 1;
 247                 *sc = SPI_CTAR_SCALE_BITS;
 248         }
 249 }
 250
 251 static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word)
 252 {
 253         u16 d16;
 254
 255         if (!(dspi->dataflags & TRAN_STATE_TX_VOID))
 256                 d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx;
 257         else
 258                 d16 = dspi->void_write_data;
 259
 260         dspi->tx += tx_word + 1;
 261         dspi->len -= tx_word + 1;
 262
 263         return  SPI_PUSHR_TXDATA(d16) |
 264                 SPI_PUSHR_PCS(dspi->cs) |
 265                 SPI_PUSHR_CTAS(0) |
 266                 SPI_PUSHR_CONT;
 267 }
 268
 269 static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word)
 270 {
 271         u16 d;
 272         unsigned int val;
 273
 274         regmap_read(dspi->regmap, SPI_POPR, &val);
 275         d = SPI_POPR_RXDATA(val);
 276
 277         if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
 278                 rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d);
 279
 280         dspi->rx += rx_word + 1;
 281 }
 282
 283 static int dspi_eoq_write(struct fsl_dspi *dspi)
 284 {
 285         int tx_count = 0;
 286         int tx_word;
 287         u32 dspi_pushr = 0;
 288
 289         tx_word = is_double_byte_mode(dspi);
 290
 291         while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
 292                 /* If we are in word mode, only have a single byte to transfer
 293                  * switch to byte mode temporarily.  Will switch back at the
 294                  * end of the transfer.
 295                  */
 296                 if (tx_word && (dspi->len == 1)) {
 297                         dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
 298                         regmap_update_bits(dspi->regmap, SPI_CTAR(0),
 299                                         SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
 300                         tx_word = 0;
 301                 }
 302
 303                 dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
 304
 305                 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
 306                         /* last transfer in the transfer */
 307                         dspi_pushr |= SPI_PUSHR_EOQ;
 308                         if ((dspi->cs_change) && (!dspi->len))
 309                                 dspi_pushr &= ~SPI_PUSHR_CONT;
 310                 } else if (tx_word && (dspi->len == 1))
 311                         dspi_pushr |= SPI_PUSHR_EOQ;
 312
 313                 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
 314
 315                 tx_count++;
 316         }
 317
 318         return tx_count * (tx_word + 1);
 319 }
 320
 321 static int dspi_eoq_read(struct fsl_dspi *dspi)
 322 {
 323         int rx_count = 0;
 324         int rx_word = is_double_byte_mode(dspi);
 325
 326         while ((dspi->rx < dspi->rx_end)
 327                         && (rx_count < DSPI_FIFO_SIZE)) {
 328                 if (rx_word && (dspi->rx_end - dspi->rx) == 1)
 329                         rx_word = 0;
 330
 331                 dspi_data_from_popr(dspi, rx_word);
 332                 rx_count++;
 333         }
 334
 335         return rx_count;
 336 }
 337
 338 static int dspi_tcfq_write(struct fsl_dspi *dspi)
 339 {
 340         int tx_word;
 341         u32 dspi_pushr = 0;
 342
 343         tx_word = is_double_byte_mode(dspi);
 344
 345         if (tx_word && (dspi->len == 1)) {
 346                 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
 347                 regmap_update_bits(dspi->regmap, SPI_CTAR(0),
 348                                 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
 349                 tx_word = 0;
 350         }
 351
 352         dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
 353
 354         if ((dspi->cs_change) && (!dspi->len))
 355                 dspi_pushr &= ~SPI_PUSHR_CONT;
 356
 357         regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
 358
 359         return tx_word + 1;
 360 }
 361
 362 static void dspi_tcfq_read(struct fsl_dspi *dspi)
 363 {
 364         int rx_word = is_double_byte_mode(dspi);
 365
 366         if (rx_word && (dspi->rx_end - dspi->rx) == 1)
 367                 rx_word = 0;
 368
 369         dspi_data_from_popr(dspi, rx_word);
 370 }
 371
 372 static int dspi_transfer_one_message(struct spi_master *master,
 373                 struct spi_message *message)
 374 {
 375         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 376         struct spi_device *spi = message->spi;
 377         struct spi_transfer *transfer;
 378         int status = 0;
 379         enum dspi_trans_mode trans_mode;
 380         u32 spi_tcr;
 381
 382         regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
 383         dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
 384
 385         message->actual_length = 0;
 386
 387         list_for_each_entry(transfer, &message->transfers, transfer_list) {
 388                 dspi->cur_transfer = transfer;
 389                 dspi->cur_msg = message;
 390                 dspi->cur_chip = spi_get_ctldata(spi);
 391                 dspi->cs = spi->chip_select;
 392                 dspi->cs_change = 0;
 393                 if (list_is_last(&dspi->cur_transfer->transfer_list,
 394                                  &dspi->cur_msg->transfers) || transfer->cs_change)
 395                         dspi->cs_change = 1;
 396                 dspi->void_write_data = dspi->cur_chip->void_write_data;
 397
 398                 dspi->dataflags = 0;
 399                 dspi->tx = (void *)transfer->tx_buf;
 400                 dspi->tx_end = dspi->tx + transfer->len;
 401                 dspi->rx = transfer->rx_buf;
 402                 dspi->rx_end = dspi->rx + transfer->len;
 403                 dspi->len = transfer->len;
 404
 405                 if (!dspi->rx)
 406                         dspi->dataflags |= TRAN_STATE_RX_VOID;
 407
 408                 if (!dspi->tx)
 409                         dspi->dataflags |= TRAN_STATE_TX_VOID;
 410
 411                 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
 412                 regmap_update_bits(dspi->regmap, SPI_MCR,
 413                                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
 414                                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
 415                 regmap_write(dspi->regmap, SPI_CTAR(0),
 416                                 dspi->cur_chip->ctar_val);
 417
 418                 trans_mode = dspi->devtype_data->trans_mode;
 419                 switch (trans_mode) {
 420                 case DSPI_EOQ_MODE:
 421                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
 422                         dspi_eoq_write(dspi);
 423                         break;
 424                 case DSPI_TCFQ_MODE:
 425                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
 426                         dspi_tcfq_write(dspi);
 427                         break;
 428                 default:
 429                         dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 430                                 trans_mode);
 431                         status = -EINVAL;
 432                         goto out;
 433                 }
 434
 435                 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
 436                         dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
 437                 dspi->waitflags = 0;
 438
 439                 if (transfer->delay_usecs)
 440                         udelay(transfer->delay_usecs);
 441         }
 442
 443 out:
 444         message->status = status;
 445         spi_finalize_current_message(master);
 446
 447         return status;
 448 }
 449
 450 static int dspi_setup(struct spi_device *spi)
 451 {
 452         struct chip_data *chip;
 453         struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
 454         u32 cs_sck_delay = 0, sck_cs_delay = 0;
 455         unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
 456         unsigned char pasc = 0, asc = 0, fmsz = 0;
 457         unsigned long clkrate;
 458
 459         if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
 460                 fmsz = spi->bits_per_word - 1;
 461         } else {
 462                 pr_err("Invalid wordsize\n");
 463                 return -ENODEV;
 464         }
 465
 466         /* Only alloc on first setup */
 467         chip = spi_get_ctldata(spi);
 468         if (chip == NULL) {
 469                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 470                 if (!chip)
 471                         return -ENOMEM;
 472         }
 473
 474         of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
 475                         &cs_sck_delay);
 476
 477         of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
 478                         &sck_cs_delay);
 479
 480         chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
 481                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
 482
 483         chip->void_write_data = 0;
 484
 485         clkrate = clk_get_rate(dspi->clk);
 486         hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
 487
 488         /* Set PCS to SCK delay scale values */
 489         ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
 490
 491         /* Set After SCK delay scale values */
 492         ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
 493
 494         chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)
 495                 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
 496                 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
 497                 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
 498                 | SPI_CTAR_PCSSCK(pcssck)
 499                 | SPI_CTAR_CSSCK(cssck)
 500                 | SPI_CTAR_PASC(pasc)
 501                 | SPI_CTAR_ASC(asc)
 502                 | SPI_CTAR_PBR(pbr)
 503                 | SPI_CTAR_BR(br);
 504
 505         spi_set_ctldata(spi, chip);
 506
 507         return 0;
 508 }
 509
 510 static void dspi_cleanup(struct spi_device *spi)
 511 {
 512         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
 513
 514         dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
 515                         spi->master->bus_num, spi->chip_select);
 516
 517         kfree(chip);
 518 }
 519
 520 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
 521 {
 522         struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
 523         struct spi_message *msg = dspi->cur_msg;
 524         enum dspi_trans_mode trans_mode;
 525         u32 spi_sr, spi_tcr;
 526         u32 spi_tcnt, tcnt_diff;
 527         int tx_word;
 528
 529         regmap_read(dspi->regmap, SPI_SR, &spi_sr);
 530         regmap_write(dspi->regmap, SPI_SR, spi_sr);
 531
 532
 533         if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
 534                 tx_word = is_double_byte_mode(dspi);
 535
 536                 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
 537                 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
 538                 /*
 539                  * The width of SPI Transfer Counter in SPI_TCR is 16bits,
 540                  * so the max couner is 65535. When the counter reach 65535,
 541                  * it will wrap around, counter reset to zero.
 542                  * spi_tcnt my be less than dspi->spi_tcnt, it means the
 543                  * counter already wrapped around.
 544                  * SPI Transfer Counter is a counter of transmitted frames.
 545                  * The size of frame maybe two bytes.
 546                  */
 547                 tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt)
 548                         % SPI_TCR_TCNT_MAX;
 549                 tcnt_diff *= (tx_word + 1);
 550                 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
 551                         tcnt_diff--;
 552
 553                 msg->actual_length += tcnt_diff;
 554
 555                 dspi->spi_tcnt = spi_tcnt;
 556
 557                 trans_mode = dspi->devtype_data->trans_mode;
 558                 switch (trans_mode) {
 559                 case DSPI_EOQ_MODE:
 560                         dspi_eoq_read(dspi);
 561                         break;
 562                 case DSPI_TCFQ_MODE:
 563                         dspi_tcfq_read(dspi);
 564                         break;
 565                 default:
 566                         dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 567                                 trans_mode);
 568                                 return IRQ_HANDLED;
 569                 }
 570
 571                 if (!dspi->len) {
 572                         if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) {
 573                                 regmap_update_bits(dspi->regmap,
 574                                                    SPI_CTAR(0),
 575                                                    SPI_FRAME_BITS_MASK,
 576                                                    SPI_FRAME_BITS(16));
 577                                 dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM;
 578                         }
 579
 580                         dspi->waitflags = 1;
 581                         wake_up_interruptible(&dspi->waitq);
 582                 } else {
 583                         switch (trans_mode) {
 584                         case DSPI_EOQ_MODE:
 585                                 dspi_eoq_write(dspi);
 586                                 break;
 587                         case DSPI_TCFQ_MODE:
 588                                 dspi_tcfq_write(dspi);
 589                                 break;
 590                         default:
 591                                 dev_err(&dspi->pdev->dev,
 592                                         "unsupported trans_mode %u\n",
 593                                         trans_mode);
 594                         }
 595                 }
 596         }
 597
 598         return IRQ_HANDLED;
 599 }
 600
 601 static const struct of_device_id fsl_dspi_dt_ids[] = {
 602         { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, },
 603         { .compatible = "fsl,ls1021a-v1.0-dspi",
 604                 .data = (void *)&ls1021a_v1_data, },
 605         { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, },
 606         { /* sentinel */ }
 607 };
 608 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
 609
 610 #ifdef CONFIG_PM_SLEEP
 611 static int dspi_suspend(struct device *dev)
 612 {
 613         struct spi_master *master = dev_get_drvdata(dev);
 614         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 615
 616         spi_master_suspend(master);
 617         clk_disable_unprepare(dspi->clk);
 618
 619         pinctrl_pm_select_sleep_state(dev);
 620
 621         return 0;
 622 }
 623
 624 static int dspi_resume(struct device *dev)
 625 {
 626         struct spi_master *master = dev_get_drvdata(dev);
 627         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 628         int ret;
 629
 630         pinctrl_pm_select_default_state(dev);
 631
 632         ret = clk_prepare_enable(dspi->clk);
 633         if (ret)
 634                 return ret;
 635         spi_master_resume(master);
 636
 637         return 0;
 638 }
 639 #endif /* CONFIG_PM_SLEEP */
 640
 641 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
 642
 643 static const struct regmap_config dspi_regmap_config = {
 644         .reg_bits = 32,
 645         .val_bits = 32,
 646         .reg_stride = 4,
 647         .max_register = 0x88,
 648 };
 649
 650 static void dspi_init(struct fsl_dspi *dspi)
 651 {
 652         regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
 653 }
 654
 655 static int dspi_probe(struct platform_device *pdev)
 656 {
 657         struct device_node *np = pdev->dev.of_node;
 658         struct spi_master *master;
 659         struct fsl_dspi *dspi;
 660         struct resource *res;
 661         void __iomem *base;
 662         int ret = 0, cs_num, bus_num;
 663
 664         master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
 665         if (!master)
 666                 return -ENOMEM;
 667
 668         dspi = spi_master_get_devdata(master);
 669         dspi->pdev = pdev;
 670         dspi->master = master;
 671
 672         master->transfer = NULL;
 673         master->setup = dspi_setup;
 674         master->transfer_one_message = dspi_transfer_one_message;
 675         master->dev.of_node = pdev->dev.of_node;
 676
 677         master->cleanup = dspi_cleanup;
 678         master->mode_bits = SPI_CPOL | SPI_CPHA;
 679         master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
 680                                         SPI_BPW_MASK(16);
 681
 682         ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
 683         if (ret < 0) {
 684                 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
 685                 goto out_master_put;
 686         }
 687         master->num_chipselect = cs_num;
 688
 689         ret = of_property_read_u32(np, "bus-num", &bus_num);
 690         if (ret < 0) {
 691                 dev_err(&pdev->dev, "can't get bus-num\n");
 692                 goto out_master_put;
 693         }
 694         master->bus_num = bus_num;
 695
 696         dspi->devtype_data = of_device_get_match_data(&pdev->dev);
 697         if (!dspi->devtype_data) {
 698                 dev_err(&pdev->dev, "can't get devtype_data\n");
 699                 ret = -EFAULT;
 700                 goto out_master_put;
 701         }
 702
 703         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 704         base = devm_ioremap_resource(&pdev->dev, res);
 705         if (IS_ERR(base)) {
 706                 ret = PTR_ERR(base);
 707                 goto out_master_put;
 708         }
 709
 710         dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 711                                                 &dspi_regmap_config);
 712         if (IS_ERR(dspi->regmap)) {
 713                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
 714                                 PTR_ERR(dspi->regmap));
 715                 return PTR_ERR(dspi->regmap);
 716         }
 717
 718         dspi_init(dspi);
 719         dspi->irq = platform_get_irq(pdev, 0);
 720         if (dspi->irq < 0) {
 721                 dev_err(&pdev->dev, "can't get platform irq\n");
 722                 ret = dspi->irq;
 723                 goto out_master_put;
 724         }
 725
 726         ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
 727                         pdev->name, dspi);
 728         if (ret < 0) {
 729                 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
 730                 goto out_master_put;
 731         }
 732
 733         dspi->clk = devm_clk_get(&pdev->dev, "dspi");
 734         if (IS_ERR(dspi->clk)) {
 735                 ret = PTR_ERR(dspi->clk);
 736                 dev_err(&pdev->dev, "unable to get clock\n");
 737                 goto out_master_put;
 738         }
 739         ret = clk_prepare_enable(dspi->clk);
 740         if (ret)
 741                 goto out_master_put;
 742
 743         master->max_speed_hz =
 744                 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
 745
 746         init_waitqueue_head(&dspi->waitq);
 747         platform_set_drvdata(pdev, master);
 748
 749         ret = spi_register_master(master);
 750         if (ret != 0) {
 751                 dev_err(&pdev->dev, "Problem registering DSPI master\n");
 752                 goto out_clk_put;
 753         }
 754
 755         return ret;
 756
 757 out_clk_put:
 758         clk_disable_unprepare(dspi->clk);
 759 out_master_put:
 760         spi_master_put(master);
 761
 762         return ret;
 763 }
 764
 765 static int dspi_remove(struct platform_device *pdev)
 766 {
 767         struct spi_master *master = platform_get_drvdata(pdev);
 768         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 769
 770         /* Disconnect from the SPI framework */
 771         clk_disable_unprepare(dspi->clk);
 772         spi_unregister_master(dspi->master);
 773
 774         return 0;
 775 }
 776
 777 static struct platform_driver fsl_dspi_driver = {
 778         .driver.name    = DRIVER_NAME,
 779         .driver.of_match_table = fsl_dspi_dt_ids,
 780         .driver.owner   = THIS_MODULE,
 781         .driver.pm = &dspi_pm,
 782         .probe          = dspi_probe,
 783         .remove         = dspi_remove,
 784 };
 785 module_platform_driver(fsl_dspi_driver);
 786
 787 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
 788 MODULE_LICENSE("GPL");
 789 MODULE_ALIAS("platform:" DRIVER_NAME);