drivers/spi/spi-fsl-espi.c

   1 /*
   2  * Freescale eSPI controller driver.
   3  *
   4  * Copyright 2010 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/fsl_devices.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/module.h>
  17 #include <linux/mm.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/pm_runtime.h>
  25 #include <sysdev/fsl_soc.h>
  26
  27 #include "spi-fsl-lib.h"
  28
  29 /* eSPI Controller registers */
  30 struct fsl_espi_reg {
  31         __be32 mode;            /* 0x000 - eSPI mode register */
  32         __be32 event;           /* 0x004 - eSPI event register */
  33         __be32 mask;            /* 0x008 - eSPI mask register */
  34         __be32 command;         /* 0x00c - eSPI command register */
  35         __be32 transmit;        /* 0x010 - eSPI transmit FIFO access register*/
  36         __be32 receive;         /* 0x014 - eSPI receive FIFO access register*/
  37         u8 res[8];              /* 0x018 - 0x01c reserved */
  38         __be32 csmode[4];       /* 0x020 - 0x02c eSPI cs mode register */
  39 };
  40
  41 struct fsl_espi_transfer {
  42         const void *tx_buf;
  43         void *rx_buf;
  44         unsigned len;
  45         unsigned n_tx;
  46         unsigned n_rx;
  47         unsigned actual_length;
  48         int status;
  49 };
  50
  51 /* eSPI Controller mode register definitions */
  52 #define SPMODE_ENABLE           (1 << 31)
  53 #define SPMODE_LOOP             (1 << 30)
  54 #define SPMODE_TXTHR(x)         ((x) << 8)
  55 #define SPMODE_RXTHR(x)         ((x) << 0)
  56
  57 /* eSPI Controller CS mode register definitions */
  58 #define CSMODE_CI_INACTIVEHIGH  (1 << 31)
  59 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
  60 #define CSMODE_REV              (1 << 29)
  61 #define CSMODE_DIV16            (1 << 28)
  62 #define CSMODE_PM(x)            ((x) << 24)
  63 #define CSMODE_POL_1            (1 << 20)
  64 #define CSMODE_LEN(x)           ((x) << 16)
  65 #define CSMODE_BEF(x)           ((x) << 12)
  66 #define CSMODE_AFT(x)           ((x) << 8)
  67 #define CSMODE_CG(x)            ((x) << 3)
  68
  69 /* Default mode/csmode for eSPI controller */
  70 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
  71 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
  72                 | CSMODE_AFT(0) | CSMODE_CG(1))
  73
  74 /* SPIE register values */
  75 #define SPIE_NE         0x00000200      /* Not empty */
  76 #define SPIE_NF         0x00000100      /* Not full */
  77
  78 /* SPIM register values */
  79 #define SPIM_NE         0x00000200      /* Not empty */
  80 #define SPIM_NF         0x00000100      /* Not full */
  81 #define SPIE_RXCNT(reg)     ((reg >> 24) & 0x3F)
  82 #define SPIE_TXCNT(reg)     ((reg >> 16) & 0x3F)
  83
  84 /* SPCOM register values */
  85 #define SPCOM_CS(x)             ((x) << 30)
  86 #define SPCOM_TRANLEN(x)        ((x) << 0)
  87 #define SPCOM_TRANLEN_MAX       0xFFFF  /* Max transaction length */
  88
  89 #define AUTOSUSPEND_TIMEOUT 2000
  90
  91 static void fsl_espi_change_mode(struct spi_device *spi)
  92 {
  93         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  94         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  95         struct fsl_espi_reg *reg_base = mspi->reg_base;
  96         __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
  97         __be32 __iomem *espi_mode = &reg_base->mode;
  98         u32 tmp;
  99         unsigned long flags;
 100
 101         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 102         local_irq_save(flags);
 103
 104         /* Turn off SPI unit prior changing mode */
 105         tmp = mpc8xxx_spi_read_reg(espi_mode);
 106         mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
 107         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 108         mpc8xxx_spi_write_reg(espi_mode, tmp);
 109
 110         local_irq_restore(flags);
 111 }
 112
 113 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
 114 {
 115         u32 data;
 116         u16 data_h;
 117         u16 data_l;
 118         const u32 *tx = mpc8xxx_spi->tx;
 119
 120         if (!tx)
 121                 return 0;
 122
 123         data = *tx++ << mpc8xxx_spi->tx_shift;
 124         data_l = data & 0xffff;
 125         data_h = (data >> 16) & 0xffff;
 126         swab16s(&data_l);
 127         swab16s(&data_h);
 128         data = data_h | data_l;
 129
 130         mpc8xxx_spi->tx = tx;
 131         return data;
 132 }
 133
 134 static int fsl_espi_setup_transfer(struct spi_device *spi,
 135                                         struct spi_transfer *t)
 136 {
 137         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 138         int bits_per_word = 0;
 139         u8 pm;
 140         u32 hz = 0;
 141         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 142
 143         if (t) {
 144                 bits_per_word = t->bits_per_word;
 145                 hz = t->speed_hz;
 146         }
 147
 148         /* spi_transfer level calls that work per-word */
 149         if (!bits_per_word)
 150                 bits_per_word = spi->bits_per_word;
 151
 152         if (!hz)
 153                 hz = spi->max_speed_hz;
 154
 155         cs->rx_shift = 0;
 156         cs->tx_shift = 0;
 157         cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 158         cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 159         if (bits_per_word <= 8) {
 160                 cs->rx_shift = 8 - bits_per_word;
 161         } else {
 162                 cs->rx_shift = 16 - bits_per_word;
 163                 if (spi->mode & SPI_LSB_FIRST)
 164                         cs->get_tx = fsl_espi_tx_buf_lsb;
 165         }
 166
 167         mpc8xxx_spi->rx_shift = cs->rx_shift;
 168         mpc8xxx_spi->tx_shift = cs->tx_shift;
 169         mpc8xxx_spi->get_rx = cs->get_rx;
 170         mpc8xxx_spi->get_tx = cs->get_tx;
 171
 172         bits_per_word = bits_per_word - 1;
 173
 174         /* mask out bits we are going to set */
 175         cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
 176
 177         cs->hw_mode |= CSMODE_LEN(bits_per_word);
 178
 179         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 180                 cs->hw_mode |= CSMODE_DIV16;
 181                 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
 182
 183                 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
 184                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 185                                 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
 186                 if (pm > 33)
 187                         pm = 33;
 188         } else {
 189                 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
 190         }
 191         if (pm)
 192                 pm--;
 193         if (pm < 2)
 194                 pm = 2;
 195
 196         cs->hw_mode |= CSMODE_PM(pm);
 197
 198         fsl_espi_change_mode(spi);
 199         return 0;
 200 }
 201
 202 static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
 203                 unsigned int len)
 204 {
 205         u32 word;
 206         struct fsl_espi_reg *reg_base = mspi->reg_base;
 207
 208         mspi->count = len;
 209
 210         /* enable rx ints */
 211         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 212
 213         /* transmit word */
 214         word = mspi->get_tx(mspi);
 215         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 216
 217         return 0;
 218 }
 219
 220 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
 221 {
 222         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 223         struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
 224         unsigned int len = t->len;
 225         int ret;
 226
 227         mpc8xxx_spi->len = t->len;
 228         len = roundup(len, 4) / 4;
 229
 230         mpc8xxx_spi->tx = t->tx_buf;
 231         mpc8xxx_spi->rx = t->rx_buf;
 232
 233         reinit_completion(&mpc8xxx_spi->done);
 234
 235         /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
 236         if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
 237                 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
 238                                 " beyond the SPCOM[TRANLEN] field\n", t->len);
 239                 return -EINVAL;
 240         }
 241         mpc8xxx_spi_write_reg(&reg_base->command,
 242                 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
 243
 244         ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
 245         if (ret)
 246                 return ret;
 247
 248         wait_for_completion(&mpc8xxx_spi->done);
 249
 250         /* disable rx ints */
 251         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 252
 253         return mpc8xxx_spi->count;
 254 }
 255
 256 static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
 257 {
 258         if (cmd) {
 259                 cmd[1] = (u8)(addr >> 16);
 260                 cmd[2] = (u8)(addr >> 8);
 261                 cmd[3] = (u8)(addr >> 0);
 262         }
 263 }
 264
 265 static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
 266 {
 267         if (cmd)
 268                 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
 269
 270         return 0;
 271 }
 272
 273 static void fsl_espi_do_trans(struct spi_message *m,
 274                                 struct fsl_espi_transfer *tr)
 275 {
 276         struct spi_device *spi = m->spi;
 277         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
 278         struct fsl_espi_transfer *espi_trans = tr;
 279         struct spi_message message;
 280         struct spi_transfer *t, *first, trans;
 281         int status = 0;
 282
 283         spi_message_init(&message);
 284         memset(&trans, 0, sizeof(trans));
 285
 286         first = list_first_entry(&m->transfers, struct spi_transfer,
 287                         transfer_list);
 288         list_for_each_entry(t, &m->transfers, transfer_list) {
 289                 if ((first->bits_per_word != t->bits_per_word) ||
 290                         (first->speed_hz != t->speed_hz)) {
 291                         espi_trans->status = -EINVAL;
 292                         dev_err(mspi->dev,
 293                                 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
 294                         return;
 295                 }
 296
 297                 trans.speed_hz = t->speed_hz;
 298                 trans.bits_per_word = t->bits_per_word;
 299                 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
 300         }
 301
 302         trans.len = espi_trans->len;
 303         trans.tx_buf = espi_trans->tx_buf;
 304         trans.rx_buf = espi_trans->rx_buf;
 305         spi_message_add_tail(&trans, &message);
 306
 307         list_for_each_entry(t, &message.transfers, transfer_list) {
 308                 if (t->bits_per_word || t->speed_hz) {
 309                         status = -EINVAL;
 310
 311                         status = fsl_espi_setup_transfer(spi, t);
 312                         if (status < 0)
 313                                 break;
 314                 }
 315
 316                 if (t->len)
 317                         status = fsl_espi_bufs(spi, t);
 318
 319                 if (status) {
 320                         status = -EMSGSIZE;
 321                         break;
 322                 }
 323
 324                 if (t->delay_usecs)
 325                         udelay(t->delay_usecs);
 326         }
 327
 328         espi_trans->status = status;
 329         fsl_espi_setup_transfer(spi, NULL);
 330 }
 331
 332 static void fsl_espi_cmd_trans(struct spi_message *m,
 333                                 struct fsl_espi_transfer *trans, u8 *rx_buff)
 334 {
 335         struct spi_transfer *t;
 336         u8 *local_buf;
 337         int i = 0;
 338         struct fsl_espi_transfer *espi_trans = trans;
 339
 340         local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
 341         if (!local_buf) {
 342                 espi_trans->status = -ENOMEM;
 343                 return;
 344         }
 345
 346         list_for_each_entry(t, &m->transfers, transfer_list) {
 347                 if (t->tx_buf) {
 348                         memcpy(local_buf + i, t->tx_buf, t->len);
 349                         i += t->len;
 350                 }
 351         }
 352
 353         espi_trans->tx_buf = local_buf;
 354         espi_trans->rx_buf = local_buf;
 355         fsl_espi_do_trans(m, espi_trans);
 356
 357         espi_trans->actual_length = espi_trans->len;
 358         kfree(local_buf);
 359 }
 360
 361 static void fsl_espi_rw_trans(struct spi_message *m,
 362                                 struct fsl_espi_transfer *trans, u8 *rx_buff)
 363 {
 364         struct fsl_espi_transfer *espi_trans = trans;
 365         unsigned int total_len = espi_trans->len;
 366         struct spi_transfer *t;
 367         u8 *local_buf;
 368         u8 *rx_buf = rx_buff;
 369         unsigned int trans_len;
 370         unsigned int addr;
 371         unsigned int tx_only;
 372         unsigned int rx_pos = 0;
 373         unsigned int pos;
 374         int i, loop;
 375
 376         local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
 377         if (!local_buf) {
 378                 espi_trans->status = -ENOMEM;
 379                 return;
 380         }
 381
 382         for (pos = 0, loop = 0; pos < total_len; pos += trans_len, loop++) {
 383                 trans_len = total_len - pos;
 384
 385                 i = 0;
 386                 tx_only = 0;
 387                 list_for_each_entry(t, &m->transfers, transfer_list) {
 388                         if (t->tx_buf) {
 389                                 memcpy(local_buf + i, t->tx_buf, t->len);
 390                                 i += t->len;
 391                                 if (!t->rx_buf)
 392                                         tx_only += t->len;
 393                         }
 394                 }
 395
 396                 /* Add additional TX bytes to compensate SPCOM_TRANLEN_MAX */
 397                 if (loop > 0)
 398                         trans_len += tx_only;
 399
 400                 if (trans_len > SPCOM_TRANLEN_MAX)
 401                         trans_len = SPCOM_TRANLEN_MAX;
 402
 403                 /* Update device offset */
 404                 if (pos > 0) {
 405                         addr = fsl_espi_cmd2addr(local_buf);
 406                         addr += rx_pos;
 407                         fsl_espi_addr2cmd(addr, local_buf);
 408                 }
 409
 410                 espi_trans->len = trans_len;
 411                 espi_trans->tx_buf = local_buf;
 412                 espi_trans->rx_buf = local_buf;
 413                 fsl_espi_do_trans(m, espi_trans);
 414
 415                 /* If there is at least one RX byte then copy it to rx_buf */
 416                 if (tx_only < SPCOM_TRANLEN_MAX)
 417                         memcpy(rx_buf + rx_pos, espi_trans->rx_buf + tx_only,
 418                                         trans_len - tx_only);
 419
 420                 rx_pos += trans_len - tx_only;
 421
 422                 if (loop > 0)
 423                         espi_trans->actual_length += espi_trans->len - tx_only;
 424                 else
 425                         espi_trans->actual_length += espi_trans->len;
 426         }
 427
 428         kfree(local_buf);
 429 }
 430
 431 static int fsl_espi_do_one_msg(struct spi_master *master,
 432                                struct spi_message *m)
 433 {
 434         struct spi_transfer *t;
 435         u8 *rx_buf = NULL;
 436         unsigned int n_tx = 0;
 437         unsigned int n_rx = 0;
 438         unsigned int xfer_len = 0;
 439         struct fsl_espi_transfer espi_trans;
 440
 441         list_for_each_entry(t, &m->transfers, transfer_list) {
 442                 if (t->tx_buf)
 443                         n_tx += t->len;
 444                 if (t->rx_buf) {
 445                         n_rx += t->len;
 446                         rx_buf = t->rx_buf;
 447                 }
 448                 if ((t->tx_buf) || (t->rx_buf))
 449                         xfer_len += t->len;
 450         }
 451
 452         espi_trans.n_tx = n_tx;
 453         espi_trans.n_rx = n_rx;
 454         espi_trans.len = xfer_len;
 455         espi_trans.actual_length = 0;
 456         espi_trans.status = 0;
 457
 458         if (!rx_buf)
 459                 fsl_espi_cmd_trans(m, &espi_trans, NULL);
 460         else
 461                 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
 462
 463         m->actual_length = espi_trans.actual_length;
 464         m->status = espi_trans.status;
 465         spi_finalize_current_message(master);
 466         return 0;
 467 }
 468
 469 static int fsl_espi_setup(struct spi_device *spi)
 470 {
 471         struct mpc8xxx_spi *mpc8xxx_spi;
 472         struct fsl_espi_reg *reg_base;
 473         int retval;
 474         u32 hw_mode;
 475         u32 loop_mode;
 476         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 477
 478         if (!spi->max_speed_hz)
 479                 return -EINVAL;
 480
 481         if (!cs) {
 482                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 483                 if (!cs)
 484                         return -ENOMEM;
 485                 spi_set_ctldata(spi, cs);
 486         }
 487
 488         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 489         reg_base = mpc8xxx_spi->reg_base;
 490
 491         pm_runtime_get_sync(mpc8xxx_spi->dev);
 492
 493         hw_mode = cs->hw_mode; /* Save original settings */
 494         cs->hw_mode = mpc8xxx_spi_read_reg(
 495                         &reg_base->csmode[spi->chip_select]);
 496         /* mask out bits we are going to set */
 497         cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
 498                          | CSMODE_REV);
 499
 500         if (spi->mode & SPI_CPHA)
 501                 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
 502         if (spi->mode & SPI_CPOL)
 503                 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
 504         if (!(spi->mode & SPI_LSB_FIRST))
 505                 cs->hw_mode |= CSMODE_REV;
 506
 507         /* Handle the loop mode */
 508         loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 509         loop_mode &= ~SPMODE_LOOP;
 510         if (spi->mode & SPI_LOOP)
 511                 loop_mode |= SPMODE_LOOP;
 512         mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
 513
 514         retval = fsl_espi_setup_transfer(spi, NULL);
 515
 516         pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
 517         pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
 518
 519         if (retval < 0) {
 520                 cs->hw_mode = hw_mode; /* Restore settings */
 521                 return retval;
 522         }
 523         return 0;
 524 }
 525
 526 static void fsl_espi_cleanup(struct spi_device *spi)
 527 {
 528         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 529
 530         kfree(cs);
 531         spi_set_ctldata(spi, NULL);
 532 }
 533
 534 void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 535 {
 536         struct fsl_espi_reg *reg_base = mspi->reg_base;
 537
 538         /* We need handle RX first */
 539         if (events & SPIE_NE) {
 540                 u32 rx_data, tmp;
 541                 u8 rx_data_8;
 542
 543                 /* Spin until RX is done */
 544                 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
 545                         cpu_relax();
 546                         events = mpc8xxx_spi_read_reg(&reg_base->event);
 547                 }
 548
 549                 if (mspi->len >= 4) {
 550                         rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 551                 } else {
 552                         tmp = mspi->len;
 553                         rx_data = 0;
 554                         while (tmp--) {
 555                                 rx_data_8 = in_8((u8 *)&reg_base->receive);
 556                                 rx_data |= (rx_data_8 << (tmp * 8));
 557                         }
 558
 559                         rx_data <<= (4 - mspi->len) * 8;
 560                 }
 561
 562                 mspi->len -= 4;
 563
 564                 if (mspi->rx)
 565                         mspi->get_rx(rx_data, mspi);
 566         }
 567
 568         if (!(events & SPIE_NF)) {
 569                 int ret;
 570
 571                 /* spin until TX is done */
 572                 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
 573                                 &reg_base->event)) & SPIE_NF), 1000, 0);
 574                 if (!ret) {
 575                         dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
 576
 577                         /* Clear the SPIE bits */
 578                         mpc8xxx_spi_write_reg(&reg_base->event, events);
 579                         complete(&mspi->done);
 580                         return;
 581                 }
 582         }
 583
 584         /* Clear the events */
 585         mpc8xxx_spi_write_reg(&reg_base->event, events);
 586
 587         mspi->count -= 1;
 588         if (mspi->count) {
 589                 u32 word = mspi->get_tx(mspi);
 590
 591                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 592         } else {
 593                 complete(&mspi->done);
 594         }
 595 }
 596
 597 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
 598 {
 599         struct mpc8xxx_spi *mspi = context_data;
 600         struct fsl_espi_reg *reg_base = mspi->reg_base;
 601         irqreturn_t ret = IRQ_NONE;
 602         u32 events;
 603
 604         /* Get interrupt events(tx/rx) */
 605         events = mpc8xxx_spi_read_reg(&reg_base->event);
 606         if (events)
 607                 ret = IRQ_HANDLED;
 608
 609         dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
 610
 611         fsl_espi_cpu_irq(mspi, events);
 612
 613         return ret;
 614 }
 615
 616 #ifdef CONFIG_PM
 617 static int fsl_espi_runtime_suspend(struct device *dev)
 618 {
 619         struct spi_master *master = dev_get_drvdata(dev);
 620         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 621         struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
 622         u32 regval;
 623
 624         regval = mpc8xxx_spi_read_reg(&reg_base->mode);
 625         regval &= ~SPMODE_ENABLE;
 626         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 627
 628         return 0;
 629 }
 630
 631 static int fsl_espi_runtime_resume(struct device *dev)
 632 {
 633         struct spi_master *master = dev_get_drvdata(dev);
 634         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 635         struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
 636         u32 regval;
 637
 638         regval = mpc8xxx_spi_read_reg(&reg_base->mode);
 639         regval |= SPMODE_ENABLE;
 640         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 641
 642         return 0;
 643 }
 644 #endif
 645
 646 static struct spi_master * fsl_espi_probe(struct device *dev,
 647                 struct resource *mem, unsigned int irq)
 648 {
 649         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 650         struct spi_master *master;
 651         struct mpc8xxx_spi *mpc8xxx_spi;
 652         struct fsl_espi_reg *reg_base;
 653         struct device_node *nc;
 654         const __be32 *prop;
 655         u32 regval, csmode;
 656         int i, len, ret = 0;
 657
 658         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 659         if (!master) {
 660                 ret = -ENOMEM;
 661                 goto err;
 662         }
 663
 664         dev_set_drvdata(dev, master);
 665
 666         mpc8xxx_spi_probe(dev, mem, irq);
 667
 668         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
 669         master->setup = fsl_espi_setup;
 670         master->cleanup = fsl_espi_cleanup;
 671         master->transfer_one_message = fsl_espi_do_one_msg;
 672         master->auto_runtime_pm = true;
 673
 674         mpc8xxx_spi = spi_master_get_devdata(master);
 675
 676         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 677         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 678                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 679                 goto err_probe;
 680         }
 681
 682         reg_base = mpc8xxx_spi->reg_base;
 683
 684         /* Register for SPI Interrupt */
 685         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
 686                           0, "fsl_espi", mpc8xxx_spi);
 687         if (ret)
 688                 goto err_probe;
 689
 690         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 691                 mpc8xxx_spi->rx_shift = 16;
 692                 mpc8xxx_spi->tx_shift = 24;
 693         }
 694
 695         /* SPI controller initializations */
 696         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 697         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 698         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 699         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 700
 701         /* Init eSPI CS mode register */
 702         for_each_available_child_of_node(master->dev.of_node, nc) {
 703                 /* get chip select */
 704                 prop = of_get_property(nc, "reg", &len);
 705                 if (!prop || len < sizeof(*prop))
 706                         continue;
 707                 i = be32_to_cpup(prop);
 708                 if (i < 0 || i >= pdata->max_chipselect)
 709                         continue;
 710
 711                 csmode = CSMODE_INIT_VAL;
 712                 /* check if CSBEF is set in device tree */
 713                 prop = of_get_property(nc, "fsl,csbef", &len);
 714                 if (prop && len >= sizeof(*prop)) {
 715                         csmode &= ~(CSMODE_BEF(0xf));
 716                         csmode |= CSMODE_BEF(be32_to_cpup(prop));
 717                 }
 718                 /* check if CSAFT is set in device tree */
 719                 prop = of_get_property(nc, "fsl,csaft", &len);
 720                 if (prop && len >= sizeof(*prop)) {
 721                         csmode &= ~(CSMODE_AFT(0xf));
 722                         csmode |= CSMODE_AFT(be32_to_cpup(prop));
 723                 }
 724                 mpc8xxx_spi_write_reg(&reg_base->csmode[i], csmode);
 725
 726                 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
 727         }
 728
 729         /* Enable SPI interface */
 730         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 731
 732         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 733
 734         pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
 735         pm_runtime_use_autosuspend(dev);
 736         pm_runtime_set_active(dev);
 737         pm_runtime_enable(dev);
 738         pm_runtime_get_sync(dev);
 739
 740         ret = devm_spi_register_master(dev, master);
 741         if (ret < 0)
 742                 goto err_pm;
 743
 744         dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
 745
 746         pm_runtime_mark_last_busy(dev);
 747         pm_runtime_put_autosuspend(dev);
 748
 749         return master;
 750
 751 err_pm:
 752         pm_runtime_put_noidle(dev);
 753         pm_runtime_disable(dev);
 754         pm_runtime_set_suspended(dev);
 755 err_probe:
 756         spi_master_put(master);
 757 err:
 758         return ERR_PTR(ret);
 759 }
 760
 761 static int of_fsl_espi_get_chipselects(struct device *dev)
 762 {
 763         struct device_node *np = dev->of_node;
 764         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 765         const u32 *prop;
 766         int len;
 767
 768         prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
 769         if (!prop || len < sizeof(*prop)) {
 770                 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
 771                 return -EINVAL;
 772         }
 773
 774         pdata->max_chipselect = *prop;
 775         pdata->cs_control = NULL;
 776
 777         return 0;
 778 }
 779
 780 static int of_fsl_espi_probe(struct platform_device *ofdev)
 781 {
 782         struct device *dev = &ofdev->dev;
 783         struct device_node *np = ofdev->dev.of_node;
 784         struct spi_master *master;
 785         struct resource mem;
 786         unsigned int irq;
 787         int ret = -ENOMEM;
 788
 789         ret = of_mpc8xxx_spi_probe(ofdev);
 790         if (ret)
 791                 return ret;
 792
 793         ret = of_fsl_espi_get_chipselects(dev);
 794         if (ret)
 795                 goto err;
 796
 797         ret = of_address_to_resource(np, 0, &mem);
 798         if (ret)
 799                 goto err;
 800
 801         irq = irq_of_parse_and_map(np, 0);
 802         if (!irq) {
 803                 ret = -EINVAL;
 804                 goto err;
 805         }
 806
 807         master = fsl_espi_probe(dev, &mem, irq);
 808         if (IS_ERR(master)) {
 809                 ret = PTR_ERR(master);
 810                 goto err;
 811         }
 812
 813         return 0;
 814
 815 err:
 816         return ret;
 817 }
 818
 819 static int of_fsl_espi_remove(struct platform_device *dev)
 820 {
 821         pm_runtime_disable(&dev->dev);
 822
 823         return 0;
 824 }
 825
 826 #ifdef CONFIG_PM_SLEEP
 827 static int of_fsl_espi_suspend(struct device *dev)
 828 {
 829         struct spi_master *master = dev_get_drvdata(dev);
 830         int ret;
 831
 832         ret = spi_master_suspend(master);
 833         if (ret) {
 834                 dev_warn(dev, "cannot suspend master\n");
 835                 return ret;
 836         }
 837
 838         ret = pm_runtime_force_suspend(dev);
 839         if (ret < 0)
 840                 return ret;
 841
 842         return 0;
 843 }
 844
 845 static int of_fsl_espi_resume(struct device *dev)
 846 {
 847         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 848         struct spi_master *master = dev_get_drvdata(dev);
 849         struct mpc8xxx_spi *mpc8xxx_spi;
 850         struct fsl_espi_reg *reg_base;
 851         u32 regval;
 852         int i, ret;
 853
 854         mpc8xxx_spi = spi_master_get_devdata(master);
 855         reg_base = mpc8xxx_spi->reg_base;
 856
 857         /* SPI controller initializations */
 858         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 859         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 860         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 861         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 862
 863         /* Init eSPI CS mode register */
 864         for (i = 0; i < pdata->max_chipselect; i++)
 865                 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
 866
 867         /* Enable SPI interface */
 868         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 869
 870         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 871
 872         ret = pm_runtime_force_resume(dev);
 873         if (ret < 0)
 874                 return ret;
 875
 876         return spi_master_resume(master);
 877 }
 878 #endif /* CONFIG_PM_SLEEP */
 879
 880 static const struct dev_pm_ops espi_pm = {
 881         SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
 882                            fsl_espi_runtime_resume, NULL)
 883         SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
 884 };
 885
 886 static const struct of_device_id of_fsl_espi_match[] = {
 887         { .compatible = "fsl,mpc8536-espi" },
 888         {}
 889 };
 890 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
 891
 892 static struct platform_driver fsl_espi_driver = {
 893         .driver = {
 894                 .name = "fsl_espi",
 895                 .of_match_table = of_fsl_espi_match,
 896                 .pm = &espi_pm,
 897         },
 898         .probe          = of_fsl_espi_probe,
 899         .remove         = of_fsl_espi_remove,
 900 };
 901 module_platform_driver(fsl_espi_driver);
 902
 903 MODULE_AUTHOR("Mingkai Hu");
 904 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
 905 MODULE_LICENSE("GPL");