1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale SPI controller driver.
5 * Maintainer: Kumar Gala
7 * Copyright (C) 2006 Polycom, Inc.
8 * Copyright 2010 Freescale Semiconductor, Inc.
10 * CPM SPI and QE buffer descriptors mode support:
11 * Copyright (c) 2009 MontaVista Software, Inc.
12 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
15 * Copyright (c) 2012 Aeroflex Gaisler AB.
16 * Author: Andreas Larsson <andreas@gaisler.com>
18 #include <linux/delay.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/fsl_devices.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
35 #include <linux/types.h>
38 #include <sysdev/fsl_soc.h>
41 /* Specific to the MPC8306/MPC8309 */
42 #define IMMR_SPI_CS_OFFSET 0x14c
43 #define SPI_BOOT_SEL_BIT 0x80000000
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
52 struct fsl_spi_match_data
{
56 static struct fsl_spi_match_data of_fsl_spi_fsl_config
= {
60 static struct fsl_spi_match_data of_fsl_spi_grlib_config
= {
64 static const struct of_device_id of_fsl_spi_match
[] = {
66 .compatible
= "fsl,spi",
67 .data
= &of_fsl_spi_fsl_config
,
70 .compatible
= "aeroflexgaisler,spictrl",
71 .data
= &of_fsl_spi_grlib_config
,
75 MODULE_DEVICE_TABLE(of
, of_fsl_spi_match
);
77 static int fsl_spi_get_type(struct device
*dev
)
79 const struct of_device_id
*match
;
82 match
= of_match_node(of_fsl_spi_match
, dev
->of_node
);
83 if (match
&& match
->data
)
84 return ((struct fsl_spi_match_data
*)match
->data
)->type
;
89 static void fsl_spi_change_mode(struct spi_device
*spi
)
91 struct mpc8xxx_spi
*mspi
= spi_master_get_devdata(spi
->master
);
92 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
93 struct fsl_spi_reg __iomem
*reg_base
= mspi
->reg_base
;
94 __be32 __iomem
*mode
= ®_base
->mode
;
97 if (cs
->hw_mode
== mpc8xxx_spi_read_reg(mode
))
100 /* Turn off IRQs locally to minimize time that SPI is disabled. */
101 local_irq_save(flags
);
103 /* Turn off SPI unit prior changing mode */
104 mpc8xxx_spi_write_reg(mode
, cs
->hw_mode
& ~SPMODE_ENABLE
);
106 /* When in CPM mode, we need to reinit tx and rx. */
107 if (mspi
->flags
& SPI_CPM_MODE
) {
108 fsl_spi_cpm_reinit_txrx(mspi
);
110 mpc8xxx_spi_write_reg(mode
, cs
->hw_mode
);
111 local_irq_restore(flags
);
114 static void fsl_spi_chipselect(struct spi_device
*spi
, int value
)
116 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
117 struct fsl_spi_platform_data
*pdata
;
118 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
120 pdata
= spi
->dev
.parent
->parent
->platform_data
;
122 if (value
== BITBANG_CS_INACTIVE
) {
123 if (pdata
->cs_control
)
124 pdata
->cs_control(spi
, false);
127 if (value
== BITBANG_CS_ACTIVE
) {
128 mpc8xxx_spi
->rx_shift
= cs
->rx_shift
;
129 mpc8xxx_spi
->tx_shift
= cs
->tx_shift
;
130 mpc8xxx_spi
->get_rx
= cs
->get_rx
;
131 mpc8xxx_spi
->get_tx
= cs
->get_tx
;
133 fsl_spi_change_mode(spi
);
135 if (pdata
->cs_control
)
136 pdata
->cs_control(spi
, true);
140 static void fsl_spi_qe_cpu_set_shifts(u32
*rx_shift
, u32
*tx_shift
,
141 int bits_per_word
, int msb_first
)
146 if (bits_per_word
<= 8) {
149 } else if (bits_per_word
<= 16) {
154 if (bits_per_word
<= 8)
159 static void fsl_spi_grlib_set_shifts(u32
*rx_shift
, u32
*tx_shift
,
160 int bits_per_word
, int msb_first
)
164 if (bits_per_word
<= 16) {
166 *rx_shift
= 16; /* LSB in bit 16 */
167 *tx_shift
= 32 - bits_per_word
; /* MSB in bit 31 */
169 *rx_shift
= 16 - bits_per_word
; /* MSB in bit 15 */
174 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs
*cs
,
175 struct spi_device
*spi
,
176 struct mpc8xxx_spi
*mpc8xxx_spi
,
181 if (bits_per_word
<= 8) {
182 cs
->get_rx
= mpc8xxx_spi_rx_buf_u8
;
183 cs
->get_tx
= mpc8xxx_spi_tx_buf_u8
;
184 } else if (bits_per_word
<= 16) {
185 cs
->get_rx
= mpc8xxx_spi_rx_buf_u16
;
186 cs
->get_tx
= mpc8xxx_spi_tx_buf_u16
;
187 } else if (bits_per_word
<= 32) {
188 cs
->get_rx
= mpc8xxx_spi_rx_buf_u32
;
189 cs
->get_tx
= mpc8xxx_spi_tx_buf_u32
;
193 if (mpc8xxx_spi
->set_shifts
)
194 mpc8xxx_spi
->set_shifts(&cs
->rx_shift
, &cs
->tx_shift
,
196 !(spi
->mode
& SPI_LSB_FIRST
));
198 mpc8xxx_spi
->rx_shift
= cs
->rx_shift
;
199 mpc8xxx_spi
->tx_shift
= cs
->tx_shift
;
200 mpc8xxx_spi
->get_rx
= cs
->get_rx
;
201 mpc8xxx_spi
->get_tx
= cs
->get_tx
;
203 return bits_per_word
;
206 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs
*cs
,
207 struct spi_device
*spi
,
210 /* QE uses Little Endian for words > 8
211 * so transform all words > 8 into 8 bits
212 * Unfortnatly that doesn't work for LSB so
213 * reject these for now */
214 /* Note: 32 bits word, LSB works iff
215 * tfcr/rfcr is set to CPMFCR_GBL */
216 if (spi
->mode
& SPI_LSB_FIRST
&&
219 if (bits_per_word
> 8)
220 return 8; /* pretend its 8 bits */
221 return bits_per_word
;
224 static int fsl_spi_setup_transfer(struct spi_device
*spi
,
225 struct spi_transfer
*t
)
227 struct mpc8xxx_spi
*mpc8xxx_spi
;
228 int bits_per_word
= 0;
231 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
233 mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
236 bits_per_word
= t
->bits_per_word
;
240 /* spi_transfer level calls that work per-word */
242 bits_per_word
= spi
->bits_per_word
;
245 hz
= spi
->max_speed_hz
;
247 if (!(mpc8xxx_spi
->flags
& SPI_CPM_MODE
))
248 bits_per_word
= mspi_apply_cpu_mode_quirks(cs
, spi
,
251 else if (mpc8xxx_spi
->flags
& SPI_QE
)
252 bits_per_word
= mspi_apply_qe_mode_quirks(cs
, spi
,
255 if (bits_per_word
< 0)
256 return bits_per_word
;
258 if (bits_per_word
== 32)
261 bits_per_word
= bits_per_word
- 1;
263 /* mask out bits we are going to set */
264 cs
->hw_mode
&= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
267 cs
->hw_mode
|= SPMODE_LEN(bits_per_word
);
269 if ((mpc8xxx_spi
->spibrg
/ hz
) > 64) {
270 cs
->hw_mode
|= SPMODE_DIV16
;
271 pm
= (mpc8xxx_spi
->spibrg
- 1) / (hz
* 64) + 1;
273 "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
274 dev_name(&spi
->dev
), hz
, mpc8xxx_spi
->spibrg
/ 1024);
278 pm
= (mpc8xxx_spi
->spibrg
- 1) / (hz
* 4) + 1;
283 cs
->hw_mode
|= SPMODE_PM(pm
);
285 fsl_spi_change_mode(spi
);
289 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi
*mspi
,
290 struct spi_transfer
*t
, unsigned int len
)
293 struct fsl_spi_reg __iomem
*reg_base
= mspi
->reg_base
;
298 mpc8xxx_spi_write_reg(®_base
->mask
, SPIM_NE
);
301 word
= mspi
->get_tx(mspi
);
302 mpc8xxx_spi_write_reg(®_base
->transmit
, word
);
307 static int fsl_spi_bufs(struct spi_device
*spi
, struct spi_transfer
*t
,
310 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
311 struct fsl_spi_reg __iomem
*reg_base
;
312 unsigned int len
= t
->len
;
316 reg_base
= mpc8xxx_spi
->reg_base
;
317 bits_per_word
= spi
->bits_per_word
;
318 if (t
->bits_per_word
)
319 bits_per_word
= t
->bits_per_word
;
321 if (bits_per_word
> 8) {
322 /* invalid length? */
327 if (bits_per_word
> 16) {
328 /* invalid length? */
334 mpc8xxx_spi
->tx
= t
->tx_buf
;
335 mpc8xxx_spi
->rx
= t
->rx_buf
;
337 reinit_completion(&mpc8xxx_spi
->done
);
339 if (mpc8xxx_spi
->flags
& SPI_CPM_MODE
)
340 ret
= fsl_spi_cpm_bufs(mpc8xxx_spi
, t
, is_dma_mapped
);
342 ret
= fsl_spi_cpu_bufs(mpc8xxx_spi
, t
, len
);
346 wait_for_completion(&mpc8xxx_spi
->done
);
348 /* disable rx ints */
349 mpc8xxx_spi_write_reg(®_base
->mask
, 0);
351 if (mpc8xxx_spi
->flags
& SPI_CPM_MODE
)
352 fsl_spi_cpm_bufs_complete(mpc8xxx_spi
);
354 return mpc8xxx_spi
->count
;
357 static int fsl_spi_do_one_msg(struct spi_master
*master
,
358 struct spi_message
*m
)
360 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
361 struct spi_device
*spi
= m
->spi
;
362 struct spi_transfer
*t
, *first
;
363 unsigned int cs_change
;
364 const int nsecs
= 50;
365 int status
, last_bpw
;
368 * In CPU mode, optimize large byte transfers to use larger
369 * bits_per_word values to reduce number of interrupts taken.
371 if (!(mpc8xxx_spi
->flags
& SPI_CPM_MODE
)) {
372 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
373 if (t
->len
< 256 || t
->bits_per_word
!= 8)
375 if ((t
->len
& 3) == 0)
376 t
->bits_per_word
= 32;
377 else if ((t
->len
& 1) == 0)
378 t
->bits_per_word
= 16;
382 /* Don't allow changes if CS is active */
384 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
387 cs_change
= t
->cs_change
;
388 if (first
->speed_hz
!= t
->speed_hz
) {
390 "speed_hz cannot change while CS is active\n");
398 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
399 if (cs_change
|| last_bpw
!= t
->bits_per_word
)
400 status
= fsl_spi_setup_transfer(spi
, t
);
403 last_bpw
= t
->bits_per_word
;
406 fsl_spi_chipselect(spi
, BITBANG_CS_ACTIVE
);
409 cs_change
= t
->cs_change
;
411 status
= fsl_spi_bufs(spi
, t
, m
->is_dma_mapped
);
416 m
->actual_length
+= t
->len
;
418 spi_transfer_delay_exec(t
);
422 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
429 if (status
|| !cs_change
) {
431 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
434 fsl_spi_setup_transfer(spi
, NULL
);
435 spi_finalize_current_message(master
);
439 static int fsl_spi_setup(struct spi_device
*spi
)
441 struct mpc8xxx_spi
*mpc8xxx_spi
;
442 struct fsl_spi_reg __iomem
*reg_base
;
443 bool initial_setup
= false;
446 struct spi_mpc8xxx_cs
*cs
= spi_get_ctldata(spi
);
448 if (!spi
->max_speed_hz
)
452 cs
= kzalloc(sizeof(*cs
), GFP_KERNEL
);
455 spi_set_ctldata(spi
, cs
);
456 initial_setup
= true;
458 mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
460 reg_base
= mpc8xxx_spi
->reg_base
;
462 hw_mode
= cs
->hw_mode
; /* Save original settings */
463 cs
->hw_mode
= mpc8xxx_spi_read_reg(®_base
->mode
);
464 /* mask out bits we are going to set */
465 cs
->hw_mode
&= ~(SPMODE_CP_BEGIN_EDGECLK
| SPMODE_CI_INACTIVEHIGH
466 | SPMODE_REV
| SPMODE_LOOP
);
468 if (spi
->mode
& SPI_CPHA
)
469 cs
->hw_mode
|= SPMODE_CP_BEGIN_EDGECLK
;
470 if (spi
->mode
& SPI_CPOL
)
471 cs
->hw_mode
|= SPMODE_CI_INACTIVEHIGH
;
472 if (!(spi
->mode
& SPI_LSB_FIRST
))
473 cs
->hw_mode
|= SPMODE_REV
;
474 if (spi
->mode
& SPI_LOOP
)
475 cs
->hw_mode
|= SPMODE_LOOP
;
477 retval
= fsl_spi_setup_transfer(spi
, NULL
);
479 cs
->hw_mode
= hw_mode
; /* Restore settings */
485 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
486 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
491 static void fsl_spi_cleanup(struct spi_device
*spi
)
493 struct spi_mpc8xxx_cs
*cs
= spi_get_ctldata(spi
);
496 spi_set_ctldata(spi
, NULL
);
499 static void fsl_spi_cpu_irq(struct mpc8xxx_spi
*mspi
, u32 events
)
501 struct fsl_spi_reg __iomem
*reg_base
= mspi
->reg_base
;
503 /* We need handle RX first */
504 if (events
& SPIE_NE
) {
505 u32 rx_data
= mpc8xxx_spi_read_reg(®_base
->receive
);
508 mspi
->get_rx(rx_data
, mspi
);
511 if ((events
& SPIE_NF
) == 0)
512 /* spin until TX is done */
514 mpc8xxx_spi_read_reg(®_base
->event
)) &
518 /* Clear the events */
519 mpc8xxx_spi_write_reg(®_base
->event
, events
);
523 u32 word
= mspi
->get_tx(mspi
);
525 mpc8xxx_spi_write_reg(®_base
->transmit
, word
);
527 complete(&mspi
->done
);
531 static irqreturn_t
fsl_spi_irq(s32 irq
, void *context_data
)
533 struct mpc8xxx_spi
*mspi
= context_data
;
534 irqreturn_t ret
= IRQ_NONE
;
536 struct fsl_spi_reg __iomem
*reg_base
= mspi
->reg_base
;
538 /* Get interrupt events(tx/rx) */
539 events
= mpc8xxx_spi_read_reg(®_base
->event
);
543 dev_dbg(mspi
->dev
, "%s: events %x\n", __func__
, events
);
545 if (mspi
->flags
& SPI_CPM_MODE
)
546 fsl_spi_cpm_irq(mspi
, events
);
548 fsl_spi_cpu_irq(mspi
, events
);
553 static void fsl_spi_grlib_cs_control(struct spi_device
*spi
, bool on
)
555 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
556 struct fsl_spi_reg __iomem
*reg_base
= mpc8xxx_spi
->reg_base
;
558 u16 cs
= spi
->chip_select
;
561 gpiod_set_value(spi
->cs_gpiod
, on
);
562 } else if (cs
< mpc8xxx_spi
->native_chipselects
) {
563 slvsel
= mpc8xxx_spi_read_reg(®_base
->slvsel
);
564 slvsel
= on
? (slvsel
| (1 << cs
)) : (slvsel
& ~(1 << cs
));
565 mpc8xxx_spi_write_reg(®_base
->slvsel
, slvsel
);
569 static void fsl_spi_grlib_probe(struct device
*dev
)
571 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
572 struct spi_master
*master
= dev_get_drvdata(dev
);
573 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
574 struct fsl_spi_reg __iomem
*reg_base
= mpc8xxx_spi
->reg_base
;
578 capabilities
= mpc8xxx_spi_read_reg(®_base
->cap
);
580 mpc8xxx_spi
->set_shifts
= fsl_spi_grlib_set_shifts
;
581 mbits
= SPCAP_MAXWLEN(capabilities
);
583 mpc8xxx_spi
->max_bits_per_word
= mbits
+ 1;
585 mpc8xxx_spi
->native_chipselects
= 0;
586 if (SPCAP_SSEN(capabilities
)) {
587 mpc8xxx_spi
->native_chipselects
= SPCAP_SSSZ(capabilities
);
588 mpc8xxx_spi_write_reg(®_base
->slvsel
, 0xffffffff);
590 master
->num_chipselect
= mpc8xxx_spi
->native_chipselects
;
591 pdata
->cs_control
= fsl_spi_grlib_cs_control
;
594 static struct spi_master
*fsl_spi_probe(struct device
*dev
,
595 struct resource
*mem
, unsigned int irq
)
597 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
598 struct spi_master
*master
;
599 struct mpc8xxx_spi
*mpc8xxx_spi
;
600 struct fsl_spi_reg __iomem
*reg_base
;
604 master
= spi_alloc_master(dev
, sizeof(struct mpc8xxx_spi
));
605 if (master
== NULL
) {
610 dev_set_drvdata(dev
, master
);
612 mpc8xxx_spi_probe(dev
, mem
, irq
);
614 master
->setup
= fsl_spi_setup
;
615 master
->cleanup
= fsl_spi_cleanup
;
616 master
->transfer_one_message
= fsl_spi_do_one_msg
;
617 master
->use_gpio_descriptors
= true;
619 mpc8xxx_spi
= spi_master_get_devdata(master
);
620 mpc8xxx_spi
->max_bits_per_word
= 32;
621 mpc8xxx_spi
->type
= fsl_spi_get_type(dev
);
623 ret
= fsl_spi_cpm_init(mpc8xxx_spi
);
627 mpc8xxx_spi
->reg_base
= devm_ioremap_resource(dev
, mem
);
628 if (IS_ERR(mpc8xxx_spi
->reg_base
)) {
629 ret
= PTR_ERR(mpc8xxx_spi
->reg_base
);
633 if (mpc8xxx_spi
->type
== TYPE_GRLIB
)
634 fsl_spi_grlib_probe(dev
);
636 master
->bits_per_word_mask
=
637 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
638 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi
->max_bits_per_word
);
640 if (mpc8xxx_spi
->flags
& SPI_QE_CPU_MODE
)
641 mpc8xxx_spi
->set_shifts
= fsl_spi_qe_cpu_set_shifts
;
643 if (mpc8xxx_spi
->set_shifts
)
644 /* 8 bits per word and MSB first */
645 mpc8xxx_spi
->set_shifts(&mpc8xxx_spi
->rx_shift
,
646 &mpc8xxx_spi
->tx_shift
, 8, 1);
648 /* Register for SPI Interrupt */
649 ret
= devm_request_irq(dev
, mpc8xxx_spi
->irq
, fsl_spi_irq
,
650 0, "fsl_spi", mpc8xxx_spi
);
655 reg_base
= mpc8xxx_spi
->reg_base
;
657 /* SPI controller initializations */
658 mpc8xxx_spi_write_reg(®_base
->mode
, 0);
659 mpc8xxx_spi_write_reg(®_base
->mask
, 0);
660 mpc8xxx_spi_write_reg(®_base
->command
, 0);
661 mpc8xxx_spi_write_reg(®_base
->event
, 0xffffffff);
663 /* Enable SPI interface */
664 regval
= pdata
->initial_spmode
| SPMODE_INIT_VAL
| SPMODE_ENABLE
;
665 if (mpc8xxx_spi
->max_bits_per_word
< 8) {
666 regval
&= ~SPMODE_LEN(0xF);
667 regval
|= SPMODE_LEN(mpc8xxx_spi
->max_bits_per_word
- 1);
669 if (mpc8xxx_spi
->flags
& SPI_QE_CPU_MODE
)
672 mpc8xxx_spi_write_reg(®_base
->mode
, regval
);
674 ret
= devm_spi_register_master(dev
, master
);
678 dev_info(dev
, "at 0x%p (irq = %d), %s mode\n", reg_base
,
679 mpc8xxx_spi
->irq
, mpc8xxx_spi_strmode(mpc8xxx_spi
->flags
));
684 fsl_spi_cpm_free(mpc8xxx_spi
);
686 spi_master_put(master
);
691 static void fsl_spi_cs_control(struct spi_device
*spi
, bool on
)
694 gpiod_set_value(spi
->cs_gpiod
, on
);
696 struct device
*dev
= spi
->dev
.parent
->parent
;
697 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
698 struct mpc8xxx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
700 if (WARN_ON_ONCE(!pinfo
->immr_spi_cs
))
702 iowrite32be(on
? 0 : SPI_BOOT_SEL_BIT
, pinfo
->immr_spi_cs
);
706 static int of_fsl_spi_probe(struct platform_device
*ofdev
)
708 struct device
*dev
= &ofdev
->dev
;
709 struct device_node
*np
= ofdev
->dev
.of_node
;
710 struct spi_master
*master
;
714 bool spisel_boot
= false;
715 #if IS_ENABLED(CONFIG_FSL_SOC)
716 struct mpc8xxx_spi_probe_info
*pinfo
= NULL
;
720 ret
= of_mpc8xxx_spi_probe(ofdev
);
724 type
= fsl_spi_get_type(&ofdev
->dev
);
725 if (type
== TYPE_FSL
) {
726 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
727 #if IS_ENABLED(CONFIG_FSL_SOC)
728 pinfo
= to_of_pinfo(pdata
);
730 spisel_boot
= of_property_read_bool(np
, "fsl,spisel_boot");
732 pinfo
->immr_spi_cs
= ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET
, 4);
733 if (!pinfo
->immr_spi_cs
)
738 * Handle the case where we have one hardwired (always selected)
739 * device on the first "chipselect". Else we let the core code
740 * handle any GPIOs or native chip selects and assign the
741 * appropriate callback for dealing with the CS lines. This isn't
742 * supported on the GRLIB variant.
744 ret
= gpiod_count(dev
, "cs");
747 if (ret
== 0 && !spisel_boot
) {
748 pdata
->max_chipselect
= 1;
750 pdata
->max_chipselect
= ret
+ spisel_boot
;
751 pdata
->cs_control
= fsl_spi_cs_control
;
755 ret
= of_address_to_resource(np
, 0, &mem
);
759 irq
= platform_get_irq(ofdev
, 0);
765 master
= fsl_spi_probe(dev
, &mem
, irq
);
767 return PTR_ERR_OR_ZERO(master
);
770 #if IS_ENABLED(CONFIG_FSL_SOC)
772 iounmap(pinfo
->immr_spi_cs
);
777 static int of_fsl_spi_remove(struct platform_device
*ofdev
)
779 struct spi_master
*master
= platform_get_drvdata(ofdev
);
780 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
782 fsl_spi_cpm_free(mpc8xxx_spi
);
786 static struct platform_driver of_fsl_spi_driver
= {
789 .of_match_table
= of_fsl_spi_match
,
791 .probe
= of_fsl_spi_probe
,
792 .remove
= of_fsl_spi_remove
,
795 #ifdef CONFIG_MPC832x_RDB
798 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
799 * only. The driver should go away soon, since newer MPC8323E-RDB's device
800 * tree can work with OpenFirmware driver. But for now we support old trees
803 static int plat_mpc8xxx_spi_probe(struct platform_device
*pdev
)
805 struct resource
*mem
;
807 struct spi_master
*master
;
809 if (!dev_get_platdata(&pdev
->dev
))
812 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
816 irq
= platform_get_irq(pdev
, 0);
820 master
= fsl_spi_probe(&pdev
->dev
, mem
, irq
);
821 return PTR_ERR_OR_ZERO(master
);
824 static int plat_mpc8xxx_spi_remove(struct platform_device
*pdev
)
826 struct spi_master
*master
= platform_get_drvdata(pdev
);
827 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
829 fsl_spi_cpm_free(mpc8xxx_spi
);
834 MODULE_ALIAS("platform:mpc8xxx_spi");
835 static struct platform_driver mpc8xxx_spi_driver
= {
836 .probe
= plat_mpc8xxx_spi_probe
,
837 .remove
= plat_mpc8xxx_spi_remove
,
839 .name
= "mpc8xxx_spi",
843 static bool legacy_driver_failed
;
845 static void __init
legacy_driver_register(void)
847 legacy_driver_failed
= platform_driver_register(&mpc8xxx_spi_driver
);
850 static void __exit
legacy_driver_unregister(void)
852 if (legacy_driver_failed
)
854 platform_driver_unregister(&mpc8xxx_spi_driver
);
857 static void __init
legacy_driver_register(void) {}
858 static void __exit
legacy_driver_unregister(void) {}
859 #endif /* CONFIG_MPC832x_RDB */
861 static int __init
fsl_spi_init(void)
863 legacy_driver_register();
864 return platform_driver_register(&of_fsl_spi_driver
);
866 module_init(fsl_spi_init
);
868 static void __exit
fsl_spi_exit(void)
870 platform_driver_unregister(&of_fsl_spi_driver
);
871 legacy_driver_unregister();
873 module_exit(fsl_spi_exit
);
875 MODULE_AUTHOR("Kumar Gala");
876 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
877 MODULE_LICENSE("GPL");