2 * Freescale SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
7 * Copyright 2010 Freescale Semiconductor, Inc.
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
14 * Copyright (c) 2012 Aeroflex Gaisler AB.
15 * Author: Andreas Larsson <andreas@gaisler.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/gpio.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/mutex.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_gpio.h>
36 #include <linux/of_platform.h>
37 #include <linux/platform_device.h>
38 #include <linux/spi/spi.h>
39 #include <linux/spi/spi_bitbang.h>
40 #include <linux/types.h>
43 #include <sysdev/fsl_soc.h>
46 /* Specific to the MPC8306/MPC8309 */
47 #define IMMR_SPI_CS_OFFSET 0x14c
48 #define SPI_BOOT_SEL_BIT 0x80000000
50 #include "spi-fsl-lib.h"
51 #include "spi-fsl-cpm.h"
52 #include "spi-fsl-spi.h"
57 struct fsl_spi_match_data
{
61 static struct fsl_spi_match_data of_fsl_spi_fsl_config
= {
65 static struct fsl_spi_match_data of_fsl_spi_grlib_config
= {
69 static const struct of_device_id of_fsl_spi_match
[] = {
71 .compatible
= "fsl,spi",
72 .data
= &of_fsl_spi_fsl_config
,
75 .compatible
= "aeroflexgaisler,spictrl",
76 .data
= &of_fsl_spi_grlib_config
,
80 MODULE_DEVICE_TABLE(of
, of_fsl_spi_match
);
82 static int fsl_spi_get_type(struct device
*dev
)
84 const struct of_device_id
*match
;
87 match
= of_match_node(of_fsl_spi_match
, dev
->of_node
);
88 if (match
&& match
->data
)
89 return ((struct fsl_spi_match_data
*)match
->data
)->type
;
94 static void fsl_spi_change_mode(struct spi_device
*spi
)
96 struct mpc8xxx_spi
*mspi
= spi_master_get_devdata(spi
->master
);
97 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
98 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
99 __be32 __iomem
*mode
= ®_base
->mode
;
102 if (cs
->hw_mode
== mpc8xxx_spi_read_reg(mode
))
105 /* Turn off IRQs locally to minimize time that SPI is disabled. */
106 local_irq_save(flags
);
108 /* Turn off SPI unit prior changing mode */
109 mpc8xxx_spi_write_reg(mode
, cs
->hw_mode
& ~SPMODE_ENABLE
);
111 /* When in CPM mode, we need to reinit tx and rx. */
112 if (mspi
->flags
& SPI_CPM_MODE
) {
113 fsl_spi_cpm_reinit_txrx(mspi
);
115 mpc8xxx_spi_write_reg(mode
, cs
->hw_mode
);
116 local_irq_restore(flags
);
119 static void fsl_spi_chipselect(struct spi_device
*spi
, int value
)
121 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
122 struct fsl_spi_platform_data
*pdata
;
123 bool pol
= spi
->mode
& SPI_CS_HIGH
;
124 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
126 pdata
= spi
->dev
.parent
->parent
->platform_data
;
128 if (value
== BITBANG_CS_INACTIVE
) {
129 if (pdata
->cs_control
)
130 pdata
->cs_control(spi
, !pol
);
133 if (value
== BITBANG_CS_ACTIVE
) {
134 mpc8xxx_spi
->rx_shift
= cs
->rx_shift
;
135 mpc8xxx_spi
->tx_shift
= cs
->tx_shift
;
136 mpc8xxx_spi
->get_rx
= cs
->get_rx
;
137 mpc8xxx_spi
->get_tx
= cs
->get_tx
;
139 fsl_spi_change_mode(spi
);
141 if (pdata
->cs_control
)
142 pdata
->cs_control(spi
, pol
);
146 static void fsl_spi_qe_cpu_set_shifts(u32
*rx_shift
, u32
*tx_shift
,
147 int bits_per_word
, int msb_first
)
152 if (bits_per_word
<= 8) {
155 } else if (bits_per_word
<= 16) {
160 if (bits_per_word
<= 8)
165 static void fsl_spi_grlib_set_shifts(u32
*rx_shift
, u32
*tx_shift
,
166 int bits_per_word
, int msb_first
)
170 if (bits_per_word
<= 16) {
172 *rx_shift
= 16; /* LSB in bit 16 */
173 *tx_shift
= 32 - bits_per_word
; /* MSB in bit 31 */
175 *rx_shift
= 16 - bits_per_word
; /* MSB in bit 15 */
180 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs
*cs
,
181 struct spi_device
*spi
,
182 struct mpc8xxx_spi
*mpc8xxx_spi
,
187 if (bits_per_word
<= 8) {
188 cs
->get_rx
= mpc8xxx_spi_rx_buf_u8
;
189 cs
->get_tx
= mpc8xxx_spi_tx_buf_u8
;
190 } else if (bits_per_word
<= 16) {
191 cs
->get_rx
= mpc8xxx_spi_rx_buf_u16
;
192 cs
->get_tx
= mpc8xxx_spi_tx_buf_u16
;
193 } else if (bits_per_word
<= 32) {
194 cs
->get_rx
= mpc8xxx_spi_rx_buf_u32
;
195 cs
->get_tx
= mpc8xxx_spi_tx_buf_u32
;
199 if (mpc8xxx_spi
->set_shifts
)
200 mpc8xxx_spi
->set_shifts(&cs
->rx_shift
, &cs
->tx_shift
,
202 !(spi
->mode
& SPI_LSB_FIRST
));
204 mpc8xxx_spi
->rx_shift
= cs
->rx_shift
;
205 mpc8xxx_spi
->tx_shift
= cs
->tx_shift
;
206 mpc8xxx_spi
->get_rx
= cs
->get_rx
;
207 mpc8xxx_spi
->get_tx
= cs
->get_tx
;
209 return bits_per_word
;
212 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs
*cs
,
213 struct spi_device
*spi
,
216 /* QE uses Little Endian for words > 8
217 * so transform all words > 8 into 8 bits
218 * Unfortnatly that doesn't work for LSB so
219 * reject these for now */
220 /* Note: 32 bits word, LSB works iff
221 * tfcr/rfcr is set to CPMFCR_GBL */
222 if (spi
->mode
& SPI_LSB_FIRST
&&
225 if (bits_per_word
> 8)
226 return 8; /* pretend its 8 bits */
227 return bits_per_word
;
230 static int fsl_spi_setup_transfer(struct spi_device
*spi
,
231 struct spi_transfer
*t
)
233 struct mpc8xxx_spi
*mpc8xxx_spi
;
234 int bits_per_word
= 0;
237 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
239 mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
242 bits_per_word
= t
->bits_per_word
;
246 /* spi_transfer level calls that work per-word */
248 bits_per_word
= spi
->bits_per_word
;
251 hz
= spi
->max_speed_hz
;
253 if (!(mpc8xxx_spi
->flags
& SPI_CPM_MODE
))
254 bits_per_word
= mspi_apply_cpu_mode_quirks(cs
, spi
,
257 else if (mpc8xxx_spi
->flags
& SPI_QE
)
258 bits_per_word
= mspi_apply_qe_mode_quirks(cs
, spi
,
261 if (bits_per_word
< 0)
262 return bits_per_word
;
264 if (bits_per_word
== 32)
267 bits_per_word
= bits_per_word
- 1;
269 /* mask out bits we are going to set */
270 cs
->hw_mode
&= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
273 cs
->hw_mode
|= SPMODE_LEN(bits_per_word
);
275 if ((mpc8xxx_spi
->spibrg
/ hz
) > 64) {
276 cs
->hw_mode
|= SPMODE_DIV16
;
277 pm
= (mpc8xxx_spi
->spibrg
- 1) / (hz
* 64) + 1;
279 "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
280 dev_name(&spi
->dev
), hz
, mpc8xxx_spi
->spibrg
/ 1024);
284 pm
= (mpc8xxx_spi
->spibrg
- 1) / (hz
* 4) + 1;
289 cs
->hw_mode
|= SPMODE_PM(pm
);
291 fsl_spi_change_mode(spi
);
295 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi
*mspi
,
296 struct spi_transfer
*t
, unsigned int len
)
299 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
304 mpc8xxx_spi_write_reg(®_base
->mask
, SPIM_NE
);
307 word
= mspi
->get_tx(mspi
);
308 mpc8xxx_spi_write_reg(®_base
->transmit
, word
);
313 static int fsl_spi_bufs(struct spi_device
*spi
, struct spi_transfer
*t
,
316 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
317 struct fsl_spi_reg
*reg_base
;
318 unsigned int len
= t
->len
;
322 reg_base
= mpc8xxx_spi
->reg_base
;
323 bits_per_word
= spi
->bits_per_word
;
324 if (t
->bits_per_word
)
325 bits_per_word
= t
->bits_per_word
;
327 if (bits_per_word
> 8) {
328 /* invalid length? */
333 if (bits_per_word
> 16) {
334 /* invalid length? */
340 mpc8xxx_spi
->tx
= t
->tx_buf
;
341 mpc8xxx_spi
->rx
= t
->rx_buf
;
343 reinit_completion(&mpc8xxx_spi
->done
);
345 if (mpc8xxx_spi
->flags
& SPI_CPM_MODE
)
346 ret
= fsl_spi_cpm_bufs(mpc8xxx_spi
, t
, is_dma_mapped
);
348 ret
= fsl_spi_cpu_bufs(mpc8xxx_spi
, t
, len
);
352 wait_for_completion(&mpc8xxx_spi
->done
);
354 /* disable rx ints */
355 mpc8xxx_spi_write_reg(®_base
->mask
, 0);
357 if (mpc8xxx_spi
->flags
& SPI_CPM_MODE
)
358 fsl_spi_cpm_bufs_complete(mpc8xxx_spi
);
360 return mpc8xxx_spi
->count
;
363 static int fsl_spi_do_one_msg(struct spi_master
*master
,
364 struct spi_message
*m
)
366 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
367 struct spi_device
*spi
= m
->spi
;
368 struct spi_transfer
*t
, *first
;
369 unsigned int cs_change
;
370 const int nsecs
= 50;
371 int status
, last_bpw
;
374 * In CPU mode, optimize large byte transfers to use larger
375 * bits_per_word values to reduce number of interrupts taken.
377 if (!(mpc8xxx_spi
->flags
& SPI_CPM_MODE
)) {
378 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
379 if (t
->len
< 256 || t
->bits_per_word
!= 8)
381 if ((t
->len
& 3) == 0)
382 t
->bits_per_word
= 32;
383 else if ((t
->len
& 1) == 0)
384 t
->bits_per_word
= 16;
388 /* Don't allow changes if CS is active */
390 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
393 cs_change
= t
->cs_change
;
394 if (first
->speed_hz
!= t
->speed_hz
) {
396 "speed_hz cannot change while CS is active\n");
404 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
405 if (cs_change
|| last_bpw
!= t
->bits_per_word
)
406 status
= fsl_spi_setup_transfer(spi
, t
);
409 last_bpw
= t
->bits_per_word
;
412 fsl_spi_chipselect(spi
, BITBANG_CS_ACTIVE
);
415 cs_change
= t
->cs_change
;
417 status
= fsl_spi_bufs(spi
, t
, m
->is_dma_mapped
);
422 m
->actual_length
+= t
->len
;
425 udelay(t
->delay_usecs
);
429 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
435 spi_finalize_current_message(master
);
437 if (status
|| !cs_change
) {
439 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
442 fsl_spi_setup_transfer(spi
, NULL
);
446 static int fsl_spi_setup(struct spi_device
*spi
)
448 struct mpc8xxx_spi
*mpc8xxx_spi
;
449 struct fsl_spi_reg
*reg_base
;
452 struct spi_mpc8xxx_cs
*cs
= spi_get_ctldata(spi
);
454 if (!spi
->max_speed_hz
)
458 cs
= kzalloc(sizeof(*cs
), GFP_KERNEL
);
461 spi_set_ctldata(spi
, cs
);
463 mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
465 reg_base
= mpc8xxx_spi
->reg_base
;
467 hw_mode
= cs
->hw_mode
; /* Save original settings */
468 cs
->hw_mode
= mpc8xxx_spi_read_reg(®_base
->mode
);
469 /* mask out bits we are going to set */
470 cs
->hw_mode
&= ~(SPMODE_CP_BEGIN_EDGECLK
| SPMODE_CI_INACTIVEHIGH
471 | SPMODE_REV
| SPMODE_LOOP
);
473 if (spi
->mode
& SPI_CPHA
)
474 cs
->hw_mode
|= SPMODE_CP_BEGIN_EDGECLK
;
475 if (spi
->mode
& SPI_CPOL
)
476 cs
->hw_mode
|= SPMODE_CI_INACTIVEHIGH
;
477 if (!(spi
->mode
& SPI_LSB_FIRST
))
478 cs
->hw_mode
|= SPMODE_REV
;
479 if (spi
->mode
& SPI_LOOP
)
480 cs
->hw_mode
|= SPMODE_LOOP
;
482 retval
= fsl_spi_setup_transfer(spi
, NULL
);
484 cs
->hw_mode
= hw_mode
; /* Restore settings */
488 if (mpc8xxx_spi
->type
== TYPE_GRLIB
) {
489 if (gpio_is_valid(spi
->cs_gpio
)) {
492 retval
= gpio_request(spi
->cs_gpio
,
493 dev_name(&spi
->dev
));
497 desel
= !(spi
->mode
& SPI_CS_HIGH
);
498 retval
= gpio_direction_output(spi
->cs_gpio
, desel
);
500 gpio_free(spi
->cs_gpio
);
503 } else if (spi
->cs_gpio
!= -ENOENT
) {
504 if (spi
->cs_gpio
< 0)
508 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
509 * indicates to use native chipselect if present, or allow for
510 * an always selected chip
514 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
515 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
520 static void fsl_spi_cleanup(struct spi_device
*spi
)
522 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
523 struct spi_mpc8xxx_cs
*cs
= spi_get_ctldata(spi
);
525 if (mpc8xxx_spi
->type
== TYPE_GRLIB
&& gpio_is_valid(spi
->cs_gpio
))
526 gpio_free(spi
->cs_gpio
);
529 spi_set_ctldata(spi
, NULL
);
532 static void fsl_spi_cpu_irq(struct mpc8xxx_spi
*mspi
, u32 events
)
534 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
536 /* We need handle RX first */
537 if (events
& SPIE_NE
) {
538 u32 rx_data
= mpc8xxx_spi_read_reg(®_base
->receive
);
541 mspi
->get_rx(rx_data
, mspi
);
544 if ((events
& SPIE_NF
) == 0)
545 /* spin until TX is done */
547 mpc8xxx_spi_read_reg(®_base
->event
)) &
551 /* Clear the events */
552 mpc8xxx_spi_write_reg(®_base
->event
, events
);
556 u32 word
= mspi
->get_tx(mspi
);
558 mpc8xxx_spi_write_reg(®_base
->transmit
, word
);
560 complete(&mspi
->done
);
564 static irqreturn_t
fsl_spi_irq(s32 irq
, void *context_data
)
566 struct mpc8xxx_spi
*mspi
= context_data
;
567 irqreturn_t ret
= IRQ_NONE
;
569 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
571 /* Get interrupt events(tx/rx) */
572 events
= mpc8xxx_spi_read_reg(®_base
->event
);
576 dev_dbg(mspi
->dev
, "%s: events %x\n", __func__
, events
);
578 if (mspi
->flags
& SPI_CPM_MODE
)
579 fsl_spi_cpm_irq(mspi
, events
);
581 fsl_spi_cpu_irq(mspi
, events
);
586 static void fsl_spi_grlib_cs_control(struct spi_device
*spi
, bool on
)
588 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
589 struct fsl_spi_reg
*reg_base
= mpc8xxx_spi
->reg_base
;
591 u16 cs
= spi
->chip_select
;
593 if (gpio_is_valid(spi
->cs_gpio
)) {
594 gpio_set_value(spi
->cs_gpio
, on
);
595 } else if (cs
< mpc8xxx_spi
->native_chipselects
) {
596 slvsel
= mpc8xxx_spi_read_reg(®_base
->slvsel
);
597 slvsel
= on
? (slvsel
| (1 << cs
)) : (slvsel
& ~(1 << cs
));
598 mpc8xxx_spi_write_reg(®_base
->slvsel
, slvsel
);
602 static void fsl_spi_grlib_probe(struct device
*dev
)
604 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
605 struct spi_master
*master
= dev_get_drvdata(dev
);
606 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
607 struct fsl_spi_reg
*reg_base
= mpc8xxx_spi
->reg_base
;
611 capabilities
= mpc8xxx_spi_read_reg(®_base
->cap
);
613 mpc8xxx_spi
->set_shifts
= fsl_spi_grlib_set_shifts
;
614 mbits
= SPCAP_MAXWLEN(capabilities
);
616 mpc8xxx_spi
->max_bits_per_word
= mbits
+ 1;
618 mpc8xxx_spi
->native_chipselects
= 0;
619 if (SPCAP_SSEN(capabilities
)) {
620 mpc8xxx_spi
->native_chipselects
= SPCAP_SSSZ(capabilities
);
621 mpc8xxx_spi_write_reg(®_base
->slvsel
, 0xffffffff);
623 master
->num_chipselect
= mpc8xxx_spi
->native_chipselects
;
624 pdata
->cs_control
= fsl_spi_grlib_cs_control
;
627 static struct spi_master
* fsl_spi_probe(struct device
*dev
,
628 struct resource
*mem
, unsigned int irq
)
630 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
631 struct spi_master
*master
;
632 struct mpc8xxx_spi
*mpc8xxx_spi
;
633 struct fsl_spi_reg
*reg_base
;
637 master
= spi_alloc_master(dev
, sizeof(struct mpc8xxx_spi
));
638 if (master
== NULL
) {
643 dev_set_drvdata(dev
, master
);
645 mpc8xxx_spi_probe(dev
, mem
, irq
);
647 master
->setup
= fsl_spi_setup
;
648 master
->cleanup
= fsl_spi_cleanup
;
649 master
->transfer_one_message
= fsl_spi_do_one_msg
;
651 mpc8xxx_spi
= spi_master_get_devdata(master
);
652 mpc8xxx_spi
->max_bits_per_word
= 32;
653 mpc8xxx_spi
->type
= fsl_spi_get_type(dev
);
655 ret
= fsl_spi_cpm_init(mpc8xxx_spi
);
659 mpc8xxx_spi
->reg_base
= devm_ioremap_resource(dev
, mem
);
660 if (IS_ERR(mpc8xxx_spi
->reg_base
)) {
661 ret
= PTR_ERR(mpc8xxx_spi
->reg_base
);
665 if (mpc8xxx_spi
->type
== TYPE_GRLIB
)
666 fsl_spi_grlib_probe(dev
);
668 master
->bits_per_word_mask
=
669 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
670 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi
->max_bits_per_word
);
672 if (mpc8xxx_spi
->flags
& SPI_QE_CPU_MODE
)
673 mpc8xxx_spi
->set_shifts
= fsl_spi_qe_cpu_set_shifts
;
675 if (mpc8xxx_spi
->set_shifts
)
676 /* 8 bits per word and MSB first */
677 mpc8xxx_spi
->set_shifts(&mpc8xxx_spi
->rx_shift
,
678 &mpc8xxx_spi
->tx_shift
, 8, 1);
680 /* Register for SPI Interrupt */
681 ret
= devm_request_irq(dev
, mpc8xxx_spi
->irq
, fsl_spi_irq
,
682 0, "fsl_spi", mpc8xxx_spi
);
687 reg_base
= mpc8xxx_spi
->reg_base
;
689 /* SPI controller initializations */
690 mpc8xxx_spi_write_reg(®_base
->mode
, 0);
691 mpc8xxx_spi_write_reg(®_base
->mask
, 0);
692 mpc8xxx_spi_write_reg(®_base
->command
, 0);
693 mpc8xxx_spi_write_reg(®_base
->event
, 0xffffffff);
695 /* Enable SPI interface */
696 regval
= pdata
->initial_spmode
| SPMODE_INIT_VAL
| SPMODE_ENABLE
;
697 if (mpc8xxx_spi
->max_bits_per_word
< 8) {
698 regval
&= ~SPMODE_LEN(0xF);
699 regval
|= SPMODE_LEN(mpc8xxx_spi
->max_bits_per_word
- 1);
701 if (mpc8xxx_spi
->flags
& SPI_QE_CPU_MODE
)
704 mpc8xxx_spi_write_reg(®_base
->mode
, regval
);
706 ret
= devm_spi_register_master(dev
, master
);
710 dev_info(dev
, "at 0x%p (irq = %d), %s mode\n", reg_base
,
711 mpc8xxx_spi
->irq
, mpc8xxx_spi_strmode(mpc8xxx_spi
->flags
));
716 fsl_spi_cpm_free(mpc8xxx_spi
);
718 spi_master_put(master
);
723 static void fsl_spi_cs_control(struct spi_device
*spi
, bool on
)
725 struct device
*dev
= spi
->dev
.parent
->parent
;
726 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
727 struct mpc8xxx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
728 u16 cs
= spi
->chip_select
;
730 if (cs
< pinfo
->ngpios
) {
731 int gpio
= pinfo
->gpios
[cs
];
732 bool alow
= pinfo
->alow_flags
[cs
];
734 gpio_set_value(gpio
, on
^ alow
);
736 if (WARN_ON_ONCE(cs
> pinfo
->ngpios
|| !pinfo
->immr_spi_cs
))
738 iowrite32be(on
? SPI_BOOT_SEL_BIT
: 0, pinfo
->immr_spi_cs
);
742 static int of_fsl_spi_get_chipselects(struct device
*dev
)
744 struct device_node
*np
= dev
->of_node
;
745 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
746 struct mpc8xxx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
747 bool spisel_boot
= IS_ENABLED(CONFIG_FSL_SOC
) &&
748 of_property_read_bool(np
, "fsl,spisel_boot");
753 ngpios
= of_gpio_count(np
);
754 ngpios
= max(ngpios
, 0);
755 if (ngpios
== 0 && !spisel_boot
) {
757 * SPI w/o chip-select line. One SPI device is still permitted
760 pdata
->max_chipselect
= 1;
764 pinfo
->ngpios
= ngpios
;
765 pinfo
->gpios
= kmalloc_array(ngpios
, sizeof(*pinfo
->gpios
),
769 memset(pinfo
->gpios
, -1, ngpios
* sizeof(*pinfo
->gpios
));
771 pinfo
->alow_flags
= kcalloc(ngpios
, sizeof(*pinfo
->alow_flags
),
773 if (!pinfo
->alow_flags
) {
775 goto err_alloc_flags
;
778 for (; i
< ngpios
; i
++) {
780 enum of_gpio_flags flags
;
782 gpio
= of_get_gpio_flags(np
, i
, &flags
);
783 if (!gpio_is_valid(gpio
)) {
784 dev_err(dev
, "invalid gpio #%d: %d\n", i
, gpio
);
789 ret
= gpio_request(gpio
, dev_name(dev
));
791 dev_err(dev
, "can't request gpio #%d: %d\n", i
, ret
);
795 pinfo
->gpios
[i
] = gpio
;
796 pinfo
->alow_flags
[i
] = flags
& OF_GPIO_ACTIVE_LOW
;
798 ret
= gpio_direction_output(pinfo
->gpios
[i
],
799 pinfo
->alow_flags
[i
]);
802 "can't set output direction for gpio #%d: %d\n",
808 #if IS_ENABLED(CONFIG_FSL_SOC)
810 pinfo
->immr_spi_cs
= ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET
, 4);
811 if (!pinfo
->immr_spi_cs
) {
819 pdata
->max_chipselect
= ngpios
+ spisel_boot
;
820 pdata
->cs_control
= fsl_spi_cs_control
;
826 if (gpio_is_valid(pinfo
->gpios
[i
]))
827 gpio_free(pinfo
->gpios
[i
]);
831 kfree(pinfo
->alow_flags
);
832 pinfo
->alow_flags
= NULL
;
839 static int of_fsl_spi_free_chipselects(struct device
*dev
)
841 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
842 struct mpc8xxx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
848 for (i
= 0; i
< pdata
->max_chipselect
; i
++) {
849 if (gpio_is_valid(pinfo
->gpios
[i
]))
850 gpio_free(pinfo
->gpios
[i
]);
854 kfree(pinfo
->alow_flags
);
858 static int of_fsl_spi_probe(struct platform_device
*ofdev
)
860 struct device
*dev
= &ofdev
->dev
;
861 struct device_node
*np
= ofdev
->dev
.of_node
;
862 struct spi_master
*master
;
867 ret
= of_mpc8xxx_spi_probe(ofdev
);
871 type
= fsl_spi_get_type(&ofdev
->dev
);
872 if (type
== TYPE_FSL
) {
873 ret
= of_fsl_spi_get_chipselects(dev
);
878 ret
= of_address_to_resource(np
, 0, &mem
);
882 irq
= irq_of_parse_and_map(np
, 0);
888 master
= fsl_spi_probe(dev
, &mem
, irq
);
889 if (IS_ERR(master
)) {
890 ret
= PTR_ERR(master
);
897 irq_dispose_mapping(irq
);
898 if (type
== TYPE_FSL
)
899 of_fsl_spi_free_chipselects(dev
);
903 static int of_fsl_spi_remove(struct platform_device
*ofdev
)
905 struct spi_master
*master
= platform_get_drvdata(ofdev
);
906 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
908 fsl_spi_cpm_free(mpc8xxx_spi
);
909 if (mpc8xxx_spi
->type
== TYPE_FSL
)
910 of_fsl_spi_free_chipselects(&ofdev
->dev
);
914 static struct platform_driver of_fsl_spi_driver
= {
917 .of_match_table
= of_fsl_spi_match
,
919 .probe
= of_fsl_spi_probe
,
920 .remove
= of_fsl_spi_remove
,
923 #ifdef CONFIG_MPC832x_RDB
926 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
927 * only. The driver should go away soon, since newer MPC8323E-RDB's device
928 * tree can work with OpenFirmware driver. But for now we support old trees
931 static int plat_mpc8xxx_spi_probe(struct platform_device
*pdev
)
933 struct resource
*mem
;
935 struct spi_master
*master
;
937 if (!dev_get_platdata(&pdev
->dev
))
940 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
944 irq
= platform_get_irq(pdev
, 0);
948 master
= fsl_spi_probe(&pdev
->dev
, mem
, irq
);
949 return PTR_ERR_OR_ZERO(master
);
952 static int plat_mpc8xxx_spi_remove(struct platform_device
*pdev
)
954 struct spi_master
*master
= platform_get_drvdata(pdev
);
955 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
957 fsl_spi_cpm_free(mpc8xxx_spi
);
962 MODULE_ALIAS("platform:mpc8xxx_spi");
963 static struct platform_driver mpc8xxx_spi_driver
= {
964 .probe
= plat_mpc8xxx_spi_probe
,
965 .remove
= plat_mpc8xxx_spi_remove
,
967 .name
= "mpc8xxx_spi",
971 static bool legacy_driver_failed
;
973 static void __init
legacy_driver_register(void)
975 legacy_driver_failed
= platform_driver_register(&mpc8xxx_spi_driver
);
978 static void __exit
legacy_driver_unregister(void)
980 if (legacy_driver_failed
)
982 platform_driver_unregister(&mpc8xxx_spi_driver
);
985 static void __init
legacy_driver_register(void) {}
986 static void __exit
legacy_driver_unregister(void) {}
987 #endif /* CONFIG_MPC832x_RDB */
989 static int __init
fsl_spi_init(void)
991 legacy_driver_register();
992 return platform_driver_register(&of_fsl_spi_driver
);
994 module_init(fsl_spi_init
);
996 static void __exit
fsl_spi_exit(void)
998 platform_driver_unregister(&of_fsl_spi_driver
);
999 legacy_driver_unregister();
1001 module_exit(fsl_spi_exit
);
1003 MODULE_AUTHOR("Kumar Gala");
1004 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
1005 MODULE_LICENSE("GPL");