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Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-imx.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_bitbang.h>
36 #include <linux/types.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_gpio.h>
40 #include <linux/pinctrl/consumer.h>
41
42 #include <mach/spi.h>
43
44 #define DRIVER_NAME "spi_imx"
45
46 #define MXC_CSPIRXDATA 0x00
47 #define MXC_CSPITXDATA 0x04
48 #define MXC_CSPICTRL 0x08
49 #define MXC_CSPIINT 0x0c
50 #define MXC_RESET 0x1c
51
52 /* generic defines to abstract from the different register layouts */
53 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
54 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
55
56 struct spi_imx_config {
57 unsigned int speed_hz;
58 unsigned int bpw;
59 unsigned int mode;
60 u8 cs;
61 };
62
63 enum spi_imx_devtype {
64 IMX1_CSPI,
65 IMX21_CSPI,
66 IMX27_CSPI,
67 IMX31_CSPI,
68 IMX35_CSPI, /* CSPI on all i.mx except above */
69 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
70 };
71
72 struct spi_imx_data;
73
74 struct spi_imx_devtype_data {
75 void (*intctrl)(struct spi_imx_data *, int);
76 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
77 void (*trigger)(struct spi_imx_data *);
78 int (*rx_available)(struct spi_imx_data *);
79 void (*reset)(struct spi_imx_data *);
80 enum spi_imx_devtype devtype;
81 };
82
83 struct spi_imx_data {
84 struct spi_bitbang bitbang;
85
86 struct completion xfer_done;
87 void __iomem *base;
88 int irq;
89 struct clk *clk;
90 unsigned long spi_clk;
91
92 unsigned int count;
93 void (*tx)(struct spi_imx_data *);
94 void (*rx)(struct spi_imx_data *);
95 void *rx_buf;
96 const void *tx_buf;
97 unsigned int txfifo; /* number of words pushed in tx FIFO */
98
99 struct spi_imx_devtype_data *devtype_data;
100 int chipselect[0];
101 };
102
103 static inline int is_imx27_cspi(struct spi_imx_data *d)
104 {
105 return d->devtype_data->devtype == IMX27_CSPI;
106 }
107
108 static inline int is_imx35_cspi(struct spi_imx_data *d)
109 {
110 return d->devtype_data->devtype == IMX35_CSPI;
111 }
112
113 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
114 {
115 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
116 }
117
118 #define MXC_SPI_BUF_RX(type) \
119 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
120 { \
121 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
122 \
123 if (spi_imx->rx_buf) { \
124 *(type *)spi_imx->rx_buf = val; \
125 spi_imx->rx_buf += sizeof(type); \
126 } \
127 }
128
129 #define MXC_SPI_BUF_TX(type) \
130 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
131 { \
132 type val = 0; \
133 \
134 if (spi_imx->tx_buf) { \
135 val = *(type *)spi_imx->tx_buf; \
136 spi_imx->tx_buf += sizeof(type); \
137 } \
138 \
139 spi_imx->count -= sizeof(type); \
140 \
141 writel(val, spi_imx->base + MXC_CSPITXDATA); \
142 }
143
144 MXC_SPI_BUF_RX(u8)
145 MXC_SPI_BUF_TX(u8)
146 MXC_SPI_BUF_RX(u16)
147 MXC_SPI_BUF_TX(u16)
148 MXC_SPI_BUF_RX(u32)
149 MXC_SPI_BUF_TX(u32)
150
151 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
152 * (which is currently not the case in this driver)
153 */
154 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
155 256, 384, 512, 768, 1024};
156
157 /* MX21, MX27 */
158 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
159 unsigned int fspi, unsigned int max)
160 {
161 int i;
162
163 for (i = 2; i < max; i++)
164 if (fspi * mxc_clkdivs[i] >= fin)
165 return i;
166
167 return max;
168 }
169
170 /* MX1, MX31, MX35, MX51 CSPI */
171 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
172 unsigned int fspi)
173 {
174 int i, div = 4;
175
176 for (i = 0; i < 7; i++) {
177 if (fspi * div >= fin)
178 return i;
179 div <<= 1;
180 }
181
182 return 7;
183 }
184
185 #define MX51_ECSPI_CTRL 0x08
186 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
187 #define MX51_ECSPI_CTRL_XCH (1 << 2)
188 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
189 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
190 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
191 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
192 #define MX51_ECSPI_CTRL_BL_OFFSET 20
193
194 #define MX51_ECSPI_CONFIG 0x0c
195 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
196 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
197 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
198 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
199
200 #define MX51_ECSPI_INT 0x10
201 #define MX51_ECSPI_INT_TEEN (1 << 0)
202 #define MX51_ECSPI_INT_RREN (1 << 3)
203
204 #define MX51_ECSPI_STAT 0x18
205 #define MX51_ECSPI_STAT_RR (1 << 3)
206
207 /* MX51 eCSPI */
208 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
209 {
210 /*
211 * there are two 4-bit dividers, the pre-divider divides by
212 * $pre, the post-divider by 2^$post
213 */
214 unsigned int pre, post;
215
216 if (unlikely(fspi > fin))
217 return 0;
218
219 post = fls(fin) - fls(fspi);
220 if (fin > fspi << post)
221 post++;
222
223 /* now we have: (fin <= fspi << post) with post being minimal */
224
225 post = max(4U, post) - 4;
226 if (unlikely(post > 0xf)) {
227 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
228 __func__, fspi, fin);
229 return 0xff;
230 }
231
232 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
233
234 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
235 __func__, fin, fspi, post, pre);
236 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
237 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
238 }
239
240 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
241 {
242 unsigned val = 0;
243
244 if (enable & MXC_INT_TE)
245 val |= MX51_ECSPI_INT_TEEN;
246
247 if (enable & MXC_INT_RR)
248 val |= MX51_ECSPI_INT_RREN;
249
250 writel(val, spi_imx->base + MX51_ECSPI_INT);
251 }
252
253 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
254 {
255 u32 reg;
256
257 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
258 reg |= MX51_ECSPI_CTRL_XCH;
259 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
260 }
261
262 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
263 struct spi_imx_config *config)
264 {
265 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
266
267 /*
268 * The hardware seems to have a race condition when changing modes. The
269 * current assumption is that the selection of the channel arrives
270 * earlier in the hardware than the mode bits when they are written at
271 * the same time.
272 * So set master mode for all channels as we do not support slave mode.
273 */
274 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
275
276 /* set clock speed */
277 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
278
279 /* set chip select to use */
280 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
281
282 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
283
284 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
285
286 if (config->mode & SPI_CPHA)
287 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
288
289 if (config->mode & SPI_CPOL)
290 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
291
292 if (config->mode & SPI_CS_HIGH)
293 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
294
295 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
296 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
297
298 return 0;
299 }
300
301 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
302 {
303 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
304 }
305
306 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
307 {
308 /* drain receive buffer */
309 while (mx51_ecspi_rx_available(spi_imx))
310 readl(spi_imx->base + MXC_CSPIRXDATA);
311 }
312
313 #define MX31_INTREG_TEEN (1 << 0)
314 #define MX31_INTREG_RREN (1 << 3)
315
316 #define MX31_CSPICTRL_ENABLE (1 << 0)
317 #define MX31_CSPICTRL_MASTER (1 << 1)
318 #define MX31_CSPICTRL_XCH (1 << 2)
319 #define MX31_CSPICTRL_POL (1 << 4)
320 #define MX31_CSPICTRL_PHA (1 << 5)
321 #define MX31_CSPICTRL_SSCTL (1 << 6)
322 #define MX31_CSPICTRL_SSPOL (1 << 7)
323 #define MX31_CSPICTRL_BC_SHIFT 8
324 #define MX35_CSPICTRL_BL_SHIFT 20
325 #define MX31_CSPICTRL_CS_SHIFT 24
326 #define MX35_CSPICTRL_CS_SHIFT 12
327 #define MX31_CSPICTRL_DR_SHIFT 16
328
329 #define MX31_CSPISTATUS 0x14
330 #define MX31_STATUS_RR (1 << 3)
331
332 /* These functions also work for the i.MX35, but be aware that
333 * the i.MX35 has a slightly different register layout for bits
334 * we do not use here.
335 */
336 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
337 {
338 unsigned int val = 0;
339
340 if (enable & MXC_INT_TE)
341 val |= MX31_INTREG_TEEN;
342 if (enable & MXC_INT_RR)
343 val |= MX31_INTREG_RREN;
344
345 writel(val, spi_imx->base + MXC_CSPIINT);
346 }
347
348 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
349 {
350 unsigned int reg;
351
352 reg = readl(spi_imx->base + MXC_CSPICTRL);
353 reg |= MX31_CSPICTRL_XCH;
354 writel(reg, spi_imx->base + MXC_CSPICTRL);
355 }
356
357 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
358 struct spi_imx_config *config)
359 {
360 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
361 int cs = spi_imx->chipselect[config->cs];
362
363 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
364 MX31_CSPICTRL_DR_SHIFT;
365
366 if (is_imx35_cspi(spi_imx)) {
367 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
368 reg |= MX31_CSPICTRL_SSCTL;
369 } else {
370 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
371 }
372
373 if (config->mode & SPI_CPHA)
374 reg |= MX31_CSPICTRL_PHA;
375 if (config->mode & SPI_CPOL)
376 reg |= MX31_CSPICTRL_POL;
377 if (config->mode & SPI_CS_HIGH)
378 reg |= MX31_CSPICTRL_SSPOL;
379 if (cs < 0)
380 reg |= (cs + 32) <<
381 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
382 MX31_CSPICTRL_CS_SHIFT);
383
384 writel(reg, spi_imx->base + MXC_CSPICTRL);
385
386 return 0;
387 }
388
389 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
390 {
391 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
392 }
393
394 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
395 {
396 /* drain receive buffer */
397 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
398 readl(spi_imx->base + MXC_CSPIRXDATA);
399 }
400
401 #define MX21_INTREG_RR (1 << 4)
402 #define MX21_INTREG_TEEN (1 << 9)
403 #define MX21_INTREG_RREN (1 << 13)
404
405 #define MX21_CSPICTRL_POL (1 << 5)
406 #define MX21_CSPICTRL_PHA (1 << 6)
407 #define MX21_CSPICTRL_SSPOL (1 << 8)
408 #define MX21_CSPICTRL_XCH (1 << 9)
409 #define MX21_CSPICTRL_ENABLE (1 << 10)
410 #define MX21_CSPICTRL_MASTER (1 << 11)
411 #define MX21_CSPICTRL_DR_SHIFT 14
412 #define MX21_CSPICTRL_CS_SHIFT 19
413
414 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
415 {
416 unsigned int val = 0;
417
418 if (enable & MXC_INT_TE)
419 val |= MX21_INTREG_TEEN;
420 if (enable & MXC_INT_RR)
421 val |= MX21_INTREG_RREN;
422
423 writel(val, spi_imx->base + MXC_CSPIINT);
424 }
425
426 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
427 {
428 unsigned int reg;
429
430 reg = readl(spi_imx->base + MXC_CSPICTRL);
431 reg |= MX21_CSPICTRL_XCH;
432 writel(reg, spi_imx->base + MXC_CSPICTRL);
433 }
434
435 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
436 struct spi_imx_config *config)
437 {
438 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
439 int cs = spi_imx->chipselect[config->cs];
440 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
441
442 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
443 MX21_CSPICTRL_DR_SHIFT;
444 reg |= config->bpw - 1;
445
446 if (config->mode & SPI_CPHA)
447 reg |= MX21_CSPICTRL_PHA;
448 if (config->mode & SPI_CPOL)
449 reg |= MX21_CSPICTRL_POL;
450 if (config->mode & SPI_CS_HIGH)
451 reg |= MX21_CSPICTRL_SSPOL;
452 if (cs < 0)
453 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
454
455 writel(reg, spi_imx->base + MXC_CSPICTRL);
456
457 return 0;
458 }
459
460 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
461 {
462 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
463 }
464
465 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
466 {
467 writel(1, spi_imx->base + MXC_RESET);
468 }
469
470 #define MX1_INTREG_RR (1 << 3)
471 #define MX1_INTREG_TEEN (1 << 8)
472 #define MX1_INTREG_RREN (1 << 11)
473
474 #define MX1_CSPICTRL_POL (1 << 4)
475 #define MX1_CSPICTRL_PHA (1 << 5)
476 #define MX1_CSPICTRL_XCH (1 << 8)
477 #define MX1_CSPICTRL_ENABLE (1 << 9)
478 #define MX1_CSPICTRL_MASTER (1 << 10)
479 #define MX1_CSPICTRL_DR_SHIFT 13
480
481 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
482 {
483 unsigned int val = 0;
484
485 if (enable & MXC_INT_TE)
486 val |= MX1_INTREG_TEEN;
487 if (enable & MXC_INT_RR)
488 val |= MX1_INTREG_RREN;
489
490 writel(val, spi_imx->base + MXC_CSPIINT);
491 }
492
493 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
494 {
495 unsigned int reg;
496
497 reg = readl(spi_imx->base + MXC_CSPICTRL);
498 reg |= MX1_CSPICTRL_XCH;
499 writel(reg, spi_imx->base + MXC_CSPICTRL);
500 }
501
502 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
503 struct spi_imx_config *config)
504 {
505 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
506
507 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
508 MX1_CSPICTRL_DR_SHIFT;
509 reg |= config->bpw - 1;
510
511 if (config->mode & SPI_CPHA)
512 reg |= MX1_CSPICTRL_PHA;
513 if (config->mode & SPI_CPOL)
514 reg |= MX1_CSPICTRL_POL;
515
516 writel(reg, spi_imx->base + MXC_CSPICTRL);
517
518 return 0;
519 }
520
521 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
522 {
523 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
524 }
525
526 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
527 {
528 writel(1, spi_imx->base + MXC_RESET);
529 }
530
531 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
532 .intctrl = mx1_intctrl,
533 .config = mx1_config,
534 .trigger = mx1_trigger,
535 .rx_available = mx1_rx_available,
536 .reset = mx1_reset,
537 .devtype = IMX1_CSPI,
538 };
539
540 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
541 .intctrl = mx21_intctrl,
542 .config = mx21_config,
543 .trigger = mx21_trigger,
544 .rx_available = mx21_rx_available,
545 .reset = mx21_reset,
546 .devtype = IMX21_CSPI,
547 };
548
549 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
550 /* i.mx27 cspi shares the functions with i.mx21 one */
551 .intctrl = mx21_intctrl,
552 .config = mx21_config,
553 .trigger = mx21_trigger,
554 .rx_available = mx21_rx_available,
555 .reset = mx21_reset,
556 .devtype = IMX27_CSPI,
557 };
558
559 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
560 .intctrl = mx31_intctrl,
561 .config = mx31_config,
562 .trigger = mx31_trigger,
563 .rx_available = mx31_rx_available,
564 .reset = mx31_reset,
565 .devtype = IMX31_CSPI,
566 };
567
568 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
569 /* i.mx35 and later cspi shares the functions with i.mx31 one */
570 .intctrl = mx31_intctrl,
571 .config = mx31_config,
572 .trigger = mx31_trigger,
573 .rx_available = mx31_rx_available,
574 .reset = mx31_reset,
575 .devtype = IMX35_CSPI,
576 };
577
578 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
579 .intctrl = mx51_ecspi_intctrl,
580 .config = mx51_ecspi_config,
581 .trigger = mx51_ecspi_trigger,
582 .rx_available = mx51_ecspi_rx_available,
583 .reset = mx51_ecspi_reset,
584 .devtype = IMX51_ECSPI,
585 };
586
587 static struct platform_device_id spi_imx_devtype[] = {
588 {
589 .name = "imx1-cspi",
590 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
591 }, {
592 .name = "imx21-cspi",
593 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
594 }, {
595 .name = "imx27-cspi",
596 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
597 }, {
598 .name = "imx31-cspi",
599 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
600 }, {
601 .name = "imx35-cspi",
602 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
603 }, {
604 .name = "imx51-ecspi",
605 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
606 }, {
607 /* sentinel */
608 }
609 };
610
611 static const struct of_device_id spi_imx_dt_ids[] = {
612 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
613 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
614 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
615 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
616 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
617 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
618 { /* sentinel */ }
619 };
620
621 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
622 {
623 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
624 int gpio = spi_imx->chipselect[spi->chip_select];
625 int active = is_active != BITBANG_CS_INACTIVE;
626 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
627
628 if (gpio < 0)
629 return;
630
631 gpio_set_value(gpio, dev_is_lowactive ^ active);
632 }
633
634 static void spi_imx_push(struct spi_imx_data *spi_imx)
635 {
636 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
637 if (!spi_imx->count)
638 break;
639 spi_imx->tx(spi_imx);
640 spi_imx->txfifo++;
641 }
642
643 spi_imx->devtype_data->trigger(spi_imx);
644 }
645
646 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
647 {
648 struct spi_imx_data *spi_imx = dev_id;
649
650 while (spi_imx->devtype_data->rx_available(spi_imx)) {
651 spi_imx->rx(spi_imx);
652 spi_imx->txfifo--;
653 }
654
655 if (spi_imx->count) {
656 spi_imx_push(spi_imx);
657 return IRQ_HANDLED;
658 }
659
660 if (spi_imx->txfifo) {
661 /* No data left to push, but still waiting for rx data,
662 * enable receive data available interrupt.
663 */
664 spi_imx->devtype_data->intctrl(
665 spi_imx, MXC_INT_RR);
666 return IRQ_HANDLED;
667 }
668
669 spi_imx->devtype_data->intctrl(spi_imx, 0);
670 complete(&spi_imx->xfer_done);
671
672 return IRQ_HANDLED;
673 }
674
675 static int spi_imx_setupxfer(struct spi_device *spi,
676 struct spi_transfer *t)
677 {
678 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
679 struct spi_imx_config config;
680
681 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
682 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
683 config.mode = spi->mode;
684 config.cs = spi->chip_select;
685
686 if (!config.speed_hz)
687 config.speed_hz = spi->max_speed_hz;
688 if (!config.bpw)
689 config.bpw = spi->bits_per_word;
690 if (!config.speed_hz)
691 config.speed_hz = spi->max_speed_hz;
692
693 /* Initialize the functions for transfer */
694 if (config.bpw <= 8) {
695 spi_imx->rx = spi_imx_buf_rx_u8;
696 spi_imx->tx = spi_imx_buf_tx_u8;
697 } else if (config.bpw <= 16) {
698 spi_imx->rx = spi_imx_buf_rx_u16;
699 spi_imx->tx = spi_imx_buf_tx_u16;
700 } else if (config.bpw <= 32) {
701 spi_imx->rx = spi_imx_buf_rx_u32;
702 spi_imx->tx = spi_imx_buf_tx_u32;
703 } else
704 BUG();
705
706 spi_imx->devtype_data->config(spi_imx, &config);
707
708 return 0;
709 }
710
711 static int spi_imx_transfer(struct spi_device *spi,
712 struct spi_transfer *transfer)
713 {
714 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
715
716 spi_imx->tx_buf = transfer->tx_buf;
717 spi_imx->rx_buf = transfer->rx_buf;
718 spi_imx->count = transfer->len;
719 spi_imx->txfifo = 0;
720
721 init_completion(&spi_imx->xfer_done);
722
723 spi_imx_push(spi_imx);
724
725 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
726
727 wait_for_completion(&spi_imx->xfer_done);
728
729 return transfer->len;
730 }
731
732 static int spi_imx_setup(struct spi_device *spi)
733 {
734 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
735 int gpio = spi_imx->chipselect[spi->chip_select];
736
737 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
738 spi->mode, spi->bits_per_word, spi->max_speed_hz);
739
740 if (gpio >= 0)
741 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
742
743 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
744
745 return 0;
746 }
747
748 static void spi_imx_cleanup(struct spi_device *spi)
749 {
750 }
751
752 static int __devinit spi_imx_probe(struct platform_device *pdev)
753 {
754 struct device_node *np = pdev->dev.of_node;
755 const struct of_device_id *of_id =
756 of_match_device(spi_imx_dt_ids, &pdev->dev);
757 struct spi_imx_master *mxc_platform_info =
758 dev_get_platdata(&pdev->dev);
759 struct spi_master *master;
760 struct spi_imx_data *spi_imx;
761 struct resource *res;
762 struct pinctrl *pinctrl;
763 int i, ret, num_cs;
764
765 if (!np && !mxc_platform_info) {
766 dev_err(&pdev->dev, "can't get the platform data\n");
767 return -EINVAL;
768 }
769
770 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
771 if (ret < 0) {
772 if (mxc_platform_info)
773 num_cs = mxc_platform_info->num_chipselect;
774 else
775 return ret;
776 }
777
778 master = spi_alloc_master(&pdev->dev,
779 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
780 if (!master)
781 return -ENOMEM;
782
783 platform_set_drvdata(pdev, master);
784
785 master->bus_num = pdev->id;
786 master->num_chipselect = num_cs;
787
788 spi_imx = spi_master_get_devdata(master);
789 spi_imx->bitbang.master = spi_master_get(master);
790
791 for (i = 0; i < master->num_chipselect; i++) {
792 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
793 if (cs_gpio < 0 && mxc_platform_info)
794 cs_gpio = mxc_platform_info->chipselect[i];
795
796 spi_imx->chipselect[i] = cs_gpio;
797 if (cs_gpio < 0)
798 continue;
799
800 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
801 if (ret) {
802 dev_err(&pdev->dev, "can't get cs gpios\n");
803 goto out_gpio_free;
804 }
805 }
806
807 spi_imx->bitbang.chipselect = spi_imx_chipselect;
808 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
809 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
810 spi_imx->bitbang.master->setup = spi_imx_setup;
811 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
812 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
813
814 init_completion(&spi_imx->xfer_done);
815
816 spi_imx->devtype_data = of_id ? of_id->data :
817 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
818
819 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
820 if (!res) {
821 dev_err(&pdev->dev, "can't get platform resource\n");
822 ret = -ENOMEM;
823 goto out_gpio_free;
824 }
825
826 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
827 dev_err(&pdev->dev, "request_mem_region failed\n");
828 ret = -EBUSY;
829 goto out_gpio_free;
830 }
831
832 spi_imx->base = ioremap(res->start, resource_size(res));
833 if (!spi_imx->base) {
834 ret = -EINVAL;
835 goto out_release_mem;
836 }
837
838 spi_imx->irq = platform_get_irq(pdev, 0);
839 if (spi_imx->irq < 0) {
840 ret = -EINVAL;
841 goto out_iounmap;
842 }
843
844 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
845 if (ret) {
846 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
847 goto out_iounmap;
848 }
849
850 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
851 if (IS_ERR(pinctrl)) {
852 ret = PTR_ERR(pinctrl);
853 goto out_free_irq;
854 }
855
856 spi_imx->clk = clk_get(&pdev->dev, NULL);
857 if (IS_ERR(spi_imx->clk)) {
858 dev_err(&pdev->dev, "unable to get clock\n");
859 ret = PTR_ERR(spi_imx->clk);
860 goto out_free_irq;
861 }
862
863 clk_enable(spi_imx->clk);
864 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
865
866 spi_imx->devtype_data->reset(spi_imx);
867
868 spi_imx->devtype_data->intctrl(spi_imx, 0);
869
870 master->dev.of_node = pdev->dev.of_node;
871 ret = spi_bitbang_start(&spi_imx->bitbang);
872 if (ret) {
873 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
874 goto out_clk_put;
875 }
876
877 dev_info(&pdev->dev, "probed\n");
878
879 return ret;
880
881 out_clk_put:
882 clk_disable(spi_imx->clk);
883 clk_put(spi_imx->clk);
884 out_free_irq:
885 free_irq(spi_imx->irq, spi_imx);
886 out_iounmap:
887 iounmap(spi_imx->base);
888 out_release_mem:
889 release_mem_region(res->start, resource_size(res));
890 out_gpio_free:
891 while (--i >= 0) {
892 if (spi_imx->chipselect[i] >= 0)
893 gpio_free(spi_imx->chipselect[i]);
894 }
895 spi_master_put(master);
896 kfree(master);
897 platform_set_drvdata(pdev, NULL);
898 return ret;
899 }
900
901 static int __devexit spi_imx_remove(struct platform_device *pdev)
902 {
903 struct spi_master *master = platform_get_drvdata(pdev);
904 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
905 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
906 int i;
907
908 spi_bitbang_stop(&spi_imx->bitbang);
909
910 writel(0, spi_imx->base + MXC_CSPICTRL);
911 clk_disable(spi_imx->clk);
912 clk_put(spi_imx->clk);
913 free_irq(spi_imx->irq, spi_imx);
914 iounmap(spi_imx->base);
915
916 for (i = 0; i < master->num_chipselect; i++)
917 if (spi_imx->chipselect[i] >= 0)
918 gpio_free(spi_imx->chipselect[i]);
919
920 spi_master_put(master);
921
922 release_mem_region(res->start, resource_size(res));
923
924 platform_set_drvdata(pdev, NULL);
925
926 return 0;
927 }
928
929 static struct platform_driver spi_imx_driver = {
930 .driver = {
931 .name = DRIVER_NAME,
932 .owner = THIS_MODULE,
933 .of_match_table = spi_imx_dt_ids,
934 },
935 .id_table = spi_imx_devtype,
936 .probe = spi_imx_probe,
937 .remove = __devexit_p(spi_imx_remove),
938 };
939 module_platform_driver(spi_imx_driver);
940
941 MODULE_DESCRIPTION("SPI Master Controller driver");
942 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
943 MODULE_LICENSE("GPL");
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